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copyright ? f uture technology devices international limited 1 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 future technology devices international ltd . ft51a ( advanced microcontroller with 8051 compatible core) the ft51 a is a multi - featured device that can be targeted at a wide range of functions or applications : ? industry compatible 8051 core running at a maximum frequency of 48mhz . ? 8 kb of d ata m emory ? 16 kb of multi - time programmable (mtp) m emory ? 16 kb of s hadow m emory for fast read access by the core . ? usb 2.0 full speed hub controller allowing cascading of multiple ft51a devices ? usb 2.0 full speed device controller compatible to ft12 series ? supports up to 8 bi - directional endpoints with 2 x 1 k b usb endpoint buffer s ? max packet size is 504 bytes for usb isochronous endpoint and 64 bytes for c ontrol / bulk / interrupt endpoint ? double buffer scheme for any endpoint , increases data transfer throughput ? fully integrated clock generation with no external cr ystal required ? data transfer rates from 300 baud to 3 m baud (rs422 , rs485 , and rs232) at ttl levels ? pwm controller ? uart interface support for 7 or 8 data bits, 1 or 2 stop bits and odd / even / mark / space / no parity ? usb battery charger d etection allowin g optimized charging profile ? supports dma operation ? i 2 c master & slave functionality ? spi master & slave functionality ? 245 fifo module provides a simple fifo interface to transmit and receive data ? timer and watchdog ? up to 16 dedicated digital io pins ? up t o 16 multiplexed analogue / digital io pins ? support adc function on analogue io pins ? io mux control for maximum flexibility in pin selection ? configurable io pin output drive strength ; 4 ma ( min) and 16 ma ( max) ? + 5v single supply operation ? internal 3 .3 v/1 .8 v voltage regulators ? integrated power - on - reset circuit ? low operating and suspend current; 20 ma (active) and 150 ua (suspend) ? e xtended operating temperature range ; - 40 to 85 ? ? available in compact pb - free , rohs compliant packages : ? 48 - p in wqfn ? 44 - pin lqfp ? 32 - pin wqfn ? 28 - pin ssop n either the whole nor any part of the information c ontained in, or the produc t des c ribed in this manual, may be adapted or re produc ed in any mate rial or elec tronic form without the prior written c ons ent of the c opyright holder. t his product and its doc umentation are s up plied on an as - is bas is and no warranty as to their s uitability for any partic ular purpose is either made or implied. future t ec hno logy d evic es i nternational l td will not ac c ept any c laim for damages hows oever aris ing as a res ult of us e or failure of this produc t. y our s tatutory rights are not affec ted. t his produc t or any variant of it is not intended for us e in any medic al applianc e , devic e or s ys tem in whic h the failure of the produc t might reas onably be expected to res ult in pers onal injury. t his doc ument provides preliminary information that may be s ubjec t to c h ange without notic e. n o freedom to us e patents or other intellectual p roperty rights is implied by the public ation of this doc ument. future t echnology d evices i nternational l td, u nit 1 , 2 seaward p lace, c enturion business p ark, g lasgow g 4 1 1 hh u nited kingdom. sc otland registered company n umber: sc 1 3 6 6 4 0
copyright ? f uture technology devices international limited 2 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 1 typical applications ? usb data acquisition ? general purpose microcontroller ? sensor and monitoring control ? mass storage data transfers across all segments, including medical, industrial data - logger, power - metering, and test instrumentation ? usb to rs232/rs422/rs485 converters ? in corporate usb interface to enable pc transfers for development system s ? interfacing mcu/pld/fpga based designs to add usb connectivity ? industrial equipment control systems ? pos systems ? usb bar code readers ? internet of things application ? home au tomation control systems 1.1 part numbers part number package ft51aq - r 48 pin qfn, body 7x7x0.75 mm, pitch 0.5mm, taped and reel, 3000 per reel ft51a q - t 48 pin qfn , body 7x7x0.75 mm, pitch 0.5mm, tray packing , 490 per tray ft51al - r 44 pin lqfp, body 10 x10x1.4 mm, pitch 0.8mm, taped and reel, 1000 per reel ft51a l - t 44 pin lqfp , body 10x10x1.4 mm, pitch 0.8mm, tray packing, 160 per tray ft51bq - r 32 pin qfn, body 6x6x0.75 mm, pitch 0.5mm, taped and reel, 3000 per reel ft51bq - t 32 pin qfn , body 6x6x0.7 5 mm, pitch 0.5mm, tray packing, 490 per tray ft51cs - r 28 pin ssop, body 10.2x 5.3 x 1.75 mm, pitch 0.65mm, taped and reel, 2000 per reel ft51cs - u 28 pin ssop , body 10.2x 5.3x1.75 mm, pitch 0.65mm, tube packing, 47 per tube table 1 - 1 C part numbers 1.2 usb compliant the ft 51a is fully compliant with the usb 2.0 specification and has been given the usb - if test - id (tid) 40 001701 (rev c ) .
copyright ? f uture technology devices international limited 3 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 table of contents 1 typical appl ications ................................ ...................... 2 1.1 part numbers ................................ ................................ ......... 2 1.2 usb compliant ................................ ................................ ........ 2 2 device pin out and signal description ........................... 5 2.1 pin out - 28 pin ssop ................................ ............................. 5 2.2 pin out - 32 pin wqfn ................................ ........................... 6 2.3 pin o ut - 44 - pin lqfp ................................ ............................. 7 2.4 pin out - 48 - pin wqfn ................................ ............................ 8 2.5 pin configuration description ................................ .................. 9 3 functional description ................................ ................ 11 3.1 key features ................................ ................................ .......... 11 3.1.1 functional integration ................................ ................................ ............. 11 3.1.2 8051 core ................................ ................................ ............................. 11 3.2 functional block descriptions ................................ ................. 12 3.2.1 8051 ports 0 - 3 ................................ ................................ ..................... 12 3.2.2 timers and watchdog ................................ ................................ .............. 12 3.2.3 pll control ................................ ................................ ............................ 13 3.2.4 16kb multi - time programmable (mtp) memory ................................ ........... 13 3.2 .5 8kb data ram ................................ ................................ ....................... 13 3.2.6 16kb shadow ram ................................ ................................ ................. 13 3.2.7 special function register ................................ ................................ ......... 1 3 3.2.8 io registers ................................ ................................ .......................... 13 3.2.9 ldo regulators ................................ ................................ ...................... 13 3.2.10 bcd detect ................................ ................................ ........................... 13 3.2.11 usb xcvr ................................ ................................ ............................. 14 3.2.12 io multiplexer ................................ ................................ ........................ 14 3.2.13 i 2 c master ................................ ................................ ............................. 14 3.2.14 i 2 c slave ................................ ................................ .............................. 15 3.2.15 spi slave ................................ ................................ .............................. 15 3.2.16 spi master ................................ ................................ ............................ 15 3.2.17 debugger ................................ ................................ .............................. 15 3.2.18 245 fif o ................................ ................................ .............................. 16 3.2.19 pwm ................................ ................................ ................................ .... 16 3.2.20 digital io pins ................................ ................................ ........................ 16 3.2.21 analogue io pins ................................ ................................ .................... 16
copyright ? f uture technology devices international limited 4 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 3.2.22 adc ................................ ................................ ................................ ..... 16 4 device characteristics and ratings .............................. 18 4.1 absolute maximum ratings ................................ .................... 18 4.2 dc characteristics ................................ ................................ .. 19 4.3 mtp memory reliability characteristics ................................ ... 23 4.4 internal clock characteristics ................................ ................. 23 4.5 digital io ac characteristics ................................ .................. 24 4.6 analogue io characteristics ................................ ................... 25 5 usb power configurations ................................ .......... 26 5.1 usb bus powered config uration ................................ ............. 26 6 connection examples ................................ .................. 27 6.1 usb upstream and downstream port connections (48pin package) ................................ ................................ ....................... 27 6.2 usb upstream and downstream port connections (44pin package) ................................ ................................ ....................... 28 6.3 usb upstream port connections (32pin packa ge) .................... 28 6.4 usb upstream port connections (28pin package) .................... 29 7 package parameters ................................ ................... 30 7.1 48 - pin wqfn package outline ................................ ................ 30 7.2 44 - pin lqfp package outline ................................ ................. 31 7.3 32 - pin wqfn package outline ................................ ................ 32 7.4 28 - pin ssop package outline ................................ ................. 33 7.5 solder reflow profile ................................ ............................. 34 8 contact information ................................ ................... 35 appendix a C references ................................ ................. 36 document references ................................ ................................ .... 36 acronyms and abbreviations ................................ .......................... 36 appendix b - list of figures and tables ............................ 37 list of figures ................................ ................................ ................ 37 list of tables ................................ ................................ ................. 37 appendix c C list of io registers ................................ ...... 39 appendix d C revisi on history ................................ ......... 43
copyright ? f uture technology devices international limited 5 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 2 device pin out and signal description ft51a is available in 4 packages: 28 pin ssop, 32 pin wqfn, 44 pin lqfp and 48 pin wqfn . 2.1 pin out - 28 pin ssop figure 2 - 1 - 28 pin ssop package y y w w - x f t 5 1 c s 1 1 4 1 5 2 8 x x x x x x x x x x x x f t d i d i o 0 d i o 1 d i o 2 d i o 3 r s t d i o 8 g n d d i o 9 d i o 1 0 d i o 1 1 d i o 1 2 d i o 1 3 d i o 1 4 d i o 1 5 d e b u g g e r g n d a i o 1 0 a i o 1 1 a i o 1 4 a i o 1 5 u p _ d p u p _ d m a i o 7 a i o 6 a i o 5 a i o 4 v c c 5 v v o u t 3 v 3
copyright ? f uture technology devices international limited 6 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 2.2 pin out - 32 pin wqfn figure 2 - 2 - 32 pin wqfn package d i o 5 d i o 1 0 d i o 7 r s t d i o 8 d i o 9 d i o 6 d i o 1 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 v o u t 3 v 3 a i o 4 v c c 5 v d i o 1 d i o 4 d i o 3 d i o 2 d i o 0 d i o 1 3 d i o 1 2 d i o 1 4 d i o 1 5 a i o 1 0 d e b u g g e r g n d g n d a i o 1 5 a i o 1 1 a i o 1 4 u p _ d p u p _ d m a i o 7 a i o 6 a i o 5 f t d i x x x x x x x x x x f t 5 1 b q y y w w - x
copyright ? f uture technology devices international limited 7 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 2.3 pin out - 4 4 - pin lqfp figure 2 - 3 - 44 pin lqfp package f t d i x x x x x x x x x x f t 5 1 a l y y w w - x 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 1 4 3 5 7 6 8 9 1 1 1 0 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 2 3 3 3 0 3 1 2 9 2 7 2 8 2 6 2 5 2 3 2 4 d i o 5 d i o 1 4 a i o 1 3 a i o 3 d i o 6 d i o 7 r s t d i o 8 v c c i o d i o 9 d i o 1 0 d i o 1 1 d i o 1 2 d i o 1 3 d i o 1 5 d e b u g g e r g n d g n d g n d a i o 8 a i o 9 a i o 1 0 a i o 1 1 a i o 1 2 a i o 1 4 a i o 1 5 d w _ d p d w _ d m u p _ d p u p _ d m a i o 7 a i o 6 a i o 5 a i o 4 a i o 2 a i o 1 a i o 0 v c c 5 v v o u t 3 v 3 d i o 0 d i o 1 d i o 2 d i o 3 d i o 4
copyright ? f uture technology devices international limited 8 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 2.4 pin out - 48 - pin wqfn figure 2 - 4 - 48 pin wqfn package d i o 4 d i o 5 2 1 4 3 5 7 6 8 9 1 1 1 0 1 2 f t d i x x x x x x x x x x f t 5 1 a q y y w w - x d i o 1 3 d i o 1 4 d i o 1 5 d e b u g g e r g n d g n d g n d a i o 8 a i o 9 a i o 1 0 a i o 1 1 a i o 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 a i o 1 4 a i o 1 3 g n d a i o 1 5 d w _ d m d w _ d p u p _ d m u p _ d p a i o 6 a i o 7 a i o 4 a i o 5 a i o 2 a i o 3 a i o 0 a i o 1 v c c 5 v g n d v r e f v o u t 3 v 3 d i o 1 d i o 0 d i o 3 d i o 2 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 5 3 6 3 3 3 4 3 2 3 0 3 1 2 9 2 8 2 6 2 7 2 5 d i o 6 d i o 7 r s t d i o 8 v c c i o g n d d i o 9 d i o 1 0 d i o 1 1 d i o 1 2
copyright ? f uture technology devices international limited 9 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 2.5 pin configuration description pin nos. name type description 48 pin 44 pin 32 pin 28 pin 42 38 26 27 ** vcc 5v power input 5 v (or 3.3 v) supply to ic 7 6 - - vccio power input 1.8v C 3.3v supply for the io pins. this option is only available on the 44 & 48 pin packages. a fixed 3.3v supply from the internal regulator is supplied to the io pins for the 28 and 32 pin pack ages 43 39 27 28 ** vout3v 3 power output 3.3v regulator output. may be used to power vccio pin . note that a 100nf cap acitor should be connected to vout3v3 for proper operation. this output can also be used to power external circuitry up to a max imum curre nt rating of 50ma (typ). 8, 17, 18, 19, 28, 41, 49* 15,16, 17 14,15 , 33* 7 , 16 gnd power input ground table 2 - 1 C power and ground * pin 49 of wqfn48 or pin 33 of wqfn32 is the exposed centre pad under th e packaged ic. connect to gnd. * * if vcc 5v is supplied by 3 .3 v then vout3v3 must also be driven by the same 3 .3 v source .
copyright ? f uture technology devices international limited 10 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 pin nos. name type description 48 pin 44 pin 32 pin 28 pin 30 27 - - dw_dm input/ output downstream usb data signal minus. 29 26 - - dw_dp input/ output downstream usb data signal plus. 32 29 21 22 up_dm input/ output upstream usb data signal minus. 31 28 20 21 up_dp input/ output upstream usb data signal plus. 5 4 4 5 rst input device reset. active high 44 - - - vref input reference voltage . connect to vout3v3. 16 14 13 15 debugg er input / output chip debug port 1,2,3,4 ,6, 9,10,11,12 13,14,15 45,46,47,48 1,2,3, 5, 7,8 9,10,11 12,13, 40,41,42 43,44 1,2,3 5,6,7 8,9,10 11,12, 28,29,30 31,32 1,2,3, 4 , 6, 8,9, 10,11 12,13 ,14 p 1 .0_ p 1 .7 p 3 .0_ p 3 .7 (d io 0_d io15) input/ output general purpose digital io pins . weak i nternal pull up enabled on exit from por or hardware reset . 20,21,22,23 24,25,26,27 33,34,35,36 37,38,39,40 18,19,20,21 22,2 3,24,25 30,31,32,33 34,35,36,37 16,17,181 9,22,23 24,25 17,18 ,19 20,23 ,24 25,26 p 0 .0_ p 0 .7 p 2 .0_ p 2 .7 (aio0_a io15) input/ output adc analogue input pins . can also be used as digital io pins . aio0 C aio7 have no pull ups when using 44 or 48 pin packages. table 2 - 2 C common function pins
copyright ? f uture technology devices international limited 11 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 3 function al description figure 3 - 1 C ft51a block diagram the ft51a acts as a usb hub supporting t wo down s tream ports; the internal 8051 core and other peripherals (spi, uart, etc.) a nd an external downstream port (typical devices can be a mouse, keyb oard, mass storage device, etc. ) . the hub can optionally be disabled (under register control) resulting in the 8051 core appear ing at the upstream port. 3.1 key features 3.1.1 functional integration fully integrated mtp memory with built in shadow ram for fast memory access , internally generated clock, p ower - on - reset (por) and ldo regulators. 3.1.2 8051 core the ft51a is based around the industry standard 8051 microcontroller capable of running at a maximum frequency of 48mhz . the core is an ultra - high performance, speed optimized single - chip 8 - bit embedded controller dedicated for operation with fast on - chip memo ries.
copyright ? f uture technology devices international limited 12 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 3.1.2.1 on - chip debugger the 8051 works with a high \ performance hardware assisted debugger which m anages the communication between the core and the s oftware. 3.1.2.2 uart / ftdi uart there are two uarts in the system C one designed by ftdi and the second incorp orated with in the 8051 core . the 8051 uart has a maximum baud rate of up to 60kbps. the ftdi uart give s speeds up to 3 mbps . when the data and control bus are configured in uart mode, the interface implements a standard asynchronous serial uart port with f ull modem control. the uart can support baud rates from 183 baud to 3 mbaud. the maximum uart speed is limited by the cpu clock . the following maximum uart speed applies : cpu frequency maximum uart speed 48 mhz 3 mbaud 24 mhz 3 mbaud 12 mhz 1.5 mbaud 3.2 functional block descriptions the following paragraphs detail each function within the ft51a . please refer to the block diagram shown in figure 3 - 1 C ft51a block diagram . 3.2.1 8051 ports 0 - 3 the 8051 c ore has four 8 - bit bi directional ports : p0, p1, p2 and p3. these ports can be fully or partially mapped to external pins on the aio and dio bus. firmware can change the pin mapping through iomux programming. table 3 - 1 shows the default pin mapping for all the 4 ports on the lqfp44 and wqfn48 packages. pin type description aio 7 - aio 0 input / output p0 .7 C C C C table 3 - 1 C 8051 ports 3.2.2 timers and watchdog apart from standard 8051 timers the ft51a has four general purpose 16 - bit t imers a, b, c and d. a 32 - bit watchdog timer is also provided.
copyright ? f uture technology devices international limited 13 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 3.2.3 pll control the block provides an internally generated 48mhz clock to the system without the need of an external reference clock. this block is trimmed at factory test to 48mhz. during usb transactions the pll will provide an accurate clock, locked to th e incoming usb data rate. 3.2.4 16kb multi - time programm able (mtp) memory 16k bytes of mtp memory are available for firmware programming . code stored with the mtp memory is copied to the shadow ram on power up or an external reset. see section 3.2.6 . 3.2.5 8kb data ram 8k bytes of data ram are provided. 3.2.6 16kb shadow ram to facilitate fast program memory access, limit any bottlenecks and to allow fast programming times in a debug environment, a shadow ram exists that th e cpu will run from. the shadow ram has the following features: ? the contents of the mtp are copied to the shadow ram after a system reset C i.e. a por reset or a pin reset. ? a single command (register write access) initiates a hard copy of the program memo ry C i.e. the contents of the shadow ram are copied to the mtp. 3.2.7 special function register the 8051 core has a special function register area (sfr) and is limited to 128 locations. this area facilitates access to io registers and the usb full - s peed device controller command/data through in - direct addressing method. 3.2.8 io reg ister s the ft51a contains approximately 300 io registers. see appendix c for a full list of the io registers. 3.2.9 ldo regulators the +3.3v ldo regulator generates the +3.3v re ference voltage for driving the usb transceiver cell output buffers. it requires an external decoupling capacitor to be attached to the regulator output pin. the main function of the ldo is to power the usb transceiver and the reset generator cells rather than to power external logic. however, it can be used to supply external circuitry requiring a +3.3v nominal supply with a maximum current of 50ma. the + 1.8 v ldo regulator generates the + 1.8 v supply voltage for internal digital circuits . 3.2.10 bcd detect spec ial circuitry inside the ft51a detects when the usb upstream port is connected to a dedicated charging port. when it detects that it is connected to a dedicated charging port, the ft51a can use a dio or aio pin to notify a microcontroller or logic on the application board which in turn controls the battery charging circuits .
copyright ? f uture technology devices international limited 14 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 3.2.11 usb xcvr the usb transceiver cell provides the usb 2.0 full - speed physical interface to the usb cable. the output drivers provide +3.3v level slew rate control signalling, whilst a differential input receiver and two single ended input receivers provide usb data in, single - ended - 0 (se0) and usb reset detection conditions respectfully. this function also incorporates a 1.5k pull up resistor on the usb up dp pin . 3.2.12 io multiplex er with the addition of the i o multiplexer any function can be configured to any dio pin , excluding the analogue adc function which is constrained to the aio pins. all other digital functionality is recommended to map to dio pin s . the i o multi plexer allows the designer to select which perip herals are connected to which i o pins. in order to assign a signal to a particular pin , two register writes are required, one to select the signal and the other to select the io pin . the ft51 a programmers guide details the pins and signals which can be connected. the selectable peripheral interfaces are only limited by the n umber of io pins available. the number of ios available is dependent on the package type. table 3 - 2 lists the peripherals which can be multiplexed to io and the typical number of pins required for each one . the designer can choose any mix of peripheral configurations as long as they are within the specific package io pin count. peripherals number of pins required (typical) uart (ftdi) 4 uart ( 8051 ) 2 adc 1 - 16 8051 port 0 - 3 32 spi master 4 spi slave 4 245 fifo 12 i 2 c master 2 i 2 c slave 2 pwm 1 - 8 table 3 - 2 C peripheral pin requirements 3.2.13 i 2 c master the ft51a provides an interface between the core and an i 2 c bus. it can be programmed to o perate with arbitration and clock synchronization allowing it to operate in multi \ master systems. i 2 c master supports transmission speeds up to 3.4 mb/s including normal, fast and high speed modes .
copyright ? f uture technology devices international limited 15 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 3.2.14 i 2 c slave the ft51a provides an interface between the core and an i 2 c bus. it can work as a slave receiver or transmitter depending on the working mode determined by the core . the core incorporates all features required by the i 2 c specification. the slave supports all the transmission modes: standard, fa st, fast \ plus and high speed. clock stretching is supported. 3.2.15 spi slave the serial peripheral interface bus is an industry standard communications interface. devices communicate in master / slave mode, with the master initiating the data transfer. the spi slave mo dule has four signals C clock, slave select, mosi (master out C slave in) and miso (master in C slave out). 3.2.16 spi master figure 3 - 2 C spi master the spi master interface is used to interface to applications such as sd cards. the main purpose of the spi master block is to transfer data between an external spi interface and the ft51a . it does this under the control of the cpu and dma engine via the o n - chip io bus. the spi maste r module has seven signals C clock, slave select 0..3, mosi (master out C slave in) and miso (master in C slave out). the spi master protocol by default does not support any form of handshaking and the only available mode is unmanaged. the spi master clock can operate up to half of the cpu system clock: ? cpu running at 48 mhz would set the spi maximum clock to 24 mhz ? cpu running at 24 mhz would set the spi maximum clock to 12 mhz ? cpu running at 12 mhz would set the spi maximum clock to 6 m h z 3.2.17 debugger th e purpose of the debugger interface is to provide the integrated development environment (ide) with the following capabilities: ? mtp program. ? application debug - application code can have breakpoints, be single stepped and can be halted. ? d etailed internal debug - memory read/write access. the single wire interface has the following features: ? half duplex operation ? 1mbps speed ? 1 start bit spi master external - spi slave clk ss # miso mosi
copyright ? f uture technology devices international limited 16 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 ? 1 stop bit ? 8 data bits ? pull up 3.2.18 245 fifo the 245 fifo interface operating in a synchronous mode has an ei ght bit data bus, in dividual read and write strobes with two hardware flow control signals . 3.2.19 pwm the pulse width modulation (pwm) block can generate a signal in which parameters such as period and duty cycle are controlled by the 8051 core . it provides 8 outputs and can generate a core interrupt if set. the main purpose is to generate pwm signals which can be used to control motors, dc/dc converters, ac/dc supplies, etc. 3.2.20 digital io pins up to 16 general purpose digital io pins are available depending on the package type. 3.2.21 analogue io pins up to 16 aio pins are available depending on the package type. the pin can function in either analog ue or digital mode, but not both modes at the same time . when in analogue mode all 16 aio pins can be configured to th e adc m ode . aio_mode_1 aio_mode_0 configuration 0 0 analogue off. if the p in is configured for digital mode, it can be controlled similar to digital io pins . 0 1 reserved . 1 0 adc mode . analogue input signal for the internal adc convertor. 1 1 reserved . table 3 - 3 C aio modes to configure these modes , specific registers of the aios must be configured. on top of these modes sits a global mode which allows multiple control of aio pins . all 16 pins can be configured depending on the package type. 3.2.22 adc th e adc block can convert the analogue input signal to a digital value and store the value in the registers. the adc block can be configured to work in single - ended mode and differential mode. in single - ended mode, an input signal from any of the aio pins ca n be the input to the adc block, with the reference voltage connected to vout3v3 . in differential mode, two aio pins are used together to form a pair of differential inputs. the voltage difference between these two pins will be converted to digital values.
copyright ? f uture technology devices international limited 17 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 the adc support s single sample and global sample. in single sample mode only one selected aio input will be sampled at a time . in global sample mode, all the selected aio inputs will be sampled at the same time. the sample and hold settling time of the ad c is programmable. once conversion is done, the respective interrupt bit will be set, and an interrupt can be generated if enabled. the accuracy of the ad c convertor is 8 - bit.
copyright ? f uture technology devices international limited 18 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 4 d evice characteristics and ratings 4.1 absolute maximum ratings the absolute maximum ratings for the ft51a devices are as follows. these are in accordanc e with the absolute maximum rating system (iec 60134). exceeding these may cause permanent damage to the device. parameter value unit conditions storage temperature - 65c to 150c degrees c floor life (out of bag) at factory ambient (30c / 60% relativ e humidity) 168 hours (ipc /jedec j - std - 033a msl level 3 c ompliant)* hours ambient operating temperature (power applied) - 40c to 85c degrees c vc c 5 v supply voltage - 0.3 to + 6 . 0 v vc c io io voltage - 0.3 to + 3. 8 v dc input voltage C usb dp/dm pins - 0.5 to +3. 8 v dc input voltage C digital pins (powered from vc c io) - 0.3 to + (vc c io +0.5) v dc output c urrent C outputs 22 ma table 4 - 1 C absolute maximum ratings * if devices are stored out of the p ackaging beyond this time limit the devices should be baked before use. the devices should be ramped up to a temperature of + 125 c and baked for up to 17 hours .
copyright ? f uture technology devices international limited 19 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 4.2 dc characteristics dc characteristics (ambient temperature = - 40c to + 85c ) parameter descri ption minimum typical maximum units conditions vcc1 vcc 5v operating supply voltage 4.0 5 5.5 v normal operation vcc2 vcc 5v operating supply voltage 3.0 3.3 3.6 v vcc5v and vout3v3 pins must connect to the same 3v3 power source vio1 vccio operating suppl y voltage 3.0 3.3 3.6 v vio2 vccio operating supply voltage 2.3 2.5 2.7 v vio3 vccio operating supply voltage 1.65 1.8 1.95 v icc1 operating supply current 6. 5 20 2 8.3 ma normal operation at 48mhz icc2 operating supply current 1 50 a table 4 - 2 C operating voltage and current
copyright ? f uture technology devices international limited 20 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 parameter description minimum typical maximum units conditions v oh output voltage high 2. 9 vc c io v ioh = +/ - 2ma io drive strength = 4ma 2. 9 vc c io v io drive strength = 8ma 2. 9 vc c io v io drive strength = 12ma 2. 9 vc c io v io drive strength = 16ma vol output voltage low 0.4 v iol = +/ - 2ma io drive strength = 4ma 0.4 v io drive strength = 8ma 0.4 v io drive strength = 12ma 0.4 v io drive strength* = 16ma vil input low switching threshold 0.8 v lvttl vih input high switching threshold 2.0 v lvttl vt switching thre shold 1. 49 v vt - schmitt trigger negative going threshold voltage 1.1 5 v vt+ schmitt trigger positive going threshold voltage 1.6 4 v rpu input pull - up resistance 40 75 190 k? vin = 0 rpd input pull - down resistance 40 75 190 k? vin =vc c io iin input leakage c urrent - 10 10 a vin = 0 table 4 - 3 C io characteristics vccio = +3v3
copyright ? f uture technology devices international limited 21 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 parameter description minimum typical maximum units conditions voh output voltage high 2.25 vc c io v ioh = +/ - 2ma io drive strength* = 4ma 2.25 vc c io v io drive strength* = 8ma 2.25 vc c io v io drive strength = 12ma 2.25 vc c io v io drive strength = 16ma vol output voltage low 0.4 v iol = +/ - 2ma io drive strength = 4ma 0.4 v i o dr ive strength = 8ma 0.4 v io drive strength = 12ma 0.4 v io drive strength = 16ma vil input low switching threshold 0.8 v lvttl vih input high switching threshold 1.7 v lvttl vt switching threshold 1.1 v vt - schmitt trigger negati ve going threshold voltage 0.8 v vt+ schmitt trigger positive going threshold voltage 1. 2 v rpu input pull - up resistance 40 75 190 k? vin = 0 rpd input pull - down resistance 40 75 190 k? vin =vc c io iin input leakage c urrent - 10 10 a vin = 0 table 4 - 4 C io characteristics vccio = +2v5
copyright ? f uture technology devices international limited 22 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 parameter description minimum typical maximum units conditions voh output voltage high 1.62 vc c io v ioh = +/ - 2ma io drive strength* = 4ma 1.62 vc c io v io drive strength* = 8ma 1.62 vc c io v io drive strength* = 12ma 1.62 vc c io v io drive strength* = 16ma vol output voltage low 0.4 v iol = +/ - 2ma io drive strength* = 4ma 0.4 v io drive strength* = 8ma 0.4 v io driv e strength* = 12ma 0.4 v io drive strength* = 16ma vil input low switching threshold 0. 63 v lvttl vih input high switching threshold 1. 17 v lvttl vt switching threshold 0.77 v vt - schmitt trigger negative going threshold voltage 0.557 v vt+ schmitt trigger positive going threshold voltage 0.893 v rpu input pull - up resistance 40 75 190 k? vin = 0 rpd input pull - down resistance 40 75 190 k? vin =vc c io iin input leakage c urrent - 10 10 a vin = 0 table 4 - 5 C io characteristics vccio = +1v8 * the io drive strength and slow slew - rate ar e configurable in the io registers .
copyright ? f uture technology devices international limited 23 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 parameter description minimum typical maximum units conditions voh output voltage high 2.8 v vol output voltage low 0.2 v vil input low switching threshold 0.8 v vih input high switching threshold 2.0 v table 4 - 6 C usb dp/dm pin characteristics 4.3 mtp memory reliability characteristics the internal 16k b yte mtp memory has the following reliability characteristics: parameter value unit data retention 1 0 years write c ycle 2 ,000 c ycles read c ycle unlimited c ycles table 4 - 7 C mtp memory characteris ti cs 4.4 internal clock characteristics the internal clock oscillator has the following characteristics: parameter value unit minimum typical maximum frequency of operation (see note 1) 47 .98 48 .00 48 .02 mhz duty cycle 45 50 55 % table 4 - 8 C internal clock characteris ti cs note 1: equivalent to +/ - 1667ppm (usb upst ream port is active)
copyright ? f uture technology devices international limited 24 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 4.5 digital io ac characteristics please refer to the dio section of the ft51 a programmers guide on how to enable / disable the schmitt trigger, control the slew rate and determine drive strength. parameter value load load input timings (ns) 0.004pf tplh tphl 1.32pf tplh tphl schmitt trigger 0 1.25 0.98 2.48 2.13 1 1.27 1.08 2.51 2.24 output timings (ns) slew rate = normal 6pf tplh tphl 120pf tplh tphl drive strength 00 3.33 2.37 13.34 11.13 01 3.13 2.21 8.22 6.78 10 3.02 2.15 6.46 5.32 11 2.95 2.10 5.5 7 4.59 output timings (ns) slew rate = slow 6pf tplh tphl 120pf tplh tphl drive strength 00 3.33 2.37 13.34 1.13 01 3.33 2.37 9.24 7.81 10 3.33 2.4 7.80 6.61 11 3.32 2.39 7.05 5.97 table 4 - 9 C digital io ac characteristics
copyright ? f uture technology devices international limited 25 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 4.6 analogue io characteristics parameter description min max units conditions inl non - linearity +/ - 2 lsb dnl differential non - linearity +/ - 1 lsb table 4 - 10 C adc characteristics
copyright ? f uture technology devices international limited 26 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 5 usb power configur ations the following section s illustrate a possible usb power configuration for the ft51a . the illustrations have omitted pin numbers for ease of understanding since the pins differ between the various package options. 5.1 usb bus powered configuration figure 5 - 1 bus powered configuration figure 5 - 1 illustrates the ft51a in a typical usb bus powered des ign configuration. a usb bus powered device gets its power from the usb bus. basic rules for usb bus power ed devices are as follows C i) on plug - in to usb, the device should draw no more current than 50 ma. ii) in usb suspend mode the device should draw no more th an 500ua . iii) a device that consumes more than 100ma cannot be plugged into a usb bus powered hub. iv) no device can draw more than 500ma from the usb bus. the power descriptors in the internal mtp memory of the ft51a should be programmed to match the current drawn by the device. a ferrite bead is connected in series with the usb power supply to reduce emi noise from the ft51a and associated circuitry being radiated down the usb cable to the usb host. the value of the ferrite bead depends on the total cur rent drawn by the application. a suitable range of ferrite beads is available from laird technologies ( http://www.lairdtech.com ) for example laird technologies part # mi0805k 601 r - 10. ft 51 a 1 2 3 4 5 shield ferrite bead gnd gnd vcc gnd vcc 5 v vcc 3 v 3 usbdm usbdp vcc 100 nf 100 nf 10 nf 4 . 7 uf + 27 r 27 r gnd 47 pf 47 pf
copyright ? f uture technology devices international limited 27 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 6 connection examples the fol lowing sections i llustrate possible connections of the ft51a . 6.1 usb upstream and downstream port connections (48pi n package) figure 6 - 1 application example showing usb upstream and downstream connecti on (48pin package) shown above are the necessary c onnectio n s to connect the upstream & downstream usb ports. the debugger module is also included for added information should it be required.
copyright ? f uture technology devices international limited 28 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 6.2 usb upstream and downstream port connections (44pin package) figure 6 - 2 application example showing usb upstream and downstream connection (44pin package) 6.3 usb upstream port connections (32pin package) figure 6 - 3 application example showing usb upstream connection (32p in package)
copyright ? f uture technology devices international limited 29 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 6.4 usb upstream port connections (28pin package) figure 6 - 4 application example showing usb upstream connection (28pin package)
copyright ? f uture technology devices international limited 30 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 7 package parameters the ft51a is available in 4 package type s. the package is lead (pb) free, rohs compliant, and uses a green compound. the package is fully compliant with european union directive 2002/95/ec. 7.1 48 - pin wqfn package outline figure 7 - 1 48 pin wqfn package marking figure 7 - 2 48 pin wqfn package dimensions note: the centre pad on the base o f the ft51a is internally connected to ground. dimensions are in mm. ft di xxxxxxxxxx ft51aq line 1 C ftdi logo l ine 4 C date code, revision l ine 2 C wafer lot number 1 48 l ine 3 C ftdi part number yyww - c
copyright ? f uture technology devices international limited 31 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 7.2 44 - pin lqfp package outline figure 7 - 3 44 pin lqfp package marking figure 7 - 4 44 pin lqfp package dimensions ft di xxxxxxxxxx ft51al line 1 C ftdi logo l ine 4 C date code, revision l ine 2 C 1 44 l ine 3 C yyww - c
copyright ? f uture technology devices international limited 32 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 7.3 32 - pin wqfn package outline figure 7 - 5 32 pin wqfn package marking note: the centre pad on the base of the ft51a is internally connecte d to ground. dimensions are in mm. figure 7 - 6 32 pin wqfn package dimensions ft di xxxxxxxxxx f t51bq line 1 C ftdi logo l ine 4 C date code, revision l ine 2 C wafer lot number 1 32 l ine 3 C ftdi part number yyww - c
copyright ? f uture technology devices international limited 33 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 7.4 28 - pin ssop package outline figure 7 - 7 28 pin ssop package marking f igure 7 - 8 28 pin ssop package dimensions ft di xxxxxxxxxx ft51cs line 1 C ftdi logo l ine 4 C date code, revision l in e 2 C wafer lot number l ine 3 C ftdi part number yyww - c
copyright ? f uture technology devices international limited 34 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 7.5 solder reflow profile the ft51a is supplied in a pb free package. the recommended solder reflow profile is shown in figure 7 - 9 ft51a solder reflow profile . figure 7 - 9 ft51a solder reflow profile the recommended values for the solder reflow prof ile are detailed in error! reference source not found. . values are shown for both a completely pb free solder process (i.e. the ft51a is used with pb free solder), and for a non - pb free solder process (i.e. the ft51a is used with non - pb free solder). profile feature pb free solder process non - pb free solder process average ramp up rate (t s to t p ) 3c / second max. 3c / second max. preheat - temperature min (t s min.) - temperature max (t s max.) - time (t s min to t s max) 150c 200c 60 to 120 seconds 100c 150c 60 to 120 seconds time maintained above critical temperature t l : - temperature (t l ) - time (t l ) 217c 60 to 150 seconds 183c 60 to 150 seconds peak temperature (t p ) 260c 240c time within 5c of actual peak temperature (t p ) 20 to 40 seconds 20 to 40 seconds ramp down rate 6c / second max. 6c / second max. time for t= 25c t o peak temperature, t p 8 minutes max. 6 minutes max. table 7 - 1 C reflow profile parameters critical zone: when t is in the range t to t t e m p e r a t u r e , t ( d e g r e e s c ) time, t (seconds) 25 p t = 25 o c to t t p t p t l t preheat s t l ramp up l p ramp down t max s t min s
copyright ? f uture technology devices international limited 35 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 8 contact information head office C glasgow, uk branch office C tigard, oregon, usa future technology devices international limited unit 1, 2 seaward place, centurion business park glasgow g41 1hh united kingdom tel: +44 (0) 141 429 2777 fax: +44 (0) 141 429 2758 future technology devices international limited (usa) 7130 sw fir loop t igard, or 97223 - 8160 usa tel: +1 (503) 547 0988 fax: +1 (503) 547 0987 e - mail (sales) sales1@ftdichip.com e - mail (sales) us.sales@ftdichip.com e - mail (support) support1@ftdichip.com e - mail (support) us.support@ftdichip.com e - mail (general enquiries) admin1@ftdichip.com e - mail (gener al enquiries) us.admin@ftdichip.com branch office C taipei, taiwan branch office C shanghai, china future technology devices international limited (taiwan) 2f, no. 516, sec. 1, neihu road taipei 114 taiwa n , r.o.c. tel: +886 (0) 2 8791 3570 fax: +886 (0) 2 8791 3576 future technology devices international limited (china) room 1103, no. 666 west huaihai road, shanghai, 200052 c hina tel: +86 21 62351596 fax: +86 21 62351595 e - mail (sales) tw.sales1@ftdichip.com e - mail (sales) cn.sales@ftdichip.com e - mail (support) tw.support1@ftdichip.com e - mail (support) cn.support@ftdichip.com e - mail (general enquiries) tw.admin1@ftdichip.com e - mail (general enquiries) cn.admin@ftdichip.com web site http://ftdichip.com distributor and sales representatives please visit the sales network page of the ftdi web site for the contact details of our distributor(s) an d sales representative(s) in your country. sys tem and equipment manufacturers and des igners are responsible to ens ure that their s ystems, and any future t echnology d evi c es i nternational l td (ftdi) devices incorporated in their s ystems, meet all applic able s afety, regulatory and s ys tem - level performanc e requirements. a ll application - related information in this doc ument (inc luding application descriptions, s uggested ftd i devices and other materials ) is provided for referenc e only. while ft di has taken c a re to as s ure it is ac c urate, this information is s ubjec t to c us tomer c onfirmation, and ft di disclaims all liability for s ys tem des igns and for any applic ations as s is tanc e provided by ft d i . u s e o f ft d i devic es in life s upport and/or s afety applic ations is e ntirely at the us ers ris k, and the us er agrees to defend, indemnify and hold harmles s ftdi from any and all damages , c laims, s uits or expense resulting from s uc h us e. t his document is s ubject to c hange without notic e. n o freedom to us e patents or other in tellectual property rights is implied by the public ation of this doc ument. n either the whole nor any part of the information c ontained in, or the produc t des cribed in this document, may be adapted or reproduc ed in any material or elec tronic form without th e prior written c ons ent of the c opyright holder. future t ec hnology d evic es i nternational l td, u nit 1 , 2 seaward p lac e, c enturion business p ark, g las gow g 4 1 1 h h , u nited kingdom. sc otland regis tered c ompany n umber: sc 1 3 6 6 4 0
copyright ? f uture technology devices international limited 36 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 appendix a C references document references tn_100 usb vendor id / product id guidelines an_352 ft51a installation guide an_345 ft51a keyboard sample an_346 ft51a mouse sample an _ 347 ft51a test and measurement sample a n_ 348 ft51a ft800 sensors sample an _ 349 ft51a ft800 spaced invaders sample an _ 354 ft51a standalone demo application an_289 ft51a programming gui de acronyms and abbreviations terms description adc analog to digital converte r cpu central processing unit fpga field programmable gate array lqfp low profile quad flat package mcu micro controller unit pld programmable logic device qfn quad flat no - leads rohs restriction of hazardous substances directive spi serial periphe ral interface uart universal asynchronous receiver/transmitter usb universal serial bus
copyright ? f uture technology devices international limited 37 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 appendix b - list of figures and tables list of figures figure 2 - 1 - 28 pin ssop package ................................ ................................ ................................ .......... 5 figure 2 - 2 - 32 pin wqfn package ................................ ................................ ................................ ......... 6 figure 2 - 3 - 44 pin lqfp package ................................ ................................ ................................ ........... 7 figure 2 - 4 - 48 pin wqfn package ................................ ................................ ................................ ......... 8 figure 3 - 1 C ft51a block diagram ................................ ................................ ................................ ........ 11 figure 3 - 2 C spi master ................................ ................................ ................................ ........................ 15 figure 5 - 1 bus powered config uration ................................ ................................ ................................ .. 26 figure 6 - 1 application example showing usb upstream and downstream connection(48pin package) .... 27 figure 6 - 2 application example showing usb upstream and downstream connection (44pin package) ... 28 figure 6 - 3 application example showing usb upstream connection (32pin package) ............................. 28 figure 6 - 4 application example showing usb upstream connection (28pin package) ............................. 29 figure 7 - 1 48 pin wqfn package marking ................................ ................................ ............................. 30 figure 7 - 2 48 pin wqfn package dimensions ................................ ................................ ....................... 30 figure 7 - 3 44 pin lqfp package marking ................................ ................................ .............................. 31 figure 7 - 4 44 p in lqfp package dimensions ................................ ................................ ......................... 31 figure 7 - 5 32 pin wqfn package marking ................................ ................................ ............................. 32 figure 7 - 6 32 pin wqfn package dimensions ................................ ................................ ....................... 32 figure 7 - 7 28 pin ssop package marking ................................ ................................ .............................. 33 figure 7 - 8 28 pin ssop package dimensions ................................ ................................ ........................ 33 figure 7 - 9 ft51a solder reflow profile ................................ ................................ ................................ . 34 list of tables table 1 - 1 C part numbers ................................ ................................ ................................ ....................... 2 table 2 - 1 C power and ground ................................ ................................ ................................ ............... 9 table 2 - 2 C common functi on pins ................................ ................................ ................................ ....... 10 table 3 - 1 C 8051 ports ................................ ................................ ................................ ......................... 12 table 3 - 2 C peripheral pin requirements ................................ ................................ ............................... 14 table 3 - 3 C aio modes ................................ ................................ ................................ ......................... 16 table 4 - 1 C absolute maximum ratings ................................ ................................ ................................ 18 table 4 - 2 C operating voltage and current ................................ ................................ ........................... 19 table 4 - 3 C io characteristics vccio = +3v3 ................................ ................................ ....................... 20 table 4 - 4 C io characteristics vccio = +2v5 ................................ ................................ ....................... 21 table 4 - 5 C io characteristics vccio = +1v8 ................................ ................................ ....................... 22 table 4 - 6 C usb dp/dm pin characteristics ................................ ................................ ........................... 23 table 4 - 7 C mtp memory characteristics ................................ ................................ ............................... 23 table 4 - 8 C internal clock characteristics ................................ ................................ ............................. 23
copyright ? f uture technology devices international limited 38 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 table 4 - 9 C digital io ac characteristics ................................ ................................ .............................. 24 table 4 - 10 C adc characteristics ................................ ................................ ................................ .......... 25 table 7 - 1 C reflow profile parameters ................................ ................................ ................................ .. 34 table 0 - 1 C io registers ................................ ................................ ................................ ....................... 42
copyright ? f uture technology devices international limited 39 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 appendix c C list of io registers user should refer to the ft51 a programmers guide for more detail. register addr ess register name description (0x0) device _control _register device control re gister (0x1) system_ clock_ divider system clock divi der (0x2) top_ usb_ control usb top - level control register (0x3) peripheral_int0 peripheral interrupt status 0 (0x4) peripheral_ien0 peripheral inte rrupt enable 0 (0x5) peripheral_int1 peripheral interrupt status 1 (0x6) peripheral_i en1 peripheral interrupt enable 1 (0x9) pin_config miscellaneous pin configuration (0xa) to (0x19) digita l_control_aio_0 to digital_control_ aio 15 aio pins 0 to 15 digital control (0x1a) to (0x29) digital_control_ dio 0 to digital_control_ dio 15 dio pins 0 to 15 digital control (0x2a) aio_differential_enable aio differential pin enable (0x2b) mtp_ c ontrol mtp memory control (0x2c) mtp_prog_addr_l mtp prog ram addr ess l ower byte (0x2d) mtp_prog_addr_u mtp prog ram addr ess upper byte (0x2e) mtp_prog_data mtp prog ram data (0x3 4 ) pin_package_config device package informa tion (0x36) crc_control crc control of mtp memory (0x37) crc_result_l crc result lower byte (0x38) crc_result_u crc result upper byte (0x39) security_level device security status register ( 0x40) iomux_control io mux control register (0x41) iomux_o utput _p in _sel select output pin number register (0x42) iomux_o utput _s ig _se l select output signal register (0x43) iomux_i n p ut _s ig _sel select input signal register (0x44) iomux_i n p ut _p in _se l select input pin number register (0x48) spi_slave_control spi_slave control register (0x4a) spi_slave_tx_data spi slave transmit data (0x4b) spi_slave_rx_data spi slave receive data (0x4c) spi_ slave_ ien spi slave interrupt enable (0x4d) spi_slave_ int spi slave interrupt status (0x4e) spi_slave_setup spi slave setup (0x50) spi_master_control spi_master control register (0x51) spi_master_data_tx spi master transmit data (0x52) spi_master_data_rx spi master receive data (0x53) spi_master_ ien spi master interrupt enable (0x54) spi_master_ int spi master interrupt status (0x55) spi_master_setup spi master setup (0x56) spi_master_clk_div spi master cl ock divider (0x57) spi_master_data_delay spi master data delay (0x58) spi_master_ss_setup spi master slave select setup (0x59) spi_master_transfer_size_l spi master transfer size l ower byte (0x5a) spi_master_transfer_size_ u spi master transfer size upper byte (0x5b) spi_master_transfer_pending spi master transfer pending (0x60) uart_control uart control register (0x61) uart_ dma_ ctrl uart dma control (0 x62) uart_ rx_ data uart receive data (0x63) uart_ tx_ data uart transmit data (0x64) uart_tx_ ien uart tx interrupt enable
copyright ? f uture technology devices international limited 40 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 register addr ess register name description (0x65) uart_tx_ int uart tx interrupt status (0x66) uart_rx_ ien uart r x interrupt enable (0x67) uart_rx_ int uart rx interrupt status (0x68) uart_line_ctrl uart line control (0x69) uart_baud_0 uart baud rate byte 0 (0x6a) uart_baud_1 uart baud rate byte 1 (0x6b) uart_baud_2 uart baud rate byte 2 (0x6c) uart_flow_ctrl uart flow control (0x6d) uart_flow_stat uart flow control status (0x70) timer_control timer top co ntrol (0x71) to (0x74) timer_control_1 to timer_control_4 timer control register 1 to 4 (0x75) timer_int timer interrupt status (0x76) timer_select timer select register (0x77) timer_wdg watchdog start value (0x 78) timer_write_ls timer start value 7:0 (0x79) timer_write_ms timer start value 15:8 (0x7a) timer_presc_ls timer prescaler value 7:0 (0x7b) timer_presc_ms timer prescaler value 15:8 (0x7c) timer_read_ls timer curre nt value 7:0 (0x7d) timer_read_ms timer current value 15:8 (0x80) pwm_control pwm control register (0x81) pwm_ctrl pwm control (0x82) pwm_prescaler pwm prescaler comparator value (0x83) pwm_cnt16_lsb pwm counter16 comparator lsb value (0x8 4) pwm_cnt16_msb pwm counter16 comparator msb value (0x85) to (0x94) pwm_cmp16_0_lsb to pwm_cmp16_7_msb pwm comparator 0 lsb value to pwm comparator 7 msb value (0x95) to (0x9c) pwm_out_toggle_en_0 to pwm_out_toggl e_en_7 pwm out toggle enable register 0 to 7 (0x9d) pwm_out_clr_en pwm out clear enable (0x9e) pwm_ctrl_bl_cmp8 pwm control cmp8 value (0x9f) pwm_init pwm init ialization register (0xa0) fifo _control fifo control register (0xa1) fifo_ctrl_ status fifo control status (0xa2) fifo_rx_data fifo receive data (0xa3) fifo_tx_data fifo transmit data (0xa4) fifo_interrupt_ena fifo interrupt enable (0xa5) fifo_interrupt fifo interrupt (0xb0) dma _control _1 dma control register (0xb1) dma_enable _1 io dma enable register (0xb2) dma_irq_ena _1 dma io interrupt enable & control register (0xb3) dma_irq _1 dma io interrupt register (0xb4) dma_src_mem_addr_l _1 dma io source mem addr register (lower bits) ( 0xb5) dma_src_mem_addr_u _1 dma io source mem addr register (upper bits) (0xb6) dma_dest_mem_addr_l _1 dma io destination mem addr register (lower bits) (0xb7) dma_dest_mem_addr_u _1 dma io destination mem addr register (upper bits)
copyright ? f uture technology devices international limited 41 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 register addr ess register name description (0xb8) dma_io_add r_l _1 dma io addr register (lower bits) (0xb9) dma_io_addr_u _1 io dma io addr register (upper bits) (0xba) dma_trans_cnt_l _1 io dma transfer byte count register (lower bits) (0xbb) dma_trans_cnt_u _1 io dma transfer byte count register (upper bit s) (0xbc) dma_curr_cnt_l _1 io dma current byte count register (lower bits) (0xbd) dma_curr_cnt_u _1 io dma current byte count register (upper bits) (0xbe) dma_fifo_data _1 io dma fifo data (0xbf) dma_afull_trigger _1 io dma almost full flag trigge r value (0xc0) dma _control _2 dma control register (0xc1) dma_enable _2 io dma enable register (0xc2) dma_irq_ena _2 dma io interrupt enable & control register (0xc3) dma_irq _2 dma io interrupt register (0xc4) dma_src_mem_ addr_l_2 dma io source mem addr register (lower bits) (0xc5) dma_src_mem_addr_u_2 dma io source mem addr register (upper bits) (0xc6) dma_dest_mem_addr_l_2 dma io destination mem addr register (lower bits) (0xc7) dma_dest_mem_addr_u_2 dma io destination mem addr register (upper bits) (0xc8) dma_io_addr_l_2 dma io addr register (lower bits) (0xc9) dma_io_addr_u_2 io dma io addr register (upper bits) (0xca) dma_trans_cnt_l_2 io dma transfer byte count register (lower bits) (0xcb) dma_trans_cnt_u_2 io d ma transfer byte count register (upper bits) (0xcc) dma_curr_cnt_l_2 io dma current byte count register (lower bits) (0xcd) dma_curr_cnt_u_2 io dma current byte count register (upper bits) (0xce) dma_fifo_data_2 io dma fifo data (0xcf) dma_afull_trigge r_2 io dma almost full flag trigger value (0xd0) dma _ control _3 dma control register (0xd1) dma_enable_3 io dma enable register (0xd2) dma_irq_ena_3 dma io interrupt enable & control register (0xd3) dma_irq_3 dma io interrupt r egister (0xd4) dma_src_mem_addr_l_3 dma io source mem addr register (lower bits) (0xd5) dma_src_mem_addr_u_3 dma io source mem addr register (upper bits) (0xd6) dma_dest_mem_addr_l_3 dma io destination mem addr register (lower bits) (0xd7) dma_dest_mem _addr_u_3 dma io destination mem addr register (upper bits) (0xd8) dma_io_addr_l_3 dma io addr register (lower bits) (0xd9) dma_io_addr_u_3 io dma io addr register (upper bits) (0xda) dma_trans_cnt_l_3 io dma transfer byte count register (lower bits) ( 0xdb) dma_trans_cnt_u_3 io dma transfer byte count register (upper bits) (0xdc) dma_curr_cnt_l_3 io dma current byte count register (lower bits)
copyright ? f uture technology devices international limited 42 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 register addr ess register name description (0xdd) dma_curr_cnt_u_3 io dma current byte count register (upper bits) (0xde) dma_fifo_data_3 io dma fifo d ata (0xdf) dma_afull_trigger_3 io dma almost full flag trigger value (0xe0) dma _control _4 dma control register (0xe1) dma_enable_4 io dma enable register (0xe2) dma_irq_ena_4 dma io interrupt enable & control register (0xe3) d ma_irq_4 dma io interrupt register (0xe4) dma_src_mem_addr_l_4 dma io source mem addr register (lower bits) (0xe5) dma_src_mem_addr_u_4 dma io source mem addr register (upper bits) (0xe6) dma_dest_mem_addr_l_4 dma io destination mem addr register (lower bits) (0xe7) dma_dest_mem_addr_u_4 dma io destination mem addr register (upper bits) (0xe8) dma_io_addr_l_4 dma io addr register (lower bits) (0xe9) dma_io_addr_u_4 io dma io addr register (upper bits) (0xea) dma_trans_cnt_l_4 io dma transfer byte cou nt register (lower bits) (0xeb) dma_trans_cnt_u_4 io dma transfer byte count register (upper bits) (0xec) dma_curr_cnt_l_4 io dma current byte count register (lower bits) (0xed) dma_curr_cnt_u_4 io dma current byte count register (upper bits) (0xee) dm a_fifo_data_4 io dma fifo data (0xef) dma_afull_trigger_4 io dma almost full flag trigger value (0x100) aio _control aio control register (0x101) aio _global_ ctrl aio global control register (0x102) to ( 0x105) aio _mode_0 to aio _mode_3 mode select for aio pins 0 - 15 . (0x108) aio _sample_0 initiates a sample of aio 0 to 7 (0x109) aio _sample_ 1 initiates a sample of aio 8 to 15 (0x10a) (0x10b) aio _glob al _ port_select _0_7 selects the aio s to be included in a global function (0x10c) aio _ global_port_select _8_15 selects the aio s to be included in a global function (0x13e) to (0x15d) aio _0_adc_data_l t o aio _15_adc_ data_u sampled adc data for aio0 to aio15 (0x16e) aio _in t errupt _0_7 interrupt status for ports 0 - 7 (0x16f) aio _i nt_enable _0 _ 7 interrupt enable for ports 0 - 7 (0x170) aio _int errupt _ 8_15 interrupt status for ports 8 - 15 (0x171) aio _i nt_enable _8_15 interrupt enable for ports 8 - 15 (0x176) aio _sh_counter_l sample&hold settling time counter, lower 8 bits (0 x177) aio _sh_counter_u sample&hold settling time, upper 2 bits (0x17a) aio _cl ock _div ider clock divider table 0 - 1 C io registers
copyright ? f uture technology devices international limited 43 ft51a advanced mcu with 8051 compatible core ic datasheet version 1.5 d oc ument n o.: ft _000877 c learance n o.: ft di#420 appendix d C revision history documen t title : ft51a advanced mcu with 8051 compatible core ic datasheet document reference no. : ft_000877 clearance no. : ftdi# 420 product page : http://www.ftdichip.com/products/ics/ft51 a .html document feedback : ds_ft51a revision changes date version 1.0 initial release 2014 - 03 - 17 version 1.1 second release 2014 - 11 - 05 version 1.2 update d pin out diagram 2014 - 12 - 12 vers ion 1.3 updated branding from ft51 to ft51a 2015 - 03 - 23 version 1.4 removed dac references 2015 - 11 - 18 version 1.5 updated figure 7.8 28 pin ssop package dimensions 2016 - 0 4 - 0 7

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