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C 28 v, ?200 ma, low noise, linear regulator data sheet adp7182 rev. i document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed b y analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 C 2016 analog devices, in c. all rights reserved. technical support www.analog.com features low n oise: 1 8 v rms p ower supply rejection ratio (p srr ): 66 db at 10 k hz at v out = ? 3 v positive or negative enable logic stable with small 2.2 f ceramic output capacitor input voltage range: ? 2.7 v to ? 28 v maximum output current: ? 200 ma low dropout voltage: ? 185 mv at ? 2 00 ma load initial accuracy: 1% accuracy over line, load, and temperature +2 % maximum / ? 3 % minimum low quiescent current , i gnd = ? 6 5 0 a with ? 2 00 ma load low shutdown current: ? 2 a adjustable output from ? 1 .22 v to ? v in + v do c urrent - limit and thermal overload protection 6 - and 8 - lead lfcsp and 5 - l ead tsot supported by adisimpower tool applications regulation to noise sensitive applications analog - to - digital converter ( adc ) and digital - to - analog converter ( dac ) circuits, p recision amplifiers communications and i nfrastructure medical and h ealthcare industrial and i nstrumentation t ypical application c ircuit s gnd en nc vin vout adp7182 on on ?2v off 0v 2v v in = ?8v v out = ?5v c out 2.2f c in 2.2f 10703-001 figure 1. adp7182 with fixed output voltage, v out = ? 5 v 13k? 40.2k? gnd en adj vin vout adp7182 on on ?2v off 0v 2v v in = ?8v v out = ?5v c out 2.2f c in 2.2f 10703-002 figure 2. adp7182 with adjustable output voltage, v out = 5 v general description the adp7182 is a cmos, low dropout (ldo) linear regulator that operate s from ? 2.7 v to ? 28 v and provide s up to ? 200 ma of output current. th is h igh input voltage ldo is ideal for regulation of high performance analog and mixed signal circuits operating from ? 27 v down t o ? 1.2 v rails. using an advanced proprietary architecture, it provide s high power supply rejection and low noise, and achieve s ex cellent line and load transi ent response with a small 2.2 f ceramic output capacitor. the adp7182 is available in fixed output voltage and an adjustable version that allows the output voltage to range from ? 1.22 v to ? v in + v do via an external feedback divider. the following fixed output volt ages are available from stock: ? 5 v (3 mm 3 mm lfcsp), ? 1.8 v, ? 2.5 v, ? 3 v, ? 5 v (tsot), ? 1.2 v, ? 1.5 v, ?2.5 v, ?5 v (2 mm 2 mm lfcsp). additional v oltages are available by special order. the adp7182 regulator output noise is 1 8 v rms independent of the output voltage. the e nable logic is capable of interfacing with positive or negative logic levels for maximum flexibility. the adp7182 is available in 5 - lead tsot , 6 - and 8 - lead lfcsp packages for a small, low profile footprint .
adp7182 data sheet rev. i | page 2 of 31 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuits ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 input and output capacitance, recommended specifications ......................................................................................................... 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 21 adjust able mode operation ..................................................... 21 applications information .............................................................. 22 adisimpower design tool ....................................................... 22 capa citor selection .................................................................... 22 enable pin operation ................................................................ 23 soft start ...................................................................................... 23 noise reduction of the adjustable adp7182 ............................ 24 current - limit and thermal overload protection ................. 24 thermal considerations ............................................................ 25 pcb layout considerations ...................................................... 28 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 31 revision history 12/2016 rev. h to rev. i changes to figure 77 ................................ ................................ ................. 21 moved theory of operation/ enable pin operation section .... 23 changes to enable pin operation section .................................. 23 1 1 /2016 rev. g to rev. h change to thermal considerations section ............................... 25 updated outline dimensions ....................................................... 30 changes to ordering guide .......................................................... 31 6/2016 rev. f to rev. g changes to figure 101 .................................................................... 28 3 / 20 16 rev. e to re v . f changes to figure 62 ...................................................................... 17 9/ 20 14 rev. d to rev. e changes to features and general description sections .............. 1 changes to figure 101 .................................................................... 28 added table 11 ............................................................................... 29 changes to ordering guide .......................................................... 31 7 / 20 14 rev. c to rev. d added 6 - lead lfcsp (throughout) ............................................. 1 added 6 - lead lfcsp thermal resistance parameters ............... 5 added figure 7, figure 8, and table 7 ........................................... 8 added 6 - lead lfcsp ja values to table 8 ; a dded 6 - lead lfcsp jb value to table 10 ......................................................... 25 added figure 92 , figure 93 , and figure 9 4 ................................. 26 changes to thermal characterization parameter, jb section and added figure 99 ...................................................................... 2 7 added figure 101 ........................................................................... 2 8 added f igure 10 4 , outline dimensions ...................................... 29 changes to ordering guid e .......................................................... 30 9 / 20 13 rev. b to rev. c changes to ordering guide .......................................................... 28 6/ 20 13 rev. a to rev. b changes to general description ..................................................... 1 updated outline dimensions ....................................................... 27 changes to ordering guide .......................................................... 28 5/ 20 13 rev. 0 to rev. a change d start - up time v out = ?5 v from 4 50 s to 5 50 s ...... 3 changes to figure 9 and figure 12 .................................................. 8 changes to figure 13 ......................................................................... 9 changes to figure 19 and figure 22 ............................................ 1 0 changes to figure 28 ...................................................................... 11 changes to figure 31 and figure 34 ............................................ 1 2 changes to figure 37 and figure 40 ............................................ 1 3 changes to figure 43 ...................................................................... 14 added adisimpower design tool section ................................. 2 1 4 / 20 1 3 revision 0: initial version
data sheet adp7182 rev. i | page 3 of 31 specifications v in = (v out ? 0.5 v) or ? 2.7 v (whichever is greater), en = v in , i out = ? 10 ma, c in = c out = 2.2 f, t j = ? 40 c to + 125c for minimum/maximum specifications, t a = 25c for typical specifications, unless otherwise noted . table 1 . parameter symbol test conditions /comments min typ max unit input voltage range v in ? 2.7 ? 28 v operating supply current i gnd i out = 0 a ? 33 ? 53 a i out = ? 10 ma ? 100 ? 150 a i out = ? 200 ma ? 6 5 0 ? 850 a shutdown current i gnd - sd en = gnd ? 2 a en = gnd , v in = ? 2.7 v to ? 28 v ? 8 a output voltage accuracy fixed output voltage accuracy v out i out = ? 10 ma , t a = 25c C 1 +1 % ? 1 ma < i out < ? 200 ma, v in = (v out ? 0.5 v) to ? 28 v C 3 + 2 % adjustable output voltage accuracy v adj i out = ? 10 ma ? 1.208 ? 1.22 ? 1.232 v ? 1 ma < i out < ? 200 ma, v in = (v out ? 0.5 v ) to ? 28 v ? 1.184 ? 1.2 44 v line regulation ? v out /?v in v in = (v out ? 0.5 v ) to ? 28 v ? 0.0 1 +0.0 1 %/v load regulation 1 ? v out /?i out i out = ? 1 ma to ? 200 ma 0.001 0.0 06 %/ma adj input bias current adj i- bias ? 1 ma < i out < ? 200 ma, v in = (v out ? 0.5 v) to ? 28 v 10 na dropout voltage 2 v do i out = ? 10 ma ? 25 ? 70 mv i out = ? 50 ma ? 46 ? 90 mv i out = ? 200 ma ? 1 85 ? 360 mv start - up time 3 t start - up v out = ? 5 v 5 50 s v out = ?2.8 v 375 s current - limit threshold 4 i limit ? 230 ? 3 5 0 ? 500 ma thermal shutdown thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd - hys 15 c en threshold positive rise v en - pos - rise v out = off to on (positive) 1.2 v negative rise v en - neg - rise v out = off to on (negative) ? 2.0 v positive fall v en - pos - fal l v out = on to off (positive) 0.3 v negative fall v en - neg - fal l v out = on to off (negative) ? 0.55 v input voltage lockout start threshold v start ? 2.695 ? 2.49 v shutdown threshold v shutdown ? 2.34 ? 2.1 v hysteresis 150 mv output noise out noise 10 hz to 100 khz, v out = ?1.5 v, v out = ? 3 v, and v out = ? 5 v 18 v rms 10 hz to 100 khz, v out = ?5 v, adjustable mode, c nr = open, r nr = open, r fb1 = 147 k? , r fb2 = 13 k? 150 v rms 10 hz to 100 khz, v out = ?5 v, adjustable mode, c nr = 100 nf, r nr = 13 k?, r fb1 = 147 k?, r fb2 = 13 k? 33 v rms
adp7182 data sheet rev. i | page 4 of 31 parameter symbol test conditions /comments min typ max unit power supply rejection ratio psrr 1 mhz, v in = ?4.3 v, v out = ?3 v 45 db 1 mhz, v in = ?6 v, v out = ?5 v 32 db 100 khz, v in = ?4.3 v, v out = ?3 v 45 db 100 khz, v in = ?6 v, v out = ?5 v 45 db 10 khz, v in = ?4.3 v, v out = ?3 v 66 db 10 khz, v in = ?6 v, v out = ?5 v 66 db 1 mhz, v in = ?16 v, v out = ?15 v, adjustable mode, c nr = 100 nf, r nr = 13 k ? , r fb1 = 13 k ? , r fb2 = 147 k ? 45 db 100 khz, v in = ?16 v, v out = ?15 v, adjustable mode, c nr = 100 nf, r nr = 13 k ? , r fb1 = 13 k ? , r fb2 = 147 k ? 45 db 10 khz, v in = ?16 v, v out = ?15 v, adjustable mode, c nr = 100 nf, r nr = 13 k ? , r fb1 = 13 k ? , r fb2 = 147 k ? 66 db 1 based on an endpoint calculation using ?1 ma and ?200 ma loads. see figure 10 for the typical load re gulation performance for loads less than 1 ma. 2 dropout voltage is defined as the input - to - output voltage differential when the input voltage is set to the nominal out put voltage. this applies only for output voltages below ?3 v. 3 start - up time is defined as the time between the rising edge of en to vout being at 90 % of the nominal value. 4 current - limit threshold is defined as the current at which the output voltage d rops to 90% of the specified typical value. for example, the current limit for a ? 5 v output voltage is defined as the current that causes the output voltage to drop to 90% of ? 5 v, or ? 4.5 v. input and output capacitance , recommended specifications table 2 . parameter symbol test conditions/comments min typ max unit input and output capacitance minimum capacitance 1 c min t a = ?40c to +125c 1.5 2.2 f capacitor effective series resistance (esr) r esr t a = ?40c to +125c 0.001 0.2 ? 1 the minimum input and output capacitance must be greater than 1.5 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r and x 5r type capacitors are recommend ed; y5v and z5u capacitors are not recommended for use with any ldo.
data sheet adp7182 rev. i | page 5 of 31 absolute maximum rat ings table 3 . parameter rating vin to gnd + 0.3 v to ? 30 v vout to gnd 0.3 v to vin en to gnd 5 v to v in en to vin +30 v to ? 0.3 v adj to gnd + 0.3 v to v out storage temperature range ? 65c to +150c operating junction temperature range ? 40c to +125c operating ambient temperature range ? 40c to +85c soldering conditions jedec j - std -020 stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adp7182 can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that junction temperature (t j ) is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. in applications with moderate power dissipation and low printed circuit board ( pcb ) thermal resistance, the maximum ambient temperature can exceed the maximum limit as lo ng as the junction temperature is within specification limits. the t j of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), a nd the junction - to - ambient thermal resistance of the package ( ja ). maximum t j is calculated from the t a and p d using the formula t j = t a + ( p d ja ) junction - to - ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4 - layer board. the junction - to - ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja can vary, depending on pcb material, layout, and environmental conditions. the speci fied values of ja are based on a 4 - layer, 4 in. 3 in. circuit board. see jesd51 - 7 and jesd 51 - 9 for detailed information on the board construction. for additional information, see the an - 617 application note , microcsp ? wafer level chip scale package . jb is the junction - to - board thermal characterization parameter with units of c/w. jb of the package is based on modeling and calculation using a 4 - layer board. the jesd51 - 12, guidelines for rep orting and using electronic package thermal information , states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than a single path as in therma l resistance, jb . therefore, jb thermal paths include convection from the top of the package as well as radiation from the package, factors that make jb more useful in real - world applications. maximum junction temperature is calculated from the board te mperature (tb) and power dissipation using the formula t j = t b + ( p d jb ) see jesd51 - 8 and jesd51 - 12 for more detailed information about jb . thermal resistance ja , jc , and jb are specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance package type ja jc jb unit 8 - lead lfcsp 50.2 31.7 18.2 c/w 6 - lead lfcsp 68.9 42.29 44.1 c/w 5 - lead tsot 170 not applicable 43 c/w esd caution
adp7182 data sheet rev. i | page 6 of 31 pin configurations a nd function descript ions adp7182 top view (not to scale) 1 gnd 2 vin 3 en 5 vout 4 nc notes 1. nc = no connect. do not connect t o this pin. 10703-003 figure 3. 5- lead tsot pin configuration, fixed output voltage adp7182 top view (not to scale) 1 gnd 2 vin 3 en 5 vout 4 adj 10703-004 figure 4. 5- lead tsot pin configuration, adjustable output voltage table 5 . 5 - lead tsot pin function descriptions tsot pin no. fixed output voltage adjustable output voltage mnemonic description 1 1 gnd ground. 2 2 vin regulator input supply. bypass vin to gnd with a 2.2 f or greater capacitor. 3 3 en drive en 2 v above or below ground to enable the regulator , or drive en to ground to turn off the regulator. for automatic startup, connect en to vin. 4 not applicable nc no connect. do not connect to this pin. not applicable 4 adj adjust able input. an external resistor divider sets the output voltage. 5 5 vout regulated output voltage. bypass vout to gnd with a 2.2 f or greater capacitor.
data sheet adp7182 rev. i | page 7 of 31 10703-005 3 nc 4 en 1 vout 2 vout 6 gnd 5 nc 8 vin 7 vin adp7182 top view (not to scale) exposed pad notes 1. nc = no connect. do not connect t o this pin. 2. the exposed pad on the bottom of the lfcsp package enhances thermal performance and is electrically connected to vin inside the package. the exposed pad must be connected to the vin plane on the board for proper operation. because this is a negative voltage regulator, vin is the most negative potential in the circuit. figure 5. 8 - lead lfcsp pin configuration, fixed output voltage 10703-006 3 adj 4 en 1 vout 2 vout 6 gnd 5 nc 8 vin 7 vin adp7182 top view (not to scale) exposed pad notes 1. nc = no connect. do not connect t o this pin. 2. the exposed pad on the bottom of the lfcsp package enhances thermal performance and is electrically connected to vin inside the package. the exposed pad must be connected to the vin plane on the board for proper operation. because this is a negative voltage regulator, vin is the most negative potential in the circuit. figure 6. 8 - lead lfcsp pin configuration, adjustable output voltage table 6 . 8 - lead lfcsp pin function descriptions lfcsp pin no. fixed output voltage adjustable output voltage mnemonic description 1, 2 1, 2 vout regulated output voltage. bypass vout to gnd with a 2.2 f or greater capacitor. not applicable 3 adj adjust able input. an external resistor divider sets the output voltage. 3 not applicable nc no connect. do not connect to this pin. 4 4 en drive en 2 v above or below ground to enable the regulator, or drive en to ground to turn off the regulator. for automatic startup, connect en to vin. 5 5 nc no connect. do not connect to this pin. 6 6 gnd ground. 7, 8 7, 8 vin regulator input supply. bypass vin to gnd with a 2.2 f or greater capacitor. 9 9 epad exposed pad. the exposed pad on the bottom of the lfcsp package enhances thermal performance and is electrically connected to vin inside the package. the exposed pad must be connected to the vin plane on the board for proper operation. because this is a negative voltage regulator, vin is the most negative potential in the circuit.
adp7182 data sheet rev. i | page 8 of 31 3 en 1 vout 2 nc 4 nc 6 vin 5 gnd 10703-107 adp7182 t op view (not to scale) exposed pad notes 1. nc = no connect. do not connect t o this pin. 2. the exposed pad on the bottom of the lfcsp package enhances thermal performance and is electrically connected to vin inside the package. the exposed pad must be connected to the vin plane on the board for proper operation. because this is a negative voltage regulator, vin is the most negative potential in the circuit. 3 en 1 vout 2 adj 4 nc 6 vin 5 gnd 10703-106 adp7182 t op view (not to scale) exposed pad notes 1. nc = no connect. do not connect t o this pin. 2. the exposed pad on the bottom of the lfcsp package enhances thermal performance and is electrically connected to vin inside the package. the exposed pad must be connected to the vin plane on the board for proper operation. because this is a negative voltage regulator, vin is the most negative potential in the circuit. figure 7. 6 - lead lfcsp pin configuration, fixed output voltage figure 8. 6 - lead lfcsp pin configuration, adjustable output voltage table 7 . 6 - lead lfcsp pin function descriptions lfcsp pin no. mnemonic description fixed output voltage adjustable output voltage 1 1 vout regulated output voltage. bypass vout to gnd with a 2.2 f or greater capacitor. not applicable 2 adj adjust able input. an external resistor divider sets the output voltage. 3 3 en drive en 2 v above or below ground to enable the regulator, or drive en to ground to turn off the regulator. for automatic startup, connect en to vin. 2, 4 4 nc no connect. do not connect to this pin. 5 5 gnd ground. 6 6 vin regulator input supply. bypass vin to gnd with a 2.2 f or greater capacitor. 7 7 epad exposed pad. the exposed pad on the bottom of the lfcsp package enhances thermal performance and is electrically connected to vin inside the package. the exposed pad must be connected to the vin plane on the board for proper operation. because this is a negative voltage regulator, vin is the most negative potential in the circuit.
data sheet adp7182 rev. i | page 9 of 31 typical performance characteristics v in = ? 3.5 v, v out = ? 3 v , i out = ? 10 ma , c in = c out = 2.2 f , t a = 25c, unless otherwise noted . ?2.970 ?3.020 ?3.015 ?3.010 ?3.005 ?3.000 ?2.995 ?2.990 ?2.985 ?2.980 ?2.975 ?40 ?5 25 85 125 v out (v) junction temperature (c) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-007 figure 9. output voltage (v out ) vs. junction temperature (t j ) ?2.95 ?3.05 ?3.04 ?3.03 ?3.02 ?3.01 ?3.00 ?2.99 ?2.98 ?2.97 ?2.96 ?200 ?150 ?50 ?100 0 50 v out (v) i load (ma) 10703-008 figure 10 . output voltage (v out ) vs. load current (i load ) ?2.90 ?2.95 ?3.00 ?3.05 ?3.10 ?30 ?20 ?10 ?25 ?15 ?5 0 v out (v) v in (v) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-009 figure 11 . output voltage (v out ) vs. input voltage (v in ) 0 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 ?40 ?5 25 85 125 ground current (a) junction temperature (c) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-010 figure 12 . ground current vs. junction temperature (t j ) ?250 ?200 ?150 ?50 ?100 0 50 ground current (a) i load (ma) 0 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 10703-0 1 1 figure 13 . ground current vs. load current (i load ) 0 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 ?30 ?20 ?10 ?25 ?15 ?5 0 ground current (a) v in (v) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-012 figure 14 . ground current vs. input voltage (v in )
adp7182 data sheet rev. i | page 10 of 31 0 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 ?50 ?25 0 25 50 75 100 125 shutdown current (a) temperature (c) v in = ?2.7v v in = ?3.0v v in = ?4.0v v in = ?5.0v v in = ?8.0v v in = ?28.0v 10703-013 figure 15. shutdown current vs. temperature at various input voltages 0 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 1 10 100 1000 dropout voltage (mv) i load (ma) 10703-014 figure 16. dropout voltage vs. load current (i load ) ? 2.55 ?3.05 ?3.00 ?2.95 ?2.90 ?2.85 ?2.80 ?2.75 ?2.70 ?2.65 ?2.60 ?3.4 ?3.2 ?3.0 ?2.8 v out (v) v in (v) i load = ?5ma i load = ?10ma i load = ?25ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-015 figure 17. output voltage (v out ) vs. input voltage (v in ) in dropout 0 ?1200 ?1000 ?800 ?600 ?400 ?200 ?3.4 ?3.2 ?3.0 ?2.8 ground current (a) v in (v) i load = ?5ma i load = ?10ma i load = ?25ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-016 figure 18. ground current vs. input voltage (v in ) in dropout ? 4.90 ?5.10 ?5.08 ?5.06 ?5.04 ?5.02 ?5.00 ?4.98 ?4.96 ?4.94 ?4.92 ?40?52585125 v out (v) junction temperature (c) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-017 figure 19. output voltage (v out ) vs. junction temperature (t j ), v out = ?5 v ? 5.000 ?5.005 ?5.010 ?5.015 ?5.020 ?5.025 ?5.030 ?5.035 ?5.040 ?5.045 ?5.050 ?200 ?150 ?100 ?50 0 v out (v) i load (ma) 10703-018 figure 20. output voltage (v out ) vs. load current (i load ), v out = ?5 v
data sheet adp7182 rev. i | page 11 of 31 ?4.97 ?4.98 ?4.99 ?5.00 ?5.01 ?5.02 ?5.03 ?30 ?20 ?10 ?25 ?15 ?5 0 v out (v) v in (v) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-019 figure 21 . output voltage (v out ) vs. input voltage (v in ), v out = ?5 v ?40 ?5 25 85 125 junction temperature (c) 0 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 ground current (a) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-020 figure 22 . ground current vs. junction temperature (t j ), v out = 5 v 0 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 ?200 ?150 ?100 ?50 0 ground current (a) i load (ma) 10703-021 figure 23 . ground current vs. load current (i load ), v out = 5 v ?30 ?20 ?10 ?25 ?15 ?5 0 v in (v) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 0 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 ground current (a) 10703-022 figure 24 . ground current vs. input voltage (v in ), v out = ?5 v 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 1 10 100 1000 dropout voltage (mv) i load (ma) 10703-023 figure 25 . dropout v oltage vs . load current (i load ), v out = 5 v ?4.60 ?4.65 ?4.70 ?4.75 ?4.80 ?4.85 ?4.90 ?4.95 ?5.05 ?5.00 ?5.4 ?5.2 ?5.0 ?4.8 v out (v) v in (v) i load = ?5ma i load = ?10ma i load = ?25ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-024 figure 26 . output voltage (v out ) vs. input voltage (v in ) in dropout , v out = 5 v
adp7182 data sheet rev. i | page 12 of 31 0 ?200 ?400 ?600 ?800 ?1000 ?1200 ?1600 ?1400 ?5.4 ?5.2 ?5.0 ?4.8 ground current (a) v in (v) i load = ?5ma i load = ?10ma i load = ?25ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-025 figure 27 . ground current vs. input voltage (v in ) in dropout , v out = ?5 v ?1.770 ?1.775 ?1.780 ?1.785 ?1.790 ?1.795 ?1.800 ?1.805 ?1.810 ?40 ?5 25 85 125 v out (v) junction temperature (c) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-026 figure 28 . output voltage (v out ) vs. junction temperature (t j ), v out = 1.8 v ?1.790 ?1.795 ?1.800 ?1.805 ?1.810 ?200 ?150 ?100 ?50 0 v out (v) i load (ma) 10703-027 figure 29 . output voltage (v out ) vs. load current (i load ), v out = 1.8 v ?1.780 ?1.785 ?1.790 ?1.795 ?1.800 ?1.805 ?1.810 ?30 ?25 ?20 ?15 ?10 ?5 0 v out (v) v in (v) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-028 figure 30 . output voltage (v out ) vs. input voltage (v in ), v out = 1.8 v 0 ?100 ?200 ?300 ?400 ?500 ?600 ?700 ?40 ?5 25 85 125 ground current (a) junction temperature (c) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-029 figure 31 . ground current vs. junction temperature (t j ), v out = 1.8 v 0 ?100 ?300 ?500 ?200 ?400 ?600 ?700 ?200 ?150 ?100 ?50 0 ground current (a) i load (ma) 10703-030 figure 32 . ground current vs. load current (i load ), v out = 1.8 v
data sheet adp7182 rev. i | page 13 of 31 0 ?700 ?600 ?500 ?400 ?300 ?200 ?100 ?30 ?25 ?20 ?15 ?10 ?5 0 ground current (a) v in (v) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-031 figure 33 . ground current vs. input voltage (v in ), v out = ?1.8 v ?1.20 ?1.21 ?1.22 ?1.23 ?1.24 ?1.25 ?40 ?5 25 85 125 v out (v) junction temperature (c) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-032 figure 34 . output voltage (v out ) vs. junction temperature (t j ), v out = 1.22 v ?1.20 ?1.25 ?1.24 ?1.23 ?1.22 ?1.21 ?200 ?150 ?100 ?50 0 v out (v) i load (ma) 10703-033 figure 35 . output voltage (v out ) vs. load current (i load ), v out = 1.22 v ?1.20 ?1.22 ?1.21 ?1.23 ?1.24 ?1.25 ?30 ?25 ?20 ?15 ?10 ?5 0 v out (v) v in (v) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-034 figure 36 . output voltage (v out ) vs. input voltage (v in ), v out = 1.22 v 0 ?700 ?600 ?500 ?400 ?300 ?200 ?100 ?40 ?5 25 85 125 ground current (a) junction temperature (c) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-035 figure 37 . ground current vs. junction temperature (t j ), v out = 1.22 v 0 ?700 ?400 ?500 ?600 ?300 ?200 ?100 ?200 ?150 ?100 ?50 0 ground current (a) i load (ma) 10703-036 figure 38 . ground current vs. load current (i load ), v out = 1.22 v
adp7182 data sheet rev. i | page 14 of 31 0 ?700 ?600 ?500 ?400 ?300 ?200 ?100 ?30 ?25 ?20 ?15 ?10 ?5 0 ground current (a) v in (v) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-037 figure 39 . ground current vs. input voltage (v in ), v out = ?1.22 v ?14.80 ?15.30 ?15.25 ?15.20 ?15.15 ?15.10 ?15.05 ?15.00 ?14.90 ?14.95 ?14.85 ?40 ?5 25 85 125 v out (v) junction temperature (c) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-038 figure 40 . output voltage (v out ) vs. junction temperature (t j ), adjustable output voltage , v out = 15 v ?14.80 ?15.30 ?15.25 ?15.20 ?15.15 ?15.10 ?15.05 ?15.00 ?14.90 ?14.95 ?14.85 v out (v) i load (ma) ?200 ?150 ?100 ?50 0 10703-039 figure 41 . output voltage (v out ) vs. load current (i load ), adjustable output voltage , v out = 15 v ?14.80 ?15.30 ?15.25 ?15.20 ?15.15 ?15.10 ?15.05 ?15.00 ?14.90 ?14.95 ?14.85 ?30 ?25 ?20 ?15 v out (v) v in (v) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-040 figure 42 . output voltage (v out ) vs. input voltage (v in ), adjustable output voltage , v out = 15 v 0 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 ?40 ?5 25 85 125 ground current (a) junction temperature (c) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-041 figure 43 . ground current vs. junction temperature (t j ), adjustable output voltage , v out = 15 v ground current (a) i load (ma) ?200 ?150 ?100 ?50 0 0 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 10703-042 figure 44 . ground current v s. load current (i load ), adjustable output voltage , v out = 15 v
data sheet adp7182 rev. i | page 15 of 31 0 ?800 ?700 ?600 ?500 ?400 ?300 ?200 ?100 ?30 ?25 ?20 ?15 ground current (a) v in (v) i load = ?100a i load = ?1ma i load = ?10ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-043 figure 45. ground current vs. input voltage (v in ), adjustable output voltage, v out = ?15 v 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 1 10 100 1000 dropout voltage (mv) i load (ma) 10703-044 figure 46. dropout voltage vs. load current (i load ), adjustable output voltage, v out = ?15 v ? 14.60 ?14.65 ?14.70 ?14.75 ?14.80 ?14.85 ?14.90 ?14.95 ?15.00 ?15.05 ?15.10 ?15.0 ?14.5 ?14.6 ?14.7 ?14.8 ?14.9 v out (v) v in (v) i load = ?10ma i load = ?10ma i load = ?25ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-045 figure 47. output voltage (v out ) vs. input voltage (v in ) in dropout, adjustable output voltage, v out = ?15 v 0 ?1600 ?1400 ?1200 ?1000 ?800 ?600 ?400 ?200 ?15.0 ?14.0 ?14.2 ?14.4 ?14.6 ?14.8 ground current (a) v in (v) i load = ?5ma i load = ?10ma i load = ?25ma i load = ?50ma i load = ?100ma i load = ?200ma 10703-046 figure 48. ground current vs. input voltage (v in ) in dropout, v out = ?15 v 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i load = ?200ma i load = ?100ma i load = ?10ma i load = ?1ma 10703-047 figure 49. power supply rejection ratio (psrr) vs. frequency, v out = ?1.22 v vs. different load currents (i load ), v in = ?2.7 v 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i load = ?200ma i load = ?100ma i load = ?10ma i load = ?1ma 10703-048 figure 50. power supply rejection ratio (psrr) vs. frequency, v out = ?1.22 v vs. different load currents (i load ), v in = ?5.7 v
adp7182 data sheet rev. i | page 16 of 31 0 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 1.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 psrr (db) headroom voltage (v) frequency = 100hz frequency = 1khz frequency = 10khz frequency = 100khz frequency = 1mhz frequency = 10mhz 10703-049 figure 51. power supply rejection ratio (psrr) vs. headroom voltage, v out = ?1.22 v, load current (i load ) = ?200 ma 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i load = ?200ma i load = ?100ma i load = ?10ma i load = ?1ma 10703-050 figure 52. power supply rejection ratio (psrr) vs. frequency, v out = ?1.8 v vs. different load currents (i load ), v in = ?2.8 v 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i load = ?200ma i load = ?100ma i load = ?10ma i load = ?1ma 10703-051 figure 53. power supply rejection ratio (psrr) vs. frequency, v out = ?1.8 v vs. different load currents (i load ), v in = ?5.5 v 0 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 1.0 4.0 3.5 3.0 2.5 2.0 1.5 psrr (db) headroom voltage (v) frequency = 100hz frequency = 1khz frequency = 10khz frequency = 100khz frequency = 1mhz frequency = 10mhz 10703-052 figure 54. power supply rejection ratio (psrr) vs. headroom voltage, v out = ?1.8 v, load current (i load ) = ?200 ma 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i load = ?200ma i load = ?100ma i load = ?10ma i load = ?1ma 10703-053 figure 55. power supply rejection ratio (psrr) vs. frequency, v out = ?3 v vs. different load currents (i load ), v in = ?4.0 v 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i load = ?200ma i load = ?100ma i load = ?10ma i load = ?1ma 10703-054 figure 56. power supply rejection ratio (psrr) vs. frequency, v out = ?3 v vs. different load currents (i load ), v in = ?5.5 v
data sheet adp7182 rev. i | page 17 of 31 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 04.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 psrr (db) headroom voltage (v) frequency = 100hz frequency = 1khz frequency = 10khz frequency = 100khz frequency = 1mhz frequency = 10mhz 10703-055 figure 57. power supply rejection ratio (psrr) vs. headroom voltage, v out = ?3 v, load current (i load ) = ?200 ma 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i load = ?200ma i load = ?100ma i load = ?10ma i load = ?1ma 10703-056 figure 58. power supply rejection ratio (psrr) vs. frequency, adjustable output voltage, v out = ?15 v vs. different load currents (i load ), v in = ?15.5 v with noise reduction network 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i load = ?200ma i load = ?100ma i load = ?10ma i load = ?1ma 10703-057 figure 59. power supply rejection ratio (psrr) vs. frequency, adjustable output voltage, v out = ?15 v vs. different load currents (i load ), v in = ?16.5 v with noise reduction network 0 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 02.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 psrr (db) headroom voltage (v) frequency = 100hz frequency = 1khz frequency = 10khz frequency = 100khz frequency = 1mhz frequency = 10mhz 10703-058 figure 60. power supply rejection ratio (psrr) vs. headroom voltage, adjustable output voltage, v out = ?15 v with noise reduction network, load current (i load ) = ?200 ma 1000 1 10 100 0.001 0.01 0.1 1 10 100 1000 noise (v rms) load current (ma) v out = ?5v v out = ?1.8v v out = ?15v adj nr v out = ?3v v out = ?1.2v v out = ?15v adj 10703-059 figure 61. rms noise vs. load current (i load ), various output voltages 100k 1 10 100 1k 10k 1 100m 10m 1m 100k 10k 1k 100 10 noise spectral density (nv hz) frequency (hz) 10703-060 v out = ?5v v out = ?1.8v v out = ?15v adj nr v out = ?3v v out = ?1.2v v out = ?15v adj figure 62. noise spectral density, various output voltages
adp7182 data sheet rev. i | page 18 of 31 ch1 500mv b w ch2 2mv b w m10s a ch3 2.52v t 10.00% 1 2 t 10703-061 v out v in figure 63 . line transient response, 500 mv step, v out = ? 1.22 v, i load = ? 200 ma ch1 500mv b w ch2 1mv b w m10s a ch3 2.52v t 10.00% 1 2 t 10703-062 v out v in figure 64 . line transient response, 500 mv step, v out = 1.22 v, i load = 10 ma ch1 500mv b w ch2 5mv b w m2s a ch3 1.60v t 10.00% 1 2 t 10703-063 v out v in figure 65 . line tr ansient response, 500 mv step, v out = 1.8 v, i load = 200 ma ch1 500mv b w ch2 5mv b w m2s a ch3 1.60v t 10.00% 1 2 t 10703-064 v out v in figure 66 . line transient response, 500 mv step, v out = 1. 8 v, i load = 10 ma ch1 1v b w ch2 5mv b w m4s a ch3 1.60v t 10.00% 1 2 t 10703-065 v out v in figure 67 . line transient response, 500 mv step, v out = 3 v , i load = 200 ma ch1 1v b w ch2 5mv b w m4s a ch3 1.60v t 10.00% 1 2 t 10703-066 v out v in figure 68 . line transient response, 500 mv step, v out = 3 v, i load = 10 ma
data sheet adp7182 rev. i | page 19 of 31 ch1 1v b w ch2 10mv b w m2s a ch3 2.02v t 10.00% 1 2 t 10703-067 v out v in figure 69 . line transient response, 5 00 mv step, v out = ? 5 v, i load = ? 200 ma ch1 1v b w ch2 5mv b w m2s a ch3 2.02v t 10.00% 1 2 t 10703-068 v out v in figure 70 . line transient response, 500 mv step, v out = 5 v , i load = 10 ma ch1 1v b w ch2 2mv b w m4s a ch3 2.52v t 10.00% 1 2 t 10703-069 v out v in figure 71 . line transient response, 500 mv step, v out = 15 v, noise reduction network, i load = 200 ma ch1 1v b w ch2 2mv b w m10s a ch3 2.52v t 10.00% 1 2 t 10703-070 v out v in figure 72 . line transient response, 500 mv step, v out = 15 v, noise reduction netwo r k, i load = 10 ma ch1 100ma b w ch2 50mv b w m40s a ch1 ?122ma t 10.40% 1 2 t 10703-071 v out load current figure 73 . load transient response, v out = 1.22 v, i load = 1 ma to 200 ma , load step = 1 a/ s ch1 100ma b w ch2 50mv b w m40s a ch1 ?122ma t 10.60% 1 2 t 10703-072 v out load current figure 74 . load transient response, v out = 3 v, i load = 1 ma to 200 ma , load step = 1 a/s
adp7182 data sheet rev. i | page 20 of 31 ch1 100ma b w ch2 50mv b w m10s a ch1 ?122ma t 10.00% 1 2 t 10703-073 v out load current figure 75 . load transient response, v out = ?5 v, i load = ? 1 ma to ? 200 ma , load step = 1 a/s ch1 100ma b w ch2 50mv b w m40s a ch1 ?122ma t 10.00% 1 2 t 10703-074 v out load current figure 76 . load transient response, v out = 15 v, i load = 1 ma to 200 m a , load step = 1 a/s , noise reduction network
data sheet adp7182 rev. i | page 21 of 31 theory of operation the adp7182 is a low quiescent current, ldo linear regulator that operates from ?2.7 v to ?28 v and can provide up to ?200 ma of output current. drawing a low ?650 a of quiescent current (typical) at full load makes the adp7182 ideal for battery-powered portable equipment. maximum shutdown current consumption is ?8 a at room temperature. optimized for use with small 2.2 f ceramic capacitors, the adp7182 provides excellent transient performance. vout gnd en vin reference shutdown short circuit thermal protect vreg 10703-075 figure 77. fixed output voltage internal block diagram vout adj gnd en vin ?1.22v reference shutdown short circuit thermal protect vreg 10703-076 figure 78. adjustable output voltage internal block diagram internally, the adp7182 consists of a reference, an error amplifier, a feedback voltage divider, and an nmos pass transistor. output current is delivered via the nmos pass transistor, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is more positive than the reference voltage, the gate of the nmos transistor is pulled toward gnd, allowing more current to pass and increasing the output voltage. if the feedback voltage is more negative than the reference voltage, the gate of the nmos transistor is pulled toward ?v in , allowing less current to pass and decreasing the output voltage. the esd protection devices are shown in the block diagram as zener diodes (see figure 77 and figure 78). adjustable mode operation the adp7182 is available in a fixed output voltage and an adjustable mode version with an output voltage that can be set to between ?1.22 v and ?27 v by an external voltage divider. the output voltage can be set according to ?v out = ?1.22 v (1 + r fb1 / r fb2 ) r fb2 must be less than 120 k to minimize the output voltage errors due to the leakage current of the adj pin. the error voltage caused by the adj pin leakage current is the parallel combination of r fb1 and r fb2 times the adj pin leakage current. for example, when r fb1 = r fb2 = 120 k, the output voltage is ?2.44 v and the error due to the typical adj pin leakage current (10 na) is 60 k times 10 na, or 6 mv. this example results in an output voltage error of 0.245%. the addition of a small capacitor (~100 pf) in parallel with r fb1 can improve the stability of the adp7182 . larger values of capacitance also reduce the noise and improve psrr (see the noise reduction of the adjustable section). r fb2 120k ? r fb1 120k ? gnd en adj vin vout adp7182 on on ?2v off 0v 2v v in = ?3v v out = ?2.44v c out 2.2f c in 2.2f 10703-077 figure 79. setting adjustable output voltage
adp7182 data sheet rev. i | page 22 of 31 application s information adi sim p ower d esign t ool the adp7182 is supported by the adisimpo wer ? design tool set. adisimpower is a collection of tools that produce complete powe r designs optimized for a specific design goal. the tools enable the user to generate a full schematic, bill of materials, and calculat e performance in minutes. adisimpower can optimize designs for cost, area, efficiency, and device s count taking into consideration the operating conditions and limitations of the ic and all real external components. for more information about, and to obtain adisimpower design tools, visit www.analog.com/adisimpower . capacitor selection output capacitor the adp7182 is designed for operation with small space - saving ceramic capacitors ; however, it function s with most commonly used capacitors as long as care is taken with regard to the esr value. the esr of the output capaci tor affects the stabi lity of the ldo control loop . a minimum of 2.2 f capacitance with an esr of 0.2 ? or less is recommended to ensure the stability of the adp7182 . t ransient response to changes in load current is also a ffected by output capacitance . using a larger value of output capacitance improve s the transient response of the adp7182 to large changes in load current . figure 80 show s the transient r esponses for an o utput capacitance value of 2.2 f . ch1 100ma b w ch2 50mv b w m40s a ch1 ?122ma t 10.60% 1 2 t 10703-078 v out load current figure 80 . output transient response, c out = 2.2 f input bypass capacitor connecting a 2.2 f capacitor from v in to gnd reduces the circuit sensitivity to pcb layout, especially when long input traces or high source impedance are encountered. when more than 2.2 f of output capacitance is required, increase the input capacitance to match it . input and output capacitor properties as long as they meet the minimum capacitance and maximum esr requirements, a ny good quality ceramic capacitors can be used with the adp7182 . ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over te mperature and applied voltage. c apacitors must have a dielectric adequat e to ensure the minimum capacitance over the necessary temperature ran ge and dc bias conditions . x5r or x7r dielectrics with a voltage rating of 25 v or 5 0 v are recommended . due to their poor temperature and dc bias characteristics, y5v and z5u dielectrics are not recommended. figure 81 depicts the capacitance vs . voltage bia s characteristic s of an 08 0 5 , 2.2 f , 25 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capa citor size and voltage rating. in general, a capacitor in a larger packag e or higher voltage rating exhibit s better stability. the temperature variation of the x5r dielectric is ~ 15% over the ? 40 c to + 85c temperature range and is not a function of package or voltage rating. 2.5 0 0.5 1.0 1.5 2.0 0 5 10 15 20 25 30 capacitance (f) dc bias (v) 10703-079 figure 81 . capacitance vs . dc bias characteristic s use equation 1 to determine the worst - case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) (1) where: c bias is the effective capacitance at the operating voltage , wh ich is ? 3 v for this example . tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (tempco) over ?40c to +85c is 15% for an x5r dielectric . the tolerance of the capacitor (tol) is 10%, and the c bias is 2.08 f at a 3 v bias , as shown in figure 81. substituting these values in equation 1 yields c eff = 2. 08 f (1 ? 0.15) (1 ? 0.1) = 1.5 9 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage of ? 3 v . to guarantee the performance of the adp7182 , it is imperative that the effects of dc bias, temperature, and toler ances on the behavior of the capacitors be evaluated for each application.
data sheet adp7182 rev. i | page 23 of 31 enable pin operation the adp7182 uses the en pin to enable and disable the vout pin under normal operating conditions. when en is at 2 v with respect to gnd, vout turns on, and when en is at 0 v, vout turns off. for automatic startup, en can be connected to vin. when the device is disabled, a ~220 k resistor connects to the vout pin, which pulls the vout pin up to gnd. the adp7182 provides a dual polarity enable pin (en) that turns on the ldo when |v en | 2 v. the enable voltage can be positive or negative with respect to ground. 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 v out (v) enable voltage (v) v out with rising v en v out with falling v en 10703-080 figure 82. typical en pin operation figure 82 shows the typical hysteresis of the en pin. this prevents on/off oscillations that can occur due to noise on the en pin as it passes through the threshold points. figure 83 shows typical en thresholds when the input voltage varies from ?2.7 v to ?28 v. 1.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 ?30 ?26 ?22 ?18 ?14 ?10 ?6 ?2 enable threshold (v) input voltage (v) enable+ disable+ enable? disable? 10703-081 figure 83. typical en pin thresholds vs. input voltage figure 84 and figure 85 show the start-up behavior for a ?5 v output with positive and negative going enable signals. ch1 500mv b w ch2 500mv b w m40s a ch1 590mv t 10.20% 1 2 t 10703-082 en v out figure 84. typical start-up behavior, positive going enable ch1 500mv b w ch2 500mv b w m40s a ch1 ?580mv t 10.20% 1 2 t 10703-083 en v out figure 85. typical start-up behavior, negative going enable soft start the adp7182 uses an internal soft start to limit the inrush current when the output is enabled. the start-up time for the ?5 v option is approximately 450 s from the time the en active threshold is crossed to when the output reaches 90% of the final value. as shown in figure 86, the start-up time is dependent on the output voltage setting. 2 ?6 ?5 ?4 ?3 ?2 ?1 0 1 0 1000900800700600 500400 300200100 output voltages (v) time (s) v en v out = ?1.22v v out = ?3v v out = ?5v 10703-084 figure 86. typical start-up behavior, different output voltages
adp7182 data sheet rev. i | page 24 of 31 noise reduction of the adjustable adp7182 the ultralow output noise of the fixed output adp7182 is achieved by keeping the ldo error amplifier in unity gain and setting the reference voltage equal to the output voltage. this architecture does not work for an adjustable output voltage ldo. the adjustable output adp7182 uses the more conventional architecture where the reference voltage is fixed and the error amplifier gain is a function of the output voltage. the disadvantage of the conventional ldo architecture is that the output voltage noise is proportional to the output voltage. the adjustable ldo circuit can be modified slightly to reduce the output voltage noise to levels close to that of the fixed output of the adp7182 . the circuit shown in figure 87 adds two additional components to the output voltage setting resistor divider. c nr and r nr are added in parallel with r fb1 to reduce the ac gain of the error amplifier. r nr is chosen to be nearly equal to r fb2 ; this limits the ac gain of the error amplifier to approximately 6 db. the actual gain is the parallel combination of r nr and r fb1 divided by r fb2 . this resistance ensures that the error amplifier always operates at greater than unity gain. c nr is chosen by setting the reactance of c nr equal to r fb1 ? r nr at a frequency between 10 hz and 100 hz. this capacitance sets the frequency where the ac gain of the error amplifier is 3 db down from the dc gain. r fb2 13k ? r fb1 147k ? gnd en adj vin vout adp7182 on on ?2v off 0v 2v v in = ?16v v out = ?15v c out 2.2f c nr 100nf c in 2.2f r nr 13k ? 10703-085 figure 87. noise reduction modification to adjustable ldo the noise of the ldo is approximately the noise of the fixed output ldo (typically 18 v rms) times r fb2 , divided by the parallel combination of r nr and r fb1 . based on the component values shown in figure 87, the adp7182 has the following characteristics: ? dc gain of 12.3 (21.8 db) ? 3 db roll-off frequency of 10.8 hz ? high frequency ac gain of 1.92 (5.67 db) ? noise reduction factor of 6.41 (16.13 db) ? measured rms noise of the adjustable ldo at ?200 ma without noise reduction of 220 v rms ? measured rms noise of the adjustable ldo at ?200 ma with noise reduction circuit of 35 v rms ? calculated rms noise of the adjustable ldo with noise reduction (assuming 18 v rms for fixed voltage option) of 34.5 v rms the noise of the ldo is approximately the noise of the fixed output ldo (typically 18 v rms) times the high frequency ac gain. the following equation shows the calculation with the values shown in figure 87. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? k /13 k 1/147 k 1/13 1 1 v 18 (2) figure 88 shows the difference in noise spectral density for the adjustable adp7182 set to ?15 v with and without the noise reduction network. in the 100 hz to 30 khz frequency range, the reduction in noise is significant. 100k 1 10 100 1k 10k 1 100m 10m 1m 100k 10k 1k 100 10 noise spectral density (nv hz) frequency (hz) ?15v adj ?15v adj nr 10703-086 figure 88. ?15 v adjustable adp7182 with and without the noise reduction network (cnr and rnr) current-limit and thermal overload protection the adp7182 is protected against damage due to excessive power dissipation by current-limit and thermal overload protection circuits. the adp7182 is designed to limit current when the output load reaches ?350 ma (typical). when the output load exceeds ?350 ma, the output voltage is reduced to maintain a constant current limit. thermal overload protection is included, which limits the junction temperature to a maximum of 150c (typical). under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 150c, the output is turned off, reducing the output current to 0 ma. when the junction temperature falls below 135c, the output is turned on again, and the output current is restored to the nominal value. consider the case where a hard short from vout to ground occurs. at first, the adp7182 limits current so that only ?350 ma is conducted into the short. if self-heating of the junction is great enough to cause the temperature to rise above 150c, thermal shutdown is activated, turning off the output and reducing the output current to 0 ma. as the junction temperature cools and falls below 135c, the output turns on and conducts ? 350 ma into the short, again causing the junction temperature to rise above 150c. this thermal oscillation between 135c and 150c causes a current oscillation between ?350 ma and 0 ma that continues as long as the short remains at the output.
data sheet adp7182 rev. i | page 25 of 31 current-limit and thermal overload protections are intended to protect the device against accidental overload conditions. for reliable operation, device power dissipation must be externally limited so that the junction temperatures do not exceed 125c. thermal considerations in most applications, the adp7182 does not dissipate much heat due to the high efficiency. however, in applications with high ambient temperature, and high supply voltage to output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125c. when the junction temperature exceeds 150c, the converter enters thermal shutdown. it recovers only after the junction temperature has decreased below 135c to prevent any permanent damage. therefore, thermal analysis for the chosen application is important to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in equation 3. to guarantee reliable operation, the junction temperature of the adp7182 must not exceed 125c. to ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. these parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air ( ja ). the ja number is dependent on the package assembly compounds that are used, and the amount of copper that solders the package vin pins to the pcb. table 8 and tabl e 9 show typical ja values of the 6- and 8-lead and 5-lead tsot packages for various pcb copper sizes. table 10 shows the typical jb values of the 6- and 8-lead and and 5-lead tsot. table 8. typical ja values of the lfcsp ja (c/w) copper size (mm 2 ) 8-lead lfcsp 6-lead lfcsp 25 1 175 177.8 100 135.6 138.2 500 77.3 79.8 1000 65.2 67.8 6400 51 53.5 1 device soldered to minimum size pin traces. table 9. typical ja values of the 5-lead tsot copper size (mm 2 ) ja (c/w) 0 1 170 50 152 100 146 300 134 500 131 1 device soldered to minimum size pin traces. table 10. typical jb values model jb (c/w) 6-lead lfcsp 44.1 8-lead lfcsp 18.2 5-lead tsot 43 the junction temperature of the adp7182 can be calculated by t j = t a + ( p d ja ) (3) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) (4) where: v in and v out are the input and output voltages, respectively. i load is the load current. i gnd is the ground current. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation simplifies to t j = t a + {[( v in ? v out ) i load ] ja } (5) as shown in equation 5, for a given ambient temperature, input-to- output voltage differential, and continuous load current, there exists a minimum copper size requirement for the pcb to ensure that the junction temperature does not rise above 125c. figure 89 to figure 97 show junction temperature calculations for different ambient temperatures, power dissipation, and areas of pcb copper. heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the adp7182 . adding thermal planes under the package also improves thermal performance. however, as listed in table 8 and table 9, a point of diminishing returns is reached eventually, beyond which an increase in the copper area does not yield significant reduction in the junction-to-ambient thermal resistance. 140 120 100 80 60 40 20 0 01.2 1.0 0.8 0.6 0.4 0.2 junction temperature, t j (c) total power dissipation (w) 6400mm 2 1000mm 2 500mm 2 100mm 2 25mm 2 jedec t j max 10703-087 figure 89. junction temperature vs. total power dissipation for the 8-lead lfcsp, t a = 25c
adp7182 data sheet rev. i | page 26 of 31 140 120 100 80 60 40 20 0 01.2 1.0 0.8 0.6 0.4 0.2 junction temperature, t j (c) total power dissipation (w) 6400mm 2 1000mm 2 500mm 2 100mm 2 25mm 2 jedec t j max 10703-088 figure 90. junction temperature vs. total power dissipation for the 8-lead lfcsp, t a = 50c 140 120 100 80 60 40 20 0 01.2 1.0 0.8 0.6 0.4 0.2 junction temperature, t j (c) total power dissipation (w) 6400mm 2 1000mm 2 500mm 2 100mm 2 25mm 2 jedec t j max 10703-089 figure 91. junction temperature vs. total power dissipation for the 8-lead lfcsp, t a = 85c 10703-191 25 35 45 55 65 75 85 95 105 115 125 135 145 0 0.20.40.60.81.01.21.41.61.82.0 junction temperature (c) total power dissipation (w) 6400 mm 2 500 mm 2 25 mm 2 t j max figure 92. junction temperature vs. total power dissipation for the 6-lead lfcsp, t a = 25c 50 60 70 80 90 100 110 120 130 140 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 junction temperature (c) total power dissipation (w) 10703-192 6400 mm 2 500 mm 2 25 mm 2 t j max figure 93. junction temperature vs. total power dissipation for the 6-lead lfcsp, t a = 50c 65 75 85 95 105 115 125 135 145 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.9 0.8 1.0 junction temperature (c) total power dissipation (w) 10703-193 6400 mm 2 500 mm 2 25 mm 2 t j max figure 94. junction temperature vs. total power dissipation for the 6-lead lfcsp, t a = 85c 140 120 100 80 60 40 20 0 01.2 1.0 0.8 0.6 0.4 0.2 junction temperature, t j (c) total power dissipation (w) 500mm 2 300mm 2 100mm 2 25mm 2 jedec t j max 10703-090 figure 95. junction temperature vs. total power dissipation for the 5-lead tsot, t a = 25c
data sheet adp7182 rev. i | page 27 of 31 140 120 100 80 60 40 20 0 00.7 0.5 0.6 0.4 0.3 0.2 0.1 junction temperature, t j (c) total power dissipation (w) 500mm 2 300mm 2 100mm 2 25mm 2 jedec t j max 10703-091 figure 96. junction temperature vs. total power dissipation for the 5-lead tsot, t a = 50c 140 120 100 80 60 40 20 0 00.40 0.35 0.25 0.30 0.20 0.15 0.10 0.05 junction temperature, t j (c) total power dissipation (w) 500mm 2 300mm 2 100mm 2 25mm 2 jedec t j max 10703-092 figure 97. junction temperature vs. total power dissipation for the 5-lead tsot, t a = 85c thermal characterization parameter, jb when the board temperature is known, use the thermal characterization parameter, jb , to estimate the junction temperature rise (see figure 98 and figure 100). maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) (6) the typical value of jb is 18.2c/w for the 8-lead lfcsp package, 44.1c/w for the 6-lead lfcsp package and 43c/w for the 5-lead tsot package. 140 120 100 80 60 40 20 0 07 56 4321 junction temperature, t j (c) total power dissipation (w) t b = 25c t b = 50c t b = 85c t j max 10703-093 figure 98. junction temperature vs. total power dissipation for the 8-lead lfcsp, t a = 85c 10703-198 junction temperature (c) total power dissipation (w) 0 20 40 60 80 100 120 140 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 t b = 25c t b = 50c t b = 65c t b = 85c t j max figure 99. junction temperature vs. total power dissipation for the 6-lead lfcsp, t a = 85c 140 120 100 80 60 40 20 0 07 56 4321 junction temperature, t j (c) total power dissipation (w) t b = 25c t b = 50c t b = 85c t j max 10703-094 figure 100. junction temperature vs . total power dissipation for the 5-lead tsot, t a = 85c
adp7182 data sheet rev. i | page 28 of 31 pcb layout considera tio ns place the input capacitor as close as possible to the vin and gnd pins. place the output capacitor as close as possible to the vout and gnd pins. use of 1206 or 0805 size capacitors and resistors achieves the smallest possible footprint solution on boar ds where area is limited. 10703-100 figure 101 . example of the 6 - lead lfcsp pcb layout 10703-095 figure 102 . example of the 8 - lead lfcsp pcb layout 10703-096 figure 103 . example of the 5 - lead tsot pcb layout
data sheet adp7182 rev. i | page 29 of 31 table 11. recommended ldos for very low noise operation device number v in range (v) v out fixed (v) v out adjust (v) i out (ma) i q at i out (a) i gnd - sd max (a) soft start p good noise (fixed) 10 hz to 100 khz (v rms) psrr 100 khz (db) psrr 1 mhz (db) package adp7102 3.3 to 20 1.5 to 9 1.22 to 19 300 750 75 no yes 15 60 40 3 mm 3 mm 8 - lead lfcsp, 8 - lead soic adp7104 3.3 to 20 1.5 to 9 1.22 to 19 500 900 75 no yes 15 60 40 3 mm 3 mm 8 - lead lfcsp, 8 - lead soic adp7105 3.3 to 20 1.8, 3.3, 5 1.22 to 19 500 900 75 yes yes 15 60 40 3 mm 3 mm 8 - lead lfcsp, 8 - lead soic adp7118 2.7 to 20 1.2 to 5 1.2 to 19 200 160 10 yes no 11 68 50 2 mm 2 mm 6 - lead lfcsp, 8 - lead soic, 5 - lead tsot adp7142 2.7 to 40 1.2 to 5 1.2 to 39 200 160 10 yes no 11 68 50 2 mm 2 mm 6 - lead lfcsp, 8 - lead soic, 5 - lead tsot adp7182 ? 2.7 to ?28 ? 1.8 to ?5 ? 1.22 to ?27 ? 200 ? 650 ? 8 no no 18 45 45 2 mm 2 mm 6 - lead lfcsp, 3 mm 3 mm 8 - lead lfcsp, 5 - lead tsot
adp7182 data sheet rev. i | page 30 of 31 outline dimensions 1.70 1.60 1.50 0.425 0.350 0.275 t op view 6 1 4 3 0.35 0.30 0.25 bottom view pin 1 index are a sea ting plane 0.60 0.55 0.50 1.10 1.00 0.90 0.20 ref 0.05 max 0.02 nom 0.65 bsc exposed pa d pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 02-06-2013-d 0.15 ref 2.10 2.00 sq 1.90 0.20 min figure 104 . 6- lead lead frame chip scale package [lfcsp] 2.00 mm 2.00 mm body and 0.55 package height (cp - 6 - 3) dimensions shown in millimeters 8 1 5 4 0.30 0.25 0.20 pin 1 index are a sea ting plane 0.80 0.75 0.70 1.55 1.45 1.35 1.84 1.74 1.64 0.203 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 0.50 0.40 0.30 compliant to jedec standards mo-229-weed-4 05- 1 1-2016- a pin 1 indic a t or (r 0.15) t op view bot t om view side view figure 105 . 8- lead lead f rame chip scale package [lfcsp] 3 mm 3 mm body and 0.75 package height (cp - 8 - 13 ) dimensions shown in millimeters
data sheet adp7182 rev. i | page 31 of 31 100708-a * compliant to jedec standards mo-193-ab with the exception of package height and thickness. 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.20 0.08 0.60 0.45 0.30 8 4 0 0.50 0.30 0.10 max * 1.00 max * 0.90 max 0.70 min 2.90 bsc 5 4 1 2 3 se a ting plane figure 106 . 5- lead thin small outline transistor package [tsot] (uj - 5) dimensions show n in millimeters ordering guide model 1 temperature range output voltage (v) 2 package description package option branding adp7182acpz -r7 ? 40c to +125c adjustable 8 - lead lfcsp cp -8 -13 ln6 adp7182acpz - 5.0-r7 ? 40c to +125c ? 5 8 - lead lfcsp cp -8 -13 ln9 adp7182aujz -r7 ? 40c to +125c adjustable 5 - lead tsot uj -5 ln6 adp7182aujz - 1.8-r7 ? 40c to +125c ? 1.8 5 - lead tsot uj -5 ln1 adp7182aujz - 2.5-r7 ? 40c to +125c ? 2.5 5 - lead tsot uj -5 ln7 adp7182aujz - 3.0 - r7 ? 40c to +125c ? 3 5 - lead tsot uj - 5 ln2 adp7182aujz - 5.0 - r7 ? 40c to +125c ? 5 5 - lead tsot uj - 5 ln9 adp7182acpz n -r7 ? 40c to +125c adjustable 6 - lead lfcsp cp -6 -3 ln6 adp7182acpz n - 5.0r7 ? 40c to +125c ? 5 6 - lead lfcsp cp -6 -3 ln9 adp7182acpz n - 2.5r7 ? 40c to +125c ? 2.5 6 - lead lfcsp cp -6 -3 ln7 adp7182acpz n - 1.5r7 ? 40c to +125c ? 1 .5 6 - lead lfcsp cp -6 -3 lqk adp7182acpzn - 1.2r7 ? 40c to +125c ? 1.2 6 - lead lfcsp cp -6 -3 lre adp7182uj - evalz evaluation board , tsot adp7182cp - evalz evaluation board , lfcsp 1 z = rohs compliant part. 2 for additional voltage options, contact a local analog devices, inc., sales or distribution representative . ? 2013 C 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10703 - 0- 12/16(i)

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