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6 0 gh z millimeterwave transmitter , 57 ghz to 64 ghz data sheet HMC6300 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infri ngements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and regist ered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2016 analog devices, inc. all rights reserved. technical support www.analog.com features frequency b and: 57 ghz to 64 ghz rf signal bandwidth: up to 1.8 ghz output power for 1 db compression: 15 dbm g ain: 5 db to 35 db digital and analog rf and if gain control integrated frequency synthesizer integrated image reject filter partial ly external loop filter support for external local oscillator ( lo ) on - chip temperature sensor support for 256 qam modulation integrated minimum shift keying ( msk ) m odulator universal a nalog i/q b aseband i nterface 3 - w ire serial digital interface 65- b all , rohs c ompliant , wafer level ball grid array applications small cell backhaul 60 ghz industrial, scientific, and medical ( ism ) band data transfer multiple gbps data communication wigig/802.11ad r adio high definition video transmission radar/ high resolutio n imaging general description the HMC6300 is a complete millimeterwave transmitter integrated circuit in a 6 mm 4 mm rohs compliant wafer level ball grid array (wlbga) that operates from 57 ghz to 64 ghz with up to 1.8 ghz modulation bandwidth. an integrated synthesizer provides tuning in 250 mhz, 500 mhz, or 540 mhz steps with excellent phase noise to support up to 64 qam modulation. optionally, an external lo can be injected allowing for u ser selectable lo characteristics or phase coherent transmit and receive operation, as well as modulation up to 256 qam. support for a wide variety of modulation formats is provided through a universal analog baseband i/q inte rface. the transmitter chip op tionally supports dedicated frequency - shift keying ( fsk ) , minimum shift keying ( msk ) , and on - off keying ( ook ) modulation formats for lower cost and lower power serial data links without the need for high speed data converters. a differential output provid es up to 15 d bm linear output power into a 100 ? load. single - ended operation is also supported up to 12 dbm. together with the hmc6301 , a complete 60 ghz transceiver chipset is provided for multiple gbps o peration in the unlicensed 60 ghz ism band. functional block dia gram refclk_p rfout_p bb_qn bb_qp bb_im bb_ip fm_mq fm_pq fm_mi fm_pi rfout_n refclk_n det out extlo_p extlo_n driver 3 2 if amp div lpf cp pfd mux HMC6300 msk mod 90 180 scanout clk data interface serial pa 14423-001 figure 1.
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HMC6300 data sheet rev. b | page 2 of 25 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical specifications, 57 ghz to 63 ghz ............................ 3 electrical specifications, 63 ghz to 64 ghz ............................ 4 recommended operating conditions ...................................... 5 power consumption .................................................................... 6 absolute maximum ratings ............................................................ 7 esd caution ...................................................................................7 pin configuration and functio n descriptions ..............................8 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 13 register array assignment and serial interface .................... 13 transmitter register array assignments ................................ 14 synthesizer settings .................................................................... 20 applications information .............................................................. 22 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 12 /2016 rev. a to rev. b changes to figure 11 and figure 14 ............................................. 11 changes to ordering guide .......................................................... 25 9 / 201 6 v 00. 0 716 to rev. a updated format .................................................................. universal added minimum gain parameter, table 1 ................................... 3 changes to recommend ed operating conditions, table 3 ....... 5 changes to figure 17 ...................................................................... 14 added ordering guide section .................................................... 25 7/2016 revision v00.0716: initial version
data sheet HMC6300 rev. b | page 3 of 25 specifications t a = 25 c , reference frequency = 71.4286 mhz, if bandwidth = maximum, input impedance = 100 ? differential, output impedance = 100 ? differential, input signal level (high modulator gain) = ?36 dbm on each of the four baseband inputs, power amplifier configuration is differential, unless otherwise noted. electrical specifica tions , 5 7 g h z to 63 g h z table 1 . electrical specifications, 57 ghz to 63 ghz parameter test conditions/comments min typ max unit frequency step size with 71.4286 mhz refe rence clock 250 m hz with 142.857 mhz reference clock 500 m hz with 154.2857 mhz reference clock 540 m hz modulation bandwidth full i/q bandwidth 1.8 ghz gain minimum gain 5 db maximum gain 32.5 35 db modulator gain control high and low gain settings 9 db if gain control 14 db rf gain control 22 db output power output power for 1 db compression (p1db) balance d into 100 ? 15 dbm saturated output power (p sat ) balanced into 100 ? 13.9 17 dbm output power for 1 db c ompression (p1db) singled - ended into 50 ? 12 dbm saturated output power (p sat ) singled - ended into 50 ? 14 dbm detector power range ?10 to + 15 dbm temperature sensor range four levels ?40 +85 c suppression and rejection sideband suppressi on 15 30 db c image rejection 40 db c lo suppression at 6/7 of rf carrier frequency (3 lo) 10 20 db c carrier suppression without calibration 30 db c phase phase noise @ 100 khz offset ?75 dbc/ hz @ 1 mhz offset ?93 dbc/ hz @ 10 mhz offset ?114 dbc/ hz @ 100 mhz offset ?122 dbc/hz phase - locked loop (pll) bandwidth using internal filter 300 khz power dissipation balanced 1.0 w single - ended 0.88 w balanced, external lo 0.75 w
HMC6300 data sheet rev. b | page 4 of 25 electrical specifica t ions, 63 g h z to 64 g h z table 2 . e lectrical specifications, 63 ghz to 64 ghz parameter test conditions/comments min typ max unit frequency step size with 71.4286 mhz reference clock 250 mhz with 142.857 mhz reference clock 500 mhz with 154.2857 mhz reference clock 540 mhz modulation bandwidth full i/q bandwidth 1.8 ghz gain maximum gain 30.5 32 db modulator gain control h igh and low gain settings 9 db if gain control 14 db rf gain contro l 22 db outp ut power output power for 1 db compression (p1db) balanced into 100 ? 15 dbm saturated output power (p sat ) balanced into 100 ? 13.9 17 dbm output power for 1 db compression (p1db) singled - ended into 50 ? 12 dbm saturated output power (p sat ) si ngled - ended into 50 ? 14 dbm detector power ? 10 to + 15 dbm temperature sensor range four levels ? 40 +85 c suppression and rejection sideband suppression 15 30 dbc image rejection 40 dbc lo suppression at 6/7 of rf carrier freque ncy ( 3 lo) 10 20 dbc carrier suppression without calibration 30 dbc phase phase noise @ 100 khz offset ? 75 dbc/hz phase noise @ 1 mhz offset ? 93 dbc/hz phase noise @ 10 mhz offset ? 114 dbc/hz phase noise @ 100 mhz offset ? 122 dbc/hz pll bandwidth using internal filter 300 khz power dissipation b alanced 1.0 w s ingle -e nded 0.88 w b alanced , external lo) 0.75 w
data sheet HMC6300 rev. b | page 5 of 25 recommended operatin g conditions table 3 . parameter symbol min typ max unit pow er supply power amplifier vcc pan , vc c pap 3.9 4 4.1 v dc vdd pa 2.565 2.7 2.835 v dc driver vcc drv 2.565 2.7 2.835 v dc divider vcc div 2.565 2.7 2.835 v dc mixer vcc mix 2.565 2.7 2.835 v dc intermediate frequency vcc if 2.565 2.7 2.835 v dc radio frequency variable gain amplifier vcc rfvga 2.565 2.7 2.835 v dc tripler vcc trip 2.565 2.7 2.835 v dc vco vcc vco 2.565 2.7 2.835 v dc digital circuit vdd d 1.3 1.35 1.48 v dc synthesizer vdd syn 1.3 1.35 1.48 v dc input voltage range serial digita l interface data, enable, clk, reset logic high 0.9 1.2 1.4 v logic low ? 0.05 + 0.1 + 0.3 v reference clock reference clock, positive refclk_p 3.3 v or 2.5 v lvpecl/lvds , v 1.2 v cmos v reference clock, negative refclk_ n 3.3 v or 2.5 v lvpecl/lvds , v 1.2 v cmos v baseband i/ q in - phase baseband input negative bb_im 5 100 750 mv p -p positive bb_ip 5 100 750 mv p -p quadrature baseband input negative bb_q n 5 100 750 mv p -p positive bb_qp 5 100 750 mv p -p baseband i/q, common mode in - phase baseband input negative bb_im 1.6 v positive bb_ip 1.6 v quadrature baseband input negative bb_q n 1.6 v positive bb_qp 1.6 v m sk data m sk in - phase input negative ( minus) fm_ mi 200 500 750 mv p -p positive fm_ pi 200 500 750 mv p -p m sk quadrature input negative ( m inus) fm_ mq 200 500 750 mv p -p positive fm_ pq 200 500 750 mv p - p msk common mode 1.1 v analog gain control rf variable gain amplifier ana rfvga 0.1 1.1 2.5 v if variable gain amplifier ana ifvga 0.1 1.1 2.5 v external lo posi tive extlo_p 0 3 5 dbm negative extlo_n 0 3 5 dbm
HMC6300 data sheet rev. b | page 6 of 25 parameter symbol min typ max unit drain current 1.35 v 10 ma 2.7 v 277 ma 4.0 v ( b alanced) 58 ma 4.0 v (singled - ended) 29 ma power consumption table 4 . parameter voltage (v) typical current (ma) typical power consumption (mw) vcc pan 4.0 29 116 vcc pap 4.0 29 116 vcc drv 2.7 32 86 vcc div 2.7 46 124 vcc mix 2.7 32 86 vcc if 2.7 31 84 vcc rfvga 2.7 20 54 vcc trip 2.7 56 151 vcc vco 2.7 52 140 vcc pa 2.7 8 22 vcc d 1.35 0.08 0.1 vcc syn 1.35 10 13
data sheet HMC6300 rev. b | page 7 of 25 absolute maximum rat ings table 5 . parameter rating vcc drv 2.85 v vcc div 2.85 v vcc pan , vcc pap 4.2 v vcc vco 2.85 v vcc rfvga 2.85 v vcc if 2.85 v vcc mix 2.85 v vcc trip 2.85 v vdd syn 1.6 v vdd pa 2.85 v vdd d 1.6 v seri al digital interface input voltage 1.5 v thermal resistance (r th ), junction to ground paddle 9.57c baseband inputs : bb, fm ( e ach) 0.75 v p -p storage temperature ? 55c to +150c operating temperature ? 40c to 85c reflow temperature (maximum peak) 260c esd sensitivity, charged device model (cdm) class c3 (250 v) stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
HMC6300 data sheet rev. b | page 8 of 25 pin configuration an d func tion descriptions HMC6300 top view (ball side down) a b c d e f g h 1 2 3 4 5 6 7 8 9 10 11 12 ground area det out ref out vcc drv bb_qn bb_qp bb_im bb_ip fm_mq fm_pq fm_mi fm_pi vcc div vcc pap rfb vcc mix vcc if gnd gnd gnd gnd extfil_p extfil_n vcc div vcc div gnd vss div vss lpf_bias_pll rfout_p vss cp_pfd refclk_p refout_n vss ref_dig refclk_n gnd vreg out vdd syn vcc pan vdd pa vcc rfvga scanout vdd d reset vcc trip vss vco vss vco vcc vco vcc vco vco rcap vcc drv ana rfvga data enable clk ana ifvga vss vco extlo_n extlo_p vss vco vss vco vss vco 14423-002 figure 2. pin configuration diagram table 6 . pin function descriptions pin no. mnemonic description a1 det out detector output ( 0.6 v dc to 2.6 v dc ) . a2 ref out detector reference output ( 0.6 v dc ) . a3, h1 vcc drv driver p ower s upply (2.7 v dc). a4 bb_qn quadrature negative baseband input. this pin is dc - coupled and matched to 50 ? . a5 bb_qp quadrature positive baseband input. this pin is dc - coupled and matched to 50 ? . a6 bb_im in -p hase negative baseband input. this pin is dc - coupled and matched to 50 ? . a7 bb_ip in -p hase positive baseband input. this pin is dc - coupled and matc hed to 50 ? . a8 fm_mq fsk negative (minus) quadrature i nput. this pin is dc - coupled and matched to 50 ? . a9 fm_pq fsk positive quadrature i nput. this pin is dc - coupled and matched to 50 ? . a10 fm_mi fsk negative (minus) in -p hase i nput. this pin is dc -co upled and matched to 50 ? . a11 fm_pi fsk positive in -p hase i nput. this pin is dc - coupled and matched to 50 ? . a12, b11, b12 vcc div divider power s upply (2.7 v dc). b1 vcc pap power amplifier power s upply (4.0 v dc). b2 rfb detector circuit feedback. b3 vcc mix mixer power s upply (2.7 v dc). b4 vcc if if power s upply (2.7 v dc). b5 to b8, c1 , f1 gnd analog ground connect.
data sheet HMC6300 rev. b | page 9 of 25 pin no. mnemonic description b9 extfil_p external pll f ilter ( p ositive). b10 extfil_n external pll f ilter ( n egative). c11 vss div digital g round for the synthesi zer. c12 vss lpf_bias_pll digital g round for s ynthesizer. d1 rfout_p radio frequency output (positive). this pin is ac - coupled and is diff erentially matched to 100 ? . this output port is disabled when single - ended output is selected. d11 vss cp_pfd digital g round for s ynthesizer. d12 refclk_p external reference clock (positive). this pin can be dc or ac matched to 50 ? . e1 rfout_n radio frequency output (negative). this pin is ac coupled and is diff matched to 100 ? . this pin is used if single - ended output is selected. e11 vss ref_dig digital g round for s ynthesizer. e12 refclk_n external reference clock (negative). this pin can be dc or ac matched to 50 ? . f11 v re g out vco regulator o utput. f12 vdd syn synthesizer power s upply (1.3 v dc). g1 vcc pan power amplifier power s upply (4.0 v dc). g2 vdd pa power amplifier power s upply (2.7 v dc). g3 vcc rfvga rf vga power s upply (2.7 v dc). g4 scanout serial digital inter face out put (1.2 v cmos). g5 vdd d digital circuits power s upply (1.3 v dc). g6 reset serial digital interface reset (1.2 v cmos). g7 vcc trip tripler power s upply (2.7 v dc). g8, g9, h7, h10 to h12 vss vco digital ground for the vco. g10, g11 vcc vco vco power s upply (2.7 v dc). g12 vco rcap external capacitor connection for the vco regulator. h2 ana rfvga 0.1 v to 2.4 v rf vga analog control. connect pin h2 to 2.7 v dc for digital control . h3 data serial digital interface data (1.2 v cmos). h4 enable s erial digital interface enable (1.2 v cmos). h5 clk serial digital interface clock (1.2 v cmos). h6 ana ifvga 0.1 v to 2.4 v if vga analog control. connect pin h6 to 2.7 v dc for digital control . h8 extlo_n external lo ( n egative) i nput. h9 extlo_p exter nal lo ( p ositive) i nput.
HMC6300 data sheet rev. b | page 10 of 25 typical performance characteristics 50 10 20 15 25 35 45 30 40 57 58 59 61 60 63 62 64 gain (db) frequency (ghz) +85c +25c ?40c 14423-003 figure 3 . maximum gain vs. frequency over temperature, if and rf a ttenuation = 0 dbm 24 22 20 18 16 14 12 10 8 6 4 2 0 0 0.3 0.5 0.8 1.0 1.3 1.5 1.8 2.0 2.2 attenuation (db) analog control voltage (v) +85c +25c ?40c 14423-004 figure 4 . rf attenuation vs. analog control voltag e over temperature, measurement t aken at 60 ghz , if attenuation = 0 dbm 18 0 4 10 14 16 8 2 6 12 0 1 2 5 7 9 11 3 4 6 8 10 12 13 14 15 attenuation (db) digital setting +85c +25c ?40c 14423-005 figure 5. rf attenuation vs. digital setting over temperature, measurement t aken at 60 ghz , if attenuation = 0 dbm ?2 14 10 4 0 6 12 8 2 0 0.50 1.00 1.50 0.25 0.75 1.25 1.75 2.00 attenuation (db) analog control voltage (v) +85c +25c ?40c 14423-006 figure 6. i f attenuation vs. analog control voltage over temperature , measurement t aken at 60 ghz , rf a ttenuation = 0 dbm 18 0 4 10 14 16 8 2 6 12 0 1 2 5 7 9 11 3 4 6 8 10 12 13 14 15 attenuation (db) digital setting +85c +25c ?40c 14423-007 figure 7 . if attenuation vs. digital setting over temperature, measurement t aken at 60 ghz , rf a ttenuation = 0 dbm 20 18 16 14 12 10 8 6 4 2 0 57 58 59 60 61 62 63 64 p1db (dbm) frequency (ghz) +85c +25c ?40c 14423-008 figure 8 . output p1db vs. frequency over temperature, if and rf attenuation = 0 dbm
data sheet HMC6300 rev. b | page 11 of 25 25 23 21 19 17 15 13 11 9 7 5 57 58 59 60 61 62 63 64 p sat (dbm) frequency (ghz) +85c +25c ?40c 14423-009 figure 9. output saturated power (p sat ) vs. frequency over temperature, if and rf attenuation = 0 dbm ?25 ?30 ?35 ?40 ?45 ?50 ?55 ?60 57 58 59 60 61 62 63 64 carrier suppression (dbc) frequency (ghz) +85c +25c ?40c 14423-010 figure 10 . carrier suppression vs. frequency over temperature , if and rf attenuation = 0 dbm ?60 ?140 ?120 ?130 ?110 ?90 ?70 ?100 ?80 1k 10k 100k 1m 100m 10m 1g phase noise (dbc/hz) frequency (hz) +85c +25c ?40c 14423-0 1 1 figure 11 . phase noise vs. frequency offset over temperature, internal lo , measurement taken at 60 ghz 25 20 10 15 5 0 57 58 59 60 61 62 63 64 oip3 (dbm) frequency (ghz) +85c +25c ?40c 14423-012 figure 12 . oip3 vs. frequency over temperature, total p out = 0 dbm, if and rf attenuation = 0 dbm ?25 ?30 ?35 ?40 ?45 ?50 ?55 ?60 sideband suppression (dbc) 57 58 59 60 61 62 63 64 frequency (ghz) +85c +25c ?40c 14423-013 figure 13 . sideband suppression vs. frequency over temperature, if and rf attenuation = 0 dbm ?60 ?140 ?120 ?130 ?110 ?90 ?70 ?100 ?80 phase noise (dbc/hz) frequency (hz) +85c +25c ?40c 14423-014 1k 10k 100k 1m 100m 10m 1g figure 14 . phase noise vs. frequency offset over temperature, external lo, measurement taken at 60 ghz
HMC6300 data sheet rev. b | page 12 of 25 10 0.01 1 0.1 0 2 4 6 8 10 12 14 16 18 20 output voltage (v) output power (dbm) +85c +25c ?40c 14423-015 figure 15 . detector output voltage vs. output power over temperature, measurement taken at 60 ghz, and 1.15 k? conne cting det out and rfb pins 1 16 4 8 2 ?40 ?30 ?20 10 30 50 70 ?10 0 20 40 60 80 90 sensor reading temperature (c) 14423-016 figure 16 . temperature sensor reading vs. temperature
data sheet HMC6300 rev. b | page 13 of 25 theory of operation an integrated frequency synthesizer creates a low phase noise lo between 16.3 ghz and 18.3 ghz. the step size of the syn thesizer equates to 250 mhz steps at rf when used with a 71.42857 mhz reference crystal or 500 mhz if used with a 142.857 reference crystal. to support ieee channels (ism band) with a 540 mhz step size, use a 154.2857 mhz reference crystal. if the chip is configured for i / q baseband input, these signals are quadrature modulated onto an 8 ghz to 9.1 ghz sliding if using the synthesized lo divided by two. there are also options to input am/fm/fsk/msk waveforms directly to the on - chip if modulators. the if sig nal is then filtered and amplified with 14 db of variable gain, then mixed with three times the lo frequency to upconvert to an rf frequency between 57 ghz and 64 ghz. integrated notch filters attenuate the lower mixing product at 40 ghz to 46 ghz. three rf amplifier stages provide gain to allow up to 15 dbm of linear and differential output power with 22 db of variable gain. if and rf gain can be controlled using e ither analog voltages or the digital spi. for lower power consump - ti on, half of the power am plifier can be disabled to run in a single - ended configuration; this drops the output power by 3 db. an on - chip power detector can be used to monitor the rms output p ower. the detector output pin (det out ) is connected through an external resistor to the rf b pin. a resistor value of 1.15 k? is recommended for optimal coverage up to the p1db point of the transmitter. the ref out pin provides the reference voltage for the detector, and the difference between det out and ref out is used to estimate the output powe r. the phase noise and quadratu re balance of the on - chip synthesize r is sufficient to support up to 64 qam modulation. for higher order modulation ( up to 256 qam or less than 250 mhz step size ) , the HMC6300 can be operated using an external lo. the HMC6300 transmitter is ideal for fdd operation together with the hmc6301 r eceiver chip. however, both devices can support tdd operation by enabling and disabling the circuits. all of the enabl es are placed in register array, four of which allow for full chip enable or disable in one spi write. there are no special power sequenci ng requirements for the HMC6300 ; all voltages are to be applied simultaneously. register array assig nment and serial interface the register arrays for both the transmitter and receiver are orga nized into 32 rows of 8 bits. using the serial interface, the arrays are written or read one row at a time , as shown in figure 17 a nd figure 18 , respectively. figu re 17 shows the sequence of signals on the enable, clk, and data lines to write one 8 - bit row of the register array. the enable line goes low, the first of 18 data bits ( b it 0) is placed on the data line, and 2 ns or longer after the data line stabilizes, the clk line goes high to clock in data bit 0. the data line should remain stable for at least 2 ns after the rising edge of clk. a write operation requires 18 data bits and 18 clock pulses, as shown in figure 17 . the 18 data bi ts contain the 8 - bit register array row data (lsb is clocked in first), followed by the register array row address (row 0 through row 23, 000000 to 001111, lsb first), the read/w rite bit (set to 1 to write), and finally the tx chip addres s 110, lsb first). the tx ic support s a serial interface running up to several hundred megahertz , and the interface is 1.2 v cmos levels. note that the register array row address is six bits, but only four are used to desi gnate 32 rows, the tw o msbs are 0. after the 18th cl ock pulse of the write operation, the enable line returns high to load the register array on the ic; prior to the rising edge of the enable line, no data is written to the array. the clk line should have stabilized in the low state at least 2 ns prior to t he rising edge of the enable line.
HMC6300 data sheet rev. b | page 14 of 25 e nable time = 0 clk data data array address chip address r/w = 1 lsb lsb lsb msb msb msb 0 1 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 14423-017 figure 17.timing diagram for writing a row of the transmitter serial interface time = 0 enable clk data scan out write data = (xxxxxxxx) array address read data lsb lsb lsb lsb msb msb msb msb r/w = 0 1 27 chip address 01234567891011121314151617 01234567 14423-018 figure 18. timing diagram for reading a row of the transmitter serial interface transmitter register array assignments in the following table, n/a means not applicable. all register arrays are read/write, unless otherwise indicated. table 7. transmitter register array assignments register array row and bit internal signal name signal function row0 n/a not used. row1 row1, bit 7 pa_sel_vgbs<3> controls the regulator for the base voltage of the power amplifier output transistors. row1, bits[7:3] = 1100 for normal operation. row1, bit 6 pa_sel_vgbs<2> row1, bit 5 pa_sel_vgbs<1> row1, bit 4 pa_sel_vgbs<0> row1, bit 3 ifvga_q_cntrl<0> row1, bit 2 pa_sel_vref<2> controls the bias current for the pow er amplifier output transistors. row1, bits[2:0] = 010 for normal operation. row1, bit 1 pa_sel_vref<1> row1, bit 0 pa_sel_vref<0>
data sheet HMC6300 rev. b | page 15 of 25 register array row and bit internal signal name signal function row2 row2, bit 7 pa_sel_alc_dac<3> factory d iagnostics; row2 . bits[7:4] = 1111 for normal operation . row2, bit 6 pa_sel_alc_dac<2> row2, bit 5 pa_sel_alc_dac<1> row2, bit 4 pa_sel_alc_dac<0> row2, bit 3 pa_sep_pa_pwrdn_f ast active high for normal operation . row2, bit 2 pa_pwrdwn_fast active high for normal operation . row2, bit 1 pa_se_sel control for t x output i nterface; a ctive low for differential t x output ; a ctive high for t x single - ended output . row2, bit 0 power_de t_pwrdn active low to enable t x power detector . row3 row3, bit 7 driver_bias<2> controls the bias current for the power amplifier driver . row3 , bits[ 7:5 ] = 111 for normal operation . row3, bit 6 driver_bias<1> row3, bit 5 driver_bias<0> row3, bit 4 driver_bias2<2> controls the bias current for the power amplifier predriver 2 . row3 , bits[ 4:2 ] = 101 for normal operation . row3, bit 3 driver_bias2<1> row3, bit 2 driver_bias2<0> row3, bit 1 en_ifmix_hicg active high to enable high gain mode in if mi xer . row3, bit 0 en_tempflash active high to enable temperature sensor . row4 row4, bit 7 driver_pwrdn active high to power down the driver amp lifier . row4, bit 6 upmixer_pwrdn active high to power down the upmixer . row4, bit 5 ifvga_pwrdn active high to power down the if vga . row4, bit 4 divider_pwrdn active high to power down the divider . row4, bit 3 pa_pwrdn active high to power down the power amplifier . row4, bit 2 rfvga_pwrdn active high to power down the rf vga . row4, bit 1 tripler_pwrdn activ e high to power down the tripler . row4, bit 0 if_upmixer_pwrdn active high to power down the if upmixer . row5 row5, bit 7 tripler_bias<13> controls bias of frequency tripler. row5, bits[7:0] = 11111111 for normal operation. row5, bit 6 tripler_bias< 12> row5, bit 5 tripler_bias<11> row5, bit 4 tripler_bias<10> row5, bit 3 tripler_bias<9> row5, bit 2 tripler_bias<8> row5, bit 1 tripler_bias<7> row5, bit 0 tripler_bias<6> row6 row6, bit 7 tripler_bias<5> controls bias of frequency tripl er. row6, bits[7:2] = 111011 for normal operation. row6, bit 6 tripler_bias<4> row6, bit 5 tripler_bias<3> row6, bit 4 tripler_bias<2> row6, bit 3 tripler_bias<1> row6, bit 2 tripler_bias<0> row6, bit 1 n/a not used . row6, bit 0 row7 row7 , bit 7 ifvga_vga_adj<3> if variable gain amplifier gain control bits. row7, bits[7:4] = 0000 is highest gain and 1101 is lowest gain. atte nuation is 1.3 db per step, 17 db maximum. row7, bit 6 ifvga_vga_adj<2> row7, bit 5 ifvga_vga_adj<1> row7, bit 4 ifvga_vga_adj<0>
HMC6300 data sheet rev. b | page 16 of 25 register array row and bit internal signal name signal function row7, bit 3 ifvga_tune<3> controls the tuning of the if filter for the variable gain amplifier. row7, bits[3:0] = 1 111 for normal operation. row7, bit 2 ifvga_tune<2> row7, bit 1 ifvga_tune<1> row7, bit 0 ifvga_tune<0> row8 row8, bit 7 ifvga_bias<3> controls the bias current of the if variable gain amplifier. row8, bits[7:4] = 1000 for normal operation. row8 , bit 6 ifvga_bias<2> row8, bit 5 ifvga_bias<1> row8, bit 4 ifvga_bias<0> row8, bit 3 if_upmixer_tune<3> controls the tuning of the if filter for the if to rf upmixer. row8, bits[3:0] = 1111 for normal operation. row8, bit 2 if_upmixer_tune<2> row 8, bit 1 if_upmixer_tune<1> row8, bit 0 if_upmixer_tune<0> row9 row9, bit 7 ifvga_q_cntrl<2> controls the q of the if filter in the baseband to if upmixer. row9, bits[7:5] = 000 for the highest q and highest gain. to reduce q and widen bandwidth, in crement row9, bits[7:5] in sequence, as follows: 001 100 101 row9, bit 6 ifvga_q_cntrl<1> row9, bit 5 ifvga_q_cntrl<0> row9, bit 4 n/a not used. row9, bit 3 row9, bit 2 row9, bit 1 row9, bit 0 row10 row10, bit 7 enable_fm active high t o enable fsk/msk modulation inputs. 0 = normal i/q operation. row10, bit 6 if_refsel reserved for diagnostic purposes. row10, bits[6:5] = 10 for normal operation. row10, bit 5 bg_monitor row10, bit 4 endig_ifvga_gain_control active high to enable digit al control of ifvga gain. row10, bit 3 ipc_pwrdn active high to power down the chip current reference generator. row10 , bit 2 if_bgmux_pwrdn active high to power down one of three on - chip band gap references (if) and associated mux. row10, bit 1 upmix_c al_pwrdn active high to power down upmixer calibration. row10, bit 0 tempsensor_pwrdn active high to power down the temperature sensor. row11 row11, bit 7 rfvgagain<3> rf variable gain amplifier control bits. row11, bits[7:4] gain settings as follows: 0000 = highest gain. 1111 = lowest gain. attenuation is 1.3 db/step, 17 db maximum. row11, bit 6 rfvgagain<2> row11, bit 5 rfvgagain<1> row11, bit 4 rfvgagain<0> row11, bit 3 enrfvga_ana active high to enable analog gain control of rfvga. row11, bit 2 rfvga_ictrl<2> controls bias curr ent of rf variable amplifier. row11, bits[2:0] = 011 for normal operation. row11, bit 1 rfvga_ictrl<1> row11, bit 0 rfvga_ictrl<0> row12 row12, bit 7 upmix_cal<7> 3 lo feedthrough calibration of rf upmixer. row12, bits[7:0] = 01100100 for uncalib rated operation. row12, bit 6 upmix_cal<7> row12, bit 5 upmix_cal<7> row12, bit 4 upmix_cal<7> row12, bit 3 upmix_cal<7>
data sheet HMC6300 rev. b | page 17 of 25 register array row and bit internal signal name signal function row12, bit 2 upmix_cal<7> row12, bit 1 upmix_cal<7> row12, bit 0 upmix_cal<7> row13 n/a not used. row14 n/a not used. row15 n/a not used. row16 row16, bit 7 byp_synth_ldo factory diagnostics. 0 = normal operation. row16, bit 6 en_cpshort factory diagnostics. 0 = normal operation. row16, bit 5 en_cpcmfb enables cmfb circuit for charge pump, set to 1 when synth esizer is in use. row16, bit 4 en_cp_dump enables auxiliary circuit for charge pump, set to 1 when synthesizer is in use. row16, bit 3 en_cptrist factory diagnostics. 0 = normal operation. row16, bit 2 en_cp enables charge pump, set to 1 when synthe sizer is in use. row16, bit 1 en_synth_ldo enables ldo for synthesizer, set to 1 when synthesizer is in use. row16, bit 0 enbar_synthbg factory diagnostics. 0 = normal operation. row17 row17, bit 7 en_lockd_clk enables lock detector for synthesize r, set to 1 when synthesizer is in use. row17, bit 6 en_test_divout factory diagnostics. 0 = normal operation. row17, bit 5 en_vtune_flash enables flash adcs for vco vtune port, set to 1 when synthesizer is in use. row17, bit 4 en_rebuf_dc enables dc coupling for reference clock buffer. row17, bit 3 en_refbuf enables reference clock buffer, set to 1 when synthesizer is in use. row17, bit 2 en_stick_div factory diagnostics. 0 = normal operation. row17, bit 1 en_fbdiv_cml2cmos enables auxiliary ci rcuit for the feedback divider chain, set to 1 when synthesizer is in use. row17, bit 0 en_fbdiv enables feedback divider chain, set to 1 when synthesizer is in use. row18 row18, bit 7 n/a not used. row18, bit 6 en_nb250m active high to enable, 250 m hz channel step size. row18, bit 5 byp_vco_ldo factory diagnostics. 0 = normal operation. row18, bit 4 en_extlo enables external lo, set to 0 when synthesizer is in use . row18, bit 3 en_vcopk factory diagnostics. 0 = normal operation. row18, bit 2 en_vco enables internal vco, set to 1 when synthesizer is in use . row18, bit 1 en_vco_reg enables internal regulator for vco, set to 1 when synthesizer is in use . row18, bit 0 enbar_vcogb factory diagnostics. 0 = normal operation. row19 row19, b it 7 n/a not used. row19, bit 6 row19, bit 5 row19, bit 4 row19, bit 3 row19, bit 2
HMC6300 data sheet rev. b | page 18 of 25 register array row and bit internal signal name signal function row19, bit 1 refsel_synthbg factory diagnostics. 1 = normal operation. row19, bit 0 muxref factory diagnostics. 0 = normal operation. row20 row20 , bit 7 n/a not used. row20, bit 6 fbdiv_code<6> feedback divider ratio for the integer - n synthesizer based on table 8 to table 10 . row20, bit 5 fbdiv_code<5> row20, bit 4 fbdiv_code< 4> row20, bit 3 fbdiv_code<3> row20, bit 2 fbdiv_code<2> row20, bit 1 fbdiv_code<1> row20, bit 0 fbdiv_code<0> row21 row21, bit 7 n/a not used. row21, bit 6 row21, bit 5 row21, bit 4 refsel_vcobg factory diagnostics. 1 = normal opera tion. row21, bit 3 vco_biastrim<3> sets vco tank bias current. row21, bit 2 vco_biastrim<2> row21, bits[3:0] = 0010 for normal operation. row21, bit 1 vco_biastrim<1> row21, bit 0 vco_biastrim<0> row22 row22, bit 7 n/a not used. row22, bit 6 row22, bit 5 row22, bit 4 vco_bandsel<4> set for desired frequency. table 8 , table 9 , and table 10 contain approximate band settings depending on the reference clock frequenc y. row22, bits[4:0] = valid range 00000 to 10011. row22, bit 3 vco_bandsel<3> row22, bit 2 vco_bandsel<2> row22, bit 1 vco_bandsel<1> row22, bit 0 vco_bandsel<0> row23 row23, bit 7 icp_biastrim<2> sets charge pump current . row23, bit 6 icp_bia strim< 1 > row23, bits[7:5] = 011 for normal operation. row23, bit 5 icp_biastrim< 0 > row23, bit 4 vco_offset<0> sets internal vco output swing. row23, bit 3 vco_offset<1> row23, bits[4:0] = 00010 for normal operation. row23, bit 2 vco_offset<2> row23 , bit 1 vco_offset<3> row23, bit 0 vco_offset<4> row24 (read only) row24, bit 7 n/a not used. row24, bit 6 row24, bit 5 row24, bit 4 row24, bit 3 lockdet monitor for lock detect. 1 = valid lock. row24, bit 2 dn monitor vco amplitude. row24, bit 1 up monitor vco amplitude. row24, bit 0 center monitor vco amplitude. row25 (read only)
data sheet HMC6300 rev. b | page 19 of 25 register array row and bit internal signal name signal function row25, bit 7 vtune_flashp<7> vco amplitude monitor (positive) . row25, bit 6 vtune_flashp<6> row25, bit 5 vtune_flashp<5> row25, bit 4 vtune_flashp <4> row25, bit 3 vtune_flashp<3> row25, bit 2 vtune_flashp<2> row25, bit 1 vtune_flashp<1> row25, bit 0 vtune_flashp<0> row26 (read only) row26, bit 7 vtune_flashn<7> vco amplitude monitor ( negative ) . row26, bit 6 vtune_flashn<6> row26, bit 5 vtune_flashn<5> row26, bit 4 vtune_flashn<4> row26, bit 3 vtune_flashn<3> row26, bit 2 vtune_flashn<2> row26, bit 1 vtune_flashn<1> row26, bit 0 vtune_flashn<0> row27 (read only) row27, bit 7 n/a not used. row27, bit 6 row27, bit 5 row27, bit 4 temps<4> thermometer encoded temperature reading. row27, bit 3 temps<3> for row27, bits[4:0], the temperature reading is as follows: row27, bit 2 temps<2> 00000 = lowest temperature. row27, bit 1 temps<1> 11111 = highest temperature. row27, bit 0 temps<0> row28 n/a not used. row29 n/a not used. row30 n/a not used. row31 n/a not used.
HMC6300 data sheet rev. b | page 20 of 25 synthesizer settings table 8. synthesizer settings, ieee channels using 154.2857 mhz reference frequency (ghz) ieee channel divider setting, fbdiv_code<5:4>, row20, bits[5:0] typical band setting, vco_bandsel<4:0>, row22, bits[4:0] 57.24 001010 00001 57.78 001011 00010 58.32 channel 1 001100 00010 58.86 001101 00010 59.40 001110 00011 59.94 001111 00011 60.48 channel 2 010000 00100 61.02 010001 00100 61.56 010010 00101 62.10 010011 00101 62.64 channel 3 010100 00101 63.18 010101 00110 63.72 010110 00110 64.26 010111 00110 64.8 channel 4 011000 00111 65.34 011001 00111 65.88 011010 01000 table 9. 500 mhz channels using 142.8571 mhz reference frequency (ghz) divider setting typical band setting 56.5 010001 00001 57 010010 00001 57.5 010011 00010 58 010100 00010 58.5 010101 00010 59 010110 00011 59.5 010111 00011 60 011000 00100 60.5 011001 00100 61 011010 00101 61.5 011011 00101 62 011100 00101 62.5 011101 00110 63 011110 00110 63.5 011111 00110 64 100000 00111
data sheet HMC6300 rev. b | page 21 of 25 table 10. 250 mhz channels using 71.42857 mhz reference frequency (ghz) divider setting typical band setting 56.5 0100010 00001 56.75 0100011 00001 57 0100100 00010 57.25 0100101 00010 57.5 0100110 00011 57.75 0100111 00011 58 0101000 00100 58.25 0101001 00100 58.5 0101010 00101 58.75 0101011 00101 59 0101100 00110 59.25 0101101 00110 59.5 0101110 00111 59.75 0101111 00111 60 0110000 01000 60.25 0110001 01000 60.5 0110010 01001 60.75 0110011 01001 61 0110100 01010 61.25 0110101 01010 61.5 0110110 01011 61.75 0110111 01011 62 0111000 01100 62.25 0111001 01100 62.5 0111010 01101 62.75 0111011 01101 63 0111100 01110 63.25 0111101 01110 63.5 0111110 01111 63.75 0111111 01111 64 1000000 01111
HMC6300 data sheet rev. b | page 22 of 25 applications information for more information about the HMC6300 evaluation kit, see the ek1hmc6350 user guide . the ek1hmc6350 contains all that is required to set up a simplex 60 ghz millimeterwave link using standard rf cable interfaces for baseband input and output. the kit comes with two motherboard printed circuit boards (pcbs) that provide on-board crystals, usb interface, supply regulators, and sma cables for connectorized i/q interfaces. software is supplied to allow the user to read from and write to all chip level registers using graphical user interface (gui) or to upload previously saved register settings. 14423-019 figure 19. evaluation pcb daughter board
data sheet HMC6300 rev. b | page 23 of 25 j4 qth-030-01-f-d-a grounding ps_4v_2 data gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd enable clk tx_scanout reset bb_qm bb_qp bb_im bb_ip tx_refclkm tx_refclkp fmp_i fmm_i fmp_q fmm_q ps_4v_2 gnd gnd gnd gnd gnd gnd gnd ana_rfvga ana_rfvga tx_vcc_pa tx_vcc_rfvga tx_vddd tx_vcc_trip tx_vcc_trip tx_vcc_vco tx_vcc_vco tx_vdd_syn nc tx_vcc_div tx_vcc_div tx_vcc_if tx_vcc_mix tx_vcc_drv tx_vcc_drv ref_out dect_out ps_4v_1 ps_4v_1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 HMC6300 u1 rfoutn rfoutp extfil_p extfil_n det_out ref_out bb_qm bb_qp bb_im bb_ip fmm_q fmp_q vreg_out vco_rcap vcc_mix vcc_if vcc_trip vcc_rfvga vcc_pap vcc_pan vcc_div vcc_div vcc_div extlo_n extlo_p fmm_i fmp_i rfb scanout reset data enable clk ana_ifvga vss_div vss_lpf_bias_pll vss_cp_pfd vss_ref_dig vss_vco vss_vco vss_vco vss_vco vss_vco vss_vco vdd_pa vdd_syn vddd gnd gnd gnd gnd gnd gnd vcc_drv vcc_drv vcc_vco vcc_vco rfoutn dect_out rfb ref_out bb_qm bb_qp bb_im bb_ip fmm_q tx_vcc_mix tx_vcc_if fmp_q tx_out j1 rfoutp extlo_n extlo_p 1 f1 4mil-balun_60ghz 3 2 j3 sma sma j2 r1 1k ? c30 1nf c29 100nf c28 100nf c26 1f depop r4 1k ? fmp_i fmm_i rfb tx_scanout reset data enable clk ana_ifvga tx_vcc_pa tx_vdd_syn tx_vddd r5 0 vss_gnd c15 1nf c24 1nf c12 1nf r3 1k? c20 1nf c21 1nf tx_vcc_trip tx_vcc_rfvga ps_4v_1 ps_4v_2 tx_vcc_div tx_vcc_drv tx_vcc_vco c23 1nf c14 1nf c22 1nf c16 1nf c31 1nf c32 1nf c17 1nf c27 100pf e1 a1 a2 a4 a5 a6 a7 a8 a9 f11 g12 b3 b4 g7 g3 a12 b11 b1 g1 a3 h1 g10 g11 b5 b6 b7 b8 c1 f1 b12 d1 b9 b10 h8 h9 a10 a11 b2 g4 g6 h3 h4 h5 h6 ana_rfvga ana_rfvga h2 ref_clkp tx_refclkp d12 ref_clkn tx_refclkn e12 c11 d11 e11 c12 g8 h10 h7 h11 h12 g2 f12 g5 g9 depop depop depop 92_mmpx-s50-0-1/111_nm-1 14423-020 figure 20. evaluation daug hter board pcb schematic
HMC6300 data sheet rev. b | page 24 of 25 usb-led pwr-supply-led sel1 mux usb 5v supply ext clock vout ip vout im bb qp bb im bb ip vout qp vout qm fmp q fmm q fmm i fmp i bb qm 600-01205-00-2 mux sel0 12 1 2 rx module tx module dect out ref out tx ifvga tx rfvga rx lna ctl rx ifvga 60 ghz evaluation board 1 2 60 59 + + + + + + + + 1 2 60 59 r155 c82 r159 r88 j28 c2 c9 j20 fb1 fb2 fb4 fb6 c1 c10 c11 c12 c13 c14 c21 c85 c88 c24 c25 c26 c28 c3 c86 c4 c42 c43 c44 c45 c46 c47 c48 c49 c5 c50 c51 c52 c6 c63 c64 c65 c66 c67 c68 c69 c7 c70 c89 c8 c58 c93 c90 c56 u3 u15 u16 d1 d4 d7 d8 j8 r119 r157 r161 r13 r15 r17 r19 r21 r22 r23 r24 r56 r57 r58 r69 r62 r63 r64 r65 r66 r68 r67 r70 r71 r72 r73 r131 r82 r85 r86 r87 r89 r90 r91 r92 r93 r94 r95 r96 r97 r98 r99 r167 r178 r123 r128 r129 r14 r16 r18 r20 r32 r59 r77 r103 r61 r79 j10 j11 j12 j13 j14 j15 j16 j17 j18 j19 j21 j9 u19 j26 j27 j1 y1 r180 r166 r169 r168 r176 r183 r177 r172 r184 r181 r175 r174 r170 r171 c84 c87 y4 y3 u17 u18 u11 r153 r152 c79 r158 j30 c80 c81 c83 c91 c92 c95 c94 r130 r154 r156 r160 r162 r163 r60 r165 r173 r182 r179 r164 u22 j31 j32 j33 j34 j29 c102 c101 c110 c96 c105 c99 c108 c103 c97 c106 c100 c109 u27 u26 u23 u24 r186 r195 r188 r189 r187 r190 r191 r192 r193 u25 c104 c98 c107 r194 r185 14423-021 figure 21. evaluation pcb motherboard
data sheet HMC6300 rev. b | page 25 of 25 outline dimensions 0.815 0.755 0.695 6.050 6.000 5.950 bottom view (ball side up) ground area top view (ball side down) side view 0.220 0.190 0.160 0.595 0.565 0.535 0.310 0.270 0.230 4.050 4.000 3.950 3.50 ref 5.50 ref 5.75 ref coplanarity 0.10 se a ting plane 01-25-2016- a 0.50 bsc 0.25 bsc 0.25 bsc pkg-005029 0.50 bsc 0.858 0.425 0.406 1. 1 15 0.455 0.075 1.258 1.03 bal l a1 identifier a b c d e f g h 1 2 3 4 5 6 7 8 9 10 11 12 figure 22 . 65 - ball wafer level ball grid array [wlbga] (bf - 65 - 1) dimensions shown in millimeters ordering guide model temperature range msl rating 1 package description package option branding 2 HMC6300bg46 ?40c to +85c msl1 65- ball wafer level ball grid array [wlbga] bf - 65- 1 bbfz #yyww xxx xxxxx - xx e v1HMC6300bg46 evaluation board, pcb only ek1hmc6350 60 ghz smt transceiver evaluation kit 1 maximum peak reflow temperature o f 260c. the peak reflow temperature must not exceed the maximum temperature for which the package is qualified according to the moisture sensitivity level (msl1). 2 bbfz = rohs compliant part, #yyww indicates the year and week number, and the assembly lot number is indicated by xxxxxxxx - xx. ? 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prope rty of their respective owners. d14423 - 0 - 12/16(b)

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