ICM7712 rev a1.5 i cm i c reserves the r i gh t to change s p e c i f i c a t i on s w i t hou t p r i o r no t i c e 1 ic m icrosystem s ic m ic tm ic m icrosystem s ic m ic tm 12-bit 1.2v low power single dac with serial interface and voltage o utput features ? 12-bit 1.2v single dac in 8 lead tssop package ? ultra-low power consumption ? guaranteed monotonic ? wide voltage output swing buffer ? three-wire spi/qspi and micro-wire interface compatible ? schmitt-triggered inputs for direct interfacing to opto-couplers application ? battery-powered applications ? audio applications ? industrial process control ? digital gain and offset adjustment dnl plot overview the ICM7712 is a 12-bit voltage output, ultra low power, single dac, with guaranteed monotonic behavior. this dac is available in 8- lead tssop package. the input interface is an easy to use three-wire spi, qspi and micro-wire compatible interface. the dac has schmitt- triggered inputs for direct interfacing to opto-couplers easily. block diagram inl plot vo ICM7712 amplifier input register dac sdi sck refin input control logic, registers and latches dac register cs
ICM7712 rev a1.5 i cm i c reserves the r i gh t to change s p e c i f i c a t i on s w i t hou t p r i o r no t i c e 2 8 7 6 5 package 08 l ea d ts s o p sck 1 sdi 2 cs 3 nc 4 refin g nd vdd vo t o p v i e w pin description (8 lead tssop) p i n n a m e i / o d e s c r i p t i on 1 s c k i s e r i a l c l oc k i npu t ( c m o s ) 2 s d i i s e r i a l data i npu t ( c m o s ) 3 c s i a c t i v e low c h i p s e l e c t ( c m o s ) 4 n c - no c onn e c t i on 5 v o o dac output v o l t a g e 6 v dd i s upp l y v o l t a g e 7 g nd i g r ound 8 re f i n i r e f e r e nc e v o l t a g e i npu t absolute maximum ratings symbol parameter v a l u e u n i t v dd s upp l y v o l t a g e 0.9 to 1.32 v i in i npu t current +/- 25.0 m a v i n d i g i t a l i npu t v o l t a g e (sck, s d i , cs ) -0.3 to 1.32 v v i n _ re f r e f e r e nc e i npu t v o l t a g e -0.3 to 1.32 v t stg storage temperature -65 to +150 o c t sol s o l d e r i ng temperature 300 o c stress greater than those li s t e d under absolute maximum r a t i n g s may cause permanent damage to t h e d e v i c e . t h i s i s a s tr e ss r a t i ng on l y and f un c t i on a l op e r a t i on of the d e v i c e at these or any other c ond i t i on s a bo v e those i nd i c a t e d i n the op e r a t i on a l s e c t i on s of t h i s s p e c i f i c a t i on i s not i m p li e d. exposure to a b s o l u t e m a x i m u m r a t i ng c ond i t i on s for extended p e r i od s may a ff e c t r e li a b ili ty .
ICM7712 rev a1.5 i cm i c reserves the r i gh t to change s p e c i f i c a t i on s w i t hou t p r i o r no t i c e 3 ordering information part operating temperature range p ac k a g e i c m 7712 -40 o c to 85 o c 08 - l ea d ts s o p dc electrical characteristics (specification: vdd=1.2v, vrefin=1.15v, temp =25c, unless otherwise specified) symbol parameter test conditions min typ max u n i t dc p er f or m an ce n r e s o l u t i on 12 b i t s dn l d i ff e r e n t i a l n on li n ea r i ty (notes 1 & 3) 0.4 + 1.0 l s b i n l i n t e g r a l n on li n ea r i ty (notes 1 & 3) 1 + 12 l s b s t a t i c accuracy ge g a i n e rr o r + 0.5 % of fs oe o ff s e t e rr o r 25 m v power r e q u i r e m e n t s v dd s upp l y v o l t a g e 0.9 1.2 1.32 v i dd s upp l y current fu ll s c a l e at v dd = 1.2 490 1000 a output c ha r a c t er i s t i c s v ou t output v o l t a g e range (note 3) 0 v dd v vo s c short c i r cu i t c u rr e n t 4 13 m a ac electrical characteristics (specification: vdd=1.2v, refin=1.15v,temp=25c, u nless otherwise specified) symbol parameter test conditions min typ max u n i t sr s l e w r a t e 4 v / s ts s e tt li ng t i m e (note 5) 2 s fs conversion speed 200 ksps td analog output delay (note 4) 150 ns note 1: l i n ea r i ty i s d e f i n e d f r o m code 127 to 3970 ( i c m 7712 ) note 2: guaranteed by d e s i gn ; not tested i n p r odu c t i on note 3: see a pp li c a t i on s i n f o r m a t i on note 4: output delay measured from the 50% point of the rising edge of input data to the full scale transition note 5: settling time measured from the 50% point of full s cale transition to the output remaining within 1/2l sb.
ICM7712 rev a1.5 i cm i c reserves the r i gh t to change s p e c i f i c a t i on s w i t hou t p r i o r no t i c e 4 timing characteristics (v dd = 0.9v to 1.32v, a ll s p e c i f i c a t i on s t min to t max un l e ss o t h e rw i s e no t e d ) s ym bo l parameter test c ond i t i on s m i n t y p m a x u n i t t 1 sck c y c l e t i m e (note 2) 30 n s t 2 data setup t i m e (note 2) 10 n s t 3 d ata h o l d t i m e (note 2) 10 n s t 4 sck f a lli ng edge t o cs rising edge (note 2) 0 n s t 5 cs f a lli ng edge to sck r i s i ng edge (note 2) 10 n s t 6 cs p u l s e w i d t h (note 2) 20 n s timing diagram clk 50% td vout 50% 0000..0000 1111..1111 data 0.5lsb vout ts
ICM7712 rev a1.5 i cm i c reserves the r i gh t to change s p e c i f i c a t i on s w i t hou t p r i o r no t i c e 5 serial interface timing and operation diagram t 5 t 1 t 4 t 6 cs sck sd i c3 c2 c1 d0 t 2 t 3 msb lsb figure 1. serial interface timing diagram cs (enable sck) (update output) sck 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sd i c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb figure 2. serial i n t e r f ace operation di a g r a m contents of input shift register d e v i ce control word data w or d m s b l s b i c m 7712 c3 c2 c1 c0 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 figure 3. contents of i npu t shift r e g i s t e r
ICM7712 rev a1.5 i cm i c reserves the r i gh t to change s p e c i f i c a t i on s w i t hou t p r i o r no t i c e 6 function c3 c2 c1 c0 data d f un c t i o n 0 0 0 0 (d11~d0) i npu t l o a d e d i n t o dac, vo upd a t e d table 1. serial interface input word detailed description the ICM7712 is a 12-bit voltage output dac. this device has a 16-bit input shift register and the dac has a double buffered digital input. this dac has a guaranteed monotonic behavior and the operating supply range is from 0.9v to 1.32v. reference input the reference input accepts positive dc and ac signals. the voltage at refin sets the full-scale output voltage of the dac. to determine the output voltage for any code, use the following equation. vout = vref x (d / (2 n )) where d is the numeric value of dac?s decimal input code, vref is the reference voltage and n is number of bits, i.e. 12 for ICM7712. output buffer amplifier this amplifier has a wide output voltage swing. the actual swing of the output amplifier will be limited by offset error and gain error. see the applications information section for a more detailed discussion. the output amplifier can drive a load of 2.0 k ? to vdd or gnd in parallel with a 500 pf load capacitance. the output amplifier has a full-scale typical settling time of 2 s and it dissipates about 500 a with a 1.2v supply voltage. serial interface and input logic this dac uses a standard 3-wire connection compatible with spi/qsp and micro wire interfaces. data is always loaded in 16-bit words which consist of 4 control bits (msbs) followed by 12 bits (see figure 3). serial data input sdi (serial data input) pin is the data input pin for the dac. data is clocked in on the falling edge of sck which has a schmitt trigger internally to allow for noise immunity on the sck pin. this specially eases the use for opto- coupled interfaces. the chip select pin which is the 3rd pin of 8 lead tssop package is active low. this pin frames the input data for synchronous loading and must be low when data is being clocked into the part. there is an onboard counter on the clock input and after the 16th clock pulse the data is automatically transferred to a 16-bit input latch and the 4 bit control word (c3~c0) is then decoded and the appropriate command is performed depending on the control word (see table 1). chip select pin must be pulled high (level-triggered) and back low for the next data word to be loaded in. this pin also disables the sck pin internally when pulled high.
ICM7712 rev a1.5 i cm i c reserves the r i gh t to change s p e c i f i c a t i on s w i t hou t p r i o r no t i c e 7 applications information power supply bypassing and layout considerations as in any precision circuit, careful consideration has to be given to layout of the supply and ground. the return path from the gnd to the supply ground should be short with low impedance. using a ground plane would be ideal. the supply should have some bypassing on it. a 10 f tantalum capacitor in parallel with a 0.1 f ceramic with a low esr can be used. ideally these would be placed as close as possible to the device. avoid crossing digital and analog signals, specially the reference, or running them close to each other. deadband figure 4. effect of negative offset output swing limitations the ideal rail-to-rail dac would swing from gnd to vdd. however, offset and gain error limit this ability. figure 4 illustrates how a negative offset error will affect the output. the output will limit close to ground since this is single supply part, resulting in a dead-band area. as a larger input is loaded into the dac the output will eventually rise above ground. this is why the linearity is specified for a starting code greater than zero. figure 5 illustrates how a gain error or positive offset error will affect the output when it is clos e to vdd. a positive gain error or positive offset will cause the output to be limited to the positive supply voltage resulting in a dead-band of codes close to full-scale. figure 5. effect of gain error and positive offset vdd vdd offset and gain error dead band positive offset negative offset
rev a1 . 5 i c m i c r e s e r v es the package i n for m a t i o n 8 lead tss o p the r i g h t to c ha n ge s p e c i f i c a t i on s w i t hou t p r i o r no t i c e ICM7712 e 8
ICM7712 rev a1.5 i cm i c reserves the r i gh t to change s p e c i f i c a t i on s w i t hou t p r i o r no t i c e 9 package i n for m a t i o n icm77x2 p g device 1 - ICM7712 g = rohs compliant lead-free package . blank = standard package. non lead-free. package t = 8-lead tssop
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