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as91l1001 july 2004 jtag test controller description t he as91l 10 01 devic e pr o v ides an interf ace b e t w e e n th e 6 0 x b u s on th e mo to rol a mpc 8260 process o r a n d t w o tota ll y ind e p end ent ieee114 9.1 interfaces, n a m el y , th e prim ar y and sec o n dar y ports. it han dles al l th e protoco l for th e 60 x bus to w r i t e an d re ad directl y to reg i sters w i t h in th e devic e w i th no ad diti ona l g l ue l o gi c. t he as91l 10 01 has t h ree distinct m odes of oper ation, na mel y slav e m ode, master mode, a nd 3 rd part y sup port mode. t hese d i fferent mo des control ho w data w i ll be tra n sferred o n the ieee1149.1 b u ses. sla v e mode : t h is is the d e f ault mo de after the as91l 10 01 h a s receive d a p o w e r-on r e set. in this mod e , there is a tran spare n t co nne ction bet w e en the prima r y and seco nd ar y jt ag ports. t he processor interfac e i s not use d in th e slave mo de. t h is confi gur atio n is t y p i ca ll y used to test a lin e car d from a s y stem bac k pla n e (th e primar y p o rt is usual l y c o n n e c ted to the bac k plan e an d the seco nd ar y port is con n e c ted to the o n boar d jt ag chai n). once testing from th e s y stem bac k pl ane i s compl e ted, the as91l1 00 1 i s reconfig ured for master mode o per atio n throug h a reg i ster. t he master mode o f oper ation is u s ed to test the onb oar d jt ag chain, usin g the micro p rocess or inter f ace. maste r mo d e : t h is mode is access ed v i a a comman d to a as91l 10 01 r egister. t he ke y fe ature of this mod e is th at both the pr i m ar y an d s e c ond ar y ar e no w b o th total l y i nde pe nd ent ieee1149. 1 bu s masters, w h ich e n a b le conc urrent oper ation o n both th e ieee1149. 1 c han nels. t he master mod e ena bles the primar y ieee1 149.1 cha n n e l to be use d to acces s other pcb ? s conn ected vi a the 5- w i r e ieee114 9. 1 interface o n th e back pl an e. t he secondar y ieee1 149.1 port is use d to test the card th at is h o sting th e as9 1l1 00 1. t h is mode may be used for performing interconnect te sti n g or f l ash/cpl d pr ogrammi ng. key features interprets between the motorola mpc8260 pro c e s sor a n d two ieee1149.1 port s thre e distin ct modes of o peratio n: slave mode, maste r mode, and 3 rd party supp ort mod e suppo rts a wi de ran ge of 3 rd party tools pinout and feature set compatible (complete se con d so urce) with the fi recron jts01 device available in a 100 -pin lqfp o r a 100 -pi n fpbga lead free pa ckag e d e vice block d i agr a m figure 1 - as91l10 01 jt ag te st con t roller alliance semiconductor 2575 augusti ne dr i v e ? santa clara, ca 95054 ? p: 408-855-4900 ? f: 408-855-4 999 ? w w w . a l sc.com
july 2004 as91l1001 description (cont.) mpc 8260 bac k p l an e t r s t bac k p l an e t d i bac k p l an e t d o bac k p l an e t m s b a c k pl an e t c k b a c k pl an e a u to- w r as 91l100 1 a s 9 1l1003 ie ee 11 49. 1 sec ond ary port o n bo ar d j t ag ch a i n i e e e 1149 .1 p r i m ary po rt figure 2 - slav e mode mpc 8260 as 91l100 1 s e co ndar y i e e e 1 149. 1 p o r t pr i m a r y i e e e 1 149. 1 p o r t bac k p l an e t r s t bac k p l an e t d i bac k p l an e t d o bac k p l an e t m s b a c k pl an e t c k b a c k pl an e a u to- w r a s 9 1l1003 bv f d a ta 3r d p a rt y da t a figure 3 - m aste r mode 3 rd part y support mode : this mode is intende d to sup port leg a c y fpga/cp l d 11 49.1 device s tha t require adaptive p r ogra mming algorith m s to ensure data retention, due to the fact that deci s ion bran chi ng is not sup p o r te d in service vector form at (svf). t h is m ode will not be requi red for devices that adhere to the ieee1532 spe c ification, as ieee1532 compli ant pa rts from all cpld/fp g a vendors adhe re to this ope n stand ard. t h e 3 rd party sup port m o d e whi c h i s acce ssi ble vi a control r egi sters i n the as91l10 01 sele cts on e of the ieee1149.1 po rts to o perate with the st anda rd svf ->bvf flo w while the remai n ing ie ee1149.1 po rt will suppo rt comm and s for the emb edde d c co de ro utines provide d by fpga/cpld vendors. th is eliminate s any issu es rega rdi ng d a ta retentio n whe n u s ing the as91l10 01 o n a pcb. allia n c e semic o nd uc to r s u pp lie s a wind ows ? executa b le that conve r ts indust r y stand ard s v f into alliance semi con d u c tor prop rieta r y bvf file forma t. use r s of th e ansi c cod e a r e onl y req u ire d to provide th e base read and write fun c tion for the strea m i/o. so in orde r to execute a bvf file, the u s er ha s t o call the prima r y c fun c tion, whi c h will then p e rf orm all the requi re d setup of the as91l10 01 along with obtainin g the bvf file to pro c e s s at th e re quired time or rep o rt any erro rs if appli c able. if the user wi she s to emb ed the ansi c routine s fro m fpga/cpl d vendo rs, t hen this i s handl ed i n a very simila r manne r. a s one of the ieee1149.1 ports will be ope rating i n allian c e semico ndu ct or bvf mode , the method of readin g and writing d a ta is the sa me as befo r e . howeve r, the u s er will need to con s ult the 3 rd party routine s to see ho w th e data flo w is perfo rmed. ultimately, the user wi ll call a al liance semi con d u c tor provide d c ro utine that will set the as91l100 1 for 3 rd party support on on e of the ieee1149.1 cha nnel s while the ot her will be use d for executin g the 3 rd party c o de. in s u mmary, 3 rd party suppo rt mode enabl es seria l shifting of d a ta on any o f the two jtag port s and i s u s ed to config ure l ega cy fpga/cpld devic es . mpc8260 as 91l100 1 sec ond ar y ieee 1 149.1 por t pr i m a r y ieee 1 149.1 por t bvf da ta 3r d p a rt y da t a ba c k p l ane t r st ba c k p l ane t d i ba c k p l ane t d o ba c k p l ane t m s ba c k p l ane t c k ba c k p l ane aut o -w r as 91l100 3 figure 4 - 3 rd part y suppo rt mode www .a lsc.com alliance semiconductor 2 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1001 signal descriptio n pin name pin type pin num be r lqfp pin num be r fpbg a description resetn in 14 f4 this ac tive low res e t s i gnal res e t s the as91l10 01 a nd pla c e s the device in slave mode jts03 _06 _selectedn in 65 e10 this a c tive low input from either a as91l10 03 o r as91l10 06 provide s the cont rol st atus of the as91l10 03/06 con n e c ted to the secon d a r y port of the as91l10 01 (operating in slave mode) primar y ieee1149.1 port prim_t di inout 19 g3 ieee1149.1 primary te st data input in slave mode; in maste r mod e , this pin ac ts as tes t data output prim_t do inout 20 g1 ieee1149.1 primary te st data outp ut in slave mod e ; in master mode, this pi n acts a s te st data input prim_trst inout 22 h2 ieee1149.1 primary te st re set input in slave mod e ; in master mode, this pi n is an outp u t prim_tms inout 21 g2 ieee1149.1 primary te st mode sele ct in slave mod e ; in master mode, this pi n is an outp u t prim_tck inout 87 a6 ieee1149.1 primary te st clo ck in slave mode; in maste r mod e , this pin is an output prim_aut o w r in 16 f1 primary auto-write inp u t co ntrolled by test equipm e n t to shorte n flash memory programming, signal is driven low for write pulse secondary ieee1149.1 sec_tdo out 57 g10 ieee1149.1 test data ou tput on se c o nd ar y p o r t sec_tdi in 58 g8 ieee1149.1 test data inp u t on se c o nd ar y p o r t sec_trs t out 64 e9 ieee1149.1 test lo gic reset on se c o nd ar y p o r t sec_tms out 60 f9 ieee1149.1 test mod e select out on se c o nd ar y p o r t sec_tck out 61 f10 ieee1149.1 test cl ock o u t on se c o nd ar y p o r t sec_aut o w r out 63 f7 secon d a r y auto-write out put controlled by test equipm e n t to shorte n flash m e mo ry programmin g , signal i s driven lo w for write pul se www .a lsc.com alliance semiconductor 3 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1001 pin name pin type pin num be r lqfp pin num be r fpbg a description slave_mode out 71 this signal, when low, indicates that the as91l10 01 is in slave mode of operation master_m ode out 72 this signal, when lo w, indicates that the as91l10 01 is in the m a ster m ode of operatio n prim_t do_ o e out 27 this a c tive low sig nal de rived whil e in slave mode, provide s the control foradditio nal curre n t drive to the buffer on the prim ary tdo sig nal data(7:0 ) i n o u t 98,97,96,9 4 ,9392,85,8 4 lsb-msb a3,b3,a4,b4, c4,c 5,c6, c 7 ( lsb-msb) 8-bit data bu s for the processor interface addr(31:28 ) i n 83,81,80,7 9 lsb-msb b7,a7,b8,a8( lsb-msb) 4-bit add re ss bus for the p r ocesso r interface wrn in 77 b9 active low, write enabl e si gnal for the pro c e s sor int e rface rdn in 76 b10 active low re ad ena ble si g nal for the pro c e s sor int e rface csn in 78 a9 ac tive low, chip s e lec t s i gnal for the pro c e s sor int e rface osc_i n in 75 c10 this is th e master clo ck int o the as91l10 01 d e vice toe in 88 b6 test outp u t enable thi s sig nal wh en tak en low tris t a tes all devices i/o g n d p o w e r 11,26,43,5 9 ,74,95,2,17, 90,55,56,3 8 ,86 d6,g5, c3,j 9, g9,d7,e5,f6, g4,h8,a5,f2, b1 as91l10 01 grou nd conn ection v c c p o w e r 39,91,3,18, 34,51,66,8 2 ,23,54 d5, g6, c8, d4, e6, f5, g7, h3, h1, h9 as91l10 01 vcc conn ecti on asic_tck in 62 f8 ieee1149.1 asic test asic_tms in 15 f3 ieee1149.1 asic test asic_tdo out 73 ieee1149.1 asic test asic_tdi in 4 ieee1149.1 asic test www .a lsc.com alliance semiconductor 4 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1001 pin name pin type pin num be r lqfp pin num be r fpbg a description no conn ect s 1,5,6,7,8,9, 10,12,13,2 4 ,25,27,28, 29,30,31,3 2 ,33, 35,36,37,4 0 ,41, 42,44,45,4 6 ,47, 48,49,50,5 2 ,53, 67,68,69,7 0 ,71, 72,89,99,1 0 0 c1,b5,e4,e3, e1,e2,a2,b2, c2,d 3,d1, d 2 , j 1 ,k1,k2,c9, d8,d10,d9,e 7,e8,j2,k3,j3 ,h4,j 4 ,k4, h5, j 5 ,k5,k6,j 6, h 6,k7,j7,h7, j 8 ,k8,k10,j10, h10 table 1 - as 91l10 01 signal desc ripti on absolute maximum ratings parameter maximum range supply voltage (vcc) -0.3v to 5.5v dc inp u t voltage (vi) -0.5v to vcc +0.5v max sink cu rrent whe n vi = -0.5v -20ma max sou r ce current wh en vi = vcc + 0. 5v +20ma max jun c tion tempe r ature with power a pplied tj +12 5 deg ree s c max storage temperature -55 to +150 d egre e c table 2 - ab solute ma ximum rating s note: str ess abov e the stated maximu m v a lues ma y cause irreparable dam a ge to the d e v i ce, correc t oper a tion of the dev i ce at these v a lues is not guar a nte e d. www .a lsc.com alliance semiconductor 5 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1001 recommended operating conditions parameter opera t ing range supply voltage (vcc) 3.0v to 3.6v input voltage (vi) 0v to vcc output voltag e (vo) 0v to vcc operating te mperature (t a) comm ercial 0 c to 70 c industri a l (ta ) -40 de g c to +85 d eg c, 3. 00v to 3.6v table 3 - re commended opera t ing conditions dc electrical characteristics sy mbol parameter min max conditio n v ih minimum hi g h input voltage 2.0 5.25 v il maximum lo w input voltage -0.3v 0.8v sy mbol parameter value conditio n v oh minimum hi gh output voltage 2.4v ioh=2 4 ma or 8ma as defined by pi n v ol minimum lo w output voltage 0.4v iol=24ma o r 8ma as defined by pi n i oz tris tate output leak age -10 o r 10 ma i cc maximum qui ece nnt s u pp ly c u rr ent 2ma i ccd maximum dynamic s u pp ly c u rr ent 80ma tck freq e q u a l to 10 mhz table 4 - as 91l10 01 dc electrical ch arac teris t ics www .a lsc.com alliance semiconductor 7 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1001 packaging information the as91l1 0 01 is availa ble in a 100-pin lqfp or a 1 00-pi n fpbg a lead free p a ckag e. d1 sq u a r e 1 d s qua r e 3 d 1 ba si c 14 . 0 0 d ba si c 18 . 0 0 l 0. 15 0. 6 0 a 2 m i n no m m a x 1 . 35 1 . 40 1. 4 5 l1 re f 1. 0 0 a ma x . 1. 6 0 b mi n m a x 0 . 1 7 0 . 2 7 a 1 0. 0 5 0 . 15 e ba si c 0. 5 0 j e d e c re f # ms - 0 2 6 cc c ma x 0. 0 8 dd d no m 0. 0 8 sym b o l 100 le a d to l . le a d s mi n m a x not e s : 1 . a l l l i n e a r d i m e n s io n s a r e i n m i l l i m e t e r s . 2 . pl as t i c bo dy d i m e n s i o ns do n o t i n c l u d e f l as h o r pr o t usi o n . m ax al l o w a bl e 0 . 2 5 per si de. 3 . l ead c o un t o n d r a w i n g n o t re presentat i ve o f a c tual packag e. 3. m a 0.2 5 0 . 09/0.20 t y p 0 - 7 typ l l1 b a1 - c - cc c l e ad co pl a n a r i t y al a l al a- b s d s a2 a 12 n o m 12 n o m e figure 6 - l q fp-1 00 www .a lsc.com alliance semiconductor 8 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1001 revisions r e v . d e s c r i p t i o n e c n d a t e a initial document release. 91253 12-04- 01 b updated ball cop l anarit y limits from 0.20mm to 0.15 mm. d e a b 2 c 0.15 c d1 e1 c d g h i k 1 2 3 4 5 6 7 8 9 1 0 f e b a b 0 . 2 5 m c 0 . 2 5 m c a b dimensions s y mb o l m i n . n o m . m a x . a - - - - 1 . 7 0 a 1 0 . 3 0 - - - - a 2 0 . 2 5 - - 1 . 1 0 b 0 . 5 0 0 . 6 0 0 . 7 0 d 1 1 . 0 0 b s c d 1 9 . 0 0 b s c e 1 1 . 0 0 b s c e 1 9 . 0 0 b s c e 1 . 0 0 packag e num ber fbg a 010 0-11 f jedec ref # mo-19 2 var. a a c-1 figure 7 - fp bg a-1 00 www .a lsc.com alliance semiconductor 9 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1001 device selector g u ide and ordering information as91l x xxx u u - cc pp - temp - l al i a n c e s emi c ond uc t o r syste m so lu tio n d e vice fa mily 1001 1002 1003 1006 pro duc t v e rs i o n s = s t andar d u = 16 - b it use r cod e bu = 8- bi t s t at us / u s e r c ode e = e nhanc ed c = com mer c i al (0 t o 70 d egrees c) i = i ndus t r i a l (- 40 t o 85 deg rees c) pa cka ge l 100 = 10 0 pi n lqf p f 100 = 1 00 pi n f p bga c l o ck spe e d 10 = 10 m h z tck 40 = 40 m h z tck b l ank = le aded f = l ead f r ee g = green figure 8 - pa rt numb erin g guide www .a lsc.com alliance semiconductor 10 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1001 part number des c ription as91l10 01s ? 10l10 0-c jtag te st controlle r, 100 -pin lq fp packa ge, co mmercial as91l10 01s ? 10l10 0-cf jtag te st controlle r, 100 -pin lq fp packa ge, co mmercial, lea d free as91l10 01s ? 10l10 0-i jtag te st controlle r, 100 -pin lq fp packa ge, ind u strial as91l10 01s ? 10l10 0-if jtag te st controlle r, 100 -pin lq fp packa ge, ind u strial, lea d free as91l10 01s ? 10f100 -c jtag te st controlle r 10 0-pin fpbga packa ge, co mmercial as91l10 01s ? 10f100 -cg jtag te st controlle r 10 0-pin fpbga, comm ercial, gree n pa ckag e as91l10 01s ? 10f100 -i jtag te st controlle r 10 0-pin fpbga packa ge, ind u strial as91l10 01s ? 10f100 -ig jtag te st controlle r 10 0-pin fpbga, indu strial, gre en pa ckage as91l10 01s ? 40l10 0-cf jtag te st controlle r, 100 -pin lq fp packa ge, co mmercial, lea d free, 40 mhz tck as91l10 01s ? 40l10 0-if jtag te st controlle r, 100 -pin lq fp packa ge, ind u strial, lea d free, 40 mhz tck as91l10 01s ? 40f100 -cg jtag te st controlle r 10 0-pin fpbga, comm ercial, gree n pa ckag e, 40 mhz tck as91l10 01s ? 40f100 -ig jtag te st controlle r 10 0-pin fpbga, indu strial, gre en pa ckage, 40 mhz tck table 5 - valid part number combinations www .a lsc.com alliance semiconductor 11 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1001 packag e options dev i ce master des c ription fpbg a-1 00 (1mm pitch) lqfp -100 as91l10 01 jtag te st controlle r x x as91l10 02 jtag te st seque ncer x x as91l10 03 u 3 - p o r t g a t e w a y x x as91l10 06b u 6 - p o r t g a t e w a y x x table 6 - jt ag contr o ller produc t family www .a lsc.com alliance semiconductor 12 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1001 www .a lsc.com alliance semiconductor 13 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.

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