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as3668 4 channel breathlight controller www.ams.com/as3668 revision 1.13 1 - 59 data sheet 1 general description the as3668 is a 4-channel led driver designed to produce lighting effects for portable devices. a highly efficient charge pump enables led driving over full li-ion battery voltage range. the device is equipped with an internal program memory, which allows control of led patterns even without processor control. this helps the whole system to save power and extend for example battery life time in every mobile application. the as3668 maintains excellent efficiency over a wide operating range by automatically selecting the best charge pump gain based on the led forward voltage requirements and the device input voltage. furthermore the chip supports an automatic power-save mode which gets active when led outputs are not active. the special power- save mode has a extremely low current consumption below 10 a (typ.).the as3668 has an i2c-compatible control interface which supports two slave address without having a dedicated address selection pin. for fancy lighting effects synchronized with an audio signal the device supports special digital filter modes in order to make music literally visible on the 4 independent configurable current sources. the as3668 is available in a very tiny 12-pin wl-csp (1.255x1.680mm) 0.4mm pitch package. figure 1. as3668 block diagram 2 key features ?? high efficiency capacitive 60ma charge pump with 1:1 and 1:2 mode ?? automatic mode switching for charge pump ?? automatic pattern mode without digital control ?? highly accurate 4 channel high side 25.5ma current sources ?? audio controlled lighting with internal digital filters ?? charge pump with soft start and overcurrent/short circuit pro- tection ?? integrated ?easy to use? pattern generator for breathlight led function with logarithmic 12bit dimming ?? small application circuit ?? minimum number of external components ?? available in 12-pin wl-csp (1.255x1.680mm) with 0.4mm pitch 3 applications the product is perfect for mobilephones, mp3 player, portable navigation devices, digital cameras, usb dongles/modems, game controllers and can be used for fun and indicator lights, backlighting and as programmable current sources.
www.ams.com/as3668 revision 1.13 2 - 59 as3668 data sheet - applications contents 1 general description ........................................................................................................ .......................................................... 1 2 key features ............................................................................................................... ............................................................. 1 3 applications ............................................................................................................... ............................................................... 1 4 pin assignments ............................................................................................................ ........................................................... 4 4.1 pin description .......................................................................................................... ...........................................................................5 5 absolute maximum ratings ................................................................................................... ................................................... 6 6 electrical characteristics ................................................................................................. ......................................................... 7 6.1 timing characteristics ................................................................................................... .......................................................................9 6.2 timing diagrams ........................................................................................................ ..........................................................................10 7 typical operating characteristics ........................................................................................... .....................................................11 8 detailed description ....................................................................................................... ........................................................ 14 8.1 charge pump .............................................................................................................. .......................................................................14 8.1.1 charge pump mode switching ............................................................................................. .....................................................15 8.1.2 soft start ............................................................................................................. .......................................................................15 8.1.3 unused charge pump ..................................................................................................... ..........................................................15 8.1.4 charge pump control register ........................................................................................... .......................................................16 8.2 current sources .......................................................................................................... ...................................................................16 8.2.1 unused current sources ................................................................................................. ..........................................................17 8.2.2 current source registers ................................................................................................ ...........................................................18 8.3 power - on reset ......................................................................................................... ......................................................................19 8.4 vbat monitor ............................................................................................................. ........................................................................20 8.4.1 vbat monitor registers . ............................................................................................... ...........................................................21 8.5 temperature supervision .................................................................................................. .................................................................21 8.6 i2c serial interface bus ................................................................................................. .....................................................................22 8.6.1 i2c device address byte ................................................................................................ ............................................................24 8.6.2 command byte ........................................................................................................... ...............................................................24 8.6.3 i2c device address selection ........................................................................................... .........................................................25 8.7 operating modes .......................................................................................................... ......................................................................25 8.7.1 gpio/audio_in automatic pattern start-up mode .......................................................................... ........................................27 8.8 general purpose input / output ........................................................................................... ..............................................................29 8.8.1 unused general purpose input / output .................................................................................. .................................................30 8.8.2 gpio control register. ................................................................................................. .............................................................30 8.9 audio input .............................................................................................................. ...........................................................................30 8.9.1 audio control register ............................................................................................... ..............................................................32 8.10 led pattern configuration ............................................................................................... ................................................................34 8.10.1 single pulse mode ..................................................................................................... ..............................................................34 8.10.2 multiple pulse mode .................................................................................................... ............................................................ 35 8.10.3 frame mask mode ....................................................................................................... ............................................................36 8.10.4 frame start delay mode ................................................................................................ ..........................................................37 8.10.5 gpio toggle mode ...................................................................................................... ............................................................37 8.10.6 led pattern control registers ........................................................................................ .......................................................38 9 register map ............................................................................................................. ........................................................... 45 10 application information .................................................................................................. ...................................................... 48 10.1 led software implementation examples .................................................................................... .....................................................48
www.ams.com/as3668 revision 1.13 3 - 59 as3668 data sheet - applications 10.1.1 simple breathlight pattern with one led ............................................................................... ..................................................48 10.1.2 dual pulse pattern with one led ....................................................................................... .....................................................48 10.1.3 rgb led pattern ....................................................................................................... .............................................................49 10.1.4 parallel up - dimming ................................................................................................. .............................................................50 10.1.5 parallel down- dimming ................................................................................................ ..........................................................50 10.2 hardware examples ....................................................................................................... ..................................................................52 11 package drawings and markings ............................................................................................. ............................................ 57 12 ordering information ...................................................................................................... ....................................................... 60
www.ams.com/as3668 revision 1.13 4 - 59 as3668 data sheet - pin assignments 4 pin assignments figure 2. pin assignments 12-pin wl-csp (1.255x1.680mm)(top view)
www.ams.com/as3668 revision 1.13 5 - 59 as3668 data sheet - pin assignments 4.1 pin description table 1. pin descriptions pin name pin number description v bat c2 positive power supply input for as3668. gnd d2 signal and power ground. provide a short, direct pcb path between this pin and the nega- tive side of the output capacitor of the charge pump capacitor c vcpout . scl b3 serial clock input for the two wire i2c interface. sda c3 serial-data i/o for i2c interface. this pin is a open drain digital i/o which requires a pull up resistor for data transfer. gpio/audio_in d3 general purpose input/output or audio input. depending on as3668 configuration this pin provided three different features. it can either be configured as general purpose input/ output 1 or as analogue audio input for music playback synchronization of as3668 with an audio source. furthermore it is possible to use it as power up pin starting up with a default pwm pattern sequence for led1. if the pin is not used it is mandatory to connect it to ground. 1. the output is an open-drain output only. therefore an external pull-up resistors is required for output operation. curr1 b2 curr1 output. this pin is a current source output which can be used to operate a led. the current source is internally connected to v cp . if the as3668 is powered up with gpio/ audio_in pin this current source is active with a default pwm pattern. curr2 c1 curr2 output. this pin is a current source output which can be used to operate a led. the current source is internally connected to v cp . curr3 a1 curr3 output. this pin is a current source output which can be used to operate a led. the current source is internally connected to v cp . curr4 d1 curr4 output. this pin is a current source output which can be used to operate a led. the current source is internally connected to v cp . v cp b1 charge pump output. this pin requires an external blocking capacitor. the capacitor must be placed as close as possible to v cp terminal. cp a2 charge pump flying capacitor. this is the positive terminal for the charge pump flying capacitor. the capacitor should be placed as close as possible to as3668. in addition it is mandatory to keep the signal trace between the capacitor and cp terminal as short as possible. cn a3 charge pump flying capacitor. this is the negative terminal for the charge pump flying capacitor. the capacitor should be placed as close as possible to as3668. in addition it is mandatory to keep the signal trace between the capacitor and cn terminal as short as possible.
www.ams.com/as3668 revision 1.13 6 - 59 as3668 data sheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 7 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments v bat , v cp , cn, cp to gnd -0.3 7 v v cp to gnd -0.3 7 v protection diode between v cp and gnd led1, led2, curr3, curr4 to gnd -0.3 7 v scl, sda, gpio/audio_in to gnd -0.3 7 v input pin current without causing latch up -100 +100 ma at 25oc, norm: eia/jesd78 electrostatic discharge esd hbm (curr1 to curr4) 2 kv jedec jesd22-a114 esd hbm (all other pins) 2 kv esd mm 100 v jedec jesd22-a115 esd cdm 500 v jedec jesd22-c101 storage temperature range -55 +125 oc temperature ranges and storage conditions continuous power dissipation 0.83 w internally limited (over temperature protection) 1 1. internal thermal shutdown circuitry protects the device from permanent damage. thermal shutdown engages at t j = 140c (typ.) and disengages at t j = 135c (typ.). storage temperature range -55 +125 oc junction to ambient thermal resistance ( ? ja ) 2 2. junction to ambient thermal resistance is highly application and board-layout dependent. in applications where high maximum p ower dissipation exists, special care must be paid to thermal dissipation issues in board design. 60 c/w humidity non-condensing 5 85 % moisture sensitive level 1 represents a max. floor life time of unlimited. package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/ jedec j-std-020 ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?.
www.ams.com/as3668 revision 1.13 7 - 59 as3668 data sheet - electrical characteristics 6 electrical characteristics v bat = 3.6v, c bat = c vcpout = 1 f, c fly = 470nf, t amb = -30oc to +85oc, typical values @ t amb = +25oc (unless otherwise specified) . table 3. electrical characteristics symbol parameter condition min typ max unit general operating conditions v bat supply voltage 2.7 5.5 v i vbat standby supply current scl = 0v and gpio = 0v 0.2 3 a normal mode supply current scl = v bat and sda = v bat , no i2c communication and no internal block enabled 10 a charge pump in 1x mode, no load, current source outputs disabled 70 a charge pump in 2x mode, no load, current source outputs disabled 2.5 ma f osc internal oscillator frequency accuracy -10 +10 % t amb operating temperature 1 -30 25 85 c charge pump r out charge pump output resistance operating mode 1:1 2 ? operating mode 1:2; v bat = 3.0v 20 f sw switching frequency 1 mhz t on v cp turn-on time 2 no load, current sources curr1 - curr4 deactivated 30 s i out = 50ma, current sources curr1 - curr4 deactivated 40 s current sources i leak leakage current (led1 to curr4) pwm = 0% 0.1 1 a i max maximum source current outputs curr1 to curr4 25.5 ma i out output current accuracy output current set to 25.5 ma -15 +15 % i match matching accuracy output current set to 25.5 ma -10 +10 % f led switching frequency pwm mode with internal oscillator 122 hz logic interface logic input scl, sda and gpio/audio_in v il input low level 0.52 v v ih input high level 1.38 v bat v i in input current -1.0 1.0 a v olgpio low level output voltage pin gpio/audio_in at 4ma 0.2 v v hys hysteresis 0.1 v f ext external pwm input only possible with gpio/audio_in 1 mhz analogue input analogue audio input gpi/audio_in v audio input signal level 2.5 v peak r audio_in audio input resistance audio preamplifier gain = -6db 400 k audio preamplifier gain = +20db 60 k
www.ams.com/as3668 revision 1.13 8 - 59 as3668 data sheet - electrical characteristics c audio_in input capacitance 10 pf a audio programmable amplifier gain -6 25 db 1. internal thermal shutdown circuitry protects the device from permanent damage. thermal shutdown engages at t j = 140c (typ.) and disengages at t j = 135c (typ.). 2. turn-on time is measured from the moment the charge pump is activated until the v cp crosses 90% of its target value table 3. electrical characteristics (continued) symbol parameter condition min typ max unit
www.ams.com/as3668 revision 1.13 9 - 59 as3668 data sheet - electrical characteristics 6.1 timing characteristics v bat = 3.6v, c bat = c vcpout = 1 f, c fly = 470nf, t amb = -30oc to +85oc, typical values @ t amb = +25oc (unless otherwise specified) . table 4. electrical characteristics i 2 c 1 1. specification is guaranteed by design and is not tested in production. v en = 1.65v to v bat . symbol parameter condition min typ max unit i2c mode timings - see f sclk scl clock frequency 1/35ms 400 khz t buf bus free time between a stop and start condition 1.3 s t hd:sta hold time (repeated) start condition 2 2. after this period the first clock pulse is generated. 0.6 s t low low period of scl clock 1.3 s t high high period of scl clock 0.6 s t su:sta setup time for a repeated start condition 0.6 s t hd:dat data hold time 3 3. a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ihmin of the sclk signal) to bridge the undefined region of the falling edge of sclk. 0 0.9 s t su:dat data setup time 4 4. a fast-mode device can be used in a standard-mode system, but the requirement t su:dat = to 250ns must then be met. this is automat- ically the case if the device does not stretch the low period of the sclk signal. if such a device does stretch the low period of the sclk signal, it must output the next data bit to the sda line t r max + t su:dat = 1000 + 250 = 1250ns before the sclk line is released. 100 ns t r rise time of both sda and scl signals 20 + 0.1c b 300 ns t f fall time of both sda and scl signals 20 + 0.1c b 300 ns t su:sto setup time for stop condition 0.6 s c b capacitive load for each bus line c b ? total capacitance of one bus line in pf 400 pf c i/o i/o capacitance (sda, scl) 10 pf
www.ams.com/as3668 revision 1.13 10 - 59 as3668 data sheet - electrical characteristics 6.2 timing diagrams figure 3. i2c mode timing diagram sclk sda t buf t hd:sta t su:sta repeated start t su:sto t f t su:dat t high t hd:dat t r t low t hd:sta start stop
www.ams.com/as3668 revision 1.13 11 - 59 as3668 2v0 data sheet - t ypical operating characteristics 7 typical operating characteristics v bat = 3.6v, c bat = c vcpout = 1 f, c fly = 470nf, t amb = -30oc to +85oc, typical values @ t amb = +25oc (unless otherwise specified) . figure 4. off mode current vs. vbat figure 5. currx linearity (0ma - 25.5ma) vs. code 0 0,2 0,4 2,73,13,53,94,34,75,15,5 i bat [a] v bat [v] off mode current 0 5 10 15 20 25 0100200 i currx [ma] register currx current [dec] figure 6. output voltage vs. load current (1:1, 4.2v,3,6v, 3,3v) l figure 7. output voltage. vs. load current (1:2, 4.2v,3,6v , 3,3v) 0 1 2 3 4 5 0 1020304050 v cp [v] i load [ma] vbat = 3.6v vbat = 3.3v vbat = 4.2v 5 5,1 5,2 5,3 0 1020304050 v cp [v] i load [ma] vbat = 3.6v vbat = 3.3v vbat = 4.2v figure 8. cp efficiency vs.v bat in 1:2 mode(10ma,30ma,60ma) figure 9. cp efficiency vs. v bat in 1:1 mode(10ma,30ma,60ma) 0 10 20 30 40 50 60 70 80 90 100 2,7 3,1 3,5 3,9 4,3 efficiency [%] v bat [v] 60ma load 30ma load 10ma load 0 10 20 30 40 50 60 70 80 90 100 2,7 3,1 3,5 3,9 4,3 efficiency [%] v bat [v] 60ma load 30ma load 10ma load
www.ams.com/as3668 revision 1.13 12 - 59 as3668 2v0 data sheet - t ypical operating characteristics figure 10. currx logarithmic pwm ramp figure 11. v cp and vbat in 1:2 mode and 50ma load current 500ms/div 1.3ma/div i currx 50mv/div 1 s/div v cp figure 12. v cp with charge pump in 1:2 mode and 10ma load current figure 13. line regulation autom. gain change to 1:2 mode with 1ma load current 1 s/div 20mv/div v cp 10ms/div 1v/div v bat v cp 3.5v 5v 2.5v figure 14. line regulation autom. gain change to 1:2 mode with 10ma load current figure 15. line regulation autom. gain change to 1:2 mode with 25.5ma load current 1v/div v bat v cp 3.5v 4.8v 2.5v 10ms/div 1v/div v bat v cp 5.2v 3v 10ms/div 4v
www.ams.com/as3668 revision 1.13 13 - 59 as3668 2v0 data sheet - t ypical operating characteristics figure 16. output current of currx vs. u(currx) with 25,5ma currx output current figure 17. output current of currx vs. u(currx) with 10ma currx output current -30 -20 -10 0 00,511,52 currx [ma] u currx [v] -15 -10 -5 0 00,511,52 currx [ma] u currx [v] figure 18. output current of currx vs. u(currx) with 1ma currx output current) figure 19. battery current vs. vbat with cp in 1:2 mode (10ma, 30ma, 60ma -1,5 -1 -0,5 0 00,511,52 currx [ma] u currx [v] 0 20 40 60 80 100 120 140 2,5 3,5 4,5 5,5 i vbat [ma] v bat [v] 10ma cp load 30ma cp load 60ma cp load figure 20. cp efficiency vs. v bat with automatic cp mode switching figure 21. cp efficiency vs. i load with automatic cp mode switching 0 10 20 30 40 50 60 70 80 90 100 2,7 3,1 3,5 3,9 4,3 efficiency [%] v bat [v] 60ma load 30ma load 10ma load 0 10 20 30 40 50 60 70 80 90 100 0 1020304050 efficiency [%] i load [ma] vbat = 3.0v vbat = 3.3v vbat = 3.6v
www.ams.com/as3668 revision 1.13 14 - 59 as3668 data sheet - detailed description 8 detailed description 8.1 charge pump the charge pump uses the external flying capacitor c fly to generate output voltages higher than the battery voltage. there are two different operating modes of the charge pump itself: ?? 1:1 bypass mode - battery input and output are connected by a low-impedance switch - battery current = output current. ?? 1:2 mode - the output voltage is up to 2 times the battery voltage (without load), but is limited to vcpoutmax all the time - battery current = 2 times output current figure 22. charge pump block diagram . as the battery voltage decreases, the charge pump must be switched from 1:1 mode to 1:2 mode in order to provide enough supply for the current sinks. depending on the actual current the mode with best overall efficiency can be automatically or manually selected: the charge pump mode switching can be done manually or automatically with the following possible software settings: ?? automatic - start with 1:1 mode - switch up automatically to 1:2 mode ?? manual - set modes 1:1 and 1:2 by software the charge pump requires the external components listed in the following table: note: the connections of the external capacitors c vcpout and c fly should be kept as short as possible. . table 5. charge pump external components symbol parameter condition min typ max unit c fly external flying capacitor ceramic low-esr capacitor between pins cp and cn 470 nf c vcpout external storage capacitor ceramic low-esr capacitor between pins v cp and v ss 1.0 f table 6. charge pump characteristics symbol parameter condition min typ max unit icpout output current continuous depending on pcb layout 0.0 60 ma vcpoutmax output voltage internally limited, including output ripple 5.6 v ?? efficiency including current sink loss; icpout = 60ma. 88 % icp1_2 power consumption without load, fclk = 1 mhz 1:2 mode 2.5 ma
www.ams.com/as3668 revision 1.13 15 - 59 as3668 data sheet - detailed description 8.1.1 charge pump mode switching if automatic mode switching is enabled the charge pump monitors the current sources, which are directly connected to the output of the charge pump v cp . in order to identify the enabled current sources, the related registers should be setup before starting the charge pump. if any of the voltage on these current sources drops below the threshold (v curr_source ), the higher mode is selected after the debounce time (t deb ). the charge pump mode switching supports only a mode change to a higher charge pump mode (e.g.: mode 1:1 to mode 1:2). in case v bat increases again during operation the automatic mode switching will not change the operation mode from 1:2 down to 1:1. in order to change the mode all current sources must be switched off to reset the charge pump mode switching mechanism. after enabling the current sou rces again the mode switching mechanism chooses the appropriate mode for the optimized operation of the charge pump either in 1:1 mode or 1:2 mode. in case an automatic pattern is used the current sources get a reset after each pattern cycle because the current sources are auto matically switched off when executing a pattern after each cycle. figure 23. charge pump mode switching . 8.1.2 soft start an implemented soft start mechanism reduces the inrush current. battery current is smoothed when switching the charge pump on a nd also at each switching condition. this precaution reduces electromagnetic radiation significantly. 8.1.3 unused charge pump if the charge pump is not used, capacitors c fly and c vcpout can be removed. the pins cp, cn and v cp should be left open and keep register cp_on and cp_auto_on at 0 (default value). rcp1_1 effective charge pump output resistance (open loop, fclk = 1mhz) 1:1 mode; v bat ?? 3.6v 2.5 ? rcp1_2 1:2 mode; v bat ?? 3v 20 fclk accuracy accuracy of clock frequency -10 10 % v curr_source led1 - curr4 current source dropout voltage if the voltage drops below this threshold, the charge pump will use the next available mode (1:1 -> 1:2) 0.2 v i soft_start current limit for soft start feature 400 ma t deb cp automatic up- switching debounce time cp_start_debounce=0 32 ms cp_start_debounce=1 200 s table 6. charge pump characteristics symbol parameter condition min typ max unit
www.ams.com/as3668 revision 1.13 16 - 59 as3668 data sheet - detailed description 8.1.4 charge pump control register . 8.2 current sources the as3668 features four general purpose current sources. all current sources and be controlled independently from each other a nd share internally the same power supply v cp . table 7. reg control register 0x00 reg control register bit bit name default access bit description 2 cp_on 0 r/w this bit enables the charge pump for operation if at lease one current source is enabled and the current source has a low voltage condition. once the charge pump is running it will be keep on even if all current sources are switched off. 0: chargepump off 1: charge pump on table 8. cp control register 0x23 current control register bit bit name default access bit description 6 cp_auto_on 1 r/w this bit enables the charge pump for operation. once at last one current source is enabled and minimum one current source has a low voltage condition the charge pump is switched on. if all current sources are switched off again the charge will also switch of automatically. 0: chargepump off 1: chargepump on in automatic mode 5 cp_start_debounce 0 r/w selects the startup debounce time of the charge pump 0: 32ms debounce time. 1: 240 s debounce time 4 cp_mode_switching 0 r/w allows the user to select between automatic mode switching or manual mode switching of the charge pump. if the bit is set, the user can change register cp_mode in order to select 1:1 mode or 1:2 mode of the charge pump. 0: automatic cp mode switching 1: manual cp mode switching using register cp_mode 2 cp_mode 0 r/w selects the charge pump operating mode if register cp_mode_switching is set to 1. reading the register return the mode in which the charge pump is operating, either 1:1 or 1:2 mode. 0: 1:1 mode 1: 1:2 mode 0 cp_clk 0 r/w selects the charge pump clock frequency. 0: 1mhz 1: 500khz table 9. current sink function overview current sink max. voltage (v) max. current (ma) resolution software current control hardware on/off control (bits) (ma) curr1 5.5 25.5 8 0.1 separate for each current source internal pwm; external pwm at gpio/audio_in, pattern generator curr2 curr3 curr4
www.ams.com/as3668 revision 1.13 17 - 59 as3668 data sheet - detailed description . figure 24. internal processing of current sources 8.2.1 unused current sources unused current sources can be left open. there are no external connections or components necessary if they are not used. table 10. current sources characteristiks symbol parameter condition min typ max unit i bit7 current sink if bit7 = 1 curr1, curr2, curr3, curr4 > 0.2v 12.8 ma i bit6 current sink if bit6 = 1 6.4 i bit5 current sink if bit5 = 1 3.2 i bit4 current sink if bit4 = 1 1.6 i bit3 current sink if bit3 = 1 0.8 i bit2 current sink if bit2 = 1 0.4 i bit1 current sink if bit1 = 1 0.2 i bit0 current sink if bit0 = 1 0.1 i match matching accuracy curr1, curr2, curr3 and curr4 -10 +10 % i out absolute accuracy -15 +15 % v cur1-4 voltage compliance 0 v cp -0.2 v
www.ams.com/as3668 revision 1.13 18 - 59 as3668 data sheet - detailed description 8.2.2 current source registers . table 11. current control register 0x01 current control register bit bit name default access bit description 7:6 curr4_mode 0 r/w 00: current source curr4 is in off mode 01: current source curr4 is in on mode 10: current source curr4 is in pwm control mode 11: current source curr4 is in led pattern generation mode 5:4 curr3_mode 0 r/w 00: current source curr3 is in off mode 01: current source curr3 is in on mode 10: current source curr3 is in pwm control mode 11: current source curr3 is in led pattern generation mode 3:2 curr2_mode 0 r/w 00: current source curr2 is in off mode 01: current source curr2 is in on mode 10: current source curr2 is in pwm control mode 11: current source curr2 is in led pattern generation mode 1:0 curr1_mode 3 r/w 00: current source curr1 is in off mode 01: current source curr1 is in on mode 10: current source curr1 is in pwm control mode 11: current source curr1 is in led pattern generation mode table 12. current source register led1 0x02 current control register bit bit name default access bit description 7:0 curr1_current 0x40 r/w 0000 0000: 0ma current output from source curr1 0000 0001: 0.1ma current output from source curr1 0000 0010: 0.2ma current output from source curr1 0000 0011: 0.3ma current output from source curr1 ... 1111 1111: 25.5ma current output from source curr1 table 13. current control register led2 0x03 current control register bit bit name default access bit description 7:0 curr2_current 0 r/w 0000 0000: 0ma current output from source curr2 0000 0001: 0.1ma current output from source curr2 0000 0010: 0.2ma current output from source curr2 0000 0011: 0.3ma current output from source curr2 ... 1111 1111: 25.5ma current output from source curr2 table 14. current control register curr3 0x04 current control register bit bit name default access bit description 7:0 curr3_current 0 r/w 0000 0000: 0ma current output from source curr3 0000 0001: 0.1ma current output from source curr3 0000 0010: 0.2ma current output from source curr3 0000 0011: 0.3ma current output from source curr3 ... 1111 1111: 25.5ma current output from source curr3
www.ams.com/as3668 revision 1.13 19 - 59 as3668 data sheet - detailed description 8.3 power - on reset the as3668 provides an power - on reset feature that is controlled by two different sources: ?? v bat supply voltage ?? serial interface state (scl only) if the internal v bat supply voltage reset is forced, when the supply voltage v bat of as3668 drops below a predefined voltage, the device enters shutdown mode. this predefined voltage is 2v (typ.) and is defined as v por_vbat . besides this hard wired voltage level where an internal reset is forced to shut down the device, as3668 supports an additional v bat monitoring feature. this means that the designer can select according to its application requirements a reset level which is appropriate for mobile li-ion battery powered applications. the use case fo r this second v bat monitoring is to make sure that if a mobile device switches off suddenly, at a dedicated voltage, to make sure that also as3668 enters power down mode. otherwise unwanted led effects could occur even if the digital system is not running any more. as3668 allows the des igner now to set the v bat monitoring level to the same voltage level the whole system is powering down. there?s no need any more for the cpu to reset or power down as3668 in a low battery case any more. the device can handle this use case automatically. in addition to the v bat voltage monitoring the device supports also a shut down function forced by the serial interface. if the voltage on the serial interface pin scl is below 1v (typ.) and gpio/audio_in pin is low, the device forces a reset. to prevent the system against wro ng resets caused by electromagnetically influences there is also a debounce timer integrated with a typical debounce time of 100ms. this debounce time is used for v bat monitoring as well. if the serial interface monitoring is not supposed to be used in an application it is also possible to dis able the feature using the corresponding register bit. table 15. current control register curr4 0x05 current control register bit bit name default access bit description 7:0 curr4_current 0 r/w 0000 0000: 0ma current output from source curr4 0000 0001: 0.1ma current output from source curr4 0000 0010: 0.2ma current output from source curr4 0000 0011: 0.3ma current output from source curr4 ... 1111 1111: 25.5ma current output from source curr4 table 16. currx low voltage status register 0x2b current source low voltage status register bit bit name default access bit description 3 curr4_low_v 0r this is a read only register and returns 0 if the voltage on current source curr4 is ok. if the voltage drops below 200mv across the current source the bit is set to 1. 0: curr4 voltage is ok 1: curr4 voltage is too low 2 curr3_low_v 0r this is a read only register and returns 0 if the voltage on current source curr3 is ok. if the voltage drops below 200mv across the current source the bit is set to 1. 0: curr3 voltage is ok 1: curr3 voltage is too low 1 curr2_low_v 0r this is a read only register and returns 0 if the voltage on current source curr2 is ok. if the voltage drops below 200mv across the current source the bit is set to 1. 0: curr2 voltage is ok 1: curr2 voltage is too low 0 curr1_low_v 0r this is a read only register and returns 0 if the voltage on current source curr1 is ok. if the voltage drops below 200mv across the current source the bit is set to 1. 0: curr1 voltage is ok 1: curr1 voltage is too low
www.ams.com/as3668 revision 1.13 20 - 59 as3668 data sheet - detailed description figure 25. reset circuit block diagram 8.4 vbat monitor the v bat monitor is a supervisory circuit. the monitor is per default disabled when the as3668 is powered up. the function can be used in order to send the device automatically into standby mode if the supply voltage of as3668 drops below the defined values in register v mon_vbat. all together the user can select between three different voltage thresholds for this function with 3.375v, 3.3v and 3.0v. if the fu nction is disabled the device switches of if the battery voltage drops below 2.0v. the monitor function has also a debouncer with 100ms implemented in order to filter the 217hz gsm noise pulses from the battery supply voltage. without the debouncer the chip would be susceptible to this noise a nd maybe enter into standby mode due to a misinterpretation of the supply voltage. table 17. power on reset parameters symbol parameter condition min typ max unit v por_vbat overall power-on reset monitor voltage on v bat ; power-on reset for all internal functions. 2.0 v v mon_vbat register defined stand by mode voltage depending on register setting the voltage can be configured 3.0v 3.3v v por_peri reset level for pins scl monitor voltage on pin scl 1.0 v t por_deb reset debounce time for pins scl 110 130 150 ms t start interface startup time 3 ms
www.ams.com/as3668 revision 1.13 21 - 59 as3668 data sheet - detailed description figure 26. v bat monitor block diagram 8.4.1 vbat monitor registers . 8.5 temperature supervision an integrated temperature sensor provides over-temperature protection for the as3668. this sensor generates a flag if the devic e temperature reaches the over temperature threshold of 140o. the threshold has a hysteresis to prevent oscillation effects. if the device temperature exceeds the t 140 threshold all current sources and the charge pump get disabled and the ov_temp flag is set. after decreasing the temperature by t hyst operation is resumed. although the device resumes ordinary operation after a overtemperature event, the register ov_temp keeps set to 1. even a read operation from the register doesn?t reset the register. therefore it?s necessary t o use the register rst_ov_temp to reset the overtemperature register ov_temp. table 18. v bat monitor parameters symbol parameter condition min typ max unit v mon_vbat register defined stand by mode voltage depending on register setting the voltage can be configured 3.0v 3.3v table 19. overtemperature control / v bat monitor register 0x29 overtemperature control / v bat monitor register bit bit name default access bit description 6:5 vmon_vbat 0 r/w 0: device enters shutdown mode if v bat voltage drops below ~2.0v 1: device enters standby mode if v bat voltage drops below 3.0v 2: device enters standby mode if v bat voltage drops below 3.15v 3:device enters standby mode if v bat voltage drops below 3.3v 4 shutdown_enable 1 r/w this bit allows the user to disable the i2c shutdown feature. if the bit is set to ?0? both i2c signal lines can be low without shutting down as3668. 0: disables the automatic shutdown of as3668 1: enables the automatic shutdown of as3668 2 rst_ov_temp 0w this register is a self clearing register. write a ?1? to this register to clear ov_temp. 1 ov_temp 0r this is a read only register and provides feedback about the junction temperature of the chip. the bit is usually set if the junction temperature reaches about 140c. 0: junction temperature ok 1: junction overtemperature 0 ov_temp_on 1 r/w this bit allows the user the enable/disable the junction temperature monitoring for as3668. 0: temperature supervision off 1: temperature supervision on
www.ams.com/as3668 revision 1.13 22 - 59 as3668 data sheet - detailed description the ov_temp flag can only be reset by first writing a 1 to the register bit rst_ov_temp. if bit ov_temp_on = 1 activates temperature supervision table 20 . it is recommend to leave this bit set (default state). 8.6 i2c serial interface bus the as3668 supports the i2c serial bus and data transmission protocol in fast mode at 400khz. the as3668 operates as a slave on the i2c bus. due to the reason that the device is also power up/down with the i2c interface there is a debouncer (130ms) on the signal lines integrated to avoid a system shut down while having i2c traffic on the bus. figure 27. serial interface block diagram the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. connections to the bus are made via the open-drain i/o pins scl and sda. the clock line scl is never held low by as3668 because clock stretching of the bus is not supported. figure 28. as3668 interface initialization table 20. overtemperature detection symbol parameter condition min typ max unit t 140 ov_temp rising threshold 140 oc t hyst ov_temp hysteresis 5 oc table 21. overtemperature control / v bat monitor register 0x29 overtemerature control / v bat monitor register bit bit name default access bit description 2 rst_ov_temp 0 w write a 1 to this register to reset ov_temp 1 ov_temp 0r 0: junction temperature is ok and below t 140 1: junction temperature is too high and above t 140 0 ov_temp_on 1 r/w 0: disables the overtemperature supervision (not recommended) 1: enabled the overtemperature supervision 19 81 9 8 0 0 0 00 x x r/w d15 d14 d13 d12 d11 d10 d9 d8 i2c register address has not been defined yet. sclk sda
www.ams.com/as3668 revision 1.13 23 - 59 as3668 data sheet - detailed description figure 29. bus protocol the bus protocol (as shown in figure 29 ) is defined as: - data transfer may be initiated only when the bus is not busy. - during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clo ck line is high will be interpreted as control signals. the bus conditions are defined as: - bus not busy. data and clock lines remain high. - start data transfer. a change in the state of the data line, from high to low, while the clock is high, defines a start condit ion. - stop data transfer. a change in the state of the data line, from low to high, while the clock line is high, defines the stop c ondition. - data valid. the state of the data line represents valid data, when, after a start condition, the data line is stable for the d uration of the high period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferr ed between start and stop conditions is not limited and is determined by the master device. the information is transferred byte-wi se and each receiver acknowledges with a ninth-bit. within the i2c bus specifications a high-speed mode (3.4mhz clock rate) is defined. - acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. th e mas- ter device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pul l down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowl edge clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by no t generat- ing an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data lin e high to enable the master to generate the stop condition. - figure 29 on page 23 details how data transfer is accomplished on the i2c bus. depending upon the state of the r/ w bit, two types of data transfer are possible: - master transmitter to slave receiver. the first byte transmitted by the master is the slave address, followed by a number of d ata bytes. the slave returns an acknowledge bit after the slave address and each received byte. - slave transmitter to master receiver. the first byte, the slave address, is transmitted by the master. the slave then returns an acknowl- edge bit. next, a number of data bytes are transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not-acknowledge is returned. the master device generate s all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the as3668 can operate in the following slave modes: - slave receiver mode. serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit i s trans- mitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performe d by hardware after reception of the slave address and direction bit. - slave transmitter mode. the first byte (the slave address) is received and handled as in the slave receiver mode. however, in this mode the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the as3668 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. sdi sclk slave address r/ w direction bit start 1 2 6 7 8 9 1 2 3-8 8 9 ack msb repeat if more bytes transferred stop or repeated start ack from receiver ack from receiver ack
www.ams.com/as3668 revision 1.13 24 - 59 as3668 data sheet - detailed description 8.6.1 i2c device address byte the address byte (see figure 30) is the first byte received following the start condition from the master device. the 7 bit device address is 0x42. figure 30. i2c device address byte - bit 1 and bit 2 of the address byte are defined by the external bus connection of the slave to the master shown in chapter 8.6 .3. a maxi- mum of two devices can be connected in parallel on the same bus at one time. - the last bit of the address byte (r/ w) define the operation to be performed. when set to a 1 a read operation is selected; when set to a 0 a write operation is selected. following the start condition, the as3668 monitors the i2c bus, checking the device type identifier being transmitted. upon rec eiving the address code, and the r/ w bit, the slave device outputs an acknowledge signal on the sda line. 8.6.2 command byte the as3668 operation, (see table 29 on page 23) is determined by a command byte (see table 31) . figure 31. command byte figure 32. command and single data byte received by as3668 figure 33. setting the pointer to a address register to select a data register for a read operation 1 0 0 0 0 ad1 ad0 r/ w msb654321lsb address: a7 a6 a5 a4 a3 a2 a1 a0 msb654321lsb from master to slave from slave to master aap a s command byte data byte slave address a6 a5 a4 a3 a2 a1 a0 a7 d6 d5 d4 d3 d2 d1 d0 d7 acknowledge from as3668 0 0 0 acknowledge from as3668 acknowledge from as3668 r/w 0 as3668 registers autoincrement memory word address 1 byte from master to slave from slave to master ap a s command byte slave address a6 a5 a4 a3 a2 a1 a0 a7 0 0 acknowledge from as3668 acknowledge from as3668 r/w 0 as3668 registers
www.ams.com/as3668 revision 1.13 25 - 59 as3668 data sheet - detailed description figure 34. reading n bytes from as3668 8.6.3 i2c device address selection the as3668 features two i2c slave addresses without having a dedicated address selection pin. the selection of the i2c address is done with the interconnection of as3668 to the bus lines shown in figure 35 below. the serial interface logic inside as3668 is able to distinguish between a direct i2c connection to the master or a second option where data and clock line are crossed. therefore it is only possible t o address a maximum of two as3668 slaves on one i2c bus. figure 35. i2c address selection application diagram the i2c addresses for the devices in the different connection modes can be found in table 22 . 8.7 operating modes due to the reason that as3668 has no dedicated enable or power - on pin the device is basically controlled with the i2c signal lines sda and scl. if the voltages on these pins are less than v por_peri for > t por_deb and gpio/audio_in input is low, the as3668 is in shut down mode with a minimized current consumption of i vbat = 1 a (typ.). all blocks inside as3668 are basically switched off except the power up reset circuit is always active. table 22. i2c addresses for as3668 device number 7 bit i2c address 8 bit read address 8 bit write address 1(default) 0x42 0x85 0x84 2 0x43 0x87 0x86 from master to slave from slave to master a/ap a s first data byte second data byte slave address d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 not acknowledge from master 0 1 0 acknowledge from master acknowledge from as3668 r/w 1 as3668 registers autoincrement memory word address n bytes autoincrement to next address stop reading device 1 device 2
www.ams.com/as3668 revision 1.13 26 - 59 as3668 data sheet - detailed description if the voltage on the i2c signal lines is bigger than v por_peri for a time frame longer than t por_deb , the device changes it?s operation mode from power off to standby mode. in this use state only the power on reset and the i2c block of the device is active with an ave rage current consumption of 10 a(typ.). the device changes its operating mode from standby to active mode automatically if one of the following blocks inside as3668 are activated: ?? charge pump ?? current source ?? pattern mode activated ?? external pwm mode via gpio/audio_in in addition to the i2c monitoring for startup of the device it is possible to power up as3668 with gpio/audio_in pin while the i2c signal lines are low. this is a special use case which starts a predefined pattern on current source curr1. for a detailed description please re fer to chapter 8.7.1. besides the monitoring of the i2c signal lines there is also an additional feature which monitors the battery supply voltage v bat . basically there are two voltage levels where this voltage monitoring becomes active. the first voltage v por_vbat can be seen as a shut down and minimum supply voltage of the device voltage which is fixed at 2v (typ.). the same voltage level is used for the power on reset circuit . if the battery voltage drops below v por_vbat the device automatically changes from active mode or standby mode to off mode. besides the v por_vbat level there is a second v bat monitoring voltage which can be activated in a register. this voltage v mon_vbat is typically set to 3.4v (default register setting) but can be reconfigured using the i2c interface down to 2.4v according to the requirements of an application. it is al so possible to disable the v bat monitoring. the v por_vbat monitoring can not be disabled. table 23. truth table for as3668 operating modes as3668 blocks off mode standby mode active mode power on/off reset enabled enabled enabled i2c disabled enabled enabled charge pump disabled disabled enabled/disabled depending on register setting current sources disabled disabled enabled/disabled depending on register setting pattern mode disabled disabled enabled/disabled depending on register setting external pwm disabled disabled enabled/disabled depending on register setting
www.ams.com/as3668 revision 1.13 27 - 59 as3668 data sheet - detailed description figure 36. startup and operating mode selection 8.7.1 gpio/audio_in automatic pattern start-up mode as described in the previous chapter it is basically possible to start up the device using the i2c clock line. in some cases it is not possible to configure as3668 in an application because the application processor is not running that time. therefore as3668 supports a spec ial startup mode shown in figure 36 and figure 37 to start up the device without pulling the i2c clock line high. if an external device is connected to the gpio/audio_in pin of as3668 and the pin is pulled high the device starts up with an default pattern running on curr1 although t he i2c clock line is low shown in figure 37 . if for example as3668 starts up with i2c and the gpio/audio_in pin is low that time the device starts up in standby mode and can be configured using the two wire interface. if the i2c signal lines become low whereas the gpio/audio_in p in is high at the same time the chip keeps activated and running as long as gpio/audio_in pin is high. once the gpio/audio_in pin goes low th e device enters shut down mode. this use case enables the user to keep on charging the battery for example and indicate this with a spec ial pwm pattern while the cpu is powered down for example. a typical application is shown in figure 38 .
www.ams.com/as3668 revision 1.13 28 - 59 as3668 data sheet - detailed description figure 37. timing diagram startup modes figure 38. typical application automatic pattern startup the application in figure 38 shows the as3668 connected to a cpu and a typical charger. most of the stand alone chargers do have a open drain output for charger indication with a led. this output pin can be used to control as3668. if the charger is active the gpi o/audio_in input pin of as3668 is pulled high. the chip starts up with a default pattern on curr1output. with this special mode it is possible t o indicate charging using for example the rgb led connected to as3668 although the cpu is not running. this use case can happen if the battery of a device is almost fully discharged and the cpu can not start up because the battery voltage is too low in trickle charge mode. the automat ic pattern start- up mode allows the operate the led on as3668 without i2c interaction with the cpu. as3668 starts up in automatic pattern start- up mode with the default pattern shown in figure 39 . please mind that the pattern is only active for current source curr1.
www.ams.com/as3668 revision 1.13 29 - 59 as3668 data sheet - detailed description figure 39. timing for automatic pattern startup 8.8 general purpose input / output the pin gpio/audio_in is a general purpose input / output which is shared as a audio input for music synchronization. the pin c an support the following features: ?? digital schmitt trigger input ?? digital output with open drain functionality ?? analogue audio input for audio controlled leds ?? pwm input for curr1, curr2, curr3 and curr4 (max. 1mhz) ?? device start-up in automatic pattern generation mode figure 40. general purpose input / output block diagram table 24. automatic pattern start-up parameters symbol parameter condition min typ max unit t r_curr rise time for dimming up curr1 2.62 s t f_curr fall time for dimming down curr1 2.62 s t on_curr on time for curr1 49 ms t off_curr off time for curr1 0.54 s i curr1 output current for curr1 6.4 ma
www.ams.com/as3668 revision 1.13 30 - 59 as3668 data sheet - detailed description although the gpio/audio_in pin supports digital output as well for simple control exercises an external pull up resistor is man datory. the pin is not able to actively drive the signal line because there is no push/pull stage integrated. the internal pull down resistor is d isabled in audio synchronization mode. for a detailed description of music playback synchronization please refer to chapter 8.9. 8.8.1 unused general purpose input / output if the pin is not used it is recommended to connect it to ground. 8.8.2 gpio control register . . 8.9 audio input the audio input pin gpio/audio_in is shared with a general purpose input/output. it is possible to switch the operating mode of the pin from a gpio to an analogue audio input. this multiplexed audio input pin allows the as3668 to do lighting effects depending on the aud io content connected to gpio/audio_in. the block diagram for the signal processing path is shown in figure 41 . the analogue audio signal is coupled into the pin gpio/audio_in with an external dc blocking capacitor. the integrated audio pre-amplifier with automatic gain control attenuates or amplifies the i nput signal to avoid clipping inside the signal processing path and furthermore increase the dynamic range of the signal in case a very small signal is applied to as3668. the agc of the preamplifier uses the audio gain defined in register audio_gain as start value and changes the gain in a range of +/- 3db. the pre-amplified audio signal is then feed into an special analogue signal processing unit to create special lighting eff ects. various settings inside the signal processing unit allow the user to define different types fancy lighting effects. this processing unit it dire ctly linked together with the control logic for the four current sources of the device. thus, besides the ordinary lighting pattern control of the curren t sources with register settings, the outputs are directly controlled in audio mode from the audio signal processing unit. table 25. gpio control register 0x06 gpio control register bit bit name default access bit description 2 gpio_in_invert 0 r/w this bit allows the user to invert input signal of gpio/audio_in if the pin is configured as digital input. 0: non-inverted digital input gpio/audio_in 1: inverted digital input gpio/audio_in 1 gpio_in_en 1 r/w 0: gpio/audio_in pin is configured as analog input (audio mode) 1: gpio/audio_in pin is configured as digital input (general purpose) 0 gpio_mode 0 r/w 0: gpio/audio_in pin is configured as input 1: gpio/audio_in pin is configured as output in open drain configuration the pin requires an external pull up resistor table 26. gpio signal register 0x08 gpio signal register bit bit name default access bit description 0 gpio_in 0r the register is a read only register. the register is set to 1, if the pin gpio/ audio_in is externally pulled high. the register is set to 0, if the pin is connected to ground. table 27. gpio output register 0x07 gpio output register bit bit name default access bit description 0 gpio_out 0 r/w this register is the output register if the pin gpio/audio_in is configured as output. writing to the register changes the output state of the pin. 0: gpio/audio_in pin low 1: gpio/audio_in pin high (external pull-up resistor required)
www.ams.com/as3668 revision 1.13 31 - 59 as3668 data sheet - detailed description figure 41. audio input block diagram
www.ams.com/as3668 revision 1.13 32 - 59 as3668 data sheet - detailed description 8.9.1 audio control register . . table 28. audio agc register 0x40 audio agc register bit bit name default access bit description 6 agc_up_level 0 r/w this bit allows the change of the agc up switching threshold. 0: default agc up switching threshold 1: increased agc up switching threshold 5 agc_down_level 0 r/w this bit allows the change of the agc down switching threshold. 0: default agc down switching threshold 1: increased agc down switching threshold 4:3 decay_agc_down 0 r/w defines the decay time for the automatic gain control of the audio input amplifier for decreasing the gain. 00: 0.131s 01: 0.262s 10: 0.393s 11: 0.524s 2:1 decay_agc_up 0 r/w defines the decay time for the automatic gain control of the audio input amplifier for increasing the gain. 00: 0.262s 01: 0.524s 10: 0.786s 11: 1.049s 0 agc_on 0 r/w this bit allows the user the enable / disable the automatic gain control of the audio input amplifier. 0: automatic gain control off 1: automatic gain control on table 29. audio input buffer register 0x41 audio input buffer register bit bit name default access bit description 7 audio_dis_start 0 r/w enables the audio input capacitor precharging. this function is only active if register audio_man_start is set to manual precharging. after precharging register audio_dis_start must be cleared again. 0: input capacitor precharging enabled 1: input capacitor precharging disabled 6 audio_man_start 0 r/w configures the input capacitor precharging mechanism for auto precharging or manual precharging. 0: automatic precharging 1: manual precharging 5:1 audio_gain 0 r/w configures the gain of the audio preamplifier. the gain can be configured in the range of -6db up to +25db according to the register setting in 1db steps. 0 0000: -6db 0 0001: -5db 0 0010: -4db 0 0011: -3db ... 1 1111: 25db 0 aud_buf_on 0 r/w this bit switches the internal audio buffer amplifier on and off according to the register setting 0: audio buffer off 1: audio buffer on
www.ams.com/as3668 revision 1.13 33 - 59 as3668 data sheet - detailed description table 30. audio control register 0x42 audio control register bit bit name default access bit description 7 audio_input_pin 0 r/w this bit enables pin gpio/audio_in or curr4 pin to be configured as audio input pin for audio playback synchronization of the current sources. 0: gpio/audio_in selected for audio synchronization 1: curr4 pin selected for audio synchronization 6 pld_off 0 r/w this bit defines if the internal pull down resistor of gpio/audio_in pin is enabled or disabled. if the audio mode is enabled the internal pull down is automatically disabled 0: pull down resistor enabled if register aud_buf_on is set to ?0? 1: pull down resistor disabled 5 adc_characteristic 0 r/w defines the adc characteristic of the adc for general purpose adc measurements depending on the selected adc characteristics in register adc_mode. 00: x*250mv (adc_mode = 0) 01: x*50mv (adc_mode = 0) 00: 75mv*2 x (adc_mode = 0 or adc_mode = 1) 4:3 audio_decay 0 r/w defines the audio decay time. 00: 10ms 01: 20ms 10: 40ms 11: 80ms 2:0 audiosync_mode 0 r/w in this register it is possible to select between different audio synchronization modes of the current sources in order to create different lighting effects. 000: 4 led bar code 001: 4 led bar code with dimming 010: running led bar code 011: running led bar code with dimming 100: rgb (curr1, curr2, curr3; curr4 not used) 101: rgb with dimming (curr1, curr2, curr3; curr4 not used) 110: 4 led parallel with dimming 111: do not use table 31. audio output register 0x43 audio output register bit bit name default access bit description 3 curr4_aud_en 0 r/w this register allows the user to select between normal control (e.g. pwm pattern control) and audio synchronization mode of current source curr4 . 0: curr4 normal function 1: curr4 audio synchronization mode 2 curr3_aud_en 0 r/w this register allows the user to select between normal control (e.g. pwm pattern control) and audio synchronization mode of current source curr3 . 0: curr3 normal function 1: curr3 audio synchronization mode 1 curr2_aud_en 0 r/w this register allows the user to select between normal control (e.g. pwm pattern control) and audio synchronization mode of current source curr2 . 0: curr2 normal function 1: curr2 audio synchronization mode 0 curr1_aud_en 0 r/w this register allows the user to select between normal control (e.g. pwm pattern control) and audio synchronization mode of current source curr1 . 0: curr1 normal function 1: curr1 audio synchronization mode
www.ams.com/as3668 revision 1.13 34 - 59 as3668 data sheet - detailed description 8.10 led pattern configuration 8.10.1 single pulse mode the as3668 supports basically three basic led pattern modes to create fancy lighting effect for the leds which can be connected to the current sources curr1, curr2, curr3 and curr4. the first and basic mode is the ?single pulse mode?. this mode is basically defined out of five parameters shown in figure 42 below. figure 42. led pattern - single pulse mode the first parameter which can be configured in register pwm_dim_speed_up is t r_curr . this time defines how long it takes to ramp up the current to the defined value in registers curr1_current, curr2_current, curr3_current and curr4_current for each current source . the dimming of the current source is of course logarithmic for a better visual effect but can be reconfigured to linear mode in register pwm_d im_shape. the second parameter t f_curr , which can be controlled in register pwm_dim_speed_down, defines the fall time for dimming down the leds. the third parameter is t on_curr and can be configured in register pattern_ton. it defines how long a current source keeps switched on with the current configured in register curr1_current, curr2_current, curr3_current and curr4_current for each current source. also this down dimming is done with a logarithmic scale for a better visual effect. the last parameter t off_curr defines how long the current sources or leds are switched off until the whole pattern cycle starts from the beginning and can be configured in register pattern_toff. please mind that the settings for t f_curr , t r_curr , t on_curr and t off_curr are valid for all four current sinks at the same time. it is not possible to define individual time values for each current source differently to each other. the only parameter which can diffe r from on current source to another is the current which can be configured in registers curr1_current, curr2_current, curr3_current and curr4_cur rent for each current source individually. an example how the mode looks like for all four current sources in parallel can be seen in figure 43 . all current sources work synchronously to each other with a fixed and parallel start point. table 32. singe pulse mode parameters symbol parameter condition min typ max unit t r_curr rise time for dimming up currx 0 8.39 s t f_curr fall time for dimming down currx 0 8.39 s t on_curr on time for currx 0.05 4.2 s t off_curr off time for currx 0.08 8.4 s
www.ams.com/as3668 revision 1.13 35 - 59 as3668 data sheet - detailed description figure 43. single pulse mode - example 8.10.2 multiple pulse mode in addition to the single pulse pattern mode described in section 8.10.1 there is a second mode which is basically based on the single pulse mode. the multiple pulse mode still uses the parameters t r_curr , t f_curr , t on_curr and t off_curr of the single pulse mode but has two more parameters. the first parameter is t p_curr and can be configured in register tp_led. this register defines the pause time between two pulses. the second new parameter is a parameter that defines the number of multiple pulses. this can be configured in register multiple_pulse table 33. timing multiple pulse mode the new parameter can be found in table 34 . all other parameters keep the same and are shared with the single pulse mode. these parameters can be found in table 32 . / table 34. singe pulse mode parameters symbol parameter condition min typ max unit t p_curr pause time between multiple pulses 0 540 ms
www.ams.com/as3668 revision 1.13 36 - 59 as3668 data sheet - detailed description please mind that the settings for t r_curr , t f_curr , t on_curr , t off_curr and t p_curr and the pulse count number in register multiple_pulse are valid for all four current sinks at the same time. it is not possible to define individual time values for each current sou rce differently to each other. the only parameter which can differ from on current source to another is the current which can be configured in register s curr1_current, curr2_current, curr3_current and curr4_current for each current source independently. figure 44. multiple pulse mode - example 8.10.3 frame mask mode an additional feature for creating unique led lighting effects is the frame mask mode. in order to use this mode there is no ad ditional timing parameter necessary. all the timing parameters described in section 8.10.1 and section 8.10.2 are also valid for this third mod e and can be combined together. there are no restrictions when using this mode together with single- or multiple pulse mode. for a better un derstanding how this special mode works a timing diagram example can be found in figure 45 below. figure 45. multiple pulse mode - example
www.ams.com/as3668 revision 1.13 37 - 59 as3668 data sheet - detailed description as the example shows, each defined pattern, no matter if it is a single pulse or multiple pulse pattern, can be divided into fr ames which are basically running in parallel mode. the pattern which has be defined with the different parameters like t r_curr , t on_curr , t off_curr and t p_curr is repeated in an endless loop. in order to enhance the functionality of the pattern generation it is possible to mask or skip frames in between the endless pattern loop. each current source comes with a dedicated register to support masking of one frame up to fou r frames. this means the frame mask mode allows the user to individually skip frames in each current source. the example above shows that the frame mask register fmask_curr2 of curr2 has been set to 1, which means every second frame will be masked out when playing the pattern. th e frame mask register fmask_curr3 of curr3 has been set to 2, therefore two frames are masked out in the example. the register fmask_cu rr4 of curr4 has been set to 3, thus three frames are masked out in the example. the frame mask order in the example is not fixed and can be easily exchanged depending on the frame mask register setting for each current source. 8.10.4 frame start delay mode the frame delay mode allows the user to add a start-delay for each current source separately in pattern generation mode. this f eature allows an user to create again more complex lighting patterns like a running led shown in the example in figure 46 . figure 46. frame start delay mode each current source has a dedicated delay register(frame_delay1, frame_delay2, frame_delay3 and frame_delay4) which allow addin g different start delays to each current source. this feature can of course be combined with the frame mask mode described in 8.10.3. in th e example above the frame_delay2 register has been set to 1 to add one frame delay to curr2. the frame_delay3 register has been set to 2 adding two frames startup delay to curr3. curr4 needs a startup delay of 3 frames which means theframe_delay4 registers must be set to 3. it is worth mentioning that there are also no restrictions when using this mode together with single- or multiple pulse mode described in c hapter 8.10.1 and 8.10.2. 8.10.5 gpio toggle mode an add on feature which enables the user to use up to eight leds in pattern generation mode in a sequential order is the gpio t oggle mode. figure 47. gpio toggle mode 1 frame the mode can be enabled with the register gpio_toggle_en. once the mode has been enabled register gpio_toggle_framenr gets acti vated and allows the user to select after how many frames the gpio/audio_in pin toggles. an example is shown in figure 47 above. the gpio_toggle_en register has been set to 1. the gpio_toggle_framenr register has also been set to 1. the gpio/audio_in pin toggles after each f rame. the pin can be used to control an external switch to enable some more leds. an example of such an application is shown in figure 48 . please mind that it is not possible to operate all eight leds in parallel. it is only possible to enable either one or the other block. this mec hanism is handled automatically with the external control transistors.
www.ams.com/as3668 revision 1.13 38 - 59 as3668 data sheet - detailed description figure 48. application proposal gpio toggle mode 8.10.6 led pattern control registers table 35. pwm control register 0x15 pwm control register bit bit name default access bit description 1 pwm_dim_shape 0 r/w this bit defines if the current sources do logarithmic or linear up/down dimming. 0: logarithmic dimming 1: linear dimming 0 pwm_src 0 r/w defines the pwm source. it can either be selected the internal pwm generator to dim the current sources or us the pin gpio/audio_in as pwm input. 0: internal pwm generator 1: external pwm input selected (gpio/audio_in)
www.ams.com/as3668 revision 1.13 39 - 59 as3668 data sheet - detailed description table 36. pwm control register 0x16 pwm timing register bit bit name default access bit description 7:4 pwm_dim_speed_up 0x08 r/w these bits define the value of t r_curr which is the dim speed when dimming up and down the current sources. the dim speed is valid for all current sources at the same time. 0000: immediate 0001: 0.12s 0010: 0.25s 0011: 0.38s 0100: 0.51s 0101: 0.77s 0110: 1.0s 0111: 1.6s 1000: 2.1s 1001: 2.6s 1010: 3.1s 1011: 4.2s 1100: 5.2s 1101: 6.2s 1110: 7.3s 1111: 8.3s 3:0 pwm_dim_speed_down 0x08 r/w these bits define the value of t r_curr which is the dim speed when dimming up and down the current sources. the dim speed is valid for all current sources at the same time. 0000: immediate 0001: 0.12s 0010: 0.25s 0011: 0.38s 0100: 0.51s 0101: 0.77s 0110: 1.0s 0111: 1.6s 1000: 2.1s 1001: 2.6s 1010: 3.1s 1011: 4.2s 1100: 5.2s 1101: 6.2s 1110: 7.3s 1111: 8.3s table 37. pwm trigger register 0x17 pwm trigger register bit bit name default access bit description 4 start_dim 0 r/w this bit defines in pwm mode of the current sources if the outputs are switched on/off directly or dimmed up/down using the timing of register pwm_dim_speed_up. 0: direct on/off of current sources 1: logarithmic/linear - up/down dimming of current sources
www.ams.com/as3668 revision 1.13 40 - 59 as3668 data sheet - detailed description 3 dim_curr4 0 r a register read of this register reflects the status of current source curr4. if the register returns 0, the current source is switched off. if the register returns 1, the current source is switch on with the current defined in register curr4_current. 0: current source curr4 is switched off 1: current source curr4 is switched on w a write to this register defines the target value for curr4. if 0 is written to this register curr4 is switched off or dimmed down depending on register start_dim. if 1 is written to this register curr4 is switched on or dimmed up depending on register start_dim. mind that this setting is only effective if curr4 is configured to pwm mode in register curr4_mode. 0: target value of curr4 for dimming down or direct control 1: target value of curr4 for dimming up or direct control 2 dim_curr3 0 r a register read of this register reflects the status of current source curr3. if the register returns 0, the current source is switched off. if the register returns 1, the current source is switch on with the current defined in register curr3_current. 0: current source curr3 is switched off 1: current source curr3 is switched on w a write to this register defines the target value for curr3. if 0 is written to this register curr3 is switched off or dimmed down depending on register start_dim. if 1 is written to this register curr3 is switched on or dimmed up depending on register start_dim. mind that this setting is only effective if curr3 is configured to pwm mode in register curr3_mode. 0: target value of curr3 for dimming down or direct control 1: target value of curr3 for dimming up or direct control 1 dim_curr2 0 r a register read of this register reflects the status of current source curr2. if the register returns 0, the current source is switched off. if the register returns 1, the current source is switch on with the current defined in register curr2_current. 0: current source curr2 is switched off 1: current source curr2 is switched on w a write to this register defines the target value for curr2. if 0 is written to this register curr2 is switched off or dimmed down depending on register start_dim. if 1 is written to this register curr2 is switched on or dimmed up depending on register start_dim. mind that this setting is only effective if curr2 is configured to pwm mode in register curr2_mode. 0: target value of curr2 for dimming down or direct control 1: target value of curr2 for dimming up or direct control 0 dim_curr1 0 r a register read of this register reflects the status of current source curr1. if the register returns 0, the current source is switched off. if the register returns 1, the current source is switch on with the current defined in register curr1_current. 0: current source curr1 is switched off 1: current source curr1 is switched on w a write to this register defines the target value for curr1. if 0 is written to this register curr1 is switched off or dimmed down depending on register start_dim. if 1 is written to this register curr1 is switched on or dimmed up depending on register start_dim. mind that this setting is only effective if curr1 is configured to pwm mode in register curr1_mode. 0: target value of curr1 for dimming down or direct control 1: target value of curr1 for dimming up or direct control table 37. pwm trigger register 0x17 pwm trigger register bit bit name default access bit description
www.ams.com/as3668 revision 1.13 41 - 59 as3668 data sheet - detailed description table 38. pattern timing register 0x18 pattern timing register bit bit name default access bit description 5:3 pattern_toff 0x03 r/w these bits define the value of the parameter t off_curr . it defines the off time of curr1, curr2, curr3 and curr4 in pattern generation mode. the same value is used for all four current sources in parallel. 000: 0.08s 001: 0.15s 010: 0.28s 011: 0.54s 100: 1.1s 101: 2.1s 110: 4.2s 111: 8.4s 2:0 pattern_ton 0 r/w these bits define the value of the parameter t on_curr . it defines the on time of curr1, curr2, curr3 and curr4 in pattern generation mode. the same value is used for all four current sources in parallel. 000: 0.04s 001: 0.07s 010: 0.14s 011: 0.27s 100: 0.53s 101: 1.1s 110: 2.1s 111: 4.2s table 39. pattern multiple pulse register 0x19 pattern multiple pulse register bit bit name default access bit description 7:6 multiple_pulse 0 r/w defines the number of multiple pulses applied to all current sources at the same time. 00: 1 pulse 01: 2 pulses 10: 3 pulses 11: 4 pulses 1:0 tp_led 0 r/w these bits define the value of parameter t p_curr . it defines the pause time for multiple pulse mode in pattern generation mode. 00: 0ms 01: 150ms 10: 280ms 11: 540ms
www.ams.com/as3668 revision 1.13 42 - 59 as3668 data sheet - detailed description table 40. pattern frame mask register 0x1a pattern frame mask register bit bit name default access bit description 7:6 fmask_curr4 0 r/w defines the frames to be masked out in pattern generation mode for current source curr4. 00: no frame mask for curr4 01: mask 1 frame for curr4 10: mask 2 frames for curr4 11: mask 3 frames for curr4 5:4 fmask_curr3 0 r/w defines the frames to be masked out in pattern generation mode for current source curr3. 00: no frame mask for curr3 01: mask 1 frame for curr3 10: mask 2 frames for curr3 11: mask 3 frames for curr3 3:2 fmask_curr2 0 r/w defines the frames to be masked out in pattern generation mode for current source curr2. 00: no frame mask for curr2 01: mask 1 frame for curr2 10: mask 2 frames for curr2 11: mask 3 frames for curr2 1:0 fmask_curr1 0 r/w defines the frames to be masked out in pattern generation mode for current source curr2. 00: no frame mask for curr1 01: mask 1 frame for curr1 10: mask 2 frames for curr1 11: mask 3 frames for curr1 table 41. pattern start control register 0x1b pattern start control register bit bit name default access bit description 2 pattern_phase_out 0 r/w the bit defines the way how a pattern is being stopped when the pattern_enable register is cleared. if the bit is set to 0 and the pattern_enable register is cleared the running pattern stops immediately. if the bit is set to 1 and the pattern_enable is cleared the pattern finishes the running frame and stops afterwards. 0: stop pattern immediately 1: phase-out pattern 1 pattern_enable 0w starts the pattern generation on current sources. 0: pattern generation off 1: start of pattern generation 0 pattern_start_src 1 r/w selects the input source to trigger the pattern generation start. 0: pattern enable by software bit 1: pattern enable by gpio/audio_in
www.ams.com/as3668 revision 1.13 43 - 59 as3668 data sheet - detailed description table 42. pattern frame start delay register 0x1c pattern frame start delay register bit bit name default access bit description 7:6 frame_delay4 0 r/w defines the start delay of curr4 in pattern generation mode. note that changes in this register are only getting active after a restart of the pattern generation unit by toggling the pattern_enable bit. 00: no start delay for curr4 01: 1 frame start delay for curr4 10: 2 frames start delay for curr4 11: 3 frames start delay for curr4 5:4 frame_delay3 0 r/w defines the start delay of curr3 in pattern generation mode. note that changes in this register are only getting active after a restart of the pattern generation unit by toggling the pattern_enable bit. 00: no start delay for curr3 01: 1 frame start delay for curr3 10: 2 frames start delay for curr3 11: 3 frames start delay for curr3 3:2 frame_delay2 0 r/w defines the start delay of curr2 in pattern generation mode. note that changes in this register are only getting active after a restart of the pattern generation unit by toggling the pattern_enable bit. 00: no start delay for curr2 01: 1 frame start delay for curr2 10: 2 frames start delay for curr2 11: 3 frames start delay for curr2 1:0 frame_delay1 0 r/w defines the start delay of curr1 in pattern generation mode. note that changes in this register are only getting active after a restart of the pattern generation unit by toggling the pattern_enable bit. 00: no start delay for curr1 01: 1 frame start delay for curr1 10: 2 frames start delay for curr1 11: 3 frames start delay for curr1 table 43. gpio toggle control register 0x1d gpio toggle control register bit bit name default access bit description 2 gpio_toggle_en 0w this bit enables the gpio/audio_in pin to toggle after a defined number of frames. the number of frames where the pin toggles is defined in register gpio_toggle_framenr. 0: gpio toggle disabled 1: gpio toggle enabled 1:0 gpio_toggle_framenr 0 r/w this register defines the number of frames where the gpio/audio_in toggles. the register setting is only active if gpio_toggle_en bit is enabled. 00: gpio toggles after 1 frame 01: gpio toggles after 2 frames 10: gpio toggles after 3 frames 11: gpio toggles after 4 frames
www.ams.com revision 1.13 44 - 59 as3668 2v0 data sheet - register map 9 register map table 44. i2c register overview addr name b7 b6 b5 b4 b3 b2 b1 b0 chip id 3eh chip id1 chip_id1<7:0> constant value ?b10100101? 3fh chip id2 chip_id2<7:4> revision<3:0> led control 01h currx control curr4_mode<7:6> 0: current source 4 off; 1:current source 4 on; 2: current source 4 pwm; 3: current source 4 patt. curr3_mode<5:4> 0: current source 3 off; 1:current source 3 on; 2: current source 3 pwm; 3: current source 3 patt. curr2_mode<3:2> 0: current source 2 off; 1:current source 2 on; 2: current source 2 pwm; 3: current source 2 patt. curr1_mode<1:0> 0: current source 1 off; 1:current source 1 on; 2: current source 1 pwm; 3: current source 1 patt. 02h curr1 current curr1_current<7:0> output current for current source curr1 = 0ma ... 25.5ma; 256 steps of 0.1ma. 03h curr2 current curr2_current<7:0> output current for current source curr2 = 0ma ... 25.5ma; 256 steps of 0.1ma. 04h curr3 current curr3_current<7:0> output current for current source curr3 = 0ma ... 25.5ma; 256 steps of 0.1ma. 05h curr4 current curr4_current<7:0> output current for current source curr4 = 0ma ... 25.5ma; 256 steps of 0.1ma. 2bh currx low voltage status curr4_low_v 0: curr4 voltage ok 1: curr4 low voltage curr3_low_v 0: curr3 voltage ok 1: curr3 low voltage curr2_low_v 0: curr2 voltage ok 1: curr2 low voltage curr1_low_v 0: curr1 voltage ok 1: curr1 low voltage gpio control 06h gpio control gpio_in_invert 0: non-inverted dig. input 1: inverted digital input gpio_in_en 0: analog input 1: digital input gpio_mode 0: input only 1: output (open drain) 07h gpio output gpio_out 0: gpio pin low 1: gpio pin high 08h gpio signal gpio_in 0: gpio pin low 1: gpio pin high pwm control 15h pwm control pwm_dim_shape 0: logarithmic ramp 1: linear ramp pwm_src 0: internal pwm 1: external pwm 16h pwm timing pwm_dim_speed_up<7:4> 0: immediate 1: 0.12s 2: 0.25s 3: 0.38s 4: 0.51s 5: 0.77s 6: 1.0s 7: 1.6s 8: 2.1s 9: 2.6s 10: 3.1s 11: 4.2s 12: 5.2s 13: 6.2s 14: 7.3s 15: 8.3s pwm_dim_speed_down 0: immediate 1: 0.12s 2: 0.25s 3: 0.38s 4: 0.51s 5: 0.77s 6: 1.0s 7: 1.6s 8: 2.1s 9: 2.6s 10: 3.1s 11: 4.2s 12: 5.2s 13: 6.2s 14: 7.3s 15: 8.3s
www.ams.com revision 1.13 45 - 59 as3668 2v0 data sheet - register map 17h pwm trigger start_dim 0: no dimming 1: start log dimming dim_curr4 0: curr4 off 1: curr4 on dim_curr3 0: curr3 off 1: curr3 on dim_curr2 0: curr2 off 1: curr2 on dim_curr1 0: curr1 off 1: curr1 on pattern control 18h pattern timing pattern_toff<5:3> 000: 0.08s 001: 0.15s 010: 0.28s 011: 0.54s 100: 1.1s 101: 2.1s 110: 4.2s 111: 8.4s pattern_ton<2:0> 000: 0.04s 001: 0.07s 010: 0.14s 011: 0.27s 100: 0.53s 101: 1.1s 110: 2.1s 111: 4.2s 19h multiple pulse multiple_pulse<7:6> 00: 1 pulse 01: 2 pulses 10: 3 pulses 11: 4 pulses tp_led<1:0> 00: 0ms 01: 150ms 10: 280ms 11: 540ms 1ah frame mask fmask_curr4<7:6> 00: no frame mask for curr4 01: mask 1 frame for curr4 10: mask 2 frame for curr4 11: mask 3 frame for curr4 fmask_curr3<5:4> 00: no frame mask for curr3 01: mask 1 frame for curr3 10: mask 2 frame for curr3 11: mask 3 frame for curr3 fmask_curr2<3:2> 00: no frame mask for curr2 01: mask 1 frame for curr2 10: mask 2 frame for curr2 11: mask 3 frame for curr2 fmask_curr1<1:0> 00: no frame mask for curr1 01: mask 1 frame for curr1 10: mask 2 frame for curr1 11: mask 3 frame for curr1 1bh start control pattern_phase_out 0: turn off immediately 1: phase out pattern pattern_enable 0: pattern off 1: start pattern pattern_start_src 0: softw. pattern enable 1: gpio pattern enable 1ch pattern frame start delay frame_delay4 0: no delay 1: curr4 1 frame delay 2: curr4 2 frames delay 3:curr4 3 frames delay frame_delay3 0: no delay 1: curr3 1 frame delay 2: curr3 2 frames delay 3:curr3 3 frames delay frame_delay2 0: no delay 1: curr2 1 frame delay 2: curr2 2 frames delay 3:curr2 3 frames delay frame_delay1 0: no delay 1: curr1 1 frame delay 2: curr1 2 frames delay 3:curr1 3 frames delay 1dh gpio toggle control gpio_toggle_en 0: disabled 1: enabled gpio_toggle_framenr 0: 1 frame 1: 2 frames 2: 3 frames 3: 4 frames adc result 26h adc_select 0: audip preamplifier 1: gpio direct adc_mode 0: linear adc 1: logarithmic adc adc_on 0: adc off 1: adc on 27h adc result adc_result<3:0> charge pump 00h reg control cp_on 0: charge pump off 1: charge pump on table 44. i2c register overview addr name b7 b6 b5 b4 b3 b2 b1 b0
www.ams.com revision 1.13 46 - 59 as3668 2v0 data sheet - register map 23h cp control cp_auto_on 0: manual cp mode 1: automatic cp mode cp_start_debounce 0: 32ms debounce time 1: 240 s debounce time cp_mode_switching 0: automatic mode 1: manual mode cp_mode 0: 1:1 mode 1: 1:2 mode cp_clk 0: 1mhz 1: 500khz overtemperature control 29h overtemp control vmon_vbat<6:5> 0: ~2v - shutdown mode 01: 3.0v - standby mode 10: 3.15v - standby mode 11: 3.3v - standby mode shutdown_enable 0: disable shutdown 1: enable shutdown rst_ov_temp ov_temp ov_temp_on 0: temp supervision off 1: temp supervision on audio control 40h audio agc agc_up_level 0: normal agc up switching level threshold 1: agc up switching threshold increased agc_down_level 0: normal agc down switching level threshold 1: agc down switching threshold increased decay_agc_down<4:3> 00: 0.131s 01: 0.262s 10: 0.393s 11: 0.524s decay_agc_up<2:1> 00: 0.262s 01: 0.524s 10: 0.786s 11: 1.049s agc_on 0: agc switched off 1: agc switched on 41h audio input buffer audio_dis_start 0: input cap precharge 1: no precharging audio_man_start 0: auto precharge 1: manual precharge audio_gain<5:1> controls the audio input gain from -6db ... +25db in 1db steps aud_buf_on 0: audio buffer off 1: audio buffer on 42h audio control audio_input_pin 0: gpio 1: curr4 pld_off 0: pull down enabled 1: pull down disabled adc_characteristic 0: x*250mv (linear) 1: x*50mv (linear) 0: 75mv*2 x (log) 1: 75mv*2 x (log) audio_decay<4:3> 00: 10ms 01: 20ms 10: 40ms 11: 80ms audiosync_mode<2:0> 000: 4 led bar code 001: 4 led bar code with dimming 010: running led bar code 011: running led bar code with dimming 100: rgb 101: rgb with dimming 110: 4 led parallel with dimming 111: - 43h audio output curr4_aud_en 0: curr4 normal mode 1: curr4 audio sync curr3_aud_en 0: curr3 normal mode 1: curr3 audio sync curr2_aud_en 0: curr2 normal mode 1: curr2 audio sync curr1_aud_en 0: curr1 normal mode 1: curr1 audio sync table 44. i2c register overview addr name b7 b6 b5 b4 b3 b2 b1 b0
www.ams.com/as3668 revision 1.13 47 - 59 as3668 data sheet - application information 10 application information 10.1 led software implementation examples 10.1.1 simple breathlight pattern with one led in this example we?d like to use curr1 in pattern generation mode to create a simple breathlight pattern without continuous i2c traffic. this helps to unload the calculation power from the cpu. figure 49. simple breathlight pattern example the timing example shown in figure 49 above, can be easily implemented with just a couple of i2c commands. table 45. code example simple breathlight pattern 10.1.2 dual pulse pattern with one led in this example we would like to use curr1 in pattern generation mode to create a simple dual pulse pattern without continuous i2c traffic. this helps again to unload the cpu. figure 50. dual pulse pattern example the timing example shown in figure 50 above, can be easily implemented with just a couple of i2c commands. register name address write value comments currx control 0x01 0x03 enable curr1 for pattern generation mode. other current sources are off curr1 current 0x02 0x96 set the output current of curr1 to 15ma. pwm timing 0x16 0x55 define rise/fall time with 0,77s pattern timing 0x18 0x32 define 0,15s on time and 4,21s off time start control 0x1b 0x02 start breathlight pattern
www.ams.com/as3668 revision 1.13 48 - 59 as3668 data sheet - application information table 46. code example dual pulse pattern example 10.1.3 rgb led pattern in this example we would like to demonstrate how to use an rgb led which is connected to curr1, curr2 and curr3. figure 51. rgb pulse pattern example with the timing example above you get a mixture of red, green and blue color. table 43 below shows how to configure the device to get the pattern shown in figure 51 . table 47. code example rgb pulse pattern register name address write value comments currx control 0x01 0x03 enable curr1 for pattern generation mode. other current sources are off curr1 current 0x02 0xff set the output current of curr1 to 25,5ma. pwm timing 0x16 0x11 define rise/fall time with 0,12s pattern timing 0x18 0x30 define 0,04s on time and 4,2s off time multiple pulse 0x19 0x41 define 2 pulses and 150ms pause time start control 0x1b 0x02 start breathlight pattern register name address write value comments currx control 0x01 0x3f enable curr1, curr2 and curr3 for pattern generation mode. curr4 is in off mode. curr1 current 0x02 0x4f set the output current of curr1 to 7,9ma. curr2 current 0x03 0xc8 set the output current of curr2 to 20ma. curr3 current 0x04 0xb6 set the output current of curr3 to 18,2ma. pwm timing 0x16 0x88 define rise/fall time with 2.1s pattern timing 0x18 0x25 define 1,1s on time and 1,1s off time multiple pulse 0x19 0x00 define single pulse mode start control 0x1b 0x02 start breathlight pattern
www.ams.com/as3668 revision 1.13 49 - 59 as3668 data sheet - application information 10.1.4 parallel up - dimming in this example we would like to demonstrate how to do simple pwm up-dimming of all four leds in parrallel. figure 52. pwm up-dimming example if the output current of all four current sources is configured according to the requirements of the application it is possible to dimm the leds up with a single i2c command. table 48. code example up-dimming 10.1.5 parallel down- dimming in this example we would like to demonstrate how to do simple pwm down-dimming of all four leds in parallel. figure 53. pwm down-dimming example register name address write value comments currx control 0x01 0xaa enable curr1, curr2, curr3 and curr4 for pwm mode. curr1 current 0x02 0x64 set the output current of curr1 to 10ma. curr2 current 0x03 0x64 set the output current of curr2 to 10ma. curr3 current 0x04 0x64 set the output current of curr3 to 10ma. curr4 current 0x05 0x64 set the output current of curr4 to 10ma. pwm timing 0x16 0x77 define dimming time with 1.6s pwm trigger 0x17 0x1f start up-dimming of all current sources with 1.7s dimming time.
www.ams.com/as3668 revision 1.13 50 - 59 as3668 data sheet - application information table 49. code example down-dimming register name address write value comments currx control 0x01 0xaa enable curr1, curr2, curr3 and curr4 for on mode. curr1 current 0x02 0x64 set the output current of curr1 to 10ma. curr2 current 0x03 0x64 set the output current of curr2 to 10ma. curr3 current 0x04 0x64 set the output current of curr3 to 10ma. curr4 current 0x05 0x64 set the output current of curr4 to 10ma. pwm trigger 0x17 0x0f enable curr1, curr2, curr3 and curr4 for pwm mode. all four current sources keep switched on when we change from on mode to pwm mode. pwm timing 0x16 0x77 define dimming time with 1.6s pwm trigger 0x17 0x10 start down-dimming of all current sources with 1.7s dimming time.
www.ams.com/as3668 revision 1.13 51 - 59 as3668 data sheet - application information 10.2 hardware examples figure 54. as3668 standard 4 channel led application example 1 1 2 2 3 3 4 4 d d c c b b a a c4 1uf gnd c3 1uf gnd c1 470nf curr1 curr2 curr3 curr4 gnd as3668 cp a2 cn a3 gnd d2 vcp b1 vbat c2 sda c3 scl b3 gpio d3 curr1 b2 curr2 c1 curr3 a1 curr4 d1 4-channel breathlight- controller u1 as3668 vbat d1 d2 d3 d4 gnd gnd gnd gnd cpu for i2c control r1 10k r2 10k c2 gnd digital_io digital_io
www.ams.com/as3668 revision 1.13 52 - 59 as3668 data sheet - application information figure 55. as3668 standard rgb led operation with gpio control application example 1 1 2 2 3 3 4 4 d d c c b b a a c4 1uf gnd c3 1uf gnd c1 470nf curr1 curr2 curr3 gnd as3668 cp a2 cn a3 gnd d2 vcp b1 vbat c2 sda c3 scl b3 gpio d3 curr1 b2 curr2 c1 curr3 a1 curr4 d1 4-channel breathlight- controller u1 as3668 vbat d2 d3 d4 gnd gnd gnd cpu for i2c control r1 10k r2 10k c2 gnd digital_io digital_io battery terminal r3 10k device to be controlled with as3668 digital_io
www.ams.com/as3668 revision 1.13 53 - 59 as3668 data sheet - application information figure 56. as3668 audio synchronization application example 1 1 2 2 3 3 4 4 d d c c b b a a c4 1uf gnd c3 1uf gnd c1 470nf curr1 curr2 curr3 gnd as3668 cp a2 cn a3 gnd d2 vcp b1 vbat c2 sda c3 scl b3 gpio d3 curr1 b2 curr2 c1 curr3 a1 curr4 d1 4-channel breathlight- controller u1 as3668 vbat d2 d3 d4 gnd gnd gnd cpu for i2c control r1 10k r2 10k c2 gnd digital_io digital_io battery terminal audio dac or amplifier d1 gnd curr4 c5 470nf r3 1k r4 1k right channel left channel curr4 can also be configured as audio input
www.ams.com/as3668 revision 1.13 54 - 59 as3668 data sheet - application information figure 57. as3668 charger application example with audio synchronization 1 1 2 2 3 3 4 4 d d c c b b a a c4 1uf gnd c3 1uf gnd c1 470nf curr1 curr2 curr3 gnd as3668 cp a2 cn a3 gnd d2 vcp b1 vbat c2 sda c3 scl b3 gpio d3 curr1 b2 curr2 c1 curr3 a1 curr4 d1 4-channel breathlight- controller u1 as3668 vbat d2 d3 d4 gnd gnd gnd cpu for i2c control r1 10k r2 10k c2 gnd digital_io digital_io battery terminal audio dac or amplifier c5 470nf r3 1k r4 1k right channel left channel integrated charger circuit q1 vbat r5 10k the led driver output of a charger can be linked together with the gpio input of as3668 to indicate trickle charging with a default breathlight pattern on curr1 while the cpu is not working at all.
www.ams.com/as3668 revision 1.13 55 - 59 as3668 data sheet - application information figure 58. as3668 dual rgb led application example 1 1 2 2 3 3 4 4 d d c c b b a a c4 1uf gnd c3 1uf gnd c1 470nf curr1 curr2 curr3 gnd as3668 cp a2 cn a3 gnd d2 vcp b1 vbat c2 sda c3 scl b3 gpio d3 curr1 b2 curr2 c1 curr3 a1 curr4 d1 4-channel breathlight- controller u1 as3668 vbat cpu for i2c control r1 10k r2 10k c2 gnd digital_io digital_io battery terminal audio dac or amplifier c5 470nf r3 1k r4 1k right channel left channel d2 d3 d4 gnd gnd q1 q2 curr4 d5 d6 d7 r5 10k please mind that the rgb leds can't be used at the same time with the white leds.
www.ams.com/as3668 revision 1.13 56 - 59 as3668 data sheet - package drawings and markings 11 package drawings and markings the device is available in a 12-pin wl-csp (1.255x1.680mm) package. figure 59. 12-pin wl-csp (1.255x1.680mm) marking table 50. packaging code xxxx xxxx encoded datecode
www.ams.com/as3668 revision 1.13 57 - 59 as3668 data sheet - package drawings and markings figure 60. 12-pin wl-csp (1.255x1.680mm) package drawing notes: ccc coplanarity all dimensions in m
www.ams.com/as3668 revision 1.13 58 - 59 as3668 data sheet - o rdering information 12 ordering information the devices are available as the standard products shown in table 51 . note: all products are rohs compliant and ams green. buy our products or get free samples online at www.ams.com/icdirect technical support is available at www.ams.com/technical-support for further information and requests, email us at sales@ams.com (or) find your local distributor at www.ams.com/distributor table 51. ordering information ordering code marking description delivery form package AS3668-BWLT as3668 4-channel smart led driver tape & reel 12-pin wl-csp (1.255x1.680mm)
www.ams.com/as3668 revision 1.13 59 - 59 as3668 data sheet - copyrights copyrights copyright ? 1997-2013, ams ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registered ?. all right s reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written con sent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by ams ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. ams ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with ams ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliabi lity applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without addi tional processing by ams ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the stan dard production flow, such as test flow or test location. the information furnished here by ams ag is believed to be correct and accurate. however, ams ag shall not be liable to recipie nt or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruptio n of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, perfo rmance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of ams ag rendering o f technical or other services. contact information headquarters ams ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel : +43 (0) 3136 500 0 fax : +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.ams.com/contact

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