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| ? semiconductor ml9050/9051 1/71 pedl9050-02 ? semiconductor ml9050/9051 132-channel lcd driver with built-in ram for lcd dot matrix displays general description the ml9050/9051 is an lsi for dot matrix graphic lcd devices carrying out bit map display. this lsi can drive a dot matrix graphic lcd display panel under the control of an 8-bit microcomputer. since all the functions necessary for driving a bit map type lcd device are incorporated in a single chip, using the ml9050/9051 makes it possible to realize a bit map type dot matrix graphic lcd display system with only a few chips. since the bit map method in which one bit of display ram data turns on or off one dot in the display panel, it is possible to carry out displays with a high degree of freedom such as chinese character displays, etc. with one chip, it is possible to construct a graphic display system with a maximum of 132 65 dots. the display can be expanded further using two chips. the ml9050/9051 is made using a cmos process. because it has a built-in ram, low power consumption is one of its features, and is therefore suitable for displays in battery-operated portable equipment. the ml9050 has 65 common signal outputs and 132 segment signal outputs and one chip can drive a display of up to 65 132 dots. the ML9051 has 49 common signal outputs and 132 segment signal outputs and one chip can drive a display of up to 49 132 dots. this device is not resistant to radiation or to light. features ? direct display of the ram data using the bit map method display ram data "1" ... dot is displayed display ram data "0" ... dot is not displayed ? display ram capacity ml9050/9051: 65 132 = 8580 dots ? lcd drive circuits ml9050: 65 common outputs, 132 segment outputs ML9051: 49 common outputs, 132 segment outputs ? microcomputer interface: can select an 8-bit parallel or serial interface ? built-in voltage multiplier circuit for the lcd drive power supply ? built-in lcd drive power supply adjustment circuit ? built-in lcd drive bias resistors ? line reversal drive/frame reversal drive (selected by a command) ? built-in oscillator circuit (internal rc oscillator/external clock input) ? a variety of commands read/write of display data, display on/off, normal/reverse display, all dots on/all dots off, set page address, set display start address, etc. ? power supply voltage logic power supply: v dd -v ss = 1.8 v to 5.5 v voltage multiplier reference voltage: v in -v ss = 1.8 v to v dd (5-times multiplier ? 1.8 v to 3.6 v, 6-times multiplier ? 1.8 to 3 v, 7-times multiplier ? 1.8 to 2.5 v) lcd drive voltage: v bi -v ss = 6.0 to 18 v ? package: gold bump chip, tcp pedl9050-02 this version: dec. 1999 previous version: jun. 1999 preliminary
? semiconductor ml9050/9051 2/71 pedl9050-02 block diagram v dd v in frs v1 v2 v3 v4 v5 v ss vc1+ vs1C vc2+ vs2C vc3+ vc4+ vc5+ vc6+ vout vr vrs irs hpm seg drivers com drivers com output state selection cricuit display data latch circuit display data ram 132 65 column address circuit bus holder c86 cs1 cs2 a0 rd (e) wr (r/ w ) p/ s res d7(si) d6(scl) d5 d4 d3 d2 d1 d0 oscillator circuit display timing generator circuit coms coms com63 com0 seg131 seg0 line address circuit i/o buffer page address circuit power supply circuit command decoder status mpu lnterface fr cl dof m/ s cls ? semiconductor ml9050/9051 3/71 pedl9050-02 pin description function pin name number of pins description mpu interface 8 i/o i/o d0 to d7 this is an 8-bit bi-directional data bus that can be connected to an 8-bit or 16-bit standard mpu data bus. when a serial interface is selected (p/ s = "l"): d7: serial data input pin (si) d6: serial clock input pin (scl) in this case, d0 to d5 will be in the hi-z state. d0 to d7 will all be in the hi-z state when the chip select is in the inactive state. 1i a0 normally, the lowest bit of the mpu address bus is connected and used for distinguishing between data and commands. a0 = "h": indicates that d0 to d7 is display data. a1 = "l": indicates that d0 to d7 is control data. 1i res initial setting is made by making res = "l". the reset operation is made during the active level of the res signal. 2i cs1 cs2 these are the chip select signals. the chip select of the lsi becomes active when cs1 is "l" and also cs2 is "h" and allows the input/output of data or commands. 1i rd (e) the active level of this signal is "l" when connected to an 80-series mpu. this terminal is connected to the rd signal of the 80-series mpu, and the data bus of the ml9050/9051 goes into the output state when this signal is "l". the active level of this signal is "h" when connected to a 68-series mpu. this pin will be the enable and clock input pin when connected to a 68- series mpu. 1i wr (r/ w ) the active level of this signal is "l" when connected to an 80-series mpu. this terminal is connected to the wr signal of the 80-series mpu. the data on the data bus is latched into the ml9052 at the rising edge of the wr signal. when connected to a 68-series mpu, this pin becomes the input pin for the read/write control signal. r/ w = "h": read, r/ w = "l": write 1i c86 this is the pin for selecting the mpu interface type. c86 = "h": 68-series mpu interface. c86 = "l": 80-series mpu interface. ? semiconductor ml9050/9051 4/71 pedl9050-02 function pin name number of pins description mpu interface i/o 1i p/ s data/command data read/write serial clock m/ s cls dof frs fr cl power supply circuit oscillator circuit "h" "h" "l" output output output output output output output input enabled enabled enabled disabled "l" "h" "l" input input output output input input input input disabled disabled disabled disabled "h" "l" a0 a0 d0 to d7 si (d7) rd , wr write only scl (d6) p/ s this is the pin for selecting parallel data input or serial data input. p/ s = "h": parallel data input. p/ s = "l": serial data input. the pins of the lsi have the following functions depending on the state of p/ s input. when p/ s is "l", d0 to d5 will go into the hi-z state. in this condition, the data on the lines d0 to d5 can be "h", "l", or open. the pins rd (e) and wr (r/ w ) should be tied to either the "h" level or the "l" level. during serial data input, it is not possible to read the display data in the ram. oscillator circuit 1i cls this is the pin for selecting whether to enable or disable the internal oscillator circuit for the display clock. cls = "h": the internal oscillator circuit is enabled. cls = "l": the internal oscillator circuit is disabled (external input). when cls = "l", the display clock is input at the pin cl. display timing generator circuit 1i m/ s this is the pin for selecting whether master operation or slave operation is made towards the ml9050/9051. during master operation, the synchronization with the lcd display system is achieved by inputting the timing signals necessary for lcd display. m/ s = "h": master operation m/ s = "l": slave operation the functions of the different circuits and pins will be as follows depending on the states of m/ s and cls signals. ? semiconductor ml9050/9051 5/71 pedl9050-02 function pin name number of pins description i/o m/ s cls cl "h" "h" "l" output input "l" "h" "l" input input display timing generator circuit 1 i/o cl this is the display clock input/output pin. the function of this pin will be as follows depending on the states of m/ s and cls signals. when the ml9050/9051 is used in the master/slave mode, the corresponding cl pin has to be connected. 1 i/o fr this is the input/output pin for lcd display frame reversal signal. m/ s = "h": output m/ s = "l": input when the ml9050/9051 is used in the master/slave mode, the corresponding fr pin has to be connected. 1 i/o dof this is the blanking control pin for the lcd display. m/ s = "h": output m/ s = "l": input when the ml9050/9051 is used in the master/slave mode, the corresponding dof pin has to be connected. 1o frs this is the output pin for static drive. this pin is used in combination with the fr pin. power supply circuit 1i irs this is the pin for selecting the resistor for adjusting the voltage v1. irs = "h": the internal resistor is used. irs = "l": the internal resistor is not used. the voltage v1 is adjusted using the external potential divider resistors connected to the pins vr. this pin is effective only in the master operation. this pin is tied to the "h" or the "l" level during slave operation. 1i hpm this is the power control pin for the lcd drive power supply circuit. hpm = "h": normal mode hpm = "l": high power mode this pin is effective only during master operation mode. this pin is tied to the "h" or the "l" level during slave operation. 13 v dd this pin is tied to the mpu power supply terminal vcc. 9 v ss this is the 0 v pin connected to the system ground (gnd). 4 v in this is the reference power supply of the voltage multiplier circuit for driving the lcd. ? semiconductor ml9050/9051 6/71 pedl9050-02 function pin name number of pins description i/o ml9050 v2 8/9 v1 6/7 v1 v3 7/9 v1 5/7 v1 v4 2/9 v1 2/7 v1 v5 1/9 v1 1/7 v1 power supply circuit 2 v rs this is the external input vreg power supply for the lcd power supply voltage adjustment circuit. (this pin should be left open when not used as an external input) this pin is effective only in the case of optional devices with the vreg external input option. 2o v out these are the output pins during voltage multiplication. connect a capacitor between these pins and v ss . 10 v1 v2 v3 v4 v5 these are the multiple level power supply pins for the lcd power supply. the voltages specified for the lcd cells are applied to these pins after resistor network voltage division or after impedance transformation using operational amplifiers. the voltages are specified taking v ss as the reference, and the following relationship should be maintained among them. v1 3 v2 3 v3 3 v4 3 v5 3 v ss master operation: when the power supply is on, the following voltages are applied to v2 to v5 from the built-in power supply circuit. the selection of voltages is determined by the lcd bias set command. 2i vr voltage adjustment pins. voltages between v1 and vss are applied using a resistance voltage divider. these pins are effective only when the internal resistors for voltage v1 adjustment are not used (irs = "l"). do not use these pins when the internal resistors for voltage v1 adjustment are used (irs = "h"). 2o vc1+ these are the pins for connecting the positive side of the capacitors for voltage multiplication. connect capacitors between vs1C and these pins. 2o vs1C these are the pins for connecting the negative side of the capacitors for voltage multiplication. connect capacitors between these pins and vc1+, vc3+, and vc5+. ML9051 v2 7/8 v1 5/6 v1 v3 6/8 v1 4/6 v1 v4 2/8 v1 2/6 v1 v5 1/8 v1 1/6 v1 ? semiconductor ml9050/9051 7/71 pedl9050-02 function pin name number of pins description i/o ram data fr output voltage normal display reverse display h h v1 v3 h l vss v4 l h v3 v1 l l v4 v ss power save v ss power supply circuit 2o vs2C these are the pins for connecting the negative side of the capacitors for voltage multiplication. connect capacitors between these pins and vc2+, vc4+, and vc6+ (during 7-times voltage multiplication). 2o vc3+ these are the pins for connecting the positive side of the capacitors for voltage multiplication. connect capacitors between vs1C and these pins. 2o vc4+ these are the pins for connecting the positive side of the capacitors for voltage multiplication. connect capacitors between vs2C and these pins. 2o vc5+ these are the pins for connecting the positive side of the capacitors for voltage multiplication. connect capacitors between vs1C and these pins. 2o vc6+ these are the pins for connecting the positive side of the capacitors for voltage multiplication. connect capacitors between vs2C and these pins (during 7-times voltage multiplication). for 6-times voltage multiplication, connect these pins to the v out pin. lcd drive output 132 o seg0 to seg131 these are the lcd segment drive outputs. one of the levels among v1, v3, v4, and v ss is selected depending on the combination of the display ram content and the fr signal. 2o vc2+ these are the pins for connecting the positive side of the capacitors for voltage multiplication. connect capacitors between vs2C and these pins. ? semiconductor ml9050/9051 8/71 pedl9050-02 function pin name number of pins description i/o lcd drive output 2o coms these are the com output pins only for indicators. both pins output the same signal. leave these pins open when they are not used. the same signal is output in both master and slave operation modes. test pin i test0 o test1 these are the pins for testing the ic chip. leave these pins open during normal use. scan data fr output voltage h h vss hlv1 lhv2 llv5 power save v ss 96 o com0 to comn these are the lcd common drive outputs. ml9050 com0 to com63 ML9051 com0 to com47 com one of the levels among v1, v2, v5, and vss is selected depending on the combination of the scan data and the fr signal. ? semiconductor ml9050/9051 9/71 pedl9050-02 functional description mpu interface ? selection of interface type the ml9050/9051 carries out data transfer using either the 8-bit bi-directional data bus (d7 to d0) or the serial data input line (si). either the 8-bit parallel data input or serial data input can be selected as shown in table 1 by setting the p/ s pin to the "h" or the "l" level. table 1 p/ s cs1 cs2 a0 rd wr c86 d7 d6 d5 to d0 h: parallel input l: serial input cs1 cs1 cs2 cs2 a0 a0 rd wr c86 d7 si d6 scl d5 to d0 (hz) a hyphen () indicates that the pin can be tied to the "h" or the "l" level. ? parallel interface when the parallel interface is selected, (p/ s = "h"), it is possible to connect this lsi directly to the mpu bus of either an 80-series mpu or a 68-series mpu as shown in table 2 depending on whether the pin c86 is set to "h" or "l". table 2 p/ s cs1 cs2 a0 rd wr d7 to d0 h: 68-series mpu bus l: 80-series mpu bus cs1 cs1 cs2 cs2 a0 a0 e rd r/ w wr d7 to d0 d7 to d0 the data bus signals are identified as shown in table 3 below depending on the combination of the signals a0, rd (e), and wr (r/ w ) of table 2. table 3 common 68-series 80-series a0 r/ wrd wr display data read display data write status read control data write (command) 1 1 0 0 1 0 1 0 0 1 0 1 1 0 1 0 ? semiconductor ml9050/9051 10/71 pedl9050-02 serial interface when the serial interface is selected (p/ s = "l"), the serial data input (si) and the serial clock input (scl) can be accepted if the chip is in the active state ( cs1 = "l" and cs2 = "h"). the serial interface consists of an 8-bit shift register and a 3-bit counter. the serial data is read in from the serial data input pin in the sequence d7, d6, ... , d0 at the rising edge of the serial clock input, and is converted into parallel data at the rising edge of the 8th serial clock pulse and processed further. the identification of whether the serial data is display data or command is judged based on the a0 input, and the data is treated as display data when a0 is "h" and as command when a0 is "l". the a0 input is read in and identified at the rising edge of the (8 n) th serial clock pulse after the chip has become active. fig. 1 shows the signal chart of the serial interface. (when the chip is not active, the shift register and the counter are reset to their initial states. no data read out is possible in the case of the serial interface. it is necessary to take sufficient care about wiring termination reflection and external noise in the case of the scl signal. we recommend verification of operation in an actual unit.) d7 si sc a0 cs2 cs1 1 d6 2 d5 3 d4 4 d3 5 d2 6 d1 7 d0 8 d7 9 d6 10 d5 11 d4 12 d3 13 d2 14 fig. 1 ? chip select the ml9050/9051 has the two chip select pins cs1 and cs2, and the mpu interface or the serial interface is enabled only when cs1 = "l" and cs2 = "h". when the chip select signals are in the inactive state, the d0 to d7 lines will be in the high impedance state and the inputs a0, rd , and wr will not be effective. when the serial interface has been selected, the shift register and the counter are reset when the chip select signals are in the inactive state. ? accessing the display data ram and the internal registers accessing the ml9050/9051 from the mpu side requires merely that the cycle time (t cyc ) be satisfied, and high speed data transfer without requiring any wait time is possible. also, during the data transfer with the mpu, the ml9050/9051 carries out a type of pipeline processing between lsis via a bus holder associated with the internal data bus. for example, when the mpu writes data in the display data ram, the data is temporarily stored in the bus holder, and is then written into the display data ram before the next data read cycle. further, when the mpu reads out data in the display data ram, first a dummy data read cycle is carried out to temporarily store the data in the bus holder which is then placed on the system bus and is read out during the next read cycle. there is a restriction on the read sequence of the display data ram, which is that the read instruction immediately after setting the address does not read out the data of that address, but that data is output as the data of the address specified during the second data read sequence, and hence care should be taken about this during reading. therefore, always one dummy read is necessary immediately after setting the address or after a write cycle. this relationship is shown in figs 2(a) and 2(b). ? semiconductor ml9050/9051 11/71 pedl9050-02 ? data write data bus holder n latch n+1 n+2 n+3 n n+1 n+2 n+3 wr mpu write signal internal timing fig. 2(a) ? data read data column address read signal address preset n n n n+1 preset n n n n+1 n+2 increment n+1 n+2 rd mpu wr bus holder internal timing address set #n dummy read data read #n data read #n+1 fig. 2(b) ? busy flag the busy flag being "1" indicates that the ml9050/9051 is carrying out internal operations, and hence no instruction other than a status read instruction is accepted during this period. the busy flag is output at pin d7 when a status read instruction is executed. if the cycle time (t cyc ) is established, there is no need to check this flag before issuing every command and hence the processing performance of the mpu can be increased greatly. ? semiconductor ml9050/9051 12/71 pedl9050-02 display data ram ? display data ram this is the ram storing the dot data for display and has an organization of 65 (8 pages 8 bits +1) 132 bits. it is possible to access any required bit by specifying the page address and the column address. since the display data d7 to d0 from the mpu corresponds to the lcd display in the direction of the common lines as shown in fig. 3, there are fewer restrictions during display data transfer when the ml9050/9051 is used in a multiple chip configuration, thereby making it easily possible to realize a display with a high degree of freedom. also, since the display data ram read/write from the mpu side is carried out via an i/o buffer, it is done independent of the signal read operation for the lcd drive. consequently, the display is not affected by flickering, etc., even when the display data ram is accessed asynchronously during the lcd display operation. d0 0111---0 d1 1000---0 d2 0000---0 d3 0111---0 d4 1000---0 display data ram com0 - - - com1 - - - com2 - - - com3 - - - com4 - - - lcd display fig. 3 ? page address circuit the page address of the display data ram is specified using the page address set command as shown in fig. 4. specify the page address again when accessing after changing the page. the page address 8 (d3, d2, d1, d0 ? 1, 0, 0, 0) is the ram area dedicated to the indicator, and only the display data d0 is valid in this page. ? column address circuit the column address of the display data ram is specified using the column address set command as shown in fig. 4. since the specified column address is incremented (by +1) every time a display data read/write command is issued, the mpu can access the display data continuously. further, the incrementing of the column address is stopped at the column address of 83h. since the column address and the page address are independent of each other, it is necessary, for example, to specify separately the new page address and the new column address when changing from column 83h of page 0 to column 00h of page 1. also, as is shown in table 4, it is possible to reverse the correspondence relationship between the display data ram column address and the segment output using the adc command (the segment driver direction select command). this reduces the ic placement restrictions at the time of assembling lcd modules. table 4 adc seg output d0 = "0" ? column address ? d0 = "1" ? column address ? 83(h) 0(h) 0(h) seg131 seg0 83(h) ? semiconductor ml9050/9051 13/71 pedl9050-02 ? line address circuit the line address circuit is used for specifying the line address corresponding to the com output when displaying the contents of the display data ram as is shown in fig. 4. normally, the topmost line in the display (com0 output in the normal display state of the common output, and com63 output and com47 output for the ml9050 and the ML9051, respectively, in the reverse display stage) is specified using the display start line address set command. the display area is 65 lines and 49 lines for the ml9050 and the ML9051, respectively, in the direction of increasing line address from the specified display start line address. it is possible to carry out screen scrolling and page changing by dynamically changing the line address using the display start line address set command. ? display data latch circuit the display data latch circuit is a latch for temporarily storing the data from the display data ram before being output to the lcd drive circuits. since the commands for selecting normal/ reverse display and turning the display on/off control the data in this latch, the data in the display data ram will not be changed. oscillator circuit this is an rc oscillator that generates the display clock. the oscillator circuit is effective only when m/ s = "h" and also cls = "h". the oscillations will be stopped when cls = "l", and the display clock has to be input to the cl pin. ? semiconductor ml9050/9051 14/71 pedl9050-02 fig. 4 0000 0001 0010 0011 0100 0101 page address d3 d2 d1 d0 data line address 0110 0111 1000 d3 d2 d1 d0 d7 d6 d5 d4 03h 02h 01h 00h 07h 06h 05h 04h 0bh 0ah 09h 08h 0fh 0eh 0dh 0ch 13h 12h 11h 10h 17h 16h 15h 14h 1bh 1ah 19h 18h 1fh 1eh 1dh 1ch 23h 22h 21h 20h 27h 26h 25h 24h 2bh 2ah 29h 28h 2fh 2eh 2dh 2ch 33h 32h 31h 30h 37h 36h 35h 34h 3ch 3bh 3ah 39h 40h 3fh 3eh 3dh com3 com2 com1 com0 com7 com6 com5 com4 com11 com10 com9 com8 com15 com14 com13 com12 com19 com18 com17 com16 com23 com22 com21 com20 com27 com26 com25 com24 com31 com30 com29 com28 com35 com34 com33 com32 com39 com38 com37 com36 com43 com42 com41 com40 com47 com46 com45 com44 com51 com50 com49 com48 com55 com54 com53 com52 com60 com59 com58 com57 coms com63 com62 com61 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 38h com56 d0 d0 00 01 02 03 04 05 06 07 83 82 81 80 7f 7e 7d 7c seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 7f 80 81 82 83 0 d0 04 03 02 01 00 1 d0 seg127 seg128 seg129 seg130 seg131 lcd out adc d7 d6 d5 d4 page0 page1 page2 page3 page4 page5 page6 page7 page8 (start) com output the 65th line and the 49th line for the ml9050 and the ML9051, respectively, accessed irrespective of the display start line address. column address when the common output state is normal display 63lines 48lines ? semiconductor ml9050/9051 15/71 pedl9050-02 display timing generator circuit this circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. the display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. this circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. the display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. the read out of the display data to the lcd drive circuits is completely independent of the display data ram access from the mpu. as a result, there is no bad influence such as flickering on the display even when the display data ram is accessed asynchronously during the lcd display. also, the internal common timing and lcd frame reversal (fr) signals are generated by this circuit from the display clock. the drive waveforms of the frame reversal drive method shown in fig. 5(a) for the lcd drive circuits are generated by this circuit. further, the drive waveforms of the line reversal method shown in fig. 5(b) can also be generated depending on the issued command. in the line reversal drive method, it is possible to carry out reverse display drive at every line to a maximum of 32 lines. fig. 5(b) shows the waveforms of the 1 line reversal drive method. ram data v ss v5 com1 6465123456 v2 v1 v ss v4 segn v3 v1 606162636465123456 v ss v5 com0 v2 v1 fr lcdck (display clock) fig. 5(a) waveforms in the frame reversal drive method ? semiconductor ml9050/9051 16/71 pedl9050-02 fig. 5(b) waveforms in the line reversal drive method when the ml9050/9051 is used in a multiple chip configuration, it is necessary to supply the slave side display timing signals (fr, cl, and dof ) from the master side. the statuses of the signals fr, cl, and dof are shown in table 5. table 5 operating mode fr cl dof master mode (m/ s = "h") output output output input output output slave mode (m/ s = "l") internal oscillator circuit enabled (cls = h) internal oscillator circuit disabled (cls = l) internal oscillator circuit enabled (cls = h) internal oscillator circuit disabled (cls = l) input input input input input input ram data v ss v5 com1 v2 v1 v ss v4 segn v3 v1 v ss v5 com0 v2 v1 6465123456 606162636465123456 lcdck (display clock) fr ? semiconductor ml9050/9051 17/71 pedl9050-02 common output state selection circuit (see table 6) since the com output scanning directions can be set using the common output state selection command in the ml9050/9051, it is possible to reduce the ic placement restrictions at the time of assembling lcd modules. table 6 state normal display reverse display com scanning direction com0 ? com63 com63 ? com0 com0 ? com47 com47 ? com0 ml9050 ML9051 lcd drive circuits this lsi incorporates 197 sets and 181 sets of multiplexers for the ml9050 and the ML9051, respectively, that generate 4-level outputs for driving the lcd. these output the lcd drive voltage in accordance with the combination of the display data, com scanning signals, and the fr signal. fig. 6 shows examples of the seg and com output waveforms in the frame reversal drive method. ? semiconductor ml9050/9051 18/71 pedl9050-02 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 fr v dd v ss com0 com1 com2 seg0 seg1 seg2 com0-seg0 com0-seg1 v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 v ss v1 v2 v3 v4 v5 0v -v5 -v4 -v3 -v2 -v1 v1 v2 v3 v4 v5 0v -v5 -v4 -v3 -v2 -v1 fig. 6 ? semiconductor ml9050/9051 19/71 pedl9050-02 power supply circuit this is the low power consumption type power supply circuit for generating the voltages necessary for driving lcd devices, and consists of voltage multiplier circuits, voltage adjustment circuits, and voltage follower circuits. in the power supply circuit, it is possible to control the on/off of each of the circuits of the voltage multiplier, voltage adjustment circuits, and voltage follower circuits using the power control set command. as a result, it is also possible to use parts of the functions of both the external power supply and the internal power supply. table 7 shows the functions controlled by the 3-bit data of the power control set command and table 8 shows a sample combination. table 7 details of functions controlled by the bits of the power control set command control bit function controlled by the bit d2 voltage multiplier circuit control bit d1 voltage adjustment circuit (v adjustment circuit) control bit d0 voltage follower circuit (v/f circuit) control bit table 8 sample combination for reference state used d2 d1 d0 circuit external voltage input voltage multiplier pins * 1 voltage multiplier v adjustment v/f only the internal power supply is used 111 v in used only v adjustment and v/f circuits are used 011 v out open only v/f circuits are used 0 0 1 v1 open only the external power supply is used 000 v1 to v5 open *1: the voltage multiplier pins are the pins vc1+, vs1-, vc2+, vs2-, vc3+, vc4+, vc5+, and vc6+. if combinations other than the above are used, normal operation is not guaranteed. ? semiconductor ml9050/9051 20/71 pedl9050-02 ? voltage multiplier circuits the connections for 2-times to 7-times voltage multiplier circuits are shown below. fig. 7 v in v ss v out vc6+ vc4+ vc2+ vs2C vc5+ vc3+ vc1+ vs1C 2-times voltage multiplier circuit open open open open v in v ss v out vc6+ vc4+ vc2+ vs2C vc5+ vc3+ vc1+ vs1C 3-times voltage multiplier circuit open open v in v ss v out vc6+ vc4+ vc2+ vs2C vc5+ vc3+ vc1+ vs1C 4-times voltage multiplier circuit open v in v ss v out vc6+ vc4+ vc2+ vs2C vc5+ vc3+ vc1+ vs1C 5-times voltage multi p lier circuit v in v ss v out vc6+ vc4+ vc2+ vs2C vc5+ vc3+ vc1+ vs1C 6-times voltage multiplier circuit v in v ss v out vc6+ vc4+ vc2+ vs2C vc5+ vc3+ vc1+ vs1C 7-times voltage multiplier circuit ? semiconductor ml9050/9051 21/71 pedl9050-02 ? voltage adjustment circuit the voltage multiplier output vout produces the lcd drive voltage v1 via the voltage adjustment circuit. since the ml9050/9051 incorporates a high accuracy constant voltage generator, a 64-level electronic potentiometer function, and also resistors for voltage v1 adjustment, it is possible to build a high accuracy voltage adjustment circuit with very few components. in addition, the ml9050/9051 is available in three models with the temperature gradients of - (1) about -0.05%/?c, (2) about -0.2%/?c, and (3) external input (input to pin vrs), as a vreg option. (a) when the internal resistors for voltage v1 adjustment are used it is possible to control the lcd power supply voltage v1 and adjust the intensity of lcd display using commands and without needing any external resistors, if the internal voltage v1 adjustment resistors and the electronic potentiometer function are used. the voltage v1 can be obtained by the following equation a-1 in the range of v1 ? semiconductor ml9050/9051 23/71 pedl9050-02 (b) when external resistors are used (voltage v1 adjustment internal resistors are not used) - case 1 it is also possible to set the lcd drive power supply voltage v1 without using the internal resistors for voltage v1 adjustment but connecting external resistors (ra' and rb') between v ss & vr and between vr & v1. even in this case, it is possible to control the lcd power supply voltage v1 and adjust the intensity of lcd display using commands if the electronic potentiometer function is used. the voltage v1 can be obtained by the following equation b-1 in the range of v1 ? semiconductor ml9050/9051 26/71 pedl9050-02 ? application circuits (1) when the voltage multiplier circuit, voltage adjustment circuit, and v/f circuits are all used (2) when the voltage multiplier circuit, voltage adjustment circuit, and v/f circuits are all used when using the voltage v1 adjustement internal resistors when not using the voltage v1 adjustement internal resistors v in = v dd 7-times voltage multiplication v in = v dd 7-times voltage multiplication (3) when only the voltage adjustment circuit and the v/f circuits are used (4) when only the v/f circuits are used when not using the voltage v1 adjustment internal resistors when using the voltage v1 adjustment internal resistors irs v in vc6+ vc4+ vc2+ vs2C vc5+ vc3+ vc1+ vs1C v1 vr v ss v out v1 v2 v3 v4 v5 m/ s v dd v ss c1: 1.0 to 4.7 m c2: 0.47 to 1.0 m f irs v in vc6+ vc4+ vc2+ vs2C vc5+ vc3+ vc1+ vs1C v1 vr v ss v out v1 v2 v3 v4 v5 m/ s v dd v ss c1: 1.0 to 4.7 m c2: 0.47 to 1.0 m f c1 c1 c1 c1 c1 c1 c1 c2 c2 c2 c2 c2 c2: 0.47 to 1.0 m f c1 c1 c1 c1 c1 c1 c1 c2 c2 c2 c2 c2 r 1 r 2 r 3 irs v in vc6+ vc4+ vc2+ vs2C vc5+ vc3+ vc1+ vs1C v1 vr v ss v out v1 v2 v3 v4 v5 m/ s v dd v ss c2: 0.47 to 1.0 m f c2 c2 c2 c2 c2 r 1 r 2 r 3 irs v in vc6+ vc4+ vc2+ vs2C vc5+ vc3+ vc1+ vs1C v1 vr v ss v out v1 v2 v3 v4 v5 m/ s v dd v ss c2 c2 c2 c2 c2 external power supply external power supply ? semiconductor ml9050/9051 27/71 pedl9050-02 irs v in vc6+ vc4+ vc2+ vs2C vc5+ vc3+ vc1+ vs1C v1 vr v ss v out v1 v2 v3 v4 v5 m/ s v dd v ss (5) when not using the internal power supply external power supply ? semiconductor ml9050/9051 28/71 pedl9050-02 ? reset circuit this lsi goes into the initialized condition when the res input goes to the "l" level. the initialized condition consists of the following conditions. (1) display off (2) normal display mode (3) adc select: incremented (adc command d0 = "l") (4) power control register: (d2, d1, d0) = (0, 0, 0) (5) the registers and data in the serial interface are cleared. (6) lcd power supply bias ratio: ml9050 ... 1/9 bias, ML9051 ... 1/8 bias (7) read-modify-write: off (8) static indicator: off static indicator register: (d1, d2) = (0, 0) (9) line 1 is set as the display start line. (10) the column address is set to address 0. (11) the page address is set to 0. (12) common output state: normal (13) voltage v1 adjustment internal resistor ratio register: (d2, d1, d0) = (1, 0, 0) (14) the electronic potentiometer register set mode is released. electronic potentiometer register: (d5, d4, d3, d2, d1, d0) = (1, 0, 0 ,0, 0, 0) (15) the lcd drive method is set to the frame reversal method. line reversal count register: (d4, d3, d2, d1, d0) = (1, 0, 0, 0, 0) on the other hand, when the reset command is used, only the conditions (7) to (15) above are set. as is shown in the "mpu interface (example for reference)", the res pin is connected to the reset pin of the mpu and the initialization of this lsi is made simultaneously with the resetting of the mpu. this lsi always has to be reset using the res pin at the time the power is switched on. also, excessive current can flow through this lsi when the control signal from the mpu is in the hi-z state. it is necessary to take measures to ensure that the input terminals of this lsi do not go into the hi-z state after the power has been switched on. when the built-in lcd drive power supply circuit of the ml9050/9051 is not used, it is necessary that res = "l" when the external lcd drive power supply goes on. during the period when res = "l", although the oscillator circuit is operating, the display timing generator would have stopped and the pins cl, fr, frs, and dof would have been tied to the "h" level. there is no effect on the pins d0 to d7. ? semiconductor ml9050/9051 29/71 pedl9050-02 commands mpu interface mpu read mode write mode 80-series pin rd = "l" pin wr = "l" 68-series pin r/ w = "h" pin e = "h" pin r/ w = "l" pin e = "h" in the case of the 80-series mpu interface, a command is started by inputting a low pulse on the rd pin or the wr pin. in the case of the 68-series mpu interface, a command is started by inputting a high pulse on the e pin. description of commands ? display on/off (write) this is the command for controlling the turning on or off the lcd panel. the lcd display is turned on when a "1" is written in bit d0 and is turned off when a "0" is written in this bit. a0 d7 d6 d5 d4 d3 d2 d1 d0 display on display off 0 0 10101111 0 ? display start line set (write) this command specifies the display starting line address in the display data ram. normally, the topmost line in the display is specified using the display start line set command. it is possible to scroll the display screen by dynamically changing the address using the display start line set command. d7 d6 d5 d4 d3 d2 line address d1 0 1 2 62 63 010 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 1 1 . . . . . . . . . . . . . . . . . . a0 0 d0 0 1 0 0 1 . . . ? semiconductor ml9050/9051 30/71 pedl9050-02 ? page address set (write) this command specifies the page address which corresponds to the lower address when accessing the display data ram from the mpu side. it is possible to access any required bit in the display data ram by specifying the page address and the column address. a0 d7 d6 d5 d4 d3 page address d2 0 1 2 7 8 010110 0 0 0 1 0 0 0 1 0 . . . . . . . . . d1 0 0 1 1 0 . . . d0 0 1 0 1 0 . . . ? column address set (write) this command specifies the column address of the display data ram. the column address is specified by successively writing the upper 4 bits and the lower 4 bits. since the column address is automatically incremented (by +1) every time the display data ram is accessed, the mpu can read or write the display data continuously. the incrementing of the column address is stopped at the address 83h. a0 d7 d6 d5 d4 d3 d2 d1 d0 upper bits lower bits 00001 0 a7 a3 a6 a2 a5 a1 a4 a0 a6 a5 a4 a3 a2 a1 column address a0 0 1 2 130 131 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 . . . . . . a7 0 0 0 1 1 . . . . . . . . . . . . . . . . . . . . . ? semiconductor ml9050/9051 31/71 pedl9050-02 ? status read (read) a0 d7 d6 d5 d4 d3 d2 d1 d0 busy 0 busy adc on/off reset 0000 when busy is '1', it indicates that the internal operations are being made or the lsi is being reset. although no command is accepted until busy becomes '0', there is no need to check this bit if the cycle time can be satisfied. adc this bit indicates the relationship between the column address and the segment driver. 0: seg0 ? seg131; column address 0h ? 83h 1: seg131 ? seg0; column address 0h ? 83h (opposite to the polarity of the adc command.) on/off this bit indicates the on/off state of the display. (opposite to the polarity of the display on/off command.) 0: display on 1: display off reset this bit indicates that the lsi is being reset due to the res signal or the reset command. 0: operating state 1: being reset ? display data write (write) this command writes an 8-bit data at the specified address of the display data ram. since the column address is automatically incremented (by +1) after writing the data, the mpu can write successive display data to the display data ram. a0 d7 d6 d5 d4 d3 d2 d1 d0 1 write data ? display data read (read) this command read the 8-bit data from the specified address of the display data ram. since the column address is automatically incremented (by +1) after reading the data, the mpu can read successive display data from the display data ram. further, one dummy read operation is necessary immediately after setting the column data. the display data cannot be read out when the serial interface is being used. a0 d7 d6 d5 d4 d3 d2 d1 d0 1 read data ? semiconductor ml9050/9051 32/71 pedl9050-02 ? adc select (segment driver direction select) (write) using this command it is possible to reverse the relationship of correspondence between the column address of the display data ram and the segment driver output. it is possible to reverse the sequence of the segment driver output pin by the command. a0 d7 d6 d5 d4 d3 d2 d1 d0 forward reverse 010100000 1 ? normal/reverse display mode (write) it is possible to toggle the display on and off condition without changing the contents of the display data ram. in this case, the contents of the display data ram will be retained. a0 d7 d6 d5 d4 d3 d2 d1 d0 forward reverse 0101 ram data lcd on voltage when "h" lcd on voltage when "l" 00110 1 ? display all-on on/off (write) using this command, it is possible to forcibly turn on all the dots in the display irrespective of the contents of the display data ram. in this case, the contents of the display data ram will be retained. this command is given priority over the normal/reverse display mode command. a0 d7 d6 d5 d4 d3 d2 d1 d0 normal display state all-on display 010100100 1 the power save mode will be entered into when the display all-on on command is executed in the display off condition. ? lcd bias set (write) this command is used for selecting the bias ratio of the voltage necessary for driving the lcd device or panel. a0 ml9050 d7 d6 d5 d4 d3 d2 d1 d0 1/9 bias 1/7 bias 010100010 1 ML9051 1/8 bias 1/6 bias ? semiconductor ml9050/9051 33/71 pedl9050-02 ? read-modify-write (write) this command is used in combination with the end command. when this command is issued once, the column address is not changed when the display data read command is issued, but is incremented (by +1) only when the display data write command is issued. this condition is maintained until the end command is issued. when the end command is issued, the column address is restored to the address that was effective at the time the read-modify-write command was issued last. using this function, it is possible to reduce the overhead on the mpu when repeatedly changing the data in special display area such as a blinking cursor. a0 d7 d6 d5 d4 d3 d2 d1 d0 011100000 ? end (write) this command releases the read-modify-write mode and restores the column address to the value at the beginning of the mode. a0 d7 d6 d5 d4 d3 d2 d1 d0 011101110 read-modify-write mode set n n+1 n+2 n+3 .... n+m n column address end restored ? reset (write) this command initializes the display start line number, column address, page address, common output state, voltage v1 adjustment internal resistor ratio, electronic potentiometer function, and the static indicator function, and also releases the read-modify-write mode or the test mode. this command does not affect the contents of the display data ram. the reset operation is made after issuing the reset command. the initialization after switching on the power is carried out by the reset signal input to the res pin. a0 d7 d6 d5 d4 d3 d2 d1 d0 011100010 ? common output state select (write) this command is used for selecting the scanning direction of the com output pins. a0 d7 d6 d5 d4 d3 d2 d1 d0 forward reverse 0 ml9050 com0 ? com63 com63 ? com0 11000 1 * * * * * * ML9051 com0 ? com47 com47 ? com0 *: invalid bits ? semiconductor ml9050/9051 34/71 pedl9050-02 ? power control set (write) this command set the functions of the power supply circuits. a0 ml9050/9051 d7 d6 d5 d4 d3 d2 d1 d0 voltage multiplier circuit: off voltage multiplier circuit: on 0001010 1 voltage adjustment circuit: off voltage adjustment circuit: on 0 1 voltage follower circuits: off voltage follower circuits: on 0 1 ? voltage v1 adjustment internal resistor ratio set this command sets the ratios of the internal resistors for adjusting the voltage v1. d7 d6 d5 d4 d3 d2 resistor ratio d0 small large 0 a0 0 01000 0 0 1 1 0 1 0 0 1 . . . . . . d1 0 0 1 1 1 . . . . . . ? electronic potentiometer (2-byte command) this command is used for controlling the lcd drive voltage v1 output by the voltage adjustment circuit of the internal lcd power supply and for adjusting the intensity of the lcd display. this is a two-byte command consisting of the electronic potentiometer mode set command and the electronic potentiometer register set command, both of which should always be issued successively as a pair. ? electronic potentiometer mode set (write) when this command is issued, the electronic potentiometer register set command becomes effective. once the electronic potentiometer mode is set, it is not possible to issue any command other than the electronic potentiometer register set command. this condition is released after data has been set in the register using the electronic potentiometer register set command. a0 d7 d6 d5 d4 d3 d2 d1 d0 010000001 ? semiconductor ml9050/9051 35/71 pedl9050-02 ? electronic potentiometer register set (write) by setting a 6-bit data in the electronic potentiometer register using this command, it is possible to set the lcd drive voltage v1 to one of the 64 voltage levels. the electronic potentiometer mode is released after some data has been set in the electronic potentiometer register using this command. d7 d6 d5 d4 d3 d2 v1 d0 small large * a0 0*0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 1 0 1 . . . . . . . . . . . . . . . d1 0 1 1 1 1 . . . . . . *: invalid bit set the data (*, *, 1, 0, 0, 0, 0, 0) when not using the electronic potentiometer function. sequence of setting the electronic potentiometer register: ? static indicator (2-byte command) this command is used for controlling the static drive type indicator display. static indicator display is controlled only by this command and is independent of all other display control commands. one of the electrodes for driving the static indicator lcd is connected to the pin fr and the other pin is connected to the pin frs. it is recommended to place the wiring pattern for the electrodes for static indicators far from those of the electrodes for dynamic drive. if these interconnection patterns are too close to each other, they may cause deterioration of the lcd device and the electrodes. since the static indicator on command is a two-byte command used in combination with the static indictor register set command, these two commands should always be used together. (the static indicator off command is a single byte command.) electronic potentiometer mode set electronic potentiometer register set end of modification? yes no the electronic potentiometer mode is released ? semiconductor ml9050/9051 36/71 pedl9050-02 ? static indicator on/off (write) when the static indicator on command is issued, the static indicator register set command becomes effective. once the static indicator on command is issued, it is not possible to issue any command other than the static indicator register set command. this condition is released only after some data is written into the register using the static indicator register set command. a0 d7 d6 d5 d4 d3 d2 d1 d0 off on static indicator 010101100 1 ? static indicator register set (write) this command is used to set data in the 2-bit static indicator register thereby setting the blinking state of the static indicator. a0 d7 d6 d5 d4 d3 d2 d1 d0 off on (blinking at about 1sec intervals) on (blinking at about 0.5sec intervals) on (continuously on) indicator 0******0 0 1 1 0 1 0 1 *: invalid bits sequence of setting the static indicator register: static indicator on static indicator register set end of modification? yes no the static indicator mode is released ? line reversal drive (2-byte command) / frame reversal drive selection it is possible to select the lcd driving method between the line reversal drive method and the frame reversal drive methods. when the line reversal method is selected, the command should be used as a two-byte command in combination with the line reversal number set command and hence these two commands should always be issued successively. ? semiconductor ml9050/9051 37/71 pedl9050-02 static indicator off power save command issue (compound command) sleep state power save off command (compound command) display all-on off command static indicator on command (2-byte command) sleep state released static indicator on standby state power save off command (display all-on off command) standby state released ? lcd drive method set (write) this command sets the lcd driving method. once the line reversal method has been set, no command other than the line reversal number set command is accepted. this state is released only after some data is set in the register using the line reversal number set command. the frame reversal set command is a single byte command. *: invalid bits ? line reversal number set (write) when the line reversal method has been set using the lcd drive method set command, it is necessary to set immediately the number of reversed lines. *: invalid bits ? power save (compound command) the lsi goes into the power save state when the display all-on on command is issued when the lsi is in the display off state, and it is possible to greatly reduce the current consumption in this state. the power save state is of two types, namely, the sleep state and the standby state, and the lsi goes into the standby state when the static indicator has been made on. the display data and the operating mode just before entering the power save mode are retained in both the sleep state and the standby state, and also the mpu can access the display data ram in these states. the power save mode is released by issuing the display all-on off command. a0 d7 d6 d5 d4 d3 d2 d1 d0 frame reversal line reversal 011010 1 * * * * * * d6 d5 d4 d3 d2 d1 number of reversed lines d0 1 2 31 32 * d7 * a0 0*0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 . . . . . . . . . . . . . . . . . . ? semiconductor ml9050/9051 38/71 pedl9050-02 ? sleep state in this state, all the operations of the lcd display system are stopped and it is possible to reduce the current consumption to a level near the idle state current consumption unless there are accesses from the mpu. the internal conditions in the sleep state are as follows: (1) the oscillator circuit and the lcd power supply are stopped. (2) all the lcd drive circuits are stopped and the segment and common driver outputs will be at the v ss level. ? standby state all operations of the dynamic lcd display section are stopped, only the static display circuits for the indicators operate and hence the current consumption will be the minimum necessary for static drive. the internal conditions in the standby state are as follows: (1) the power supply circuit for lcd drive is stopped. the oscillator circuit will be operating. (2) the lcd drive circuits for dynamic display are stopped and the segment and common driver outputs will be at the vss level. the static display section will be operating. when a reset command is issued in the standby state, the lsi goes into the sleep state. ? nop (write) this is a no operation command. a0 d7 d6 d5 d4 d3 d2 d1 d0 011100011 ? test (write) this is a command for testing the ic chip. do not use this command. when the test command is issued by mistake, this state can be released by issuing a nop command. this command will be ineffective if the test0 pin is open or at the "l" level. *: invalid bits a0 d7 d6 d5 d4 d3 d2 d1 d0 01111**** ? semiconductor ml9050/9051 39/71 pedl9050-02 list of commands 76543210 rd 1 10101110 1 1 1 2 01address 1 a0 0 0 0 wr no operation dn comment 0 0 0 display off display on lcd display: off when d0 = 0 on when d0 = 1 display start line set the display starting line address in the display ram is set. 3 1011address 1 00 page address set the page address in the display ram is set. 4 0001address (upper) 0000address (lower) 1 1 0 0 0 0 column address set (upper bits) column address set (lower bits) the upper 4 bits of the column address in the display ram is set. the lower 4 bits of the column address in the display ram is set. 5 status0000 0 01 status read the status information is read out from the upper 4 bits. 6 write data 1 10 display data write writes data to the display data ram. 7 read data 0 11 display data read reads data from the display data ram. 8 10100000 1 1 1 0 0 0 0 adc select forward reverse correspondence between the display data ram address and seg output. forward when d0 = 0; reverse when d0 = 1 9 10100110 1 1 1 0 0 0 0 normal display reverse display normal or reverse lcd display mode. normal mode when d0 = 0; reverse when d0 = 1 10 10100100 1 1 1 0 0 0 0 lcd normal display all-on display lcd normal display when d0 = 0; all-on display when d0 = 1 11 10100010 1 1 1 0 0 0 0 lcd bias set sets the lcd drive voltage bias ratio. ml9050: 1/9 when d0 = 0 and 1/7 when d0 = 1 ML9051: 1/8 when d0 = 0 and 1/6 when d0 = 1 12 11100000 1 00 read-modify-write incrementing column address during a write: +1; during a read: 0 13 11101110 1 00 end releases the read-modify-write state. 14 11100010 1 00 reset internal reset 15 11000*** 1*** 1 1 0 0 0 0 common output state select selects the com output scanning direction. forward when d3 = 0; reverse when d3 = 1 16 00101 operating state 1 00 power control set selects the operating state of the internal power supply. 17 00100 resistor ratio setting 1 00 voltage v1 adjustment internal resistor ratio set selects the internal resistor ratio. ? semiconductor ml9050/9051 40/71 pedl9050-02 76543210 rd a0 wr no operation dn comment 18 10000001 **electronic potentiometer value 1 1 0 0 0 0 electronic potentiometer mode set external potentiometer register set sets the v1 output voltage in the electronic potentiometer register. 19 10101100 1 ******state 1 1 1 0 0 0 0 0 0 static indicator on/off static indicator register set off when d0 = 0 on when d0 = 1 sets the blinking state. 20 11010*** 1*** ***line number 1 1 1 0 0 0 0 0 0 lcd drive method set line reversal number set frame reversal when d3 = 0. line reversal when d3 = 1. sets the number of lines ireversed. 21 power save compound command of display off and display all-on. 22 11100011 1 00 nop the "no operation" command. 23 1111**** 1 00 test the command for factory testing of the ic chip. *: invalid bits ? semiconductor ml9050/9051 41/71 pedl9050-02 description of commands examples of settings for the instructions (reference examples) ? initial setting v dd -v ss power supply on power supply stabilization reset input wait for more than 20ms *1 initial settings state (default) *2 initial setting state complete function stabilization using command input (user settings) lcd bias set adc select common output state selection line reversal / frame reversal drive method selection function stabilization using command input (user settings) function stabilization using command input (user settings) setting voltage v1 adjustment internal resistor ratio electronic potentiometer power control set *3 *4 *5 *6 *7 *8 *9 notes: sections to be referred to *1: stabilization time of the internal oscillator *2: function description "reset circuit" *3: command description "lcd bias set" *4: command description "adc select" *5: command description "common output state select" *6: command description "line reversal/frame reversal drive select" *7: function description "power supply circuit", command description "voltage v1 adjustment internal resistor ratio set" *8: function description "power supply circuit", command description "electronic potentiometer" *9: function description "power supply circuit", command description "power control set" ? semiconductor ml9050/9051 42/71 pedl9050-02 examples of settings for the instructions (reference examples) ? initial setting note: after the power is switched on, this lsi outputs at the lcd drive output pins seg and com the v ss potential. if any charge is remaining on the smoothing capacitors connected between the v out pin and the pins for the lcd drive voltage outputs (v1 to v5), there may be some abnormality in the display such as temporary blacking out of the display screen when the power is switched on. the following procedure is recommended for avoiding such abnormalities at the time the power is switched on. ? when using the internal power supply immediately after power-on v dd -v ss power supply on when the pin res = "l" power supply stabilization release reset state ( res pin = "h") initial settings state (default) *1 initial setting state complete function stabilization using command input (user settings) lcd bias set adc select common output state selection line reversal / frame reversal drive method selection function stabilization using command input (user settings) function stabilization using command input (user settings) setting voltage v1 adjustment internal resistor ratio electronic potentiometer power control set *2 *3 *4 *5 *6 *7 *8 *(a) *(a): carry out power control set within 5ms after releasing the reset state. the 5ms duration changes depending on the panel characteristics and the value of the smoothing capacitor. we recommend verification of operation using an actual unit. ? semiconductor ml9050/9051 43/71 pedl9050-02 notes: sections to be referred to *1: function description "reset circuit" *2: command description "lcd bias set" *3: command description "adc select" *4: command description "common output state select" *5: command description "line reversal/frame reversal drive select" *6: function description "power supply circuit", command description "voltage v1 adjustment internal resistor ratio set" *7: function description "power supply circuit", command description "electronic potentiometer" *8: function description "power supply circuit", command description "power control set" ? semiconductor ml9050/9051 44/71 pedl9050-02 ? when not using the internal power supply immediately after power-on power supply stabilization v dd -v ss power supply on when the pin res = "l" release reset state ( res pin = "h") initial settings state (default) start power save mode (compound command) function stabilization using command input (user settings) lcd bias set adc select common output state selection line reversal / frame reversal drive method selection function stabilization using command input (user settings) power save off setting voltage v1 adjustment internal resistor ratio electronic potentiometer *2 *3 *4 *5 *9 *1 *(a) *6 *7 function stabilization using command input (user settings) power control set *8 *9 initial setting state complete *(b) *(a): enter the power save state within 5ms after releasing the reset state. *(b): carry out power control set within 5ms after releasing the power save state. the 5ms duration in *(a) and *(b) changes depending on the panel characteristics and the value of the smoothing capacitor. we recommend verification of operation using an actual unit. ? semiconductor ml9050/9051 45/71 pedl9050-02 notes: sections to be referred to *1: function description "reset circuit" *2: command description "lcd bias set" *3: command description "adc select" *4: command description "common output state select" *5: command description "line reversal/frame reversal drive select" *6: function description "power supply circuit", command description "voltage v1 adjustment internal resistor ratio set" *7: function description "power supply circuit", command description "electronic potentiometer" *8: function description "power supply circuit", command description "power control set" *9: the power save state can be either the sleep state or the standby state. command description "power save (compound command)" ? semiconductor ml9050/9051 46/71 pedl9050-02 ? data display end of initial settings function stabilization using command input (user settings) display start line set page address set column address set function stabilization using command input (user settings) end of data display display data write *10 *11 *12 *13 function stabilization using command input (user settings) display on/off *14 notes: sections to be referred to *10: command description "display start line set" *11: command description "page address set" *12: command description "column address set" *13: command description "display data write" *14: command description "display on/off" ? power supply off (*15) any state function stabilization using command input (user settings) power save v dd -v ss power supply off *16 *17 notes: sections to be referred to *15: the power supply of this lsi is switched off after switching off the internal power supply. function description "power supply circuit" if the power supply of this lsi is switched off when the internal power supply is still on, since the state of supplying power to the built-in lcd drive circuits continues for a short duration, it may affect the display quality of the lcd panel. always follow the power supply switching off sequence. *16: command description "power save" *17: do not enter reset when switching the power supply off. ? semiconductor ml9050/9051 47/71 pedl9050-02 ? refresh use the refresh sequence at regular intervals. refresh sequence set to the state in which all commands have been set. test mode release command (f0h) refresh ddram ? semiconductor ml9050/9051 48/71 pedl9050-02 absolute maximum ratings parameter symbol condition rated value unit power supply voltage v dd ta = 25?c v C0.3 to +7 bias voltage v bi ta = 25?c v C0.3 to +20 voltage multiplier reference voltage v in 6-times multiplication 7-times multiplication v C0.3 to +3.3 C0.3 to +2.8 input voltage v i ta = 25?c v C0.3 to vdd+0.3 storage temperature range t stg tcp chip ?c C55 to +100 C55 to +125 applicable pins v dd , v ss v out , v1 to v5 vin, vss all inputs v ss = 0 v ta: ambient temperature recommended operating conditions parameter symbol condition rated value unit power supply voltage v dd v 1.8 to 5.5 bias voltage v bi v 6 to 18 voltage multiplier reference voltage v in 6-times multiplication 7-times multiplication v 1.8 to 3 1.8 to 2.5 voltage multiplier output voltage v out v 18 reference voltage v reg0 v reg1 C0.05%/?c * 1 C0.2%/?c * 1 v applicable pins v dd , v ss v out , v1 to v5 vin, vss vout operating temperature range t op ?c C40 to +85 (3.0) note 1: the voltages v dd , v1 to v5, and v out are values taking v ss = 0 v as the reference. note 2: the highest bias potential is v1 and the lowest is v ss . note 3: always maintain the relationship v1 3 v2 3 v3 3 v4 3 v5 3 v ss among these voltages. *1: ta = 25?c v cc gnd v in v dd v ss v out v1 to v4 v5 ml9050/9051 system (mpu) side ? semiconductor ml9050/9051 49/71 pedl9050-02 electrical characteristics dc characteristics parameter symbol condition unit "h" input voltage "l" input voltage v ih v il v "h" output voltage "l" output voltage v oh v ol ioh = C0.5ma iol = 0.5ma v "h" input current "l" input current i ih i il vi = vdd vi = 0 v m a lcd driver on resistance r on io = 50 m ak w max vdd 0.2 vdd vdd 0.2 vdd 1.0 3.0 10 typ min 0.8 vdd vss 0.8 vdd vss C1.0 C3.0 applicable pins *1 [ta = C40 to +85?c] *2 *3 *4 seg1 to 132 com1 to 97 current consumption i dds standby m a 5v dd input pin capacitance c in ta = 25?c, f = 1mhz pf 8 5 internal oscillation ta = 25?c khz 26 22 18 *6 oscillator frequency external input ml9050 khz 26 22 18 cl*6 internal oscillation ta = 25?c khz 39 33 27 *6 external input ML9051 khz 20 17 14 cl*6 *1: a0, d0 to d5, d6 (scl), d7 (si), rd (e), wr (r/ w ), cs1 , cs2, cls, cl, fr, m/ s , c86, p/ s , dof , res , irs, hpm pins *2: d0 to d7, fr, frs, dof , cl pins dof , res , irs, hpm pins *3: a0, rd (e), wr (r/ w ), cs1 , cs2, cls, m/ s , c86, p/ s , res , irs, hpm pins *4: applicable to the pins d0 to d5, d6 (scl), d7 (si), cl, fr, dof in the high impedance state. *5: com1 to com65 in the ml9050, com1 to com65 in the ML9051. *6: see table 24 for the relationship between the oscillator frequency and the frame frequency. table 24. relationship among the oscillator frequency (f osc ), display clock frequency (f lcdck ), and lcd frame frequency (f fr ) parameter display clock frequency (f lcdck ) lcd frame frequency (f fr ) when the internal oscillator is used f osc /4 f osc /4 65 when the internal oscillator is used f osc /8 f osc /8 49 ml9050 ML9051 when the internal oscillator is not used external input (f lcdck )f lcdck /260 when the internal oscillator is not used external input (f lcdck )f lcdck /196 ? semiconductor ml9050/9051 50/71 pedl9050-02 ? operating current consumption value (ta = 25?c) (1) during display operation, internal power supply off (the current consumption of the entire ic when an external power supply is used) display mode: all-white symbol condition rated value unit remarks min typ max i dd v dd = 5 v, v1-v ss = 11 v v dd = 3 v, v1-v ss = 11 v model ml9050 v dd = 3 v, v1-v ss = 11 v v dd = 5 v, v1-v ss = 8 v v dd = 3 v, v1-v ss = 8 v ML9051 m a (18) (16) (13) (11) (9) display mode: checker pattern symbol condition rated value unit remarks min typ max i dd v dd = 5 v, v1-v ss = 11 v v dd = 3 v, v1-v ss = 11 v model ml9050 v dd = 3 v, v1-v ss = 11 v v dd = 5 v, v1-v ss = 8 v v dd = 3 v, v1-v ss = 8 v ML9051 m a tbd tbd tbd tbd tbd (2) during display operation, internal power supply on display mode: all-white symbol condition rated value unit remarks min typ max i dd v dd = 5 v, 3-times voltage multiplication, v1-v ss = 11 v v dd = 3 v, 4-times voltage multiplication, v1-v ss = 11 v normal mode high power mode normal mode high power mode model ml9050 v dd = 5 v, 3-times voltage multiplication, v1-v ss = 8 v v dd = 3 v, 4-times voltage multiplication, v1-v ss = 8 v normal mode high power mode normal mode high power mode ML9051 v dd = 3 v, 4-times voltage multiplication, v1-v ss = 11 v normal mode high power mode m a (67) tbd (81) tbd (35) tbd (43) tbd (72) tbd ? semiconductor ml9050/9051 51/71 pedl9050-02 display mode: checker pattern symbol condition rated value unit remarks min typ max i dd v dd = 5 v, 6-times voltage multiplication, v1-v ss = 11 v v dd = 3 v, 7-times voltage multiplication, v1-v ss = 11 v normal mode high power mode normal mode high power mode model ml9050 v dd = 5 v, 6-times voltage multiplication, v1-v ss = 8 v v dd = 3 v, 7-times voltage multiplication, v1-v ss = 8 v normal mode high power mode normal mode high power mode ML9051 v dd = 3 v, 7-times voltage multiplication, v1-v ss = 11 v normal mode high power mode m a tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ? power save mode current consumption, vss = 0 v, vdd = 3 v 10% parameter condition rated value unit remarks min typ max symbol i dds1 i dds2 ml9050 sleep state ml9050 standby state i dds1 i dds2 ML9051 sleep state ML9051 standby state m a (0.1) (4) (0.1) (4) ? semiconductor ml9050/9051 52/71 pedl9050-02 timing characteristics ? system bus read/write characteristics 1 (80-series mpu) parameter condition rated value [v dd = 4.5 v to 5.5 v, ta = C40 to +85?c] unit min max symbol t ah8 t aw8 t cyc8 applicable pins a0 a0 0 0 address hold time address setup time system cycle time ns 166 t cclw t cclr t cchw t cchr wr rd wr rd control l pulse width ( wr ) control l pulse width ( rd ) control h pulse width ( wr ) control h pulse width ( rd ) 30 70 30 30 t ds8 t dh8 d0 to d7 data setup time data hold time 30 10 t acc8 t oh8 rd access time output disable time 5 cl = 100pf 70 50 a 0 cs1 wr , rd d 0 to d 7 (write) d 0 to d 7 (read) (cs2= "1") t aw8 t ds8 t acc8 t dh8 t cclr, t cclw t cchr, t cchw t ah8 t oh8 t cyc8 ? semiconductor ml9050/9051 53/71 pedl9050-02 parameter condition rated value [v dd = 2.7 v to 4.5 v, ta = C40 to +85?c] unit min max symbol t ah8 t aw8 t cyc8 applicable pins a0 a0 0 0 address hold time address setup time system cycle time ns 300 t cclw t cclr t cchw t cchr wr rd wr rd control l pulse width ( wr ) control l pulse width ( rd ) control h pulse width ( wr ) control h pulse width ( rd ) 60 120 60 60 t ds8 t dh8 d0 to d7 data setup time data hold time 40 15 t acc8 t oh8 rd access time output disable time 10 cl = 100pf 140 100 parameter condition rated value [v dd = 1.8 v to 2.7 v, ta = C40 to +85?c] unit min max symbol t ah8 t aw8 t cyc8 applicable pins a0 a0 0 0 address hold time address setup time system cycle time ns 1000 t cclw t cclr t cchw t cchr wr rd wr rd control l pulse width ( wr ) control l pulse width ( rd ) control h pulse width ( wr ) control h pulse width ( rd ) 120 240 120 120 t ds8 t dh8 d0 to d7 data setup time data hold time 80 30 t acc8 t oh8 rd access time output disable time 10 cl = 100pf 280 200 note 1: the input signal rise and fall times are specified as 15ns or less. when using the system cycle time for fast speed, the specified values are (tr+tf) (t cyc8 -t cclw -t cchw ) or (tr+tf) (t cyc8 -t cclr -t cchr ). note 2: all timings are specified taking the levels of 20% and 80% of vdd as the reference. note 3: the values of t cclw and t cclr are specified during the overlapping period of cs1 at "l" (cs2 = "h") and the "l" levels of wr and rd , respectively. ? semiconductor ml9050/9051 54/71 pedl9050-02 ? system bus read/write characteristics 2 (68-series mpu) parameter condition rated value [v dd = 4.5 v to 5.5 v, ta = C40 to +85?c] unit min max symbol t ah6 t aw6 t cyc6 applicable pins a0 a0 0 0 address hold time address setup time system cycle time ns 166 t ewhr t ewhw e read write enable h pulse width 70 30 t ewlr t ewlw e read write enable l pulse width 30 30 t ds6 t dh6 d0 to d7 data setup time data hold time 30 10 t acc6 t oh6 access time output disable time 10 cl = 100pf 70 50 a 0 cs1 e r/ w d 0 to d 7 (write) d 0 to d 7 (read) (cs2 = "1") t aw6 t ds6 t acc6 t dh6 t ewhr, t ewhw t ewlr, t ewlw t ah6 t oh6 t cyc6 ? semiconductor ml9050/9051 55/71 pedl9050-02 parameter condition rated value [v dd = 2.7 v to 4.5 v, ta = C40 to +85?c] unit min max symbol t ah6 t aw6 t cyc6 applicable pins a0 a0 0 0 address hold time address setup time system cycle time ns 300 t ewhr t ewhw e read write enable h pulse width 120 60 t ewlr t ewlw e read write enable l pulse width 60 60 t ds6 t dh6 d0 to d7 data setup time data hold time 40 15 t acc6 t oh6 access time output disable time 10 cl = 100pf 140 100 parameter condition rated value [v dd = 1.8 v to 2.7 v, ta = C40 to +85?c] unit min max symbol t ah6 t aw6 t cyc6 applicable pins a0 a0 0 0 address hold time address setup time system cycle time ns 1000 t ewhr t ewhw e read write enable h pulse width 240 120 t ewlr t ewlw e read write enable l pulse width 120 120 t ds6 t dh6 d0 to d7 data setup time data hold time 80 30 t acc6 t oh6 access time output disable time 10 cl = 100pf 280 200 note 1: the input signal rise and fall times are specified as 15ns or less. when using the system cycle time for fast speed, the specified values are (tr+tf) (t cyc6 -t ewlw -t ewhw ) or (tr+tf) (t cyc6 -t ewlr -t ewhr ). note 2: all timings are specified taking the levels of 20% and 80% of vdd as the reference. note 3: the values of t ewlw and t ewlr are specified during the overlapping period of cs1 at "l" (cs2 = "h") and the "h" level of e. ? semiconductor ml9050/9051 56/71 pedl9050-02 ? serial interface parameter condition rated value [v dd = 4.5 v to 5.5 v, ta = C40 to +85?c] unit min max symbol t scyc t shw t slw t sas t sah applicable pins scl a0 200 75 75 serial clock period scl "h" pulse width scl "l" pulse width address setup time address hold time ns 50 100 t sds t sdh si data setup time data hold time 50 50 t css t csh cs cs-scl time 100 100 cs1 a0 scl si (cs2 = "1") t css t slw t sds t shw t csh t sas t scyc t sah t sdh ? semiconductor ml9050/9051 57/71 pedl9050-02 parameter condition rated value [v dd = 2.7 v to 4.5 v, ta = C40 to +85?c] unit min max symbol t scyc t shw t slw t sas t sah applicable pins scl a0 250 100 100 serial clock period scl "h" pulse width scl "l" pulse width address setup time address hold time ns 150 150 t sds t sdh si data setup time data hold time 100 100 t css t csh cs cs-scl time 150 150 parameter condition rated value [v dd = 1.8 v to 2.7 v, ta = C40 to +85?c] unit min max symbol t scyc t shw t slw t sas t sah applicable pins scl a0 400 150 150 serial clock period scl "h" pulse width scl "l" pulse width address setup time address hold time ns 250 250 t sds t sdh si data setup time data hold time 150 150 t css t csh cs cs-scl time 250 250 note 1: the input signal rise and fall times are specified as 15ns or less. note 2: all timings are specified taking the levels of 20% and 80% of v dd as the reference. ? semiconductor ml9050/9051 58/71 pedl9050-02 ? display control output timing parameter condition rated value [v dd = 4.5 v to 5.5 v, ta = C40 to +85?c] unit min max symbol t dfr applicable pins fr fr delay time cl = 50pf 40 ns typ 10 parameter condition rated value [v dd = 2.7 v to 4.5 v, ta = C40 to +85?c] unit min max symbol t dfr applicable pins fr fr delay time cl = 50pf 80 ns typ 20 parameter condition rated value [v dd = 1.8 v to 2.7 v, ta = C40 to +85?c] unit min max symbol t dfr applicable pins fr fr delay time cl = 50pf 200 ns typ 50 cl(out) fr t dfr ? semiconductor ml9050/9051 59/71 pedl9050-02 ? reset input timing parameter condition rated value [v dd = 4.5 v to 5.5 v, ta = C40 to +85?c] unit min max symbol t r applicable pins reset time 0.5 m s typ t rw res 0.5 reset "l" pulse width parameter condition rated value [v dd = 2.7 v to 4.5 v, ta = C40 to +85?c] unit min max symbol t r applicable pins reset time 1 m s typ t rw res 1 reset "l" pulse width parameter condition rated value [v dd = 1.8 v to 2.7 v, ta = C40 to +85?c] unit min max symbol t r applicable pins reset time 1.5 m s typ t rw res 1.5 reset "l" pulse width res internal state being reset reset complete t rw t r note 1: all timings are specified taking the levels of 20% and 80% of v dd as the reference. ? semiconductor ml9050/9051 60/71 pedl9050-02 mpu interface the ml9050/9051 series ics can be connected directly to the 80-series and 68-series mpus. further, by using the serial interface, it is possible to operate the lsi with a minimum number of signal lines. in addition, it is possible to expand the display area by using the ml9050/9051 series lsis in a multiple chip configuration. in this case, it is possible to select the individual lsi to be accessed using the chip select signals. v dd reset v ss v cc gnd a0 a1 to a7 iorq d0 to d7 rd wr res v dd v ss a0 cs1 cs2 d0 to d7 rd wr res c86 p/ s decoder ? 80-series mpu v dd reset v ss v cc gnd a0 a1 to a15 vma d0 to d7 e r/ w res v dd v ss a0 cs1 cs2 d0 to d7 e r/ w res c86 p/ s decoder ? 68-series mpu v dd reset v ss v cc gnd a0 a1 to a7 port1 port2 res v dd v ss a0 cs1 cs2 si scl res c86 p/ s decoder ? serial interface can be tied to either level. mpu ml9050/9051 mpu ml9050/9051 mpu ml9050/9051 ? semiconductor ml9050/9051 61/71 pedl9050-02 pad configuration pad layout ; ml9050 chip size : 11.05 3.39mm pad coordinates y x 290 334 1 135 291 91 292 133 134 90 pad no. pad name x ( m m) y ( m m) C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 dummy dummy dummy dummy frs fr cl dof test0 gnd cs1 cs2 v dd res a0 gnd wr rd v dd db0 C5000 C4888 C4776 C4664 C4552 C4440 C4328 C4216 C4104 C3992 C3880 C3768 C3656 C3544 C3432 C3320 C3208 C3096 C2984 C2872 pad no. pad name x ( m m) y ( m m) db1 db2 db3 db4 db5 db6 db7 v dd v dd v dd v dd v in v in v in v in gnd gnd gnd v out v out C2760 C2648 C2536 C2424 C2312 C2200 C2088 C1976 C1896 C1816 C1736 C1656 C1576 C1496 C1416 C1336 C1256 C1176 C1076 C951 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ? semiconductor ml9050/9051 62/71 pedl9050-02 vc2+ vc2+ vc4+ vc4+ vc6+ vc6+ vs2C vs2C vs1C vs1C vc5+ vc5+ vc3+ vc3+ vc1+ vc1+ gnd gnd vrs vrs v dd v dd v1 v1 v2 v2 v3 v3 v4 v4 v5 v5 vr vr v dd v dd test1 v dd ms cls C826 C701 C576 C451 C326 C201 C76 49 174 299 424 549 674 799 924 1049 1174 1299 1424 1549 1674 1799 1924 2049 2174 2299 2424 2549 2674 2799 2924 3049 3174 3299 3424 3549 3674 3786 3898 4010 gnd c86 ps v dd hpm gnd irs v dd dummy dummy dummy dummy dummy dummy dummy dummy dummy com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 com16 com15 com14 com13 com12 com11 com10 com9 4122 4234 4346 4458 4570 4682 4794 4906 5018 5130 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 61 101 62 102 63 103 64 104 65 105 66 106 67 107 68 108 69 109 70 110 71 111 72 112 73 113 74 114 75 115 76 116 77 117 78 118 79 119 80 120 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1363.2 C1298.2 C1233.2 C1168.2 C1103.2 C1038.2 C973.2 C908.2 C843.2 C778.2 C713.2 C648.2 C583.2 C518.2 C453.2 C388.2 C323.2 C258.2 C193.2 C128.2 C63.2 1.8 66.8 131.8 196.8 261.8 326.8 391.8 456.8 521.8 pad no. pad name x ( m m) y ( m m) pad no. pad name x ( m m) y ( m m) ? semiconductor ml9050/9051 63/71 pedl9050-02 com8 com7 com6 com5 com4 com3 com2 com1 com0 coms1 dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5037.5 4972.5 4907.5 4842.5 4777.5 4712.5 4647.5 4582.5 4517.5 4452.5 4387.5 4322.5 4257.5 4192.5 4127.5 4062.5 3997.5 3932.5 3867.5 3802.5 3737.5 3672.5 3607.5 3542.5 3477.5 3412.5 3347.5 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 3282.5 3217.5 3152.5 3087.5 3022.5 2957.5 2892.5 2827.5 2762.5 2697.5 2632.5 2567.5 2502.5 2437.5 2372.5 2307.5 2242.5 2177.5 2112.5 2047.5 1982.5 1917.5 1852.5 1787.5 1722.5 1657.5 1592.5 1527.5 1462.5 1397.5 1332.5 1267.5 1202.5 1137.5 1072.5 1007.5 942.5 877.5 812.5 747.5 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 586.8 651.8 716.8 781.8 846.8 911.8 976.8 1041.8 1106.8 1171.8 1236.8 1301.8 1366.8 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 pad no. pad name x ( m m) y ( m m) pad no. pad name x ( m m) y ( m m) ? semiconductor ml9050/9051 64/71 pedl9050-02 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 seg81 seg82 seg83 seg84 seg85 seg86 seg87 seg88 seg89 seg90 seg91 seg92 seg93 seg94 682.5 617.5 552.5 487.5 422.5 357.5 292.5 227.5 162.5 97.5 32.5 C32.5 C97.5 C162.5 C227.5 C292.5 C357.5 C422.5 C487.5 C552.5 C617.5 C682.5 C747.5 C812.5 C877.5 C942.5 C1007.5 C1072.5 C1137.5 C1202.5 C1267.5 C1332.5 C1397.5 C1462.5 C1527.5 C1592.5 C1657.5 C1722.5 C1787.5 C1852.5 seg95 seg96 seg97 seg98 seg99 seg100 seg101 seg102 seg103 seg104 seg105 seg106 seg107 seg108 seg109 seg110 seg111 seg112 seg113 seg114 seg115 seg116 seg117 seg118 seg119 seg120 seg121 seg122 seg123 seg124 seg125 seg126 seg127 seg128 seg129 seg130 seg131 dummy dummy dummy C1917.5 C1982.5 C2047.5 C2112.5 C2177.5 C2242.5 C2307.5 C2372.5 C2437.5 C2502.5 C2567.5 C2632.5 C2697.5 C2762.5 C2827.5 C2892.5 C2957.5 C3022.5 C3087.5 C3152.5 C3217.5 C3282.5 C3347.5 C3412.5 C3477.5 C3542.5 C3607.5 C3672.5 C3737.5 C3802.5 C3867.5 C3932.5 C3997.5 C4062.5 C4127.5 C4192.5 C4257.5 C4322.5 C4387.5 C4452.5 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 pad no. pad name x ( m m) y ( m m) pad no. pad name x ( m m) y ( m m) ? semiconductor ml9050/9051 65/71 pedl9050-02 dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 C4517.5 C4582.5 C4647.5 C4712.5 C4777.5 C4842.5 C4907.5 C4972.5 C5037.5 C5102.5 C5167.5 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 com45 com46 com47 com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 coms0 dummy dummy dummy dummy dummy dummy dummy C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1366.8 1301.8 1236.8 1171.8 1106.8 1041.8 976.8 911.8 846.8 781.8 716.8 651.8 586.8 521.8 456.8 391.8 326.8 261.8 196.8 131.8 66.8 1.8 C63.2 C128.2 C193.2 C258.2 C323.2 C388.2 C453.2 C518.2 C583.2 C648.2 C713.2 C778.2 C843.2 C908.2 C973.2 C1038.2 C1103.2 C1168.2 C1233.2 C1298.2 C1363.2 pad no. pad name x ( m m) y ( m m) pad no. pad name x ( m m) y ( m m) ? semiconductor ml9050/9051 66/71 pedl9050-02 pad configuration pad layout ; ML9051 chip size : 11.05 3.39mm pad coordinates y x 290 334 1 135 291 91 292 133 134 90 pad no. pad name x ( m m) y ( m m) C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 dummy dummy dummy dummy frs fr cl dof test0 gnd cs1 cs2 v dd res a0 gnd wr rd v dd db0 C5000 C4888 C4776 C4664 C4552 C4440 C4328 C4216 C4104 C3992 C3880 C3768 C3656 C3544 C3432 C3320 C3208 C3096 C2984 C2872 pad no. pad name x ( m m) y ( m m) db1 db2 db3 db4 db5 db6 db7 v dd v dd v dd v dd v in v in v in v in gnd gnd gnd v out v out C2760 C2648 C2536 C2424 C2312 C2200 C2088 C1976 C1896 C1816 C1736 C1656 C1576 C1496 C1416 C1336 C1256 C1176 C1076 C951 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ? semiconductor ml9050/9051 67/71 pedl9050-02 vc2+ vc2+ vc4+ vc4+ vc6+ vc6+ vs2C vs2C vs1C vs1C vc5+ vc5+ vc3+ vc3+ vc1+ vc1+ gnd gnd vrs vrs v dd v dd v1 v1 v2 v2 v3 v3 v4 v4 v5 v5 vr vr v dd v dd test1 v dd ms cls C826 C701 C576 C451 C326 C201 C76 49 174 299 424 549 674 799 924 1049 1174 1299 1424 1549 1674 1799 1924 2049 2174 2299 2424 2549 2674 2799 2924 3049 3174 3299 3424 3549 3674 3786 3898 4010 gnd c86 ps v dd hpm gnd irs v dd dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy com23 com22 com21 com20 com19 com18 com17 com16 com15 com14 com13 com12 com11 com10 com9 4122 4234 4346 4458 4570 4682 4794 4906 5018 5130 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 61 101 62 102 63 103 64 104 65 105 66 106 67 107 68 108 69 109 70 110 71 111 72 112 73 113 74 114 75 115 76 116 77 117 78 118 79 119 80 120 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1550 C1363.2 C1298.2 C1233.2 C1168.2 C1103.2 C1038.2 C973.2 C908.2 C843.2 C778.2 C713.2 C648.2 C583.2 C518.2 C453.2 C388.2 C323.2 C258.2 C193.2 C128.2 C63.2 1.8 66.8 131.8 196.8 261.8 326.8 391.8 456.8 521.8 pad no. pad name x ( m m) y ( m m) pad no. pad name x ( m m) y ( m m) ? semiconductor ml9050/9051 68/71 pedl9050-02 com8 com7 com6 com5 com4 com3 com2 com1 com0 coms1 dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5037.5 4972.5 4907.5 4842.5 4777.5 4712.5 4647.5 4582.5 4517.5 4452.5 4387.5 4322.5 4257.5 4192.5 4127.5 4062.5 3997.5 3932.5 3867.5 3802.5 3737.5 3672.5 3607.5 3542.5 3477.5 3412.5 3347.5 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 3282.5 3217.5 3152.5 3087.5 3022.5 2957.5 2892.5 2827.5 2762.5 2697.5 2632.5 2567.5 2502.5 2437.5 2372.5 2307.5 2242.5 2177.5 2112.5 2047.5 1982.5 1917.5 1852.5 1787.5 1722.5 1657.5 1592.5 1527.5 1462.5 1397.5 1332.5 1267.5 1202.5 1137.5 1072.5 1007.5 942.5 877.5 812.5 747.5 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 586.8 651.8 716.8 781.8 846.8 911.8 976.8 1041.8 1106.8 1171.8 1236.8 1301.8 1366.8 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 pad no. pad name x ( m m) y ( m m) pad no. pad name x ( m m) y ( m m) ? semiconductor ml9050/9051 69/71 pedl9050-02 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 seg81 seg82 seg83 seg84 seg85 seg86 seg87 seg88 seg89 seg90 seg91 seg92 seg93 seg94 682.5 617.5 552.5 487.5 422.5 357.5 292.5 227.5 162.5 97.5 32.5 C32.5 C97.5 C162.5 C227.5 C292.5 C357.5 C422.5 C487.5 C552.5 C617.5 C682.5 C747.5 C812.5 C877.5 C942.5 C1007.5 C1072.5 C1137.5 C1202.5 C1267.5 C1332.5 C1397.5 C1462.5 C1527.5 C1592.5 C1657.5 C1722.5 C1787.5 C1852.5 seg95 seg96 seg97 seg98 seg99 seg100 seg101 seg102 seg103 seg104 seg105 seg106 seg107 seg108 seg109 seg110 seg111 seg112 seg113 seg114 seg115 seg116 seg117 seg118 seg119 seg120 seg121 seg122 seg123 seg124 seg125 seg126 seg127 seg128 seg129 seg130 seg131 dummy dummy dummy C1917.5 C1982.5 C2047.5 C2112.5 C2177.5 C2242.5 C2307.5 C2372.5 C2437.5 C2502.5 C2567.5 C2632.5 C2697.5 C2762.5 C2827.5 C2892.5 C2957.5 C3022.5 C3087.5 C3152.5 C3217.5 C3282.5 C3347.5 C3412.5 C3477.5 C3542.5 C3607.5 C3672.5 C3737.5 C3802.5 C3867.5 C3932.5 C3997.5 C4062.5 C4127.5 C4192.5 C4257.5 C4322.5 C4387.5 C4452.5 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 pad no. pad name x ( m m) y ( m m) pad no. pad name x ( m m) y ( m m) ? semiconductor ml9050/9051 70/71 pedl9050-02 dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 C4517.5 C4582.5 C4647.5 C4712.5 C4777.5 C4842.5 C4907.5 C4972.5 C5037.5 C5102.5 C5167.5 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 coms0 dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 C5340 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1366.8 1301.8 1236.8 1171.8 1106.8 1041.8 976.8 911.8 846.8 781.8 716.8 651.8 586.8 521.8 456.8 391.8 326.8 261.8 196.8 131.8 66.8 1.8 C63.2 C128.2 C193.2 C258.2 C323.2 C388.2 C453.2 C518.2 C583.2 C648.2 C713.2 C778.2 C843.2 C908.2 C973.2 C1038.2 C1103.2 C1168.2 C1233.2 C1298.2 C1363.2 pad no. pad name x ( m m) y ( m m) pad no. pad name x ( m m) y ( m m) ? semiconductor ml9050/9051 71/71 pedl9050-02 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 1999 oki electric industry co., ltd. printed in japan |
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