ST3421SRG p channel enhancement mode mosfet -5.0a stanson technology 120 bentley square, mountain view, ca 94040 usa www.stansontech.com ST3421SRG 2013. rev.1 description ST3421SRG is the p-channel logic enhancement mode p ower field effect transistor which is produced using high cell density, dmos tre nch technology. this high density process is especially tailored to minimize on-state resistance. these devices are particularly suited for low voltage application suc h as cellular phone and notebook computer power management, other battery powered ci rcuits, and low in-line power loss are required. the product is in a very small o utline surface mount package. pin configuration sot-23 1.gate 2.source 3.drain part marking sot-23 y: year code a: process code feature -60v/-5.0a, r ds(on) = 150m-ohm (typ.) @vgs = -10v -60v/-2.5a, r ds(on) = 185m-ohm @vgs = -4.5v super high density cell design for extremely low r ds(on) exceptional on-resistance and maximum dc current capability sot-23 package design 3 1 2 d g s 3 1 2 21ya
ST3421SRG p channel enhancement mode mosfet -5.0a stanson technology 120 bentley square, mountain view, ca 94040 usa www.stansontech.com ST3421SRG 2013. rev.1 absoulte maximum ratings (ta = 25 unless otherwise noted ) parameter symbol typical unit drain-source voltage v dss -60 v gate-source voltage v gss 20 v continuous drain currenttj=150 ) t a =25 t a =70 i d -5.0 -3.5 a pulsed drain current i dm -12 a continuous source current (diode conduction) i s -1.25 a power dissipation t a =25 t a =70 p d 1.25 0.8 w operation junction temperature t j 150 storgae temperature range t stg -55/150 thermal resistance-junction to ambient r ja 100 /w
ST3421SRG p channel enhancement mode mosfet -5.0a stanson technology 120 bentley square, mountain view, ca 94040 usa www.stansontech.com ST3421SRG 2013. rev.1 electrical characteristics ( ta = 25 unless otherwise noted ) parameter symbol condition min typ max unit static drain-source breakdown voltage v (br)dss v gs =0v,i d =-10ua -60 v gate threshold voltage v gs(th) v ds =vgs,i d =-250ua -1.0 -3.0 v gate leakage current i gss v ds =0v,v gs = 20v 100 na zero gate voltage drain current i dss v ds =-48v,v gs =0v -1 ua v ds =-48v,v gs =0v t j =55 -10 drain-source on-resistance r ds(on) v gs =-10v,i d =-5.0a v gs =-4.5v,i d =-2.5a 0.150 0.185 0.160 0.200 forward transconductance g fs v ds =-10v,i d =-1.7v 2.4 s diode forward voltage v sd i s =-1.25a,v gs =0v -0.8 -1.2 v dynamic total gate charge q g v ds =-30v v gs =-10v i d -2a 16 nc gate-source charge q gs 8 gate-drain charge q gd 3.0 input capacitance c iss v ds =-30v v gs =0v f=1mh z 1200 pf output capacitance c oss 115 reverse transfer capacitance c rss 7 turn-on time t d(on) tr v dd =-10v r l =15 i d =-1.0a v gen =-3v r g =2.5 9 ns 109 turn-off time t d(off) tf 25 11
ST3421SRG p channel enhancement mode mosfet -5.0a stanson technology 120 bentley square, mountain view, ca 94040 usa www.stansontech.com ST3421SRG 2013. rev.1 typical characterictics (25 unless noted)
ST3421SRG p channel enhancement mode mosfet -5.0a stanson technology 120 bentley square, mountain view, ca 94040 usa www.stansontech.com ST3421SRG 2013. rev.1 typical characterictics (25 unless noted)
ST3421SRG p channel enhancement mode mosfet -5.0a stanson technology 120 bentley square, mountain view, ca 94040 usa www.stansontech.com ST3421SRG 2013. rev.1 sot-23 package outline
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