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( d s 8 5 8 2 r e v . o ) 0 6 / 1 3 hi-8582, hi-8583 pin configura tion (t op v iew) hi-8582pqi hi-8582pqt & hi-8583pqi hi-8583pqt 5 2 - d / r 1 5 1 - r i n 2 b n 5 0 - r i 2 a r n 4 9 - i 1 b r 4 8 - i n 1 a v 4 7 - d d 4 6 - n / c 4 e 5 - t s t 4 4 - m r 4 3 - t x c l k k 4 2 - c l 4 1 - r s r 4 0 - n / c 39 - n/c 38 - cwstr37 - entx 36 - v+ 35 - txbout 34 - txaout 33 - v - 32 - fft31 - hft 30 - tx/r 29 - pl228 - pl1 27 - bd00 b d 1 0 - 1 4 b d 0 9 - 1 5 b d 0 8 - 1 6 b d 0 7 - 1 7 b d 0 6 - 1 8 n / c - 1 9 g n d - 2 0 n f d - 2 1 b d 0 5 - 2 2 b d 0 4 - 2 3 b d 0 3 - 2 4 b d 0 2 - 2 5 b d 0 1 - 2 6 ff1 - 1 hf1 - 2 d/r2 - 3 ff2 - 4 hf2 - 5 sel - 6 en1 - 7en2 - 8 bd15 - 9bd14 - 10 bd13 - 1 1 bd12 - 12 bd1 1 - 13 general description the hi-8582/hi-8583 from holt integrated circuits are a silicon gate cmos devices for interfacing a 16-bit parallel data bus directly to the arinc 429 serial bus. the hi-8582/hi-8583 design of fers many enhancements to the in du st ry st an da rd hi -8 28 2 ar ch it ec tu re . th e de vi ce provides two receivers each with label recognition, 32 by 32 fifo, and analog line receiver . up to 16 labels may be programmed for each receiver . the independent transmit- ter has a 32 x 32 fifo and a built-in line driver . the status of all three fifos can be monitored using the external status pins, or by polling the hi-8582/hi-8583 status register . other new features include a programmable option of data or parity in the 32nd bit, and the ability to unscramble the 32 bit word. also, versions are available with dif ferent values of input resistance and output resistance to allow users to more easily add external lightning protection circuitry . the device can be used at nonstandard data rates when an option pin, nfd, is invoked. the 16-bit parallel data bus exchanges the 32-bit arinc data word in two steps when either loading the transmitter or interrogating the receivers. the databus and all control signals are cmos and ttl compatible. the hi-8582/hi-8583 apply the arinc protocol to the receivers and transmitter . t iming is based on a 1 mega- hertz clock. although the line driver shares a common substrate with the receivers, the design of the physical isolation does not allow parasitic crosstalk, and thereby achieves the same isolation as common hybrid layouts. applica tions ! av i o n i c s d a t a c o m m u n i c a t i o n ! s e r i a l t o p a r a l l e l c o n v e r s i o n ! p a r a l l e l t o s e r i a l c o n v e r s i o n fea tures ! arinc specification 429 compatible ! dual receiver and transmitter interface ! analog line driver and receivers connect directly to arinc bus ! programmable label recognition ! on-chip 16 label memory for each receiver ! 32 x 32 fifos each receiver and transmitter ! independent data rate selection for transmitter and each receiver ! status register ! data scramble control ! 32nd transmit bit can be data or parity ! self test mode ! low power ! industrial & extended temperature ranges 52 - pin plastic quad flat pack (pqfp) (see page 14 for additional pin configuration) june 2013 arinc 429 system on a chip h o l t i n t e g r a t e d c i r c u i t s w w w. h o l t i c . c o m
pin descriptions signal function description vdd power +5v % rin1a input arinc receiver 1 positive input rin1b input arinc receiver 1 negative input rin2a input arinc receiver 2 positive input rin2b input arinc receiver 2 negative input d/r1 output receiver 1 data ready flag ff1 output fifo full receiver 1 hf1 output fifo half full, receiver 1 d/r2 output receiver 2 data ready flag ff2 output fifo full receiver 2 hf2 output fifo half full, receiver 2 sel input receiver data byte selection (0 = byte 1) (1 = byte 2) en1 input data bus control, enables receiver 1 data to outputs en2 input data bus control, enables receiver 2 data to outputs if en1 is high bd15 i/o data bus bd14 i/o data bus bd13 i/o data bus bd12 i/o data bus bd1 1 i/o data bus bd10 i/o data bus bd09 i/o data bus bd08 i/o data bus bd07 i/o data bus bd06 i/o data bus gnd power 0 v bd05 i/o data bus bd04 i/o data bus bd03 i/o data bus bd02 i/o data bus bd01 i/o data bus bd00 i/o data bus pl1 input latch enable for byte 1 entered from data bus to transmitter fifo. pl2 input latch enable for byte 2 entered from data bus to transmitter fifo. must follow pl1. tx/r output t ransmitter ready flag. goes low when arinc word loaded into fifo. goes high after transmission and fifo empty . hft output t ransmitter fifo half full fft output t ransmitter fifo full v - power -9.5v to -10.5v txaout output line driver output - a side txbout output line driver output - b side v+ power +9.5v to +10.5v entx input enable t ransmission cwstr input clock for control word register rsr input read status register if sel=0, read control register if sel=1 nfd input no frequency discrimination if low (pull-up) clk input master clock input tx clk output t ransmitter clock equal to master clock (clk), divided by either 10 or 80. mr input master reset, active low test input disable t ransmitter output if high (pull-down) 5 hi-8582, hi-8583 h o l t i n t e g r a t e d c i r c u i t s 2
functional description control word register the hi-8582/hi-8583 contain a 16-bit control register which is used to configure the device. the control register bits cr0 - cr15 are loaded from bd00 - bd15 when cwstr is pulsed low . the control register contents are output on the databus when sel = 1 and rsr is pulsed low . each bit of the control register has the following function: st a tus register the hi-8582/hi-8583 contain a 9-bit status register which can be interrogated to determine the status of the arinc receivers, data fifos and transmitter . the contents of the status register are output on bd00 - bd08 when the rsr pin is taken low and sel = 0. unused bits are output as zeros. the following table defines the status register bits. hi-8582, hi-8583 sr function st a te description bit sr0 data ready 0 receiver 1 fifo empty (receiver 1) 1 receiver 1 fifo contains valid data resets to zero when all data has been read. d/r1 pin is the inverse of this bit sr1 fifo half full 0 receiver 1 fifo holds less than 16 (receiver 1) words 1 receiver 1 fifo holds at least 16 words. hf1 pin is the inverse ofthis bit. sr2 fifo full 0 receiver 1 fifo not full (receiver 1) 1 receiver 1 fifo full. t o avoid data loss, the fifo must be read withinone arinc word period. ff1 pin is the inverse of this bit sr3 data ready 0 receiver 2 fifo empty (receiver 2) 1 receiver 2 fifo contains valid data resets to zero when all data has been read. d/r2 pin is the inverse of this bit sr4 fifo half full 0 receiver 2 fifo holds less than 16 (receiver 2) words 1 receiver 2 fifo holds at least 16 words. hf2 pin is the inverse ofthis bit. sr5 fifo full 0 receiver 2 fifo not full (receiver 2) 1 receiver 2 fifo full. t o avoid data loss, the fifo must be read withinone arinc word period. ff2 pin is the inverse of this bit sr6 t ransmitter fifo 0 t ransmitter fifo not empty empty 1 t ransmitter fifo empty . sr7 t ransmitter fifo 0 t ransmitter fifo not full full 1 t ransmitter fifo full. fft pin is the inverse of this bit. sr8 t ransmitter fifo 0 t ransmitter fifo contains less than half full 16 words 1 t ransmitter fifo contains at least 16 words.hft pin is the inverse of this bit. cr function st a te description bit cr0 receiver 1 0 data rate = clk/10 data clock select 1 data rate = clk/80 cr1 label memory 0 normal operation read / w rite 1 load 16 labels using pl1 / pl2 read 16 labels using en1 / en2 cr2 enable label 0 disable label recognition recognition (receiver 1) 1 enable label recognition cr3 enable label 0 disable label recognition recognition (receiver 2) 1 enable label recognition cr4 enable 0 t ransmitter 32nd bit is data 32nd bit as parity 1 t ransmitter 32nd bit is parity cr5 self t est 0 the transmitter ? s digital outputs are internally connected to the receiver logic inputs 1 normal operation cr6 receiver 1 0 receiver 1 decoder disabled decoder 1 arinc bits 9 and 10 must match cr7 and cr8 cr7 - - if receiver 1 decoder is enabled, the arinc bit 9 must match this bit cr8 - - if receiver 1 decoder is enabled, the arinc bit 10 must match this bit cr9 receiver 2 0 receiver 2 decoder disabled decoder 1 arinc bits 9 and 10 must match cr10 and cr1 1 cr10 - - if receiver 2 decoder is enabled, the arinc bit 9 must match this bit cr1 1 - - if receiver 2 decoder is enabled, the arinc bit 10 must match this bit cr12 invert 0 t ransmitter 32nd bit is odd parity t ransmitter parity 1 t ransmitter 32nd bit is even parity cr13 t ransmitter 0 data rate=clk/10, o/p slope=1.5us data clock select 1 data rate=clk/80, o/p slope=10us cr14 receiver 2 0 data rate=clk/10 data clock select 1 data rate=clk/80 cr15 data 0 scramble arinc data format 1 unscramble arinc data h o l t i n t e g r a t e d c i r c u i t s 3
the hi-8582/hi-8583 guarantee recognition of these levels with a common mode v oltage with respect to gnd less than 4v for the worst case condition (4.75v supply and 13v signal level). the tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger . if the arinc signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. receiver logic opera tion figure 2 shows a block diagram of the logic section of each receiver . bit timing the arinc 429 specification contains the following timing specifi- cation for the received data: high speed low speed bit ra te 100k bps 1% 12k -14.5k bps pulse rise time 1.5 0.5 sec 10 5 sec pulse f all time 1.5 0.5 sec 10 5 sec pulse width 5 sec 5% 34.5 to 41.7 sec if the nfd pin is high, the hi-8582/hi-8583 accept signals that meet these specifications and rejects signals outside the tolerances. the way the logic operation achieves this is described below: 3. each data bit must follow its predecessor by not less than 8 samples and no more than 12 samples. in this manner the bit rate is checked. with exactly 1mhz input clock frequency , the acceptable data bit rates are as follows: high speed low speed da t a bit ra te min 83k bps 10.4k bps da t a bit ra te max 125k bps 15.6k bps 4. the w ord gap timer samples the null shift register every 10 input clocks (80 for low speed) after the last data bit of a valid reception. if the null is present, the w ord gap counter is incremented. a count of 3 will enable the next reception. if nfd is held low , frequency discrimination is disabled and any data stream totaling 32 bits is accepted even with gaps between bits. the protocol still requires a word gap as defined in 4. above. functional description (cont.) the receivers arinc bus interf ace figure 1 shows the i nput circuit for each recei ver . the arinc 429 specification requires the following detection levels: st a te differential vol t age one +6.5 v olts to +13 v olts null +2.5 v olts to -2.5 v olts zero -6.5 v olts to -13 v olts 1. key to the performance of the timing checking logic is an ac- curate 1mhz clock source. less than 0.1% error is recom- mended. 2. the sampling shift registers are 10 bits long and must show three consecutive ones, zeros or nulls to be considered valid data. additionally , for data bits, the one or zero in the upper bits of the sampling shift registers must be followed by a null in the lower bits within the data bit time. for a null in the word gap, three consecutive nulls must be found in both the upper and lower bits of the sampling shift register . in this manner the mini- mum pulse width is guaranteed. g n d g n d r i n 1 b o r r i n 2 b r i n 1 a o r r i n 2 a d i f f e r e n t i a l a m p l i f i e r s o n e s c o m p a r a t o r s n u l l z e r o e s v d d v d d figure 1. arinc receiver input byte 2 da t a bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bus 15 14 13 12 1 1 10 09 08 07 06 05 04 03 02 01 00 arinc 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 bit cr15=0 arinc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit cr15=1 p a r i t y p a r i t y s d i s d i l a b e l l a b e l s d i s d i l a b e l l a b e l l a b e l l a b e l l a b e l l a b e l l a b e l l a b e l l a b e l l a b e l l a b e l l a b e l l a b e l l a b e l arinc 429 da t a forma t control register bit cr15 is used to control how individual bits in the received or transmitted arinc word are mapped to the hi-8582/ hi-8583 data bus during data read or write operations. the following table describes this mapping: byte 1 da t a bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bus 15 14 13 12 1 1 10 09 08 07 06 05 04 03 02 01 00 arinc 13 12 1 1 10 9 31 30 32 1 2 3 4 5 6 7 8 bit cr15=0 arinc 16 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 bit cr15=1 hi-8582, hi-8583 h o l t i n t e g r a t e d c i r c u i t s 4
fifo load control sel en control bit / r/w control 32 t o 16 driver 32 bit shift register t o pins controlbits cr0, cr14 clock option clock clk bit counter and end of sequence p arity check 32nd bit da t a bit clock word gap word gap timer bit clock end st ar t sequence control error clock error detection shift register shift register null zeros shift register ones eos figure 2. receiver block diagram label / decode comp are 16 x 8 label memor y 32 x 32 fifo d/r ff mux contro l control bits hf functional description (cont.) hi-8582, hi-8583 receiver p arity the 32nd bit of received arinc words stored in the receive fifo is used as a parity flag indicating whether good odd parity is received from the incoming arinc word. odd parity received the parity bit is reset to indicate correct parity was received and the resulting word is written to the receive fifo. even parity received the receiver sets the 32nd bit to a ?1?, indicating a parity error and the resulting word is then written to the receive fifo. therefore, the 32nd bit retrieved from the receiver fifo will always be ?0? when valid (odd parity) arinc 429 words are received. retrieving da t a once 32 valid bits are recognized, the receiver logic generates an end of sequence (eos). depending upon the state of control register bits cr2-cr1 1, the received arinc 32-bit word is then checked for correct decoding and label matching before being loaded into the 32 x 32 receive fifo. cr2(3) arinc word cr6(9) arinc word fifo matches bits 9,10 label match cr7,8 (10,1 1) 0 x 0 x load fifo 1 no 0 x ignore data 1 y es 0 x load fifo 0 x 1 no ignore data 0 x 1 y es load fifo 1 y es 1 no ignore data 1 no 1 y es ignore data 1 no 1 no ignore data 1 y es 1 y es load fifo arinc words which do not meet the necessary 9th and 10th arinc bit or label matching are ignored and are not loaded into the receive fifo. the following table describes this operation. h o l t i n t e g r a t e d c i r c u i t s 5
c r 4 , 1 2 f ig u r e 3 . t r a n s m it t e r b l o c k d ia g r a m d a t a c l o c k c r 1 3 p l 1 p l 2 c l k t x c l k p a r it y g e n e r a t o r d a t a a n d n u l l t im e r s e q u e n c e r l in e d r iv e r b it a n d w o r d g a p c o u n t e r s t a r t s e q u e n c e w o r d c o u n t e r a n d f if o c o n t r o l in c r e m e n t w o r d c o u n t d a t a c l o c k d iv id e r f if o l o a d in g s e q u e n c e r t x a o u t t x b o u t 3 2 x 3 2 f if o 3 2 b it p a r a l l e l l o a d s h if t r e g is t e r b it c l o c k w o r d c l o c k a d d r e s s l o a d d a t a b u s t x /r e n t x t e s t h f t f f t reading labels after the write that changes cr1 from 0 to 1, the next 16 data reads of the selected receiver (en taken low) are labels. en1 is used to read labels for receiver 1, and en2 to read labels for receiver 2. label data is presented on bd0-bd7. when writing to, or reading from the label memory , sel must be a one, all 16 locations should be accessed, and cr1 must be written to zero before returning to normal operation. label recognition must be disabled (cr2/3=0) during the label read sequence. transmitter fifo opera tion the fifo is loaded sequentially by first pulsing pl1 to load byte 1 and then pl2 to load byte 2. the control logic automatically loads the 31 bit word (or 32 bit word if cr4=0) in the next available position of the fifo. if tx/r, the transmitter ready flag is high (fifo empty), then up to 32 words, each 31 or 32 bits long, may be loaded. if tx/r is low , then only the available positions may be loaded. if all 32 positions are full, the fft flag is asserted and the fifo ignores further attempts to load data. a transmitter fifo half-full flag hft is provided. when the transmit fifo contains less than 16 words, hft is high, indicating to the system microprocessor that a 16 arinc word block write sequence can be initiated. in normal operation (cr4=1), the 32nd bit transmitted is a parity bit. odd or even parity is selected by programming control register bit cr12 to a zero or one. if cr4 is programmed to a 0, then all 32-bits of data loaded into the transmitter fifo are treated as data and are transmitted. the chip compares the incoming label to the stored labels if label recognition is enabled. if a match is found, the data is processed. if a match is not found, no indicators of receiving arinc data are presented. note that 00(hex) is treated in the same way as any other label value. label bit significance is not changed by the status of control register bit cr15. label bits bd00 - bd07 are always compared to received arinc bits 1 - 8 respectively . loading labels after a write that takes cr1 from 0 to 1, the next 16 writes of data (pl pulsed low) load label data into each location of the label memory from the bd00 - bd07 pins. the pl1 pin is used to write label data for receiver 1 and pl2 for receiver 2. note that arinc word reception is suspended during the label memory write sequence. once a valid arinc word is loaded into the fifo, then eos clocks the data ready flag flip flop to a "1", d/r1 or d/r2 (or both) will go low . the data flag for a receiver will remain low until both arinc bytes from that receiver are retrieved and the fifo is empty . this is accomplished by first activating en with sel, the byte selector , low to retrieve the first byte and then activating en with sel high to retrieve the second byte. en1 retrieves data from receiver 1 and en2 retrieves data from receiver 2. up to 32 arinc words may be loaded into each receiver ? s fifo. the ff1 (ff2) pin will go low when the receiver 1 (2) fifo is full. failure to retrieve data from a full fifo will cause the next valid arinc word received to overwrite the existing data in fifo location 32. a fifo half full flag hf1 (hf2) goes low if the fifo contains 16 or more received arinc words. the hf1 (hf2) pin is intended to act as an interrupt flag to the system? s external microprocessor , allowing a 16 word data retrieval routine to be performed, without the user needing to continually poll the hi-8582/hi-8583 status register bits. label recognition hi-8582, hi-8583 functional description (cont.) h o l t i n t e g r a t e d c i r c u i t s 6
the hi-8582 has 37.5 ohms in series with each line driver output. the hi-8583 has 10 ohms in series. the hi-8583 is for applications where external series resistance is needed, typically for lightning protection devices. repea ter opera tion repeater mode of operation allows a data word that has been received by the hi-8582/hi-8583 to be placed directly into the transmitter fifo. repeater operation is similar to normal receiver operation. in normal operation, either byte of a received data word may be read from the receiver latches first by use of sel input. during repeater operation however , the lower byte of the data word must be read first. this is necessary because, as the data is being read, it is also being loaded into transmitter fifo which is always loaded with the lower byte of the data word first. signal flow for repeater operation is shown in the t iming diagrams section. hi-8582-10 and hi-8583-10 the hi-8582-10/hi-8583-10 options are similar to the hi-8582/ hi-8583 with the exception that they allow an external 10 kohm re- sistor to be added in series with each arinc input without af fect- ing the arinc input thresholds. this option is especially useful in applications where lightning protection circuitry is also required. each side of the arinc bus must be connected through a 10 kohm series resistor in order for the chip to detect the correct arinc levels. the typical 10 volt dif ferential signal is translated and input to a window comparator and latch. the comparator lev- els are set so that with the external 10 kohm resistors, they are just below the standard 6.5 volt minimum arinc data threshold and just above the standard 2.5 volt maximum arinc null thresh- old. please refer to the holt an-300 application note for additional information and recommendations on lightning protection of holt line drivers and line receivers. high speed opera tion the hi-8582 and hi-8583 may be operated at clock frequencies beyond that required for arinc compliant operation. for operation at master clock (clk) frequencies up to 5mhz, please contact holt applications engineering. power suppl y sequencing the power supplies should be controlled to prevent large currents during supply turn-on and turn-of f. the recommended sequence is v+ followed by v dd , always ensuring that v+ is the most positive supply . the v - supply is not critical and can be asserted at any time. master reset (mr) on a master reset data transmission and reception are immedi- ately terminated, all three fifos are cleared as are the fifo flags at the device pins and in the status register . the control register is not af fected by a master reset. da t a transmission when entx goes high, enabling transmission, the fifo positions are incremented with the top register loading into the data transmission shift register . within 2.5 data clocks the first data bit appears at txaout and txbout . the 31 or 32 bits in the data transmission shift register are presented sequentially to the outputs in the arinc 429 format with the following timing: high speed low speed arinc da t a bit time 10 clocks 80 clocks da t a bit time 5 clocks 40 clocks null bit time 5 clocks 40 clocks word gap time 40 clocks 320 clocks the word counter detects when all loaded positions have been transmitted and sets the transmitter ready flag, tx/r, high. transmitter p arity the parity generator counts the ones in the 31-bit word. if control register bit cr12 is set low , the 32nd bit transmitted will make parity odd. if the control bit is high, the parity is even. setting cr4 to a zero bypasses the parity generator , and allows 32 bits of data to be transmitted. self test if control register bit cr5 is set low , the transmitter serial output data are internally connected to each of the two receivers, bypassing the analog interface circuitry . data is passed unmodified to receiver 1 and inverted to receiver 2. t aking test high forces txaout and txbout into the null state regardless of the state of cr5. system opera tion t h e t w o r e c e i v e r s a r e i n d e p e n d e n t o f t h e t r a n s m i t t e r . therefore, control of data exchanges is strictly at the option of the user . the only restrictions are: 1. the received data will be overwritten if the receiver fifo is full and at least one location is not retrieved before the next complete arinc word is received. 2. the transmitter fifo can store 32 words maximum and ignores attempts to load additional data if full. line driver opera tion the line driver in the hi-8582/hi-8583 are designed to directly drive the arinc 429 bus. the two arinc outputs (txaout and txbout) provide a dif ferential voltage to produce a +10 volt one, a -10 volt zero, and a 0 volt null. control register bit cr13 controls both the transmitter data rate, and the slope of the dif ferential output signal. no additional hardware is required to control the slope. programming cr13 to zero causes a 100 kbits/s data rate and a slope of 1.5 s on the arinc outputs; a one on cr13 causes a 12.5 kbit/s data rate and a slope of 10 s. t iming is set by on-chip resistor and capacitor and tested to be within arinc requirements. hi-8582, hi-8583 functional description (cont.) h o l t i n t e g r a t e d c i r c u i t s 7
d a t a r a t e - e x a m p l e p a t t e r n txaout arinc bit txbout null da t a da t a da t a null null word gap bit 1 next word bit 32 bit 31 bit 30 t r a n s m i t t e r o p e r a t i o n pl2 dwset t dwhld t tx/r t dwhld t pl12 t pl t da t a bus pl1 tx/r, hft, fft byte 2 v alid pl t pl12 t dwset t byte 1 v alid selen t ensel t selen t b y t e 1 da t aen t enda t a t readen t r e c e i v e r o p e r a t i o n d /r , h f , f f a r in c d a t a s e l e n da t a bus b it 3 1 b it 3 2 selen t d/r t da t aen t d/ren t end/r t en t ensel t enda t a t enda t a t enen t d o n 't c a r e b y t e 1 v a l id b y t e 2 v a l id l o a d i n g c o n t r o l w o r d cwhld t cwset t cwstr t da t a bus cwstr v alid t i m i n g d i a g r a m s hi-8582, hi-8583 h o l t i n t e g r a t e d c i r c u i t s 8
l a b e l m e m o r y r e a d s e q u e n c e c w s t r e n 1 o r e n 2 da t a bus set cr1=1 label #1 label #16 set cr1=0 cwstr t cwset t cwhld t enda t a t label #2 da t aen t readen t l a b e l m e m o r y l o a d s e q u e n c e c w s t r p l 1 o r p l 2 da t a bus s e t c r 1 = 1 l a b e l # 1 l a b e l # 2 l a b e l # 1 6 s e t c r 1 = 0 cwstr t cwset t cwhld t dwset t dwhld t pl t label t c o n t r o l r e g i s t e r r e a d c y c l e b y t e s e l e c t s e l r s r da t a bus selen t da t aen t ensel t enda t a t d o n 't c a r e d o n 't c a r e d a t a v a l id s t a t u s r e g i s t e r r e a d c y c l e b y t e s e l e c t s e l r s r da t a bus selen t da t aen t ensel t enda t a t d o n 't c a r e d o n 't c a r e d a t a v a l id t i m i n g d i a g r a m s ( c o n t . ) hi-8582, hi-8583 h o l t i n t e g r a t e d c i r c u i t s 9
r e p e a t e r o p e r a t i o n t i m i n g don't care rin d/r en pl1 pl2 sel txr entx txaout txbout bit 32 don't care d/r t en t d/ren t enen t en t end/r t selen t ensel t enpl t plen t selen t ensel t enpl t plen t tx/r t tx/ren t enda t t entx/r t dtx/r t null t bit 1 bit 32 t r a n s m i t t i n g d a t a arinc bit arinc bit arinc bit pl2 entx txaout txbout diff v (txaout) - txbout) +5v +5v +5v +10v +10v -10v -5v -5v -5v txr pl2en t enda t t dtx/r t entx/r t da t a bit 1 da t a bit 2 da t a bit 32 one level zero level null level 90% 90% 10% 10% t fx t rx t fx t rx t i m i n g d i a g r a m s ( c o n t . ) hi-8582, hi-8583 h o l t i n t e g r a t e d c i r c u i t s 1 0
supply v oltages v dd ........................................... -0.3v to +7v v+ ...................................................... +12.5v v - ...................................................... -12.5v v oltage at pins rin1a, rin1b, rin2a, rin2b ..... -120v to +120v v oltage at any other pin ............................... -0.3v to v dd +0.3v solder temperature (reflow) ............................................... 260c power dissipation at 25c plastic quad flat pack ..................1.5 w , derate 10mw/c ceramic j-lead cerquad ...... 1.0 w , derate 7mw/c dc current drain per pin .............................................. 10ma storage t emperature range ........................ -65c to +150c operating t emperature range (industrial): .... -40c to +85c (extended): .... 55c to +125c - a b s o l u t e m a x i m u m r a t i n g s note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only . functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may af fect device reliability . hi-8582, hi-8583 h o l t i n t e g r a t e d c i r c u i t s 1 1
limits p arameter symbol conditions unit min typ max arinc inputs - pins rin1a, rin1b, rin2a, rin2b dif ferential input v oltage: one v ih common mode voltages 6.5 10.0 13.0 v (rin1a to rin1b, rin2a to rin2b) zero v il less than 4v with -13.0 -10.0 -6.5 v null v nul respect to gnd -2.5 0 2.5 v input resistance: dif ferential r i 12 46 k w t o gnd r g 12 38 k w t o v dd r h 12 38 k w input current: input sink i ih 200 a input source i il -450 a input capacitance: dif ferential c i (rin1a to rin1b, rin2a to rin2b) 20 pf (guaranteed but not tested) t o gnd c g 20 pf t o v dd c h 20 pf bi-directional inputs - pins bd00 - bd15 input v oltage: input v oltage hi v ih 2.0 v input v oltage lo v il 0.8 v input current: input sink i ih 1.5 a input source i il -1.5 a other inputs input v oltage: input v oltage hi v ih 2.0 v input v oltage lo v il 0.8 v input current: input sink i ih 1.5 a input source i il -1.5 a pull-up current (nfd pin) i pu -150 -50 a pull-down current (test pin) i pd 50 150 a arinc outputs - pins txaout , txbout arinc output voltage (ref. t o gnd) one or zero v dout no load and magnitude at pin, 4.50 5.00 5.50 v null v nout v dd = 5.0 v -0.25 0.25 v arinc output voltage (dif ferential) one or zero v ddif no load and magnitude at pin, 9.0 10.0 1 1.0 v null v ndif v dd = 5.0 v -0.5 0.5 v arinc output current i out 80 ma other outputs output v oltage: logic "1" output v oltage v oh i oh = -1.5ma 2.7 v logic "0" output v oltage v ol i ol = 1.6ma 0.4 v output current: output sink i ol v out = 0.4v 1.6 ma (all outputs & bi-directional pins) output source i oh v out = v dd - 0.4v -1.0 ma output capacitance: c o 15 pf operating v oltage range vdd 4.75 5.25 v v+ 9.5 10.5 v v - -9.5 -10.5 v operating supply currentvdd i dd1 4 20 ma v+ i dd2 3.2 16 ma v - i ee1 3.2 16 ma d c e l e c t r i c a l c h a r a c t e r i s t i c s v dd = 5v , gnd = 0v , t a = operating t emperature range (unless otherwise specified). v+ = 10v , v - = -10v , hi-8582, hi-8583 h o l t i n t e g r a t e d c i r c u i t s 1 2
a c e l e c t r i c a l c h a r a c t e r i s t i c s vdd = 5v , v+=10v , v -=-10v , gnd = 0v , t a = oper . t emp. range and fclk=1mhz +0.1% with 60/40 duty cycle limits p arameter symbol units min typ max control word timing pulse width - cwstr t cwstr 80 ns setup - da t a bus v alid to cwstr high t cwset 50 ns hold - cwstr high to da t a bus hi-z t cwhld 0 ns receiver fifo and label read timing delay - start arinc 32nd bit to d/r low : high speed t d/r 16 s low speed t d/r 128 s delay - d/r low to en low t d/ren 0 ns delay - en high to d/r high t end/r 250 350 ns setup - sel to en low t selen 10 ns hold - sel to en high t ensel 10 ns delay - en low to da t a bus v alid t enda t a 60 100 ns delay - en high to da t a bus hi-z t da t aen 50 80 ns pulse width - en1 or en2 t en 60 ns spacing - en high to next en low (same arinc w ord) t enen 60 ns spacing -en high to next en low (next arinc w ord) t readen 200 ns transmitter fifo and label write timing pulse width - pl1 or pl2 t pl 80 ns setup - da t a bus v alid to pl high t dwset 105 ns hold - pl high to da t a bus hi-z t dwhld 10 ns spacing - pl1 or pl2 t pl12 85 ns spacing between label w rite pulses t label 200 ns delay - pl2 high to tx/r low t tx/r 300 ns transmission timing spacing - pl2 high to entx high t pl2en 0 s delay - 32nd arinc bit to tx/r high t dtx/r 50 ns spacing - tx/r high to entx low t entx/r 0 ns line driver output timing delay - entx high to txaout or txbout : high speed t enda t 25 s delay - entx high to txaout or txbout : low speed t enda t 200 s line driver transition dif ferential times: (high speed, control register cr13 = logic 0) high to low t fx 1.0 1.5 2.0 s low to high t rx 1.0 1.5 2.0 s (low speed, control register cr13 = logic 1) high to low t fx 5.0 10 15 s low to high t rx 5.0 10 15 s repea ter opera tion timing delay - en low to pl low t enpl 0 ns hold - pl high to en high t plen 0 ns delay - tx/r low to entx high t tx/ren 0 ns master reset pulse width t mr 50 ns arinc da t a ra te and bit timing 1% hi-8582, hi-8583 h o l t i n t e g r a t e d c i r c u i t s 1 3
additional hi-8582 / hi-8583 pin configura tions 7 - d / r 1 6 - r i n 2 b 5 - r i n 2 a 4 - r i n 1 b 3 - r i n 1 a 2 - v d d 1 - / c n 5 2 - t e s t 5 1 - m r 0 - t x c l k 5 4 9 - c l k 4 8 - r s r 4 7 - n / c 46 - n/c 45 - cwstr44 - entx 43 - v+ 42 - txbout 41 - txaout 40 - v - 39 - fft38 - hft 37 - tx/r 36 - pl235 - pl1 34 - bd00 2 b d 1 0 - 1 2 b d 0 9 - 2 2 b d 0 8 - 3 0 b d 7 - 2 4 0 b d 6 - 2 5 n / c - 2 6 g n d - 2 7 n f d - 2 8 b d 0 5 - 2 9 b d 0 4 - 3 0 b d 0 3 - 3 1 b d 0 2 - 3 2 b d 0 1 - 3 3 ff1 - 8 hf1 - 9 d/r2 - 10 ff2 - 1 1 hf2 - 12 sel - 13 en1 - 14en2 -15 bd15 - 16bd14 - 17 bd13 - 18 bd12 - 19 bd1 1 - 20 hi-8582cji hi-8582cjt & hi-8583cji hi-8583cjt ordering informa tion hi - 85xx xx x x - xx 10 ohms 27.5 ohms 37.5 ohms 0 p art number 8582 8583 output series resist ance buil t -in required externall y p ackage description 52 pin cerquad j lead (52u) not available pb-free p art number cj 52 pin plastic quad fla t p ack pqfp (52pqs) pq tempera ture range burn in -40c t o +85c no -55c t o +125c no t p art number t i flow i lead finish p art number 100% matte t in (pb-free, rohs compliant) f t in / lead (sn / pb) solder blank input series resist ance buil t -in required externall y p art number 25 kohm 10 kohm -10 35 kohm 0 no dash number 52 - pin cerquad j-lead (see page 1 for additional pin configuration) hi-8582, hi-8583 h o l t i n t e g r a t e d c i r c u i t s 1 4
revision hist or y revision date description of change ds8582, rev . o 06/13/13 receiver bus pins and clarified solder temperature in absolute maximum ratings table. updated pqfp package drawing. clarified description of receiver parity . updated max voltages at arinc 429 h o l t i n t e g r a t e d c i r c u i t s 1 5 hi-8582, hi-8583
hi-8582 / hi-8583 p ackage dimensions 52-pin j-lead cerquad inches (millimeters) package t ype: 52u bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .019 .002 (.483 .051) 8 7 1 52 47 .788 (20.0) .720 .010 (18.29 .25) .750 .007 (19.05 .18) .190 (4.826) max ( 1 . 0 2 . 0 1 3 ) . 0 4 0 . 0 0 5 .050 (1.27) bsc sq. max h o l t i n t e g r a t e d c i r c u i t s 1 6 52-pin plastic quad fla t p ack (pqfp) inches (millimeters) package t ype: 52pqs d etail a see detail a 0 q 7 .520 (13.2) bsc sq .394 (10.0) bsc sq .063 (1.6) typ .008 (.20) min .005 (.13) r min r min .005 (.13) .0256 (.65) bsc .012 .004 (.310 .09) .035 .006 (.88 .15) .079 .008 (2.0 .20) .106 (2.7) max. bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95)

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