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cy62168ev30 mobl ? 16-mbit (2 m 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-07721 rev. *f revised september 17, 2013 16-mbit (2 m 8) static ram features very high speed: 45 ns wide voltage range: 2.20 v to 3.60 v ultra low standby power ? typical standby current: 1.5 a ? maximum standby current: 12 a ultra low active power ? typical active current: 2.2 ma at f = 1 mhz easy memory expansion with ce 1 , ce 2 and oe features automatic power-down when deselected cmos for optimum speed/power offered in pb-free 48-ball fbga package. for pb-free 48-pin tsop i package, refer to cy62167ev30 data sheet. functional description the cy62168ev30 is a high performance cmos static ram organized as 2 m words by 8-bits. this device features advanced circuit design to provide an ultra low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99% when deselected (chip enable 1 (ce 1 ) high or chip enable 2 (ce 2 ) low). the input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when: the device is deselected (chip enable 1 (ce 1 ) high or chip enable 2 (ce 2 ) low), outputs are disabled (oe high), or a write operation is in progress (chip enable 1 (ce 1 ) low and chip enable 2 (ce 2 ) high and we low). write to the device by taking chip enable 1 (ce 1 ) low and chip enable 2 (ce 2 ) high and the write enable (we) input low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 20 ). read from the device by taking chip enable 1 (ce 1 ) and output enable (oe ) low and chip enable 2 (ce 2 ) high while forcing write enable (we ) high. under these conditions, the contents of the memory locati on specified by the address pins will appear on the i/o pins. the eight input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or a write operation is in progress (ce 1 low and ce 2 high and we low). see the truth table on page 11 for a complete description of read and write modes. a 0 i/o 0 i/o 7 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 sense amps power down we oe a 13 a 14 a 15 a 16 row decoder column decoder 2m x 8 array data in drivers a 10 a 11 a 17 ce 1 ce 2 a 12 a 18 a 19 a 20 logic block diagram
cy62168ev30 mobl ? document number: 001-07721 rev. *f page 2 of 16 contents pin configuration ............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 dc electrical characteristics .......................................... 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagram ............................................................ 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 16 worldwide sales and design s upport ......... .............. 16 products .................................................................... 16 psoc? solutions ...................................................... 16 cypress developer community ................................. 16 technical support ................. .................................... 16
cy62168ev30 mobl ? document number: 001-07721 rev. *f page 3 of 16 pin configuration figure 1. 48-ball fbga pinout (top view) [1] product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [2] max typ [2] max typ [2] max typ [2] max cy62168ev30ll 2.2 3.0 3.6 45 2.2 4.0 25 30 1.5 12 we v cc a 0 ce 1 oe v ss ce 2 nc v cc 3 2 6 5 4 1 d e b a c f g h v ss a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 16 a 14 a 15 a 12 a 13 a 9 a 10 a 8 a 18 a 11 a 19 i/o 0 i/o 1 i/o 2 i/o 3 a 20 i/o 4 i/o 5 i/o 6 i/o 7 nc nc nc nc nc nc nc nc nc nc notes 1. nc pins are not connected on the die. 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c.
cy62168ev30 mobl ? document number: 001-07721 rev. *f page 4 of 16 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage to ground potential ....................................... ?0.3 v to v cc(max) + 0.3 v dc voltage applied to outputs in high z state [3, 4] .......................?0.3 v to v cc(max) + 0.3 v dc input voltage [3, 4] ................. ?0.3 v to v cc (max) + 0.3 v output current into outputs (low) ............................. 20 ma static discharge voltage (mil-std-883, method 3015) ................................. > 2001 v latch-up current .................................................... > 200 ma operating range range ambient temperature (t a ) [5] v cc [6] industrial ?40 c to +85 c 2.2 v to 3.6 v dc electrical characteristics over the operating range parameter description test conditions cy62168ev30-45 unit min typ [7] max v oh output high voltage 2.2 < v cc < 2.7 i oh = ? 0.1 ma 2.0 ? ? v 2.7 < v cc < 3.6 i oh = ? 1.0 ma 2.4 ? ? v ol output low voltage 2.2 < v cc < 2.7 i ol = 0.1 ma ? ? 0.4 v 2.7 < v cc < 3.6 i oh = 2.1 ma ? ? 0.4 v ih input high voltage 2.2 < v cc < 2.7 1.8 ? v cc + 0.3 v 2.7 < v cc < 3.6 2.2 ? v cc + 0.3 v il input low voltage 2.2 < v cc < 2.7 ?0.3 ? 0.6 v 2.7 < v cc < 3.6 ?0.3 ? 0.8 i ix input leakage current gnd < v i < v cc ?1 ? +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = 3.6 v, i out = 0 ma, cmos level ?2530ma f = 1 mhz ? 2.2 4.0 i sb1 [8] automatic ce power-down current ? cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v, f = f max (address and data only), f = 0 (oe , we ) ? 1.5 12 a i sb2 [8] automatic ce power-down current ? cmos inputs ce 1 > v cc ? 0.2 v or ce 2 < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = 3.6 v ? 1.5 12 a notes 3. v il (min) = ?2.0 v for pulse durations less than 20 ns. 4. v ih (max) = v cc + 0.75 v for pulse durations less than 20 ns. 5. t a is the ?instant-on? case temperature. 6. full device ac operation assumes a 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. 7. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ), t a = 25 c. 8. chip enables (ce 1 and ce 2 ) must be at cmos level to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating.
cy62168ev30 mobl ? document number: 001-07721 rev. *f page 5 of 16 capacitance parameter [9] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 8pf c out output capacitance 10 pf thermal resistance parameter [9] description test conditions 48-ball fbga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 55 ? c/w ? jc thermal resistance (junction to case) 16 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms parameters 2.5 v (2.2 v to 2.7 v) 3.0 v (2.7 v to 3.6 v) unit r1 16600 1103 ? r2 15400 1554 ? r th 8000 645 ? v th 1.2 1.75 v v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% output v th equivalent to: th venin equivalent all input pulses r th r1 fall time: 1 v/ns rise time: 1 v/ns note 9. tested initially and after any design or process changes that may affect these parameters.
cy62168ev30 mobl ? document number: 001-07721 rev. *f page 6 of 16 data retention characteristics over the operating range parameter description conditions min typ [10] max unit v dr v cc for data retention 1.5 ? 3.6 v i ccdr [11] data retention current v cc = 1.5 v ce 1 > v cc ?? 0.2 v or ce 2 < 0.2 v v in > v cc ?? 0.2 v or v in < 0.2 v ? ? 10 a t cdr [12] chip deselect to data retention time 0??ns t r [13] operation recovery time 45 ? ? ns data retention waveform figure 3. data retention waveform v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r ce 1 v cc ce 2 or notes 10. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ), t a = 25 c. 11. chip enables (ce 1 and ce 2 ) must be at cmos level to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. 12. tested initially and after any design or process changes that may affect these parameters. 13. full device ac operation requires linear v cc ramp from v dr to v cc (min) > 100 s or stable at v cc (min) ? 100 s.
cy62168ev30 mobl ? document number: 001-07721 rev. *f page 7 of 16 switching characteristics over the operating range parameter [14, 15] description 45 ns unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce 1 low and ce 2 high to data valid ? 45 ns t doe oe low to data valid ? 22 ns t lzoe oe low to low z [16] 5?ns t hzoe oe high to high z [16, 17] ?18ns t lzce ce 1 low and ce 2 high to low z [16] 10 ? ns t hzce ce 1 high or ce 2 low to high z [16, 17] ?18ns t pu ce 1 low and ce 2 high to power-up 0 ? ns t pd ce 1 high or ce 2 low to power-down ? 45 ns write cycle [18] t wc write cycle time 45 ? ns t sce ce 1 low and ce 2 high to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [16, 17] ?18ns t lzwe we high to low z [16] 10 ? ns notes 14. in an earlier revision of this device, un der a specific application condition, read and write operations were limited to swi tching of the chip enable signal as described in the application note an66311 . however, the issue has been fixed and in production now, and hen ce, this application note is no longer applicable. it is avai lable for download on our website as it contains information on the dat e code of the parts, beyond wh ich the fix has been in producti on. 15. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns or less (1 v/ns), t iming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in figure 2 on page 5 . 16. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 17. t hzoe , t hzce , and t hzwe transitions are measured when the outputs enter a high impedance state. 18. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the s ignal that terminates the write.
cy62168ev30 mobl ? document number: 001-07721 rev. *f page 8 of 16 switching waveforms figure 4. read cycle no. 1 (address transition controlled) [19, 20] figure 5. read cycle no. 2 (oe controlled) [20, 21] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzce oe ce 1 address ce 2 data out v cc supply current high i cc i sb impedance notes 19. the device is continuously selected. oe , ce 1 = v il , and ce 2 = v ih . 20. we is high for read cycle. 21. address valid before or similar to ce 1 transition low and ce 2 transition high.
cy62168ev30 mobl ? document number: 001-07721 rev. *f page 9 of 16 figure 6. write cycle no. 1 (we controlled) [22, 23, 24] figure 7. write cycle no. 2 (ce 1 or ce 2 controlled) [22, 23, 24] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data note 25 ce 1 address ce 2 we data i/o oe t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data t sa note 25 ce 1 address ce 2 we data i/o oe notes 22. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the s ignal that terminates the write. 23. data i/o is high impedance if oe = v ih . 24. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 25. during this period the i/os are in output state. do not apply input signals.
cy62168ev30 mobl ? document number: 001-07721 rev. *f page 10 of 16 figure 8. write cycle no. 3 (we controlled, oe low) [26] switching waveforms (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe note 27 ce 1 address ce 2 we data i/o notes 26. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high impedance state. 27. during this period the i/os are in output state. do not apply input signals.
cy62168ev30 mobl ? document number: 001-07721 rev. *f page 11 of 16 truth table ce 1 ce 2 we oe i/o mode power hx [28] x x high z deselect/power-down standby (i sb ) x [28] l x x high z deselect/power-down standby (i sb ) l h h l data out (i/o 0 ?i/o 7 ) read active (i cc ) l h h h high z output disabled active (i cc ) l h l x data in (i/o 0 ?i/o 7 ) write active (i cc ) note 28. the ?x? (do not care) state for the chip enables in the truth table refers to the logic state (either high or low). intermed iate voltage levels on these pins is not permitted.
cy62168ev30 mobl ? document number: 001-07721 rev. *f page 12 of 16 ordering information the below table lists the cy62168ev30 mobl key package features a nd ordering codes. the table cont ains only the parts that are currently available. if you do not see what you are looking for, contact your local sales representative. for more information, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products . ordering code definitions speed (ns) ordering code package diagram package type operating range 45 CY62168EV30LL-45BVXI 51-85150 48-ball vfbga (pb-free) industrial temperature grade: i = industrial pb-free package type: bv = 48-ball vfbga speed grade: 45 ns ll = low power voltage range = 3 v typical process technology: 90 nm bus width = 8 density = 16-mbit family code: mobl sram family company id: cy = cypress cy - 45 bv 621 6 8 e v30 ll i x
cy62168ev30 mobl ? document number: 001-07721 rev. *f page 13 of 16 package diagram figure 9. 48-ball vfbga (6 8 1 mm) bv48/bz48 package outline, 51-85150 51-85150 *h
cy62168ev30 mobl ? document number: 001-07721 rev. *f page 14 of 16 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor fbga fine-pitch ball grid array i/o input/output oe output enable sram static random access memory tsop thin small outline package vfbga very fine-pitch ball grid array we write enable symbol unit of measure c degree celsius mhz megahertz a microampere ? s microsecond ma milliampere mm millimeter ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy62168ev30 mobl ? document number: 001-07721 rev. *f page 15 of 16 document history page document title: cy62168ev30 mobl ? , 16-mbit (2 m 8) static ram document number: 001-07721 rev. ecn no. orig. of change issue date description of change ** 457686 nxr see ecn new data sheet. *a 464509 nxr see ecn removed tsop i package; added reference to cy62167ev30 tsop i package which can be used as a 2 m 8 sram changed the i sb2(typ) value from 1.3 a to 1.5 a changed the i cc(typ) value from 2 ma to 2.2 ma for f=1 mhz test condition changed the i cc(typ) value from 15 ma to 22 ma and i cc(max) value from 40 ma to 25 ma for f = 1 mhz test condition changed the i ccdr(max) value from 8.5 a to 8 a *b 1138883 vkn see ecn converted from preliminary to final changed i cc(max) spec from 2.8 ma to 4.0 ma for f=1 mhz changed i cc(typ) spec from 22 ma to 25 ma for f=f max changed i cc(max) spec from 25 ma to 30 ma for f=f max added footnote# 8 related to i sb2 and i ccdr changed i sb1 and i sb2 spec from 8.5 a to 12 a changed i ccdr spec from 8 a to 10 a *c 2934385 vkn 06/03/10 corrected typo in functional description section corrected v cc stabilization time to 200 sec updated template. added footnote #28 related to chip enable updated package diagram *d 3279426 rame 06/10/2011 removed the note ?for best practice recommendations, refer to the cypress application note an1064, sram system guidelines.? in page 1 and its reference in functional description . updated package diagram . updated in new template. *e 4100078 vini 08/20/2013 updated switching characteristics : added note 14 and referred the same note in ?parameter? column. updated package diagram : spec 51-85150 ? changed revision from *f to *h. updated in new template. *f 4126351 nile 09/17/2013 updated maximum ratings : updated note 3.
document number: 001-07721 rev. *f revised september 17, 2013 page 16 of 16 all products and company names mentioned in this document may be the trademarks of their respective holders. cy62168ev30 mobl ? ? cypress semiconductor corporation, 2006-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reaso nably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufact urer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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