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3.75 kv, 7 - channel , spisolator multiple slave, digital isolator for spi data sheet adum3154 features supports up to 17 mhz spi clock speed 4 high speed, low propagation delay, spi signal isolation channels supports up to 4 slave devices 20- lead ssop package with 5 .1 mm creepage high temperature operation: 125c high common - mode transient immunit y: >25 kv/s safety and regulatory approvals ul recognition per ul 1577 3750 v rms for 1 minute c sa component acceptance notice 5a vde certificate of conformity din v vde v 0884 - 10 (v de v 0884 - 10):2006 - 12 v iorm = 56 5 v peak applications industrial programmable logic controllers (plcs) sensor i solation functional block dia gram encode control block decode decode encode encode decode encode decode v dd1 gnd 1 mclk mo mi mss ssa0 ssa1 nic nic = not internally connected v dd2 gnd 2 sclk si so ss0 ss1 ss2 ss3 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 gnd 1 gnd 2 9 10 12 11 adum3154 12369-001 control block mux f igure 1. general description the adum3154 1 is a n spisolator? digital isolator optimized for a serial peripheral interface (spi) that includes support for up to four slave devices. based on the analog devices, inc., i coupler ? chip scale transformer technology, the low prop agation delay and jitter in the clk, mo/si, mi/ so , and ss spi bus signals support spi clock rates of up to 17 mhz. the adum3154 isolator also provides a s lave s elect multiple xing system that allows up to four slave devices to be s erviced from one isolator. when a target slave is selected, t he sl ave s elect signal propagates to the desired output with low propagation delay , allowing tight tim ing control. the isolated ssx is addr essed through a 250 kbps low speed , 2- channel address bus , allowing the target slave device to be changed in a s little as 2.5 s. t able 1 . related products product description adum3150 3. 75 kv, high speed, clock delayed spisolator adum3151 / adum3152 / adum3153 3.75 kv, multichannel spisolator adum4150 5 kv, high speed, clock delayed spisolator adum4151 / adum4152 / adum4153 5 kv, multichannel spi solator adum4154 5 kv, multiple slav e spi solat or 1 protected by u.s. patents 5,952,849; 6,262,600; 6,873,065; and 7075329. other patents are pending. rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. o ne technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 C 2015 analog devices, inc. all rights reserved. tech nical support www.analog.com
adum3154 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 5 v operation ................................ 3 electrical characteristics 3.3 v operation ............................ 5 electrical characteristics mixed 5 v/3.3 v operation ........ 7 e lectrical characteristics mixed 3.3 v/5 v operation ........ 9 package characteristics ............................................................. 10 regulatory information ............................................................. 11 insulation and safety related specifications .......................... 11 din v vde v 0884- 10 (vde v 0884 - 10):2006 - 12 insulation characteristics ............................................................................ 12 recommended operating conditions .................................... 12 absolute maximum ratings ......................................................... 13 esd caution ................................................................................ 13 pin configuration and function descriptions ........................... 14 typical performance characteristics ........................................... 16 applications information .............................................................. 17 introduction ................................................................................ 17 printed circuit board (pcb) layout ....................................... 19 propagation delay related parameters ................................... 19 dc correctness and magnetic field immunity ..................... 19 power consumpt ion .................................................................. 20 insulation lifetime ..................................................................... 20 outline dimensions ....................................................................... 22 ordering gui de .......................................................................... 22 revision history 3 / 15 rev. 0 to rev. a changes to features section and table 1 ...................................... 1 changes to supply current parameter, table 3 ............................ 4 changes to supply current parameter, table 5 ............................ 6 changes to supply current parameter, ta ble 7 ............................ 8 changes to supply current parameter, table 9 and table 10 ... 10 changes to table 11 ........................................................................ 11 changes to table 13 and figure 2 ................................................. 12 changes to high speed channels section .................................. 17 changes to ordering guide .......................................................... 22 7 /14 rev ision 0 : initial version rev. a | page 2 of 22
data sheet adum3154 specifications electric al characteristics 5 v operation all typical specifications are at t a = 25c and v dd1 = v dd2 = 5 v. minimum and maximum specifications apply over the entire recommended operation range: 4.5 v v dd1 5.5 v , 4.5 v v dd2 5.5 v , and ? 40c t a +12 5c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise noted. table 2 . switching spec i fications param eter symbol a grade b grade unit test conditions /comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 1 17 mhz data rate fast (mo, so) dr fas t 2 34 mbps within pwd limit propagation delay t phl , t plh 25 12 14 ns 50% input to 50% output pulse width pw 10 0 12.5 ns within pwd limit pulse width distortion pwd 2 2 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 2 2 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fas t 2 34 mbps within pwd limit propagation delay t phl , t plh 21 26 21 26 ns 50% input to 50% output pu lse width pw 100 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns ssa0, ssa1 data rate slow dr slow 250 250 kbps withi n pwd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s ssax 3 minimum input skew 4 t ssax skew 3 40 40 ns 1 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 the mss signal is glitch filte red in both speed grades, whereas the other fast signals are not glitch filtered in the b grade. to guarantee that mss reaches the output ahead of another fast signal, set up mss prior to the competing signal by differen t times depending on speed grade. 3 ssax = ssa1 or ssa2 . 4 an internal asynchronous clock , not available to users , samples the low speed signals. if edge sequence in codirectional channels is critical to the end application, the leading pulse must be at le ast 1 t ssax skew ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. rev. a | page 3 of 22
adum3154 data sheet table 3 . for all models 1, 2, 3 parameter symbol min typ max unit test conditions /comments supply current a grade and b grade i dd1 4.8 8.5 ma c l = 0 pf, d r fas t = 1 mhz, dr slow = 0 mhz i dd2 6.5 13 ma c l = 0 pf, d r fas t = 1 mhz, dr slow = 0 mhz b grade i dd1 10 18 ma c l = 0 pf, d r fas t = 17 mhz, dr slow = 0 mhz i dd2 13.5 19 ma c l = 0 pf, d r fas t = 17 mhz, dr slow = 0 mhz dc specifications mclk, mss , mo, so, ssa0, ssa 1 input threshold logic high v ih 0.7 v ddx v logic low v il 0.3 v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, mi, si, ss0, ss1, ss2, ss3 output voltages logic high v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current for high speed channels dynamic input i ddi(d) 0.080 ma/mbps dynamic output i ddo(d) 0.046 ma/mbps supply current for all low speed channels quiescent input i dd1(q) 4.2 ma quiescent output i dd2(q) 6.1 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v, transient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, ssa0, or ssa1 pins. 3 i output is the outpu t current of any of the sclk, mi, si, ss0 , ss1, ss2, or ss3 pins . 4 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining output voltages within the v oh and v ol limits. the common - mode voltage slew rates apply to both ri sing and falling common - mode voltage edges. rev. a | page 4 of 22
data sheet adum3154 electrical character istics 3 .3 v operation all typical specifications are at t a = 25c and v dd1 = v dd2 = 3. 3 v. minimum and maximum specifications apply over the entire recommended operation range: 3.0 v v dd1 3.6 v , 3.0 v v dd2 3.6 v , and ? 40 c t a +12 5c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise noted . table 4 . switching specifications parameter symbol a grade b grade unit test conditions /comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 1 12.5 mhz data rate fast ( mo, so ) dr fas t 2 34 mbps within pwd limit propagation delay t phl , t plh 30 21 ns 50% input to 50% output pulse width pw 100 12.5 ns within pwd limit pulse width distortion pwd 3 2 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 3 2 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fas t 2 34 mbps within pwd limit propagation delay t phl , t plh 34 34 ns 50% input to 50% output pulse width pw 100 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns ssa0, ssa1 data rate slow dr slow 250 250 kbps within p wd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s ssax 3 minimum input skew 4 t ssax skew 3 40 40 ns 1 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 the mss signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the b grade. to guarantee that mss reaches the output ahead of another fast signal, set up mss prior to the competing signal by different times depending on speed grade. 3 ssax = ssa1 or ssa2 . 4 an internal asynchronous clock , not available to users , samples the low speed signals. if edge sequence in codirectional channels is critical to the end application, the leading pulse must be at least 1 t ssax skew ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. rev. a | page 5 of 22
adum3154 data sheet table 5 . for all models 1, 2, 3 parameter symbol min typ max unit test conditions /comments supply current a grade and b grade i dd1 3.4 6.5 ma c l = 0 pf, d r fas t = 1 mhz, dr slow = 0 mhz i dd2 5 9 ma c l = 0 pf, d r fas t = 1 mhz, dr slow = 0 mhz b grade i dd1 11.7 15 ma c l = 0 pf, d r fas t = 17 mhz, dr slow = 0 mhz i dd2 10 14 ma c l = 0 pf, d r fas t = 17 mhz, dr slow = 0 mhz dc specifications mclk, mss , mo, so, ssa0, ssa1 input threshold logic high v ih 0.7 v ddx v logic low v il 0.3 v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, mi, si, ss0, ss1, ss2, ss3 output voltages logic high v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current for high speed channels dynamic input i ddi(d) 0.078 ma/mbps dynamic output i ddo(d) 0.026 ma/mbps supply current for all low speed channels quiescent input i dd1(q) 2.9 ma quiescent output i dd2(q) 4.7 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v, transient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, ssa0, or ssa1 pins. 3 i output is the output current of any of the sclk, mi, si, ss0 ss1, ss2, or ss3 pins . 4 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining output voltages within the v oh and v ol limits. the common - mode voltage slew rates appl y to both rising and falling common - mode voltage edges. rev. a | page 6 of 22
data sheet adum3154 electrical character istics mixed 5 v/3 .3 v operation all typical specifications are at t a = 25c and v dd1 = 5 v, v dd2 = 3. 3 v. minimum and maximum specifications apply over the entire recommended operation range: 4. 5 v v dd1 5.5 v , 3.0 v v dd2 3.6 v , and ? 40c t a +12 5c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise noted. table 6. switching specifications parameter symbol a grade b grade unit test conditions /comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 1 15.6 mhz data rate fast ( mo, so ) dr fas t 2 34 mbps within pwd limit propagation delay t phl , t plh 27 17 ns 50% input to 50% output pulse width pw 25 12.5 ns within pwd limit pulse width distortion pwd 2 2 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 2 2 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fas t 2 34 mbps within pwd limit propagation delay t phl , t plh 30 30 ns 50% input to 50% output puls e width pw 25 12.5 ns within pwd limit pulse width distortion pwd 2 2 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns ssa0, ssa1 data rate slow dr slow 250 250 kbps within p wd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s |t plh ? t phl | ssax 3 minimum input skew 4 t ssax skew 3 40 40 ns 1 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 the mss signal is glitch filtered in both speed grades, w hereas the other fast signals are not glitch filtered in the b grade. to guarantee that mss reaches the output ahead of another fast signal, set up mss prior to the com peting signal by different times depending on speed grade. 3 ssax = ssa1 or ssa2 . 4 an internal asynchronous clock , not available to users , samples the low speed signals. if edge sequence in codirectional channels is critical to the end application, the le ading pulse must be at least 1 t ssax skew ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. rev. a | page 7 of 22
adum3154 data sheet table 7 . for all models 1, 2, 3 parameter symbol min typ max unit test conditions /comments supply current a grade and b grade i dd1 4.8 8.5 ma c l = 0 pf, d r fas t = 1 mhz, dr slow = 0 mhz i dd2 5 9 ma c l = 0 pf, d r fas t = 1 mhz, dr slow = 0 mhz b grade i dd1 10 18 ma c l = 0 pf, d r fas t = 17 mhz, dr slow = 0 mhz i dd2 10 14 ma c l = 0 pf, d r fas t = 17 mhz, dr slow = 0 mhz dc specifications mclk, mss , mo, so, ss a0, ssa1 input threshold logic high v ih 0.7 v ddx v logic low v il 0.3 v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, mi, si, ss0, ss1, ss2, ss3 output vol tages logic high v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lo ckout uvlo 2.6 v supply current for all low speed channels quiescent input i dd1(q) 4.2 ma quiescent output i dd2(q) 4.7 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v, transient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, ssa0, or ssa1 pin s. 3 i output is the output current of any of the sclk, mi, si, ss0 , ss1, ss2, or ss3 pins . 4 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining output voltages within the v oh and v ol limits. the common - mode voltage sl ew rates apply to both rising and falling common - mode voltage edges. rev. a | page 8 of 22
data sheet adum3154 el ectrical characteris tics mixed 3 .3 v/ 5 v operation all typical specifications are at t a = 25c and v dd1 = 3. 3 v, v dd2 = 5 v . minimum and maximum specifications apply ove r the entire recommended operation range: 3.0 v v dd1 3.6 v, 4.5 v v dd2 5.5 v, and ? 40c t a +12 5c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise noted. table 8. switching specifications parameter symbol a grade b grade unit test conditions /comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 1 1 5.6 mhz data rate fast ( mo, so ) dr fas t 2 34 mbps within pwd limit propagation delay t phl , t plh 28 17 ns 50% input to 50% output pulse width pw 10 0 12.5 ns within pwd limit pulse width distortion pwd 2 2 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 2 2 ns jitter, high speed j hs 1 1 ns mss jitter 1 1 ns data rate fast dr fas t 2 34 mbps within pwd limit propagation delay t phl , t plh 28 21 28 ns 50% inpu t to 50% output pulse width pw 100 12.5 ns within pwd limit pulse width distortion pwd 2 2 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns ssa0, ssa1 data rate slow dr slow 2 50 250 kbps within pwd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s |t plh ? t phl | ssax 3 minimum input skew 4 t ssax skew 3 40 40 ns 1 codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 the mss signal is glitch filtered in both speed grades, wh ereas the other fast signals are not glitch filtered in the b grade. to guarantee that mss reaches the output ahead of another fast signal, set up mss pri or to the competing signal by different times depending on speed grade. 3 ssax = ssa1 or ssa2 . 4 an internal asynchronous clock , not available to users , samples the low speed signals. if edge sequence in codirectional channels is critical to the end applic ation, the leading pulse must be at least 1 t ssax skew ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. rev. a | page 9 of 22
adum3154 data sheet table 9 . for all models 1, 2, 3 parameter symbol min typ max unit test conditions /comments supply current a grade and b grade i dd 3.4 6.5 ma c l = 0 pf, d r fas t = 1 mhz, dr slow = 0 mhz i dd2 6.5 13 ma c l = 0 pf, d r fas t = 1 mhz, dr slow = 0 mhz b grade i dd 11.7 15 ma c l = 0 pf, d r fas t = 17 mhz, dr slow = 0 mhz i dd2 13.5 19 ma c l = 0 pf, d r fas t = 17 mhz, dr slow = 0 mhz dc specifications mclk, mss , mo, so, ssa0, ssa1 input threshold logic high v ih 0.7 v ddx v logic low v il 0.3 v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, mi, si, ss0, ss1, ss2, ss3 output voltages logic high v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current for all low speed channels quiescent input i dd1q) 2.9 ma quiescent output i dd2(q) 6.1 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode t ransient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v, transient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, ssa0 , or ssa1 pins. 3 i output is the output current of any of the sclk, mi, si, ss0 , ss1, ss2, or ss3 pins . 4 |cm| is the maximum common - mode voltage slew rate that can be sustained wh ereas maintaining output voltages within the v oh and v ol limits. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. package characterist ics table 10 . parameter symbol min typ max unit test conditions /comments resistance (input to output) 1 r i-o 10 12 ? capacitance (input to output) 1 c i-o 1.0 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction to case thermal resistance jc 68.5 c/w 4- layer jedec test board, jesd 51 - 7 specification 1 the device is considered a 2 - terminal device: pin 1 through p in 10 are shorted together, and pin 11 through pin 20 are shorted to gether. 2 input capacitance is from any i nput data pin to ground . rev. a | page 10 of 22
data sheet adum3154 reg ulatory information the adum315 4 is a pprov ed by the organizations listed in table 11. see table 16 and the insulation lifetime section for recommended maximum working voltages for specific cro ss isolation waveforms and insulation levels. table 11 . ul csa vde recognized under 1577 c omponent recognition program 1 ap proved under csa component acceptance notice #5a certified according to din v vde v 0884 - 10 (vde v 0884 - 10):2006- 12 2 3750 v rms single protection basic insulation per csa 60950 -1- 07+a1+a2 and iec 60950 -1 2 nd ed.+a1+a2, 510 v rms (721 v peak) maximum worki ng voltage 3 reinforced insulation, 56 5 v peak file e214100 file 205078 file 2471900 - 4880 - 0001 1 in accordance with ul 1577, each adum3154 is proof tested by applyi ng an insulation test voltage 45 00 v rms for 1 sec ond (cur rent leakage detection limit = 10 a). 2 in accordance with din v vde v 0884 - 10 , each adum3154 is proof tested by applying an insulation test voltage 525 v peak for 1 second (partial discharge detection limit = 5 pc). the asterisk (*) marked on the component designates din v vde v 0884 - 10 approval. 3 see table 16 for recommended maximum working voltages under various operating conditions. insulation and safety related specificatio ns table 12 . parameter symbol value unit test conditions/ co mments rated dielectric insulati on voltage 3750 v rms 1 minute duration minimum external air gap (clearance) l(i01) 5 .1 mm min measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 5 .1 m m min measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 mm min d istance through insulation tracking resistance (comparative tracking index) cti > 400 v din iec 112/vde 0303 part 1 material group ii material g roup (din vde 0110, 1/89, table 1) rev. a | page 11 of 22
adum3154 data sheet din v vde v 0884 - 10 (vde v 0884 - 10) : 2006 - 12 insulation character istics this isolator is suitable for reinforced electrical isolation only within the safety limit data. maintenance of th e safety data is ensured by protective circuits. the asterisk ( * ) marked on packages denotes din v vde v 0884 - 10 approval. table 13 . description test conditions/comments symbol characteristic unit installation classification per di n vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 565 v peak input - to - output test voltage, method b1 v iorm 1.875 = v pd(m) , 100% production test, t ini = t m = 1 sec, partial discharge < 5 pc v pd(m) 1059 v peak input - to - output test voltage, method a after environmen tal tests subgroup 1 v iorm 1.5 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 848 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 67 8 v peak highest allowable overvoltage v iotm 5000 v peak surge isolation voltage v iosm(test) = 10 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 6250 v peak safety limiting values maximum value allowed in the event of a failure (see figure 2 ) case temperature t s 150 c safety total dissipated power i s1 1.4 w insulation resistance at t s v io = 500 v r s >10 9 ? 1.6 1.8 2.0 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 50 200 100 150 12369-002 safe limiting power (w) ambient temperature (c) figure 2 . thermal derating curve, dependence of safety limiting values with case temperature per din v vde v 0884 - 10 recommended operating conditions table 14 . parameter symbol min max unit operating temperature range t a ? 40 +1 25 c supply voltage range 1 v dd1 , v dd2 3.0 5.5 v input signal rise and fall times 1.0 ms 1 see the dc correctness and magnetic field immunity section for information on the i mmunity to the external magnetic fields. rev. a | page 12 of 22
data sheet adum3154 absolute maximum r atings t a = 25c, unless othe rw ise noted table 15. parameter rating storage temperature (t st ) range ?65c to +150 c ambient operating temperature (t a ) range ?40c to +1 2 5 c supply voltages (v dd1 , v dd2 ) ?0.5 v to +7.0 v input volta g es ( mclk, mss , mo, so, ssa0, ssa1 ) ?0.5 v to v ddx + 0.5 v output voltages ( sclk, mi, si, s s0 ss1, ss2, ss3) ?0.5 v to v ddx + 0.5 v average output current per pin 1 ?10 ma to +10 ma common - mode transients 2 ?100 kv/ s to +100 kv/ s 1 see figure 2 for maximum safety rated current values across temperature. 2 refers to c ommon - mode transients across the insulation barrier. common - mode transients exceeding the absolute maximum ratings may cause latch - up or permanent damage. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the pr oduct. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. table 16. maximum continuous working voltage 1 parameter max unit constraint ac 60 hz rms voltage 400 v rms 20- year lifetime at 0.1% failure rate, zero average voltage dc voltage 722 v peak l imited by the creepage of the packa ge, pollution degree 2, material g roup ii 2, 3 1 see the insulation lifetime section for details . 2 other pollution degree and material group requirements yield a different limit. 3 some system level standards allow components to use the printed wiring board ( pwb ) creepage values. the supported dc voltage may be higher for those standards. esd caution rev. a | page 13 of 22
adum3154 data sheet pin configuration an d function descripti ons v dd1 1 gnd 1 2 mclk 3 mo 4 20 19 18 17 mi 5 mss 6 ssa0 7 16 15 14 ssa1 8 13 nic notes 1. nic = not internal l y connected. this pin is not internal l y connected and se r ves no function in the adum3154. 9 12 gnd 1 v dd2 gnd 2 sclk si so ss0 ss1 ss2 ss3 gnd 2 10 1 1 12369-003 adum3154 (not to scale) t o p view figure 3 . pi n configuration table 17. pin function descriptions pin no. mnemonic direction description 1 v dd1 power input power supply for side 1. a bypass capacitor from v dd1 to gnd 1 to local ground is required. 2, 10 gnd 1 return ground 1. ground reference for isolator side 1. 3 mclk input spi clock from the master c ontroller . 4 mo input spi data from the master to the slave mo / si l ine . 5 mi output spi data f rom the slave to the m aster mi / so l ine. 6 mss input slave se lect from the master. this signal uses an active low logic. the s lave select pin can require as much as a 10 n s setup time f rom the next clock or data edge depending on the speed grade . 7 ssa0 input multiplex e r s election i nput, l ow o rder b it. 8 ssa1 inpu t multiplex e r s election i nput, h igh o rder b it. 9 nic no t i nterna l l y c onnect ed . this pin is not internally connected and serves no function in the adum3154 . 11, 19 gnd 2 return ground 2. groun d reference for isolator side 2. 12 ss3 output routed slave select signal . high - z when ss3 is not selected. 13 ss2 output routed slave select signal . high - z when ss2 is not selected. 14 ss1 output routed slave select signal . high - z when ss1 is not selec ted. 15 ss0 output routed slave select signa l. high - z when ss0 is not selected. 16 so input spi data f rom the s lave to the m aster mi / so l ine. 17 si output spi data f rom the m aster to the slave mo / si l ine. 18 sclk output spi clock from the master c ontro ller . 20 v dd2 power input power supply for side 2. a bypass capacitor from v dd2 to gnd 2 to local ground is required. rev. a | page 14 of 22
data sheet adum3154 table 18 . multiplex e r select truth table 1 master m ux inputs slave m ux outputs mss s sa0 ssa1 ss0 ss1 ss2 ss3 1 0 0 1 z z z 0 0 0 0 z z z 1 1 0 z 1 z z 0 1 0 z 0 z z 1 0 1 z z 1 z 0 0 1 z z 0 z 1 1 1 z z z 1 0 1 1 z z z 0 1 z = high impedance. table 19. power off default state truth table (positive logic) 1, 2 master side slave side power state output inputs power state input outputs v dd1 mi mclk mo v dd2 so sclk si unpowered 3 z x x powered x z z powered z x x unpowered 3 x z z powered 1 1 1 powered 1 1 1 powered 0 0 0 powered 0 0 0 1 z = high impedance. 2 x = irrelevant. 3 outputs on an unpowered side are high impedance within one diode drop of ground. rev. a | page 15 of 22
adum3154 data sheet typical performance characteristics 0 1 2 3 4 5 7 6 0 20 40 60 80 d at a r a te (mbps) 3 . 3 v 5 .0v 12369-004 dynamic supp l y current per input channe l (ma) figure 4 . typical dynamic supply current per input channel vs. data rate for 5.0 v and 3.3 v operation 0 5 10 15 20 25 30 0 20 40 60 80 i dd1 supp l y current (ma) d at a r a te (mbps) 3 . 3 v 5 .0v 12369-006 figure 5 . typical i dd1 supply current vs. data r ate for 5.0 v and 3 .3 v operation 0 2 4 6 8 10 12 14 16 ?40 10 60 1 10 pro p ag a tion del a y (ns) ambient temper a ture (c) 3 . 3 v 5 .0v 12369-008 figure 6 . typical propagation delay vs. ambient temperature for high speed channels without glitch filter (see the high speed channels section) 12369-005 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 20 40 60 80 d at a r a te (mbps) 3 . 3 v 5 .0v dynamic supp l y current per output channe l (ma) figure 7 . typical dynamic supply current per output channel vs. data rate for 5 .0 v and 3.3 v operation 0 5 10 15 20 25 0 20 40 60 80 i dd2 supp l y current (ma) dat a r a te (mbps) 3 . 3 v 5 .0v 12369-007 figure 8 . typical i dd2 supply current vs. data rate for 5.0 v and 3 .3 v operation ?40 10 60 1 10 ambient temper a ture (c) 3 . 3 v 5 .0v 0 5 10 15 20 25 pro p ag a tion del a y (ns) 12369-009 figure 9 . typical propagation delay vs. ambient temperature for high speed channels with glitch filter (see the high speed channels section) rev. a | page 16 of 22
data sheet adum3154 application s information introduction the adum3154 was created to optimiz e isolation of the spi for speed an d provide additional low speed c h annels for control and status monitoring functio ns. the isolator is based on d ifferential signaling i coupler technology for enhanced speed and noise immunity. high speed channels the adum 3154 has four high speed channels . the first three channels , clk, mi / so, and mo / si (the slash indicates the connection of the particular input an d output channel across the isolator) , are optimized for either low propagation delay in the b grade, or high noise immunity in the a grade. the difference between the grades is the addition of a glitch filter to these three channels in the a grade version , which increases the propagation delay. the b grade version, with a maximum prop agation delay of 1 4 ns , support s a maximum clock rate of 17 mhz in standard 4 - wire spi . however , because the glitch filter is not present in the b grade version, en sure that s purious glitches of less than 10 n s are not present. glitches of less than 10 n s in the b grade devices can cause the second edge of the glitch to be miss ed . this pulse condition is then seen as a spurious data transition on the output that is corrected by a refresh or the next valid data edge. it is recommended to use the a grade devices in noisy environments. the relationship between the spi signal paths and the pin mnemonic s of the adum315 4 a nd data directions is detail ed in table 20. table 20. pin mnemonic s correspondence to spi signal path names spi signal path master side 1 data direction slave side 2 clk mclk the data paths are spi mode agnostic. the clk and mosi spi datapaths are optimized for propagation delay and channel to channel matching. the miso spi datapath is optimized for pro pagation delay. the device does n ot synchronize to the clock channel ; therefore, there are no constraints on the clock polarity or the timing with respect to the data line . to allow compatibility with non standard spi interfaces, the mi pin is a lways active , and does not tris tate when the slave select is not asserted. this precludes tying several mi line s together without adding a tri sate buffer or multiplexor. the ss (slave select bar) is typically an active low signal. it can have many different functions in spi and spi like busses. many of these functions are edge triggered, so the ss path contains a glitch filter in both the a grade and the b grade . the glitch filter prevent s short pulses from propagating to the outpu t or causing other errors in operation . t he mss signal requires a 10 ns setup time in the b grade devices prior to the first active clock edge to allow the added propagation time of the glitch filter . slave select multiplexer the adum3154 can control up to four independent slave devices. figure 10 shows how this can be done using general - purpose isolators. an isolation channel is required for each slav e select ; therefore, seven high speed channels are required to transfer bidirectional data to four slaves. master isol a t or sl a ve 0 clk mosi miso 12369-010 ss0 clk mosi miso ss0 sl a ve 1 clk mosi miso ss1 sl a ve 2 clk mosi miso ss2 sl a ve 3 clk mosi miso ss3 ss1 ss2 ss3 figure 10 . multiple slave control with standard isolators rev. a | page 17 of 2 2
adum3154 data sheet figure 11 shows how the adum3154 can control up to four slaves by routing the mss input to one of four outputs on the slave side of the isolator , which eliminates three isolation channels compared to the standard solution. master adum3154 sl a ve 0 clk mosi miso 12369-0 1 1 mux clk mosi miso ss0 sl a ve 1 clk mosi miso ss1 sl a ve 2 clk mosi miso ss2 sl a ve 3 clk mosi miso ss3 ssa0 ssa1 mss figure 11 . multiple slave control the multiplex e r select lines are low speed channels implemented as part of the dc correctness scheme in the adum31 54. the dc value of all high and low speed inputs on a given side of the device are sampled simultaneously, packetized , and shifted across an isolation coil. the high speed channels are compared for dc accuracy , and the low speed mux select lines , ssa0 an d ssa1 , are transferred to t he mux control block . the dc correctness data for the high speed channels is handled internally with no visibility off chip . this data is regulated b y a free running internal clock. because data is sa m pled at discrete times base d on this clock, the propagation del ay for mux select lines is between 1 00 n s and 2.6 s depending on where the input data edge changes with respect to the internal sample clock. after an address propagation delay time of up to 2.6 s , th e multiplex e r rout es the mss signals to the desired output. the outputs that are not selected are set to high - z , and the application pull s them to the desired idle state . figure 12 illustrates the behavior of the ssa0 an d ss a1 channels. this diagram assume s that mss is low and that ss0, ss1, ss2, and ss3 are pulled up. ssa0 ss0 sample clock output clock b c ssa1 ss1 ss2 ss3 a b c 12369-012 a a figure 12 . m ux select timing the following details the mux select timing shown in figure 12: ? point a: the mux select lines must be switched simultaneously to within the t ssax skew time. failure to do this may allow sampling the inputs between the edges and selecting an incorrect mux output. point a on ss1 is a metastable stat e on the output mux resulting from wide spacing between ssa0 and ssa1 . ? point b: for mux select lines to be processed predictably, a state of ssa0 and ssa1 must be stable for longer than 4 s before switching the mux to another output. this guarantees that at least two samples are taken of the inputs before the mux output is changed. ? point c: this point in figure 12 shows a clean transfer between ss3 being active and ss0 being active. the mux was designed to eliminate any short dura tion metastable states between any two selected outputs. rev. a | page 18 of 22
data sheet adum3154 p rinted c ircuit board (pcb) layout the adum315 4 digital isolator requires no external interface circuitry for the logic inte rfaces. power supply bypassing is strongly recommended at both input and output supply pins , v dd1 and v dd2 ( see figure 13 ). the capacitor value must be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the input power supply pin must not exceed 20 mm. by p ass < 2mm 12369-013 v dd1 gnd 1 mclk mo mi mss ssa0 ssa1 v dd2 gnd 2 sclk si so ss0 ss1 ss2 nic gnd 1 ss3 gnd 2 adum3154 t o p view (not to scale) figure 13 . recommended pcb layout in applications involving high common - mode transients, it is important to minimize board coupling across the isolation barrier. furthermore, design the board layout so that any coupling that does occur affects all pins equally on a given component side. failure to ensure this c an cause voltage differentials between pins exceeding the absolute maximum rating s of the device , thereby leading to latch - up or permanent damage. propagation delay related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. the input to output propagation delay time for a high to low transition may differ from the propagation delay time of a low to high transition . input output t plh t phl 50% 50% 12369-014 figure 14 . propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and a n indication of how accurately the timing of the input signal is preserved. channel to channel matching refers to the maximum amount the propagation delay differs between channels within a single adum315 4 component. dc correctness and m agnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. the decoder is bistable and is, therefore, eith er set or reset by the pulses indicating input logic transitions. in the absence of logic transitions at the input for more than ~1 .2 s, a periodic set of refresh pulses indicative of the correct input state are sent via the low speed channel to ensure dc correctness at the output. if the low speed decoder receives no pulses for more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a high - z state by the watchdog timer circuit . the limitation on the magnetic field immunity of the device is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. the following analysis defines such conditions. th e adum 3154 is examined in a 3 v operating condition because it represents the most susceptible mode of operation for this product . the pulses at the transformer output have an amplitude greater than 1.5 v. the decoder has a sensing threshold of about 1.0 v ; there by establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ? d / dt ) ? r n 2 ; n = 1, 2, , n where: is the mag netic flux density. r n is the radius of the n th turn in the receiving coil. n is the number of turns in the receiving coil. given the geometry of the receiving coil in the adum 3154 and an imp osed requirement that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated, as shown in figure 15. magnetic field frequency (hz) maximum allowable magnetic flux density (kgauss) 1k 0.001 100 100m 10 1 0.1 0.01 10k 100k 1m 10m 12369-015 figure 15 . maximum allowable extern al magnetic flux density rev. a | page 19 of 22
adum3154 data sheet for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.5 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty outp ut transition. if such an event occurs, with the worst - case polarity, during a transmitted pulse , it reduce s the received pulse from >1.0 v to 0.75 v , which is still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the adum 3154 transformers. figure 16 expresse s these allowable current magni tudes as a f unction of frequency for selected distances. the adum 3154 is insensitive to external fields. only extremely large, high frequency currents very close to the component are potentially a concern. for the 1 mhz example noted, a user would have to place a 1.2 ka current 5 mm away from the adum 3154 to affect component operation. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 12369-016 figure 16 . maximum allowable curr ent for various current to adum3154 spacings a t combinations of a strong magnetic field and high frequency, any loops formed by the pcb traces may induce sufficiently large error voltages to t rigger the thresholds of succeeding circuitry. take care to avoid pcb structures that form loops. power consumption the supply current at a given channel of the adum3154 isolator is a function of the supply voltage, the data rate of the channel , the output load of the channel , and whether it is a high or low speed channel. the low speed channels draw a constant quiescent current caused by the internal ping - p ong datapath. the operating frequency is low enough that the capacitive losses caused by the recommended capacitive load are negligible compared to the quiescent current. the explicit calculation for the data rate is eliminated for simplicity, and the quiescent current for each side of the iso lator due to the low speed channels can be found in table 3 , table 5 , table 7 , and table 9 for the particular operating voltages . t hese quiescent current s add to the high speed current as is shown in the following equations for the total current for each side of the isolator. dynamic currents are taken from table 3 and table 5 for the respective voltages. f or s ide 1 , the supply current is given by ( ) ( ) ( ) ( ) dd1(q) dd1 l(mi) ddo(d) mi mo mclk ddi(d) dd1 i v c i f f f f i i + + + + + = ? 3 mss 10 5 . 0 for s ide 2 , the supply current is given by ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) (q) dd dd l(ssx) ddo(d) ssx dd l(si) ddo(d) si dd l(sclk) ddo(d) sclk so ddi(d) dd i v c i f v c i f v c i f f i i 2 2 3 2 3 2 3 2 10 5 . 0 10 5 . 0 10 5 . 0 + + + + + + + = ? ? ? i ddi (d) , i ddo ( d) are the input and output dynamic supply currents per channel (ma/mbps). f x is the logic signal data rate for the specified channel ( mbps ) . c l (x) is the load capacitance of the specified output (pf). v dd x is the supply voltage of the side being evaluated (v ) . i dd1 (q) , i dd2 (q) are the specified s ide 1 and s ide 2 quiescent supply currents (ma ) . figure 4 and figure 7 show the supply current per channel as a function of data rate fo r an input and unloaded output . figure 5 and figure 8 show the total i dd1 and i dd2 supply current s as a function of data rate for adum3154 channel configurations with all high speed channels running at the same speed and the low speed channels at idle. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a s ufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage wavefor m applied across the insulation , as well as the materials and material interfaces . two types of insulation degradation are of primary inte rest : breakdown along surfaces exposed to the air and insulation wear out. surface breakdown is the phenomenon of surface tracking and the primary determinant of surface creepage requirements in system level standards. insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long - term insulation degradation. rev. a | page 20 of 22
data sheet adum3154 surface tracking surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions , and the properti es of the insulation material. safety agencies perform characterization testing on the surface insulation of components that allow the components to be categorized in different material groups. lower material g roup ratings are more resistant to surface tracking and , therefore , can provide adequate lifetime with smaller creepage . the minimum creepage f or a given working voltage and m aterial group is in each system level standard and is based on t he total rms voltage across the isolation , pollution degree, and material g roup . the material g roup and creepage for the adum3154 isolator are detailed in table 12. in sulation wear out the lifetime of insulation caused by wear out is determined by its thickness, the material properties , and the voltage stress applied. it is important to verify that the produ ct lifetime is adequate at th e application working voltage. the working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. it is the working voltage applicable to tracking that is specified in most standards. testing and modeling have shown that the primary driver of long - term degradation is displacement current in the polyimide insulation causing incremental damage. the stress on the insulation can be broken down into two broad categories , such as dc stress , which causes very little wear out because there i s no displacement current , and an ac component time varying voltage stress , which cause s wear out . the ratings in certification documents are usually based on 60 hz sinusoidal stress , be c ause this reflects isolation from line voltage. however , m any practic al applications have combinations of 60 hz ac and dc across the barrier , as shown in equation 1 . because only the ac portion of the stress causes wear out , the equation can be rearranged to solve for the ac rms voltage , as shown in equation 2. for insulati on wear out with the pol yimide materials used in this product , the ac rms voltage determines the product lifetime. 2 2 dc rms ac rms v v v + = dc rms rms ac v v v ? = v rms is the total rms working voltage. v ac rms is the time varying po r tion of the working voltage. v dc is the dc offset of the working voltage. calculation and use of parameters example the following is an example that frequently arises in power conversion applications. assume that the line voltage on one side of the isolation i s 240 v ac rms , and a 400 v dc bus voltage is present on the other side of the isolation barrier. the isolator material is polyimide. to establish the critical voltages in determining the creepage clearance and lifetime of a device , see figure 17 and the following equations . isol a tion vo lt age time v ac rms v rms v dc 12369-017 v peak figure 17 . critical voltage example the working voltage across the barrier from equation 1 is 2 2 dc rms ac rms v v v + = + = rms v v rms = 466 v this is the working voltage us ed together with the material group and pollution degree when looking up the creepage required by a system standard. to determine if the lifetime is adequate , obtain the time varying portion of the working voltage. t he ac rms voltage can be obtained from e quation 2 . 2 2 dc rms rms ac v v v ? = ? = rms ac v v ac rms = 240 v rms in this case, the v ac rms is simply the line voltage of 240 v rms . this calculation is more relevant when the waveform is not sinusoidal. the value is compared to the limits for t he working voltage listed in table 16 for the expected lifeti me, under a 60 hz sine wave, and it is well within the limit for a 50 - year service life. note that the dc working voltage limit in table 16 is set by the creepage of the package as specified in iec 60664- 1 . this value may differ for specific system level standards . rev. a | page 21 of 22
adum3154 data sheet rev. a | page 22 of 22 outline dimensions compliant to jedec standards mo-150-ae 060106-a 20 11 10 1 7.50 7.20 6.90 8.20 7.80 7.40 5.60 5.30 5.00 seating plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarity 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 18. 20-lead shrink small outline package [ssop] (rs-20) dimensions shown in millimeters ordering guide model 1 no. of inputs, v dd1 side no. of inputs, v dd2 side maximum data rate (mhz) maximum propagation delay, 5 v (ns) isolation rating (v rms) temperature range package description package option adum3154arsz 5 1 1 25 3750 ?40c to +125c 20-lead ssop rs-20 adum3154arsz-rl7 5 1 1 25 3750 ?40c to +125c 20-lead ssop, 7 tape and reel rs-20 ADUM3154BRSZ 5 1 17 14 3750 ?40c to +125c 20-lead ssop rs-20 ADUM3154BRSZ-rl7 5 1 17 14 3750 ?40c to +125c 20-lead ssop, 7 tape and reel rs-20 eval-adum3154z evaluation board 1 z = rohs compliant part. ?2014C2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12369-0-3/15(a)

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