linear integrated s ystems ? 4042 clipper court ? fremont, ca 94538 ? tel: 510 490 - 9160 ? fax: 510 353 - 0261 doc 201123 03/18/2015 rev#a8 ecn# sst/ u4 01 sst/ u406 features low drift v gs1 - 2 /t= 10v/oc typ. low noise e n =6nv/hz@10hz typ. low pinchoff v p =2.5v max . absolute maximum ratings note 1 @ 25 c (unless otherwise noted ) maximum temperatures storage temperature - 55 to +150c operating junction temp erature - 55 to +150c maximum voltage and current for each transistor note 1 - v gss gate voltage to drain or source 50v - v dso drain to source voltage 50v - i g(f) gate forward current 10m a maximum power dissipation per side note 2 device dissipation ta = 25 c 300mw matching characteristics @ 25c (unless otherwise noted) symbol characteristic u 40 1 u 40 2 u 40 3 u 40 4 u 405 u 40 6 units conditions v gs1 - 2 /t max. drift vs. temperature 10 10 25 2 5 4 0 80 v/oc v dg = 10v , i d = 200a t a = - 55oc to +125oc v gs1 - 2 max. offset voltage 5 10 10 15 20 40 mv v dg = 10v, i d = 200a electrical characteristics ta = 25oc (unless otherwise noted) note 3 symbol characteristic min. typ. max. units conditions bv gss breakdown voltage - 50 - 60 -- v v ds = 0 i d = 1na bv g1g2 gate - to - gate breakdown 50 -- -- v i g = 1a i d = 0, i s = 0 transconductance g fss full conduction 2000 -- 7000 s v dg = 10v v gs = 0 f = 1khz g fs typical operation 1000 -- 2000 s v dg = 15v i d = 200a f = 1khz g fs 1 /g fs2 mismatch 0.97 -- 1.0 idss saturation drain current 0.5 -- 10 ma v dg = 10v v gs = 0 idss1 idss 2 saturation current ratio 0.9 0.98 1.0 gate voltage v gs (off) or v p pinchoff voltage - 0.5 -- - 2.5 v v ds = 15v i d = 1na v gs operating range -- -- - 2.3 v v ds = 15v i d = 200a gate current i g operating -- - 4 - 15 pa v dg = 15v i d = 200 a i g high temperature -- -- - 10 na t a =+125oc i gss gate reverse current -- -- - 100 pa v gs = - 30v, v ds = 0v i g1g2 gate to gate isolation c urrent -- -- 1.0 a v g1 - v g2 = 50v, i d = is= 0 sst/ u401 C sst/ u406 low noise low drift monolithic dual n - channel jfet amplifier to - 71 top view soic top view
linear integrated s ystems ? 4042 clipper court ? fremont, ca 94538 ? tel: 510 490 - 9160 ? fax: 510 353 - 0261 doc 201123 03/18/2015 rev#a8 ecn# sst/ u4 01 sst/ u406 symbol characteristic min. typ. max. units conditions output conductance g oss full conduction -- -- 40 s v ds = 10v, v gs = 0 v , f = 1khz g os operating -- 2 2 .7 s v ds = 15v, i d = 2 00a , f = 1khz common mode rejectio n v dg1 = 10v cmrr - 20 log [ ( v gs1 - v gs2 ) / v dg 1 - 2 ] 95 -- -- db v dg2 = 20v i d 1 = i d2= 200 a noise nf figure -- -- 0.5 db v ds = 15v v gs = 0 r g =10m f= 100hz nbw= 6hz e n voltage -- 6 20 nv/hz v ds = 15v i d = 200a f= 10hz nbw= 1hz cap acitance c iss input -- 4 8 pf v ds = 15v i d = 200a f= 1m hz c rss reverse transfer -- 1.5 3 pf notes: 1. these ratings are limiting values above which the serviceability of any semiconductor may be impaired . 2. derate 2.4mw/ o c when ta is greater than 25 o c 3. all min/typ/max limits are absolute numbers. negative signs indicate electrical polarity only. information furnished by linear integrated systems is believed to be accurate and reliable. however, no responsibility is ass umed for its use; nor for any infringement of patents or other rights o f third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of linear integrated systems. 8 4 8 4 0.210 0.170 to - 71 to - 78 p - dip soic note: all dimensions in inches linear integrated systems (lis) is a 25 - year - old, third - generation precision semiconductor company providing high - quality discrete components. expertise brought to lis is based on processes and products developed at amelco, union carbide, intersil and micro power systems by company president john h. hall. hall, a protg of silicon valley legend dr. jean hoerni, was the director of ic development at union carbide, co - founder and vice president of r&d at intersil, and founder/president of micro power systems.
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