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as3644 ultra small low cost 320ma in ductive white le d flash driver www.austriamicrosystems.com/as3644 1.2.2 1 - 23 (ptr) datasheet 1 general description the as3644 is an inductive high efficient dcdc step up converter driving a current source. the dcdc step up converter operates at a fixed frequency of 4mhz and includes soft startup to allow easy integration into noise sensitive rf systems. the cu rrent source operates in flash/torch/assist (v ideo/autofocus) mode. the as3644 includes flash timer, overvoltage, overtem- perature, undervoltage and led short circuit protection functions. the as3644 is able to detect a broken coil. together with the led short and ope n detection the as3644 can be used to verify the connection to its external compo- nents and allowing in-circuit test. this reduces test time and simplifies production test procedures. the as3644 is controlled by an i 2 c interface to allow sophisticated control of all settings like currents and tim- ings. the complete flash driver solution measures only 11mm 2 pcb area. the as3644 is available in a space-saving wl-csp package measuring only 1. 5x1.1x0.6mm and operates over the -30oc to + 85oc temperature range. figure 1. typical operating circuit 2 key features ?? total flash driver solution only 11mm 2 ?? high efficiency 4mhz fixed frequency dcdc boost converter with soft start allows small coils ?? led currents 260ma to 320ma flash current (20ma steps) 51.6ma or 72.3ma assist light (=torch) current ?? flash led(s) cathode connected to ground: improved thermal performance (ground = heat sink) simplified pcb layout ?? adjustable flash timer 30ms to 480ms in 30ms steps ?? flash, torch, assist and indicator mode ?? protection functions: automatic flash timer to protect the led overvoltage and undervoltage protection overtemperature protection led short circuit protection ?? available in tiny wl-csp packages 2x3 balls 0.5mm pitch, 1.5x1.1x0.6mm package size 3 applications flash/torch for mobile phones, digital cameras and pda as3644 as3644 ams ag technical content still valid
www.austriamicrosystems.com/as3644 1.2.2 2 - 23 as3644 datasheet - pinout 4 pinout pin assignment figure 2. pin assignments (top view) pin description table 1. pin description for as3644 pin number pin name description a1 sw dcdc converter switching node - make a short connection to the coil l dcdc a2 gnd power and signal ground - connect to gnd and make a short connection to c vout b1 led_out flash led current source output b2 vout dcdc converter output capacitor and supply for as3644 - make a short connection to c vout c1 scl serial clock input in i 2 c interface c2 sda serial data input/output for i 2 c interface (needs external pullup resistor)

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www.austriamicrosystems.com/as3644 1.2.2 3 - 23 as3644 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other cond itions beyond those indicated in table 3, ?electrical characteristics,? on page 4 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments vout, sw to gnd -0.3 +7.0 v scl, sda, led_out to gnd -0.3 vout+ 0.3 vmax. +7v vout to sw -0.3 v note: diode between vout and sw input pin current without causing latchup -100 +100 +i in ma norm: eia/jesd78 continuous power dissipation (t a = +70oc) continuous power dissipation 530 mw p t 1 at 70oc ambient 1. depending on actual pcb layout and pcb used; for peak power dissipation during flashing see document 'as3644 thermal measurements' continuous power dissipation derating factor 7.2 mw/oc p derate 2 2. p derate derating factor changes the total continuous power dissipation (p t ) if the ambient te mperature is not 70oc. therefore for e.g. t amb =85oc calculate p t at 85oc = p t - p derate * (85oc - 70oc) electrostatic discharge esd hbm 2000 v norm: jedec jesd22-a114f esd cdm 500 v norm: jedec jesd 22-c101c esd mm 100 v norm: jedec jesd 22-a115-a level a temperature ranges and storage conditions junction temperature +150 oc internally limited (overtemperature protection) max. 20000s storage temperature range -55 +125 oc humidity 5 85 % non condensing body temperature during soldering +260 oc according to ipc/jedec j-std-020 ams ag technical content still valid
www.austriamicrosystems.com/as3644 1.2.2 4 - 23 as3644 datasheet - electrical characteristics 6 electrical characteristics v vin = +2.7v to +5.5v, t amb = -30oc to +85oc, unless otherwise specified. typical values are at v vin = +3.7v, t amb = +25oc, unless otherwise specified. table 3. electrical characteristics symbol parameter condition min typ max unit general operating conditions v vin supply voltage 2.7 3.7 4.5 v v vinreduce d_func supply voltage as3644 functionally working, but not all parameters fulfilled 1 2.5 5.0 v i shutdown shutdown current scl=l, sda=l, v vin <3.7v, 0oc < t amb < 50oc 0.5 1.0 a i stanby standby current interface active, v vin <3.7v 0.5 5 a t amb operating temperature -30 25 85 oc dcdc step up converter v vout dcdc boost output voltage (pin vout) for high supply voltages the output voltage can reach up to v voutmax (the as3644 always runs in pwm mode unless v vout >v voutmax or during startup) 2.8 4.7 v eta efficiency i led_out =300ma,v vout =4.2v 82 % f clk operating frequency all internal timings are derived from this oscillator -7.5% 4.0 +7.5% mhz dcdc operating frequency for short pulses (close to 100% operating mode) -7.5% 1.0 +7.5% current source i led_out led_out current source output 51.6 320 ma i led_out ? led_out current source accuracy i led_out =300ma or 72.3ma -7 +7 % i led_out ramp led_out ramp time at i led_out =300ma ramp-up during startup 0.6 1.0 ms ramp-down after as3644 is disabled by interface 0.2 0.7 ms i led_out ripple led_out current ripple i led_out = 300ma 10 ma pp v iled_comp led_out current source voltage compliance minimum voltage between pin vout and led_out for operation of the current source 210 350 mv protection and fault detection functions (see page 9) v voutmax v vout overvoltage protection dcdc converter overvoltage protection 5.0 5.25 5.5 v i limit current limit for coil l dcdc (pin sw) measured at 50% pwm duty cycle 2 maximum 40000s lifetime operation in overcurrent limit 0.7 0.8 0.9 a v ledshort flash led short circuit detection voltage voltage measured on pin led_out 1.45 1.65 v ams ag technical content still valid
www.austriamicrosystems.com/as3644 1.2.2 5 - 23 as3644 datasheet - electrical characteristics t ovtemp overtemperature protection junction temperature 144 oc t ovtemphy st overtemperature hysteresis 5oc t flashtimer flash timer can be adjusted by register flash_timer (see page 16) -7.5% 30 to 480 +7.5% ms v uvlo undervoltage lockout 3 falling v vin 2.3 2.4 2.5 v rising v vin v uvlo +0.05 v uvlo +0.1 v uvlo +0.15 v digital interface v ih high level input voltage pins scl, sda 4 1.26 v vin - 0.2 v v il low level input voltage 0.0 0.54 v v ol low level output voltage pin sda with pullup >1k ? to digital supply <2v, v vin >2.7v 0.3 v i 2 c interface timings - see figure 3 on page 6 t wakeup wakeup time minimum time from sda or scl going high to first i 2 c start command 500 s t timeout i 2 c timeout time in flash, assist light and indicator mode if scl and sda are l for t timeout , the as3644 enters automatically shutdown mode 35 ms f sclk scl clock frequency 1/ t timeo ut 400 khz t buf bus free time between a stop and start condition 1.3 s t hd:sta hold time (repeated) start condition 5 0.6 s t low low period of scl clock 1.3 s t high high period of scl clock 0.6 s t su:sta setup time for a repeated start condition 0.6 s t hd:dat data hold time 6 00 . 9 s t su:dat data setup time 7 100 ns t r rise time of both sda and scl signals 20 + 0.1c b 300 ns t f fall time of both sda and scl signals 20 + 0.1c b 300 ns t su:sto setup time for stop condition 0.6 s c b capacitive load for each bus line c b ? total capacitance of one bus line in pf 400 pf table 3. electrical characteristics (continued) symbol parameter condition min typ max unit ams ag technical content still valid
www.austriamicrosystems.com/as3644 1.2.2 6 - 23 as3644 datasheet - electrical characteristics timing diagrams figure 3. i 2 c interface timing diagram c i/o i/o capacitance (sda, scl) 10 pf 1. limited to max. 5v due to over voltage protection circuit on pin vout 2. due to slope compensation of the current limit, i limit changes with duty cycle - see figure 16 on page 9 . 3. due to the architecture (the supply of the as3644 is connected to the output vout), the undervoltage lockout is only detected when the dcdc converter is not switching 4. the logic input levels v ih and v il allow for 1.8v supplied driving circuit (70%/30% of 1.8v) 5. after this period, the first clock pulse is generated. 6. a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. 7. a fast-mode device can be used in a stand ard-mode system, but the requirement t su:dat = to 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max + t su:dat = 1000 + 250 = 1250ns before the scl line is released. table 3. electrical characteristics (continued) symbol parameter condition min typ max unit scl sda t buf t hd:sta t su:sta repeated start t su:sto t f t su:dat t high t hd:dat t r t low t hd:sta start stop ams ag technical content still valid
www.austriamicrosystems.com/as3644 1.2.2 7 - 23 as3644 datasheet - typical operating characteristics 7 typical operating characteristics v vin = 3.7v, t a = +25oc (unless otherwise specified) figure 4. dcdc efficiency vs. v vin figure 5. application efficiency (p led /p vin ) vs. v vin 50 55 60 65 70 75 80 85 90 95 100 2,7 3,1 3,5 3,9 4,3 input voltage (v) dcdc efficiency (%) iout = 50ma iout = 12 0ma iout = 220ma iout = 320ma 50 55 60 65 70 75 80 85 90 2,7 3,1 3,5 3,9 4,3 input voltage (v) efficiency pled/pvin (%) iout = 50ma iout = 12 0ma iout = 220ma iout = 320ma figure 6. i led startup (i led_out =300ma) figure 7. i vin startup (i led_out =300ma) 250s/div i led_out 100ma/div 1v/div v vin ,v led_out ,v out 250s/div i vin 100ma/div 1v/div v vin ,v led_out ,v out figure 8. i led startup (i led_out = 51.6 ma) figure 9. vout / i led_out ripple, i led_out = 300ma 50s/div i led_out 20ma/div 1v/div v vin ,v led_out ,v out 100ns/div i led_out 20ma/div 50mv/div v led_out ams ag technical content still valid
www.austriamicrosystems.com/as3644 1.2.2 8 - 23 as3644 datasheet - typical operating characteristics figure 10. i led rampdown (i led_out =300ma) figure 11. i led_out linearity of current sink 250s/div i led_out 100ma/div 1v/div v vin ,v led_out ,v out 0 50 100 150 200 250 300 350 0 0,4 0,8 1,2 1,6 2 2,4 vout-led_out (v) iled_out (ma) iout = 50 ma iout = 120 ma iout = 220ma iout = 320ma figure 12. i led_out vs. t amb figure 13. oscillator frequency f clk vs. t amb 318 319 320 321 -30 -10 10 30 50 70 ambient temperature (c) iled_out (ma) 3,90 3,92 3,94 3,96 3,98 4,00 -30 -10 10 30 50 70 ambient temperature (c) frequency (mhz ) figure 14. dcdc f clk change 4mhz->1mhz(300ma) figure 15. dcdc f clk change 4mhz->1mhz(51ma) 5s/div v led_out, v out 100ma/div 1v/div i sw 5s/div v led_out, v out 50ma/div 1v/div i sw ams ag technical content still valid
www.austriamicrosystems.com/as3644 1.2.2 9 - 23 as3644 datasheet - detailed description 8 detailed description the as3644 is a high performance dcdc step up converter with internal pmos and nmos switches. the switching frequency of 4mhz allows the use of tiny coils. its output is connected to a flash led by an internal current source. the as3644 is controlled by an i 2 c interface. all timings and currents can be accurately adjusted by this interface. it support following operating modes: 1. flash mode (enabled by mode =11): the led current (260ma...320ma) is defined by register flash_current . a timer defines the output flash dura- tion (30ms...480ms in 30ms steps defined by register flash_timer ). the flash is started immediately after the end of the i 2 c command. if scl and sda are l for more than t timeout , shutdown mode is automatically entered. 2. assist light mode (=video or torch light mode) (enabled by mode =10): the led current (51.6ma or 72.3m a) is defined by register assist_current . the current is enabled until another mode is chosen by the interface. if scl and sda are l for more than t timeout , shutdown mode is automatically entered. 3. shutdown mode ( mode =00), scl=0v, sda=0v: the dcdc and the current source is disabled and t he as3644 is configured to draw minimum current. internal circuit the as3644 includes a fixed frequency dcdc step-up with accura te startup control. together with the output current source (on led_out) it includes protection and safety fu nctions as shown in the following internal blockdiagram: figure 16. as3644 internal circuit the dcdc converter always operates in pwm mode (exception: pfm mode is allowed during startup) to reduce emi in emi sensitive systems. for flash and assist light mode and high duty cycles close to 100% on-time (maximum duty cycle) of the pmos, the dcdc converter can switch into a 1mhz operating mode and maximum duty cycle to improve efficiency for this load condition. the dcdc converter returns back to its normal 4mhz operating frequency when load or supply conditions change. due to this switching between two fixed frequencies the noise spectrum of the system is exactly defined and predictable. if improved efficiency is r equired, the fixed switching between 1mhz / 4mhz can be disabled by freq_switch_on (see page 15) =0. in this case pulseskip will be used. the internal circuit for switching between these two frequencies is shown in figure 17 :

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www.austriamicrosystems.co m/as3644 1.2.2 10 - 23 as3644 datasheet - detailed description figure 17. internal circuit of 4mhz/1mhz selection external strobe input to start the flash operation by an hardware input using an external strobe input, use schematic shown in figure 18 : figure 18. external strobe input to enable this function, program the flash time r with the exact flash duration (by programming flash_timer ) and set external_strobe =1. the as3644 waits for an external strobe signal on pin led_out and starts the flash pulse with a duration defined by flash_timer . protection and fault detection functions the protection functions protect the as3644 and the led(s) against physical damage. in most cases a register bit is set, which can be readout with the inte rface. the fault bits are cleared 1 by a readout of the fault register. 1. except overtemperature protection bit fault_overtemp : this bit can be cleared once the temperature drops below t ovtemp -t ovtemphyst .

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www.austriamicrosystems.co m/as3644 1.2.2 11 - 23 as3644 datasheet - detailed description dcdc overvoltage protection in case of no or a broken led at the pin led_out and an enabled dcdc converter, the voltage on vout rises until it reaches v voutmax (overvoltage condition) and the voltage across the current source does not reach regulation (vout-v led < v iled_comp ). if this condition is detected, the dcdc c onverter is stopped, the current sources are dis- abled and the bit fault_ovp (see page 17) is set. dcdc broken coil detection if the coil l dcdc is broken, the as3644 is not powered by the pin sw connected to vout by t he internal switch. due to the protection diodes between scl to vout and sda to vout, the as3644 can be powered through these diodes. the as3644 detects this error condition by comparing the vo ltage on scl and vout. if the voltage on vout is lower compared to the voltage on scl, the as3644 will ignore any i 2 c write commands. therefore the application can simply detect this condition. note: due to the broken coil detection, the high levels of sda and scl should be always below the supply voltage. led short circuit protection after the startup of the dcdc converter, the voltage on led_out is continuously monitored and compared against v ledshort . if the voltage stays below v ledshort , the dcdc is stopped (as a shorted led is assumed), the current sources are disabled and the bit fault_led_short (see page 17) is set. overtemperature protection the junction temperature of the as3644 is contin uously monitored. if the temperature exceeds t ovtemp , the dcdc is stopped, the current sources are disabled and the bit fault_overtemp (see page 17) is set. the driver cannot be re- enabled unless the junction temperature drops below t ovtemp -t ovtemphyst . flash timer the duration of the flash is defined by the register flash_timer (see page 16) . after the timer expires, the dcdc is stopped and the flash current source (on pin led_out) is disabled. supply undervoltage protection if the voltage on the pin vout (=battery voltage) is or falls below v uvlo , the as3644 is kept in shutdown state and in all registers are set to their default state. note: during operation of the dcdc converter, the supply under voltage protection will still monitor the dcdc output voltage only. therefore the supply undervoltage protec tion will only monitor the battery voltage if the dcdc converter is switched off and the output capa citor is discharged down to the supply voltage. wakeup circuit - power off detection in flash, assist light and indicator mode , if scl and sda are l for more than t timeout , shutdown mode is automatically entered. this feature aut omatically detects a power-off of the controlling circuit driving scl and sda. i 2 c serial data bus the as3644 supports the i 2 c bus protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are referred to as slaves. a master device that generates the serial clock (s cl), controls the bus access, and generates the start and stop conditions must control the bus. the as3644 operates as a slave on the i 2 c bus. within the bus specifications a standard mode (100khz maximum clock rate) and a fast mode (400khz maximum clock rate) are defined. the as3644 works in both modes. connections to the bus are made through the open-drain i/o lines sda and scl. the following bus protocol has been defined ( figure 19 ): ?? data transfer may be initiated only when the bus is not busy. ?? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high are interpreted as control signals. accordingly, the following bus conditions have been defined: ams ag technical content still valid
www.austriamicrosystems.co m/as3644 1.2.2 12 - 23 as3644 datasheet - detailed description bus not busy both data and clock lines remain high. start data transfer a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. data valid the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line mu st be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and te rminated with a stop condition. the number of data bytes transferred between start and stop conditions are not li mited, and are determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line duri ng the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. figure 19. data transfer on i 2 c serial bus depending upon the state of the r/w bit, two types of data transfer are possible: 1. data transfer from a master transmitter to a slave receiver. the first byte transmitt ed by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. data is transferred with the most significant bit (msb) first. 2. data transfer from a slave transmitter to a master receiver. the master transmits the first byte (the slave address). the slave then returns an acknowledge bit, followed by the slave transmitting a number of data bytes. the master returns an acknowledge bit after all rece ived bytes other than the la st byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses slave address acknowledgement signal from receiver acknowledgement signal from receiver repeated if more bytes are transferred stop condition or repeated start condition start condition scl sda msb r/w direction bit ack 1 2 6 78 9 1 2 3-8 89 ams ag technical content still valid
www.austriamicrosystems.co m/as3644 1.2.2 13 - 23 as3644 datasheet - detailed description and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. data is transferred with t he most significant bit (msb) first. the as3644 can operate in the following two modes: 1. slave receiver mode (write mode): serial data and clock are received through sda and scl. after each byte is received an acknowledge bit is transmitted. start and stop conditions are recognized as the begin- ning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit (see figure 20) . the slave address byte is the first byte received after the master generates the start condition. the slave address byte contains the 7-bit as3644 address, which is 0110000, followed by the direction bit (r/w ), which, for a write, is 0. 2 after receiving and decoding the slave address byte the device outputs an acknowledge on the sda lin e. after the as3644 acknowledges the slave address + write bit, the master transmi ts a register address to the as3644. this sets the register pointer on the as3644. the master may then transmit zero or more bytes of data, with the as3644 acknowledging each byte received. the address pointer will increment after each data byte is transferred. the master generates a stop condition to terminate the data write. 2. slave transmitter mode (read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indicates that t he transfer direction is reversed. serial data is transmit- ted on sda by the as3644 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer ( figure 21 and figure 22 ). the slave address byte is the first byte received after the master generates a start condition. the slave address byte contains the 7-bit as3644 address, which is 0110000, followed by the direction bit (r/w), which, for a read, is 1. 3 after receiving and decoding the slave address byte the device outputs an acknowledge on the sda line. the as3644 then begins to transmit data starting with the register address pointed to by the register pointer. if the register pointer is not written to befor e the initiation of a read mode the first address that is read is the last one stored in the register pointer. the as3644 must receive a ?not acknowledge? to end a read. figure 20. data write - slave receiver mode 2. the address for writing to the as3644 is 60h = 01100000b 3. the address for read mode from the as3644 is 61h = 01100001b s 0110000 0 a xxxxxxxx a aa xxxxxxxx xxxxxxxx a xxxxxxxx p s - start a - acknowledge (ack) p - stop data transferred (x + 1 bytes + acknowledge) ams ag technical content still valid
www.austriamicrosystems.co m/as3644 1.2.2 14 - 23 as3644 datasheet - detailed description figure 21. data read (from current po inter location) - slave transmitter mode figure 22. data read (write pointer, then read) - slave receive and transmit s 0110000 1 a xxxxxxxx a aa xxxxxxxx xxxxxxxx na xxxxxxxx p s - start a - acknowledge (ack) p - stop na - not acknowledge (nack) data transferred (x + 1 bytes + acknowledge) note: last data byte is followed by a nack s 0110000 0 a xxxxxxxx a 1 a 0110000 s - start sr - repeated start a - acknowledge (ack) p - stop na - not acknowledge (nack) xxxxxxxx a aa xxxxxxxx xxxxxxxx na xxxxxxxx p sr data transferred (x + 1 bytes + acknowledge) note: last data byte is followed by a nack ams ag technical content still valid
www.austriamicrosystems.co m/as3644 1.2.2 15 - 23 as3644 datasheet - detailed description register description table 4. design info register addr: 0 design info register this register has a fixed id bit bit name default access description 7:0 fixed_id 13h r this is a fixed identificat ion (e.g. to verify the i 2 c communication) table 5. version control register addr: 1 version control register this register defines design versions bit bit name default access description 3:0 version xh r as3644 version number 7:4 reserved xh r reserved - don?t use table 6. current set register addr: 2 current set register this register defines the current settings bit bit name default access description 1:0 reserved 0h r reserved - don?t use 2 freq_switch_on 1r/w exact frequency switching between 4mhz/1mhz for assist and flash modes for operation close to maximum pulsewidth - see figure 17 on page 10 0 pulseskip operation is allowed for all modes - results in better efficiency 1 in flash and assist light mode, the dcdc is running at 4mhz or 1mhz (pulseskip is disabled) - results in improved noise performance 4:3 reserved 10 r reserved - don?t use 5 assist_current 1r/w define the current on pin led_out in assist light mode 0i led_out = 51.6ma 1i led_out = 72.3ma 7:6 flash_current 10 r/w define the current on pin led_out in flash mode 00 i led_out = 260ma 01 i led_out = 280ma 10 i led_out = 300ma 11 i led_out = 320ma ams ag technical content still valid
www.austriamicrosystems.co m/as3644 1.2.2 16 - 23 as3644 datasheet - detailed description table 7. control register addr: 3 control register this register defines the operating mode and different protection functions in i 2 c interface bit bit name default access description 3:0 flash_timer 4h r/w define the duration of the flash timer 0h 30ms 1h 60ms 2h 90ms 3h 120ms 4h 150ms default value 5h 180ms 6h 210ms 7h 240ms 8h 270ms 9h 300ms ah 330ms bh 360ms ch 390ms dh 420ms eh 450ms fh 480ms 5:4 mode 00 r/w as3644 operating mode selection 00 shutdown mode 01 shutdown mode, readout of this register will return 00b 10 assist light mode 1 with assist_current 11 flash mode with duration flash_timer with flash_current 6 reserved 0 r reserved - don?t use 7 external_strobe 2 0r/w external strobe signal from pin led_out 0 no external strobe 1 a flash pulse with current defined by flash_current is triggered on a rising edge on led_out (e.g. due to an external signal pulling it high). at the same time this register is automatica lly cleared. after the flash pulse (duration defined by flash_timer ) the as3644 returns to shutdown mode. note: setting this bit automatically sets mode (see page 16) =11 (flash mode) a ongoing flash started with external_strobe can be stopped by writing ?0? to external_strobe and ?00? to mode. ams ag technical content still valid
www.austriamicrosystems.co m/as3644 1.2.2 17 - 23 as3644 datasheet - detailed description register map 1. torch mode and assist light mode share the same operating mode and identical currents. 2. before changing external_strobe register, contact austriamicrosystems to obtain the unlock sequence for this register (needs one additional register writ e access for enabling acce ss to this register). table 8. fault register addr: 4 fault register this register identifies all the di fferent fault condi tions and provide information about the led detection bit bit name default access description 4:0 reserved 0 r reserved - don?t use 5 fault_overtemp 0r see overtemperature protection on page 11 0no fault 1 junction temperature limit has been exceeded 6 fault_led_short 0r see led short circuit protection on page 11 0n o f a u l t 1 a shorted led is detected (pin led_out) 7 fault_ovp 0r see dcdc overvoltage protection on page 11 0n o f a u l t 1 an overvoltage condition is detected (pin vout) table 9. register map register definition addr default content name b7 b6 b5 b4 b3 b2 b1 b0 design info 0 13h fixed_id version control 1 xxh reserved version current set 2 b4h flash_current assist_c urrent reserved freq_swi tch_on reserved control 3 04h external _strobe reserve d mode flash_timer fault 4 00h fault_ov p fault_le d_short fault_ov ertemp reserved ams ag technical content still valid
www.austriamicrosystems.co m/as3644 1.2.2 18 - 23 as3644 datasheet - application information 9 application information the as3644 can be directly connected to an (existing) i 2 c bus (e.g. from the baseband or camera processor). all func- tions are accessible by this interface. external components input capacitor c vin low esr input capacitors reduce input switching noise and reduce the peak current drawn from the battery. ceramic capacitors are required for input decoupling and should be located as close to the device as is practical. if a different input capacitor is chosen , ensure similar esr value and at least 1.6 f capacitance at the maximum input supply voltage. larger capacitor val ues (c) may be used without limitations. output capacitor c vout low esr capacitors should be used to minimize vout ripple. multi-layer ceramic capacitors are recommended since they have extremely low esr and are available in small foot prints. the capacitor should be located as close to the device as is practical. x5r dielectric material is recommended due to their ability to maintain capacitance over wide voltage and temperature range. if a different output capacitor is chosen, ensure similar esr values and at least 1.0f capacitance at maximum output voltage. inductor l dcdc the fast switching frequency (4mhz) of the as3644 allows fo r the use of small smds for the external inductor. the inductor should have low dc resistance (dcr) to reduce the i 2 r power losses - high dcr values will reduce effi- ciency. table 10. recommended input capacitor part number c tc code esr rated voltage size manufacturer cl05a395mq5nqkl 4.7f +/-10% >1.6f @ v vin x5r <20m ? 6v3 0402 samsung electro- mechancs www.sem.samsung.co.kr table 11. recommended output capacitor part number c tc code esr rated voltage size manufacturer ecjunbpj155k 2x1.5f +/-15% x5r <10m ? 6v3 0405 2-array panasonic www.panasonic.com cl14a185mq8sakl samsung electro- mechancs www.sem.samsung.co.kr table 12. recommended inductor part number l dcr l @ 0.9a size manufacturer lqm21pn1r0ngc 1.1h 100m ? >0.7h 2x1.25x0.9mm murata www.murata.com elgtea1r0sn 1.0h >0.7h 2x1.25x0.9mm panasonic www.panasonic.com cig21k1r0sce 1.17h 135m ? >0.7h 2x1.25x0.9mm samsung electro- mechancs www.sem.samsung.co.kr ams ag technical content still valid
www.austriamicrosystems.co m/as3644 1.2.2 19 - 23 as3644 datasheet - application information if a different inductor is chosen, ensure similar dcr values and at least 0.7h inductance at 0.9a input current. led use led and optics as re quired by the system. pcb layout guideline the high speed operation requires proper layout for optimum per formance. route the power traces first and try to min- imize the area and wire length of th e two high frequency/high current loops: loop1: c vin - l dcdc - pin sw - pin gnd - c vin loop2: c vin - l dcdc - pin sw - pin vout - c vout - pin gnd - c vin at the pin gnd a single via (or more vias, which are closely combined) connects to the common ground plane. this via(s) will isolate the dcdc high frequency currents from th e common ground (as most high frequency current will flow between loop1 and loop2 and will not pass the ground plane) - see the ?ground via? in figure 23 . figure 23. layout recommendation note: if component placement rules allow, move all components close to the as3644 to reduce the area and length of loop1 and loop2. the recommended pcb pad size for the as3644 is 250m. ckp2012n1r0m 1.0h 110m ? >0.7h 2x1.25x0.9mm taiyo yuden www.t-yuden.com mlp2012l1r0mt 1.0h >0.7h 2x1.25x0.9mm tdk www.tdk.com mdt2012-cr1r0an 1.0h 110m ? >0.7h 2x1.25x0.9mm to k o www.toko.co.jp table 13. recommended leds part number name lumen @ 300ma size manufacturer ceramos luw c9sm ceramos 55 2.04x1.64x0.75mm osram opto semiconductors www.osram-os.com lxcl-pwf3 luxeon pwf3 30 2.04x1.64x0.7mm philips lumileds www.philipslumileds.com table 12. recommended inductor (continued) part number l dcr l @ 0.9a size manufacturer '( )

as3644 ams ag technical content still valid
www.austriamicrosystems.co m/as3644 1.2.2 20 - 23 as3644 datasheet - application information application self testing guideline using the in-build self testing features of the as3644, the errors as shown in figure 24 during the assembling and sol- dering of the as3644, can be detected - this simp lifies and can reduce cost during manufacturing: figure 24. self testing - detecting assembling and soldering errors the self testing procedure is simple: 1. write 0x20 into register 0x03 ( control register) [enable assist light with default 72ma]. 2. read back 4 register 0x03 - must return 0x20, otherwise l dcdc or i 2 c (scl or sda) is broken 3. write 0x00 into re gister 0x03 [power off] 4. read register 0x04 ( fault register) - must return 0x00, ot herwise the led is open or shorted see table 14 to identify the different possible soldering errors: 4. alternative testing method: instead of reading the in ternal registers, the current into the as3644 can be measured. during assist light mode, the supply current must increase by at least 60ma. if an error is detected, the current source and the d cdc is automatically switched off - see protection and fault detec- tion functions on page 10 table 14. how-to identify errors error identified by scl or sda broken writing 0x20 to 0x03 and read back of register 0x03 does not return 0x20 l dcdc broken writing 0x20 to 0x03 and read back of r egister 0x03 does not return 0x20 - see dcdc broken coil detection on page 11 flash led shorted register fault_led_short (see page 17) is set flash led open register fault_ovp (see page 17) is set as3644 ams ag technical content still valid
www.austriamicrosystems.co m/as3644 1.2.2 21 - 23 as3644 datasheet - package drawings and markings 10 package drawings and markings figure 25. 6pin wl-csp marking note: line 1: as3644 line 2:

 encoded datecode (4 characters) figure 26.  6pin wl-csp package dimensions the coplanarity of the balls is 40m. 	

	 	

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 www.austriamicrosystems.co m/as3644 1.2.2 22 - 23 as3644 datasheet - ordering information 11 ordering information the devices are available as the standard products shown in  table 15 . note: AS3644-ZWLT as3644- z temperature range: -30oc - 85oc wl package: wafer level chip scale package (wl-csp) 1.5x1.1x0.6mm t delivery form: tape & reel table 15.  ordering information model description delivery form package AS3644-ZWLT ultra small low cost 320ma inductive white led  flash driver tape & reel 6-pin wl-csp (1.5mm x 1.1mm x 0.6mm) rohs compliant / pb-free  ams  ag  technical  content  still  valid

 www.austriamicrosystems.co m/as3644 1.2.2 23 - 23 as3644 datasheet - ordering information copyrights copyright ? 1997-2011, austriamicrosystems ag, schloss premstaetten, 8141 unterpremstaetten, austria-europe.  trademarks registered ?. all rights reserved. the material herei n may not be reproduced, adapted, merged, trans- lated, stored, or used without the  prior written consent of the copyright owner.  all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing  in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding  the information set  forth herein or regarding the freedom of the described devices from patent infringement. austriami- crosystems ag reserves the right to change specifications a nd prices at any time and  without notice. therefore, prior  to designing this product into a system, it is necessary to  check with austriamicrosystems ag for current information.  this product is intended for use in normal commercial a pplications. applications requiring extended temperature  range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life- sustaining equipment are specifically not recommended without additional  processing by austriamicrosystems ag for  each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the standard  production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag  is believed to be correct  and accurate. however,  austriamicrosystems ag shall not be liable to recipient or  any third party for any damages, in cluding but not limited to  personal injury, property damage, loss of profits, loss of  use, interruption of business or indirect, special, incidental or  consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech- nical data herein. no obligation or liability to recipie nt or any third party shall arise or flow out of  austriamicrosystems ag rendering of technical or other services.  contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 schloss premstaetten a-8141 austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit:  http://www.austriamicrosystems.com/contact  ams  ag  technical  content  still  valid

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