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december 2009 doc id 14454 rev 1 1/12 AN2715 application note ibis models for signal integrity simulation of spear600 applications introduction this application note is int ended for hardware developers that are using the spear600 embedded mpu in their target design. the ibis models are mandatory to run signal integrity simulation in the application pcb. pcb simulation is very important to make sure that the layout of the pcb does not introduce any functional problems or timing marginality in high speed interfaces like ddr2 and ethernet. the ibis models provided for spear600 are organized in a mode l library containing several models for each i/o pin (or for a functional group of i/os). each i/o pin or functional group of i/o has a set of models; each model corresponds to a certain operating mode of the i/o pads. the operating modes are programmable and are defined by a proper setting of two registers, one in the miscellaneous register block and the other one in the memory controller block of the spear600 device (for more details please refer to the miscellaneous registers and memory controller sections of the spear600 user manual). this document explains how to select the correct model from the library sp600_v13.ibs after reading the regist er settings or knowin g the operating mode from the spear600 user manual. note: the registers referred to in this document are described in detail in the spear600 user manual . www.st.com
pl_clk & pl_gpio ibis model selection AN2715 2/12 doc id 14454 rev 1 1 pl_clk & pl_gpio ibis model selection the i/o signals of the pl_clk & pl_gpio interface form two main groups. please refer to the following table for the i/o signals and the associated model name. table 1. relation between the pl_.... block signals and the used model pl_.... block signal name ibis model group name pl_clk[4:1] pl_clk pl_gpio[83:0] pl_gpio
AN2715 gmac ibis model selection doc id 14454 rev 1 3/12 2 gmac ibis model selection the i/o signals of the gmac interface form two main groups. please refer to the following table for the i/o signals and the associated model name. table 2. relation between the gmac block signals and the used model gmac block signal name ibis model group name gmii_txclk gmii_txclk125 mii_txclk txd_0 txd_1 txd_2 txd_3 gmii_txd_4 gmii_txd_5 gmii_txd_6 gmii_txd_7 tx_er tx_en rx_er rx_dv rx_clk rxd_0 rxd_1 rxd_2 rxd_3 gmii_rxd_4 gmii_rxd_5 gmii_rxd_7 gmii_rxd_6 col crs gmac_hf mdio mdc gmac_lf
smi ibis model selection AN2715 4/12 doc id 14454 rev 1 3 smi ibis model selection the i/o signals of the smi interface form two main groups. please refer to the following table for the smi interface i/o signals and the associated model name. table 3. relation between the smi block signals and the used model smi block signal name ibis model group name smi_clk smidatain smidataout smics_0 smics_1 pl_gpio
AN2715 lvds ibis model selection doc id 14454 rev 1 5/12 4 lvds ibis model selection the i/o signals of the lvds interface form two main groups. please refer to the following table for the i/o signals and the associated model name. table 4. relation between the lvds block signals and the used model lv d s b l o ck signal name ibis model group name ph0 ph0n ph1 ph1n ph2 ph2n ph3 ph3n ph4 ph4n ph5 ph5n ph6 ph6n ph7 ph7n lvds_out ph8 ph8n lv d s _ i n
ddr ibis model selection AN2715 6/12 doc id 14454 rev 1 5 ddr ibis model selection the i/o signals of the ddr interface form three main groups. each group has one set of models associated. please refer to the following table for the i/o signals and the assocated model names. each model group name contains a set of models depending upon the value of the 8 bits [b7:b0] for ddr_diff and 7 bits [b7:b3 & b1:b0] for ddr_g_ sig and ddr_v_sig. in order to determine the value of these 7 or 8 bits, refer to the user manual of the spear600 device for the fo llowing register names: sstlpad_cfg_ctr mem11_ctl table 5. relation between the ddr block signals and the used model ddr block signal name ibis model group name ddr_clkp & ddr_clkn ddr_dqs_0 & ddr_ndqs_0 ddr_dqs_1 & ddr_ndqs_1 ddr_diff_[b7:b0] = ddr_diff_xxxxxxxx ddr_add[14,12,10,8,6,4,2,0] ddr_data[15,13 ,11,9,6,4,2,0] ddr_gate_0 ddr_dm_1 ddr_clken ddr_cs_1 ddr_odt_1 ddr_ba_1 ddr_cas ddr_g_sig_[b7:b3 & b1:b0] = ddr_g_sig_xxxxxxx see note (1) 1. the b2 bit is not present. ddr_add[13,11,9,7,5,3,1] ddr_data[14,12 ,10,8,7,5,3,1] ddr_gate_1 ddr_dm_0 ddr_cs_0 ddr_odt_0 ddr_ba_0 ddr_ba_2 ddr_ras ddr_we ddr_v_sig_[b7:b3 & b1:b0] = ddr_v_sig_xxxxxxx see note (1)
AN2715 ddr ibis model selection doc id 14454 rev 1 7/12 the correlation between bits 0-8 (or 0-7) of the model group names and the bits of each register is given below: register sstlpad_cfg_ctr (address 0xfca800f0). b7 = sstlpad_cfg_ctr [15] = dram_type (1 = ddr2 interface) b6 = sstlpad_cfg_ctr [3] = drive_mode_s_w (1 = weak drive strength) b5 = sstlpad_cfg_ctr [2] = prog_a (slope of the signals. 00 = slower slope) b4 = sstlpad_cfg_ctr [1] = prog_b (slope of the signals. 11 = higher slope) b3 = internal level forced to zero. b2 = two cases: ? internal level forced to zero for clkp or clkn signals. ? sstlpad_cfg_ctr [12] = pseudo_dif_ this is the bit register value for the signals dqs & ndqs (0 = diff. sig.). register mem11_ctl [1:0] (address 0xfc60002c) = rtt_pad_terminat[1:0]. the following table is for the dqs, ndqs and dq signals only. for all the other signals b1 = b0 = 0 (no odt). note: ?-? means ?don?t care?. 5.1 example the setting of the registers sstlpad_cfg_ctr and mem11_ctl is normally done at each system boot-up by the xloader part of the boot code. let?s assume, as an example, that at the end of the boot operation the application reads these two registers and finds the following values: register sstlpad_cfg_ctr (add ress 0xfca800f0) = 0x0000eaad. register mem11_ctl register (a ddress 0xfc60002c) = 0x03000002. the correct model to be selected from the library with the above values is the following: table 6. dqs, ndqs and dq on die termination (odt) mem11_ctl [1] mem11_ctl [0] b1 b0 description 000- odt disabled 0 1 1 1 odt= 75 ohm 1 0 1 0 odt = 150 ohm 11 reserved table 7. example of relation betw een ddr block signals and the used model ddr block signal name ibis mo del used for application board ddr_clkp & ddr_clkn ddr_diff_[b7:b0] = ddr_diff_ 1 110 0000 ddr_dqs_0 & nddr_dqs_0 ddr_dqs_1 & nddr_dqs_1 if read => ddr_diff_[b7:b0] = ddr_diff_ 1 110 00 10 if write => ddr_diff_[b7:b0] = ddr_diff_ 1 110 0000
ddr ibis model selection AN2715 8/12 doc id 14454 rev 1 note: in bold the fixed bx bit values for the stm ddr2 application board. ddr_data[15,13, 11,9,6,4,2,0] if read => ddr_g_sig_[b7:b3 & b1:b0] = ddr_g_sig_ 1 110 0 10 if write => ddr_g_sig_[b7:b3 & b1:b0] = ddr_g_sig_ 1 110 000 ddr_add[14,12,10,8,6,4,2,0] ddr_gate_0 ddr_dm_1 ddr_clken ddr_cs_1 ddr_odt_1 ddr_ba_1 ddr_cas ddr_g_sig_[b7:b3 & b1:b0] = ddr_g_sig_ 1 110 000 ddr_data[14,12, 10,8,7,5,3,1] if read => ddr_v_sig_[b7:b3 & b1:b0] = ddr_v_sig_ 1 110 0 10 if write => ddr_v_sig_[b7:b 3 & b1:b0] = ddr_v_sig_ 1 110 000 ddr_add[13,11,9,7,5,3,1] ddr_gate_1 ddr_dm_0 ddr_cs_0 ddr_odt_0 ddr_ba_0 ddr_ba_2 ddr_ras ddr_we ddr_v_sig_[b7:b3 & b1:b0] = ddr_v_sig_ 1 110 000 table 7. example of re lation between ddr block signals and th e used model (continued) ddr block signal name ibis mo del used for application board
AN2715 ddr ibis model selection doc id 14454 rev 1 9/12 figure 1. clkp signal simulation case (for example) with the hyperlynx tool as shown in the above picture, if the simulation tool supports the model selector function, it?s pretty easy to select the right model. when you select the pin name of the package (ball name) to be used in the simulation, the tool points automatically to the signal name and shows the model group name, listing in a window all the models contained in the group. as you can see in the model selector windows, all the models with all t he available combination of the 7 or 8 bits are presented. knowing the operational mode or the content of the two registers explained in the previous paragraph, you can select the right model to be used by the simulation. in this specific example, the selected model is ddr_diff_11100000 there are simulation tools that do not support the model selector function. in this case, you must probably manually remove from the ibis model library all the models with the bit settings that are not used in the simulation, only leaving in the library the models with the combination of bits related to the used operating mode.
usb ibis model selection AN2715 10/12 doc id 14454 rev 1 6 usb ibis model selection all the i/o signals of the usb interface are grouped in one main group. please refer to the following table for the i/o signals and the assocated model names. table 8. relation between the usb block signals and the used model usb block signal name ibis model group name usb_device_dm usb_device_dp usb_host2_dm usb_host2_dp usb_host1_dm usb_host1_dp usb2phy_p3_tx (if transmitter) usb2phy_p3_rx (if receiver)
AN2715 revision history doc id 14454 rev 1 11/12 7 revision history table 9. document revision history date revision changes 04-dec-2009 1 initial release.
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