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this is information on a product in full production. january 2015 docid024752 rev 5 1/31 m93cx6-a125 automotive 16-kbit, 8-kbit, 4-kbit, 2-kbit and 1-kbit (8-bit or 16-bit wide) microwire? serial eeprom datasheet - production data features ? industry standard microwire? bus ? memory array: 1 kb, 2 kb, 4 kb, 8 kb or 16 kb ? dual organization: by word (x16) or byte (x8) ? write ? byte within 4 ms ? word within 4 ms ? ready/busy signal during programming ? 2 mhz clock rate ? sequential read operation ? single supply voltage: 1.8 v to 5.5 v ? operating temperature range: -40 c up to 125 c ? enhanced esd protection ? write cycle endurance ? 4 million write cycles at 25 c ? 1.2 million write cycles at 85 c ? 600 k write cycles at 125 c ? data retention ? 50 years at 125 c ? more than 100 years at 25 c ? packages ? rohs-compliant and halogen-free (ecopack2 ? ) so8 (mn) 150 mil width tssop8 (dw) 169 mil width wfdfpn8 (mf) 2 x 3 mm table 1. device summary reference part number m93cx6-a125 m93c46-a125 m93c56-a125 M93C66-A125 m93c76-a125 m93c86-a125 www.st.com
contents m93cx6-a125 2/31 docid024752 rev 5 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.3 power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.4 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 read data from memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 erase and write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2.1 write enable and write disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2.2 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2.3 write all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.4 ecc (error correction code) and write cycling . . . . . . . . . . . . . . . . . . 15 5.2.5 erase byte or word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.6 erase all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6ready/busy status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 common i/o operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
docid024752 rev 5 3/31 m93cx6-a125 contents 3 12 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 13 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
list of tables m93cx6-a125 4/31 docid024752 rev 5 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. memory size versus organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. instruction set for the m93cx6-a125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. instruction set for the m93c46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. instruction set for the m93c56 and m93c66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. instruction set for the m93c76 and m93c86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. operating conditions (m93cx6-a125) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. input and output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12. cycling performance by byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 13. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 14. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 15. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 16. tssop8 ? 8-lead thin shrink small outline, pa ckage mechanical data. . . . . . . . . . . . . . . . 26 table 17. wfdfpn8 (mlp8) ? 8-lead very thin fine pitch dual flat package no lead 2 x 3 mm, 0.5 mm pitch, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 18. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 19. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
docid024752 rev 5 5/31 m93cx6-a125 list of figures 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. m93cx6-a125 org input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. read, write, wen, wd s sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. wral sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. erase, eral sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. write sequence with one clock g litch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. ac testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. synchronous timing (start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. synchronous timing (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. synchronous timing (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14. tssop8 ? 8 lead thin shrink small outline, pack age outline . . . . . . . . . . . . . . . . . . . . . . . 26 figure 15. wfdfpn8 (mlp8) ? 8-lead very thin fine pitch dual flat package no lead 2 x 3 mm, 0.5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
description m93cx6-a125 6/31 docid024752 rev 5 1 description the m93c46 (1 kbit), m93c56 (2 kbit), m93c66 (4 kbit), m93c76 (8 kbit) and m93c86 (16 kbit) are electrica lly erasable programmable memo ry (eeprom) de vices accessed through the microwire? bus protocol. the memory array can be configured either in bytes (x8b) or in words (x16b). the m93cx6-a125 devices operate within a voltage supply range from 1.8 v to 5.5 v the m93cx6-a125 devices are guaranteed over the -40 c/+125 c temperature range and are compliant with the automotive standard aec-q100 grade 1. figure 1. logic diagram table 2. memory size versus organization device number of bits number of 8-bit bytes number of 16-bit words m93c86 16384 2048 1024 m93c76 8192 1024 512 m93c66 4096 512 256 m93c56 2048 256 128 m93c46 1024 128 64 table 3. signal names signal name function direction s chip select input d serial data input input q serial data output output c serial clock input org organization select input v cc supply voltage - v ss ground - !) $ 6 ## -#x 6 33 # 1 3 /2'
docid024752 rev 5 7/31 m93cx6-a125 description 30 the m93cx6-a125 is accessed by a set of instructions, as summarized in table 4 , and in more detail in table 5: instruction set for the m93c46 to table 7: instruction set for the m93c76 and m93c86 ). a read data from memory (read) instruction loads the address of the first byte or word to be read in an internal address register. the dat a at this address is then clocked out serially. the address register is automatically incremented after the data is output and, if chip select input (s) is held high, the m93cx6-a125 can output a sequential stream of data bytes or words. in this way, the memory can be read as a data stream from eight to 16384 bits long (in the case of the m93c86), or continuously (the address counter automatically rolls over to 00h when the highest address is reached). programming is internally self-timed (the external clock signal on serial clock (c) may be stopped or left running after the start of a wr ite cycle) and does not require an erase cycle prior to the write instruct ion. the write instruction writes 8 or 16 bits at a time into one of the byte or word locations of the m93cx6-a125. after the start of the programming cycle, a busy/ready signal is available on serial data output (q) when chip select input (s) is driven high. an internal power-on data protection mechanism in the m93cx6-a125 inhibits the device when the supply is too low. figure 2. 8-pin package connections (top view) 1. see section 12: package mechanical data for package dimensions, and how to identify pin-1. 2. du = don?t use. the du (do not use) pin does not co ntribute to the normal operation of the device. it is reserved for use by stmicroelectronics during test sequences. the pin may be left unconnected or may be connected to v cc or v ss . table 4. instruction set for the m93cx6-a125 instruction description data read read data from memory byte or word write write data to memory byte or word wen write enable - wds write disable - erase erase byte or word byte or word eral erase all memory - wral write all memory with same data - 6 33 1 /2' $5 # 36 ## $ !)" -#x
connecting to the serial bus m93cx6-a125 8/31 docid024752 rev 5 2 connecting to the serial bus figure 3 shows an example of three memory devices connected to an mcu, on a serial bus. only one device is selected at a time, so only one device drives the serial data output (q) line at a time, the other devices are high impedance. the pull-down resistor r (represented in figure 3 ) ensures that no device is selected if the bus master leaves the s line in the high impedance state. in applications where the bus master may be in a state where all inputs/outputs are high impedance at the same time (for example, if the bus master is reset during the transmission of an instruction), the clock line (c) must be connected to an external pull-down resistor so that, if all inputs/outputs become high impedanc e, the c line is pulled low (while the s line is pulled low): this ensures that c does not become high at the same time as s goes low, and so, that the t slch requirement is met. the typical value of r is 100 k . figure 3. bus master and memory devices on the serial bus !)b "usmaster -xxx memorydevice 3$/ 3$) 3#+ #1$ 3 -xxx memorydevice #1$ 3 -xxx memorydevice #1$ 3 #3 #3 #3 /2' /2' /2' 22 2 6 ## 6 ## 6 ## 6 ## 6 33 6 33 6 33 6 33 2
docid024752 rev 5 9/31 m93cx6-a125 operating features 30 3 operating features 3.1 supply voltage (v cc ) 3.1.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied. in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid unt il the end of the transmission of the instruction and, for a write instructio n, until the completion of the internal write cycle (t w ). 3.1.2 power-up conditions when the power supply is turned on, v cc rises from v ss to v cc . during this time, the chip select (s) line is not allowed to float and should be driven to v ss , it is therefore recommended to connect the s line to v ss via a suitable pull-down resistor. 3.1.3 power-up and device reset in order to prevent inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up (continuous rise of v cc ), the device does not respond to any instruction until v cc has reached the power on reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in operating conditions, in section 11: dc and ac parameters ). when v cc passes the por threshold, the device is reset and is in the following state: ? standby power mode ? deselected (assuming that there is a pull-down resistor on the s line) 3.1.4 power-down at power-down (continuous decrease in v cc ), as soon as v cc drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any inst ruction sent to it. during power-down, the device must be deselected and in the standby power mode (that is, there should be no internal write cycle in progress).
memory organization m93cx6-a125 10/31 docid024752 rev 5 4 memory organization the m93cx6-a125 memory is organized either as bytes (x8) or as words (x16). if organization select (org) is left unconnected (or connected to v cc ) the x16 organization is selected; when organization select (org) is connected to ground (v ss ) the x8 organization is selected. when the m93cx6-a125 is in standby mode, organization select (org) should be set either to v ss or v cc to reach the device minimum power consumption (as any voltage between v ss and v cc applied to org input ma y increase the device standby current). figure 4. m93cx6-a125 org input connection 06y9 9ff 25* 9vv 9ff 25* 9vv 9ff 25* 9vv 1rw frqqhfwhg [rujdql]dwlrq [rujdql]dwlrq [rujdql]dwlrq
docid024752 rev 5 11/31 m93cx6-a125 instructions 30 5 instructions the instruction set of the m93cx6-a125 de vices contains seven instructions, as summarized in table 5 to table 7 . each instruction consists of the following parts, as shown in figure 5: read, write, wen, wds sequences : ? each instruction is preceded by a rising edge on chip select inpu t (s) with serial clock (c) being held low. ? a start bit, which is the first ?1? read on se rial data input (d) during the rising edge of serial clock (c). ? two op-code bits, read on serial data input (d) during the rising edge of serial clock (c). (some instructions also use the first two bits of the address to define the op-code). ? the address bits of the byte or word th at is to be accessed. for the m93c46, the address is made up of 6 bits for the x16 org anization or 7 bits for the x8 organization (see table 5 ). for the m93c56 and m93c66, the address is made up of 8 bits for the x16 organization or 9 bits for the x8 organization (see table 6 ). for the m93c76 and m93c86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8 organization (see table 7 ). the m93cx6-a125 devices are fabricated in cm os technology and are therefore able to run as slow as 0 hz (static input signals) or as fast as the maximum ratings specified in ?ac characteristics? tables, in section 11: dc and ac parameters . table 5. instruction set for the m93c46 instruction description start bit op- code x8 origination (org = 0) x16 origination (org = 1) address (1) data required clock cycles address (1) data required clock cycles read read data from memory 1 10 a6-a0 q7-q0 - a5-a0 q15-q0 - write write data to memory 1 01 a6-a0 d7-d0 18 a5-a0 d15-d0 25 wen write enable 1 00 11x xxxx - 10 11 xxxx - 9 wds write disable 1 00 00x xxxx - 10 00 xxxx - 9 erase erase byte or word 1 11 a6-a0 - 10 a5-a0 - 9 eral erase all memory 1 00 10x xxxx - 10 10 xxxx - 9 wral write all memory with same data 100 01x xxxx d7-d0 18 01 xxxx d15-d0 25 1. x = don't care bit.
instructions m93cx6-a125 12/31 docid024752 rev 5 table 6. instruction set for the m93c56 and m93c66 instruction description start bit op- cod e x8 origination (org = 0) x16 origination (org = 1) address (1) (2) data required clock cycles address (1) (3) data required clock cycles read read data from memory 1 10 a8-a0 q7- q0 -a7-a0 q15- q0 - write write data to memory 1 01 a8-a0 d7- d0 20 a7-a0 d15-d0 27 wen write enable 1 00 1 1xxx xxxx -12 11xx xxxx -11 wds write disable 1 00 0 0xxx xxxx -12 00xx xxxx -11 erase erase byte or word 1 11 a8-a0 - 12 a7-a0 - 11 eral erase all memory 1 00 1 0xxx xxxx -12 10xx xxxx -11 wral write all memory with same data 100 0 1xxx xxxx d7- d0 20 01xx xxxx d15-d0 27 1. x = don't care bit. 2. address bit a8 is not decoded by the m93c56. 3. address bit a7 is not decoded by the m93c56. table 7. instruction set for the m93c76 and m93c86 instruction description start bit op- code x8 origination (org = 0) x16 origination (org = 1) address (1)(2) data required clock cycles address (1) (3) data required clock cycles read read data from memory 1 10 a10-a0 q7-q0 - a9-a0 q15-q0 - write write data to memory 1 01 a10-a0 d7-d0 22 a9-a0 d15-d0 29 wen write enable 1 00 11x xxxx xxxx -14 11 xxxx xxxx -13 wds write disable 1 00 00x xxxx xxxx -14 00 xxxx xxxx -13 erase erase byte or word 1 11 a10-a0 - 14 a9-a0 - 13 eral erase all memory 1 00 10x xxxx xxxx -14 10 xxxx xxxx -13 wral write all memory with same data 100 01x xxxx xxxx d7-d0 22 01 xxxx xxxx d15-d0 29 1. x = don't care bit. 2. address bit a10 is not decoded by the m93c76. 3. address bit a9 is not decoded by the m93c76.
docid024752 rev 5 13/31 m93cx6-a125 instructions 30 5.1 read data from memory the read data from memory (read) instruction outputs data on serial data output (q). when the instruction is receiv ed, the op-code and address are decoded, and the data from the memory is transferre d to an output shift register. a du mmy 0 bit is output first, followed by the 8-bit byte or 16-bit wo rd, with the most significant bit first. output data changes are triggered by the rising edge of serial clock (c). the m93cx6-a125 automatically increments the internal address register and clocks out the next byte (or word) as long as the chip select input (s) is he ld high. in this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read (the address counter automatically rolls over to 00h when the highest address is reached). 5.2 erase and write data 5.2.1 write enable and write disable the write enable (wen) instruction enables the future execution of erase or write instructions, and the write disable (wds) inst ruction disables it. when power is first applied, the m93cx6-a125 initializes itself so that erase an d write instructions are disabled. after a write enable (wen) in struction has been executed, erasing and writing remains enabled until a write disable (wds) instruction is executed, or until v cc falls below the power-on reset threshold voltage. to protec t the memory contents from accidental corruption, it is advisable to issue the writ e disable (wds) instruction after every write cycle. the read data from memo ry (read) instruction is not affected by the write enable (wen) or write disable (wds) instructions. 5.2.2 write for the write data to memory (write) instructio n, 8 or 16 data bits follow the op-code and address bits. these form the byte or word that is to be written. as with the other bits, serial data input (d) is sampled on the rising edge of serial clock (c). after the last data bit has been sampled, the chip select input (s) must be taken low before the next rising edge of serial clock (c). if chip select input (s) is brought low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. the completion of the cycle can be detected by monitoring the ready/ busy line, as described la ter in this document. once the write cycle has been started, it is inte rnally self-timed (the ex ternal clock signal on serial clock (c) may be stopped or left running after the start of a write cycle). the write cycle is automatically preceded by an erase cycle, so it is unnecessary to execute an explicit erase instruction before a writ e data to memory (write) instruction.
instructions m93cx6-a125 14/31 docid024752 rev 5 figure 5. read, write, wen, wds sequences 1. for the meanings of an, xn, qn and dn, see table 5 , table 6 and table 7 . !)d !n ! 1n 1 $!4!/54 $ 3 1 2ead 3 7rite !$$2 /0 #/$% !n ! $!4!). $ 1 /0 #/$% $n $ "539 2%!$9 3 7rite %nable 8n8 $ /0 #/$% 3 7rite $isable 8n8 $ /0 #/$% #(%#+ 34!453 !$$2
docid024752 rev 5 15/31 m93cx6-a125 instructions 30 5.2.3 write all as with the erase all memory (eral) instruct ion, the format of the write all memory with same data (wral) instruction requires that a dummy address be provided. as with the write data to memory (write) instruction, th e format of the write all memory with same data (wral) instruction requires that an 8-bit data byte, or 16-bit data word, be provided. this value is written to all the addresses of the memory device. the co mpletion of the cycle can be detected by monitoring the ready/ busy line, as described next. figure 6. wral sequence 1. for the meanings of xn and dn, please see table 5 , table 6 and table 7 . 5.2.4 ecc (error correction code) and write cycling the devices identified with the process letter ?k? embed an error correction code (ecc) internal logic function whic h is transparent for the microwire communication protocol. the ecc logic is implemented on each byte. !)# 3 72)4% !,, $!4!). $ 1 !$$2 /0 #/$% $n $ "539 2%!$9 #(%#+ 34!453 8n 8
instructions m93cx6-a125 16/31 docid024752 rev 5 5.2.5 erase byte or word the erase byte or word (erase) instruction sets the bits of the addressed memory byte (or word) to 1. once the address has been correctly decoded, the falling edge of the chip select input (s) starts the self-timed eras e cycle. the completion of the cycle can be detected by monitoring the ready/ busy line, as described in section 6: ready/busy status . figure 7. erase, eral sequences 1. for the meanings of an and xn, please see table 5 , table 6 and table 7 . 5.2.6 erase all the erase all memory (eral) instruction erases the whole memory (all memory bits are set to 1). the format of the instruction requires that a dummy address be provided. the erase cycle is conducted in the same way as the erase instructi on (erase). the completion of the cycle can be detected by monitoring the ready/ busy line, as described in section 6: ready/busy status . !)" 3 %2!3% $ 1 !$$2 /0 #/$% "539 2%!$9 #(%#+ 34!453 3 %2!3% !,, $ 1 /0 #/$% "539 2%!$9 #(%#+ 34!453 !n ! 8n 8 !$$2
docid024752 rev 5 17/31 m93cx6-a125 ready/busy status 30 6 ready/busy status while the write or erase cycle is underw ay, for a write, eras e, wral or eral instruction, the busy signal (q=0) is returned whenever chip select inpu t (s) is driven high. (please note, though, that there is an initial delay, of t slsh , before this status information becomes available). in this state, the m93cx6 -a125 ignores any data on the bus. when the write cycle is completed, and chip select in put (s) is driven high, the ready signal (q=1) indicates that the m93cx6-a125 is ready to rece ive the next instruction. serial data output (q) remains set to 1 until the ch ip select input (s) is brought low or until a new start bit is decoded. 7 initial delivery state the device is delivered with all bits in the me mory array set to 1 (each byte contains ffh). 8 common i/o operation serial data output (q) and serial data input (d) can be connected together, through a current limiting resistor, to form a common, sing le-wire data bus. some precautions must be taken when operating the memory in this way, mostly to prevent a short circuit current from flowing when the last address bit (a0) clashes wi th the first data bit on serial data output (q). please see the application note an394 for details.
clock pulse counter m93cx6-a125 18/31 docid024752 rev 5 9 clock pulse counter in a noisy environment, the number of pulses received on serial clock (c) may be greater than the number delivered by the master (the microcontroller). this can lead to a misalignment of the instruction of one or more bits (as shown in figure 8 ) and may lead to the writing of erroneous data at an erroneous address. to avoid this problem, the m93cx6-a125 has an on-chip counter that counts the clock pulses from the start bit until the falling edge of the chip sele ct input (s). if the number of clock pulses received is no t the number expected, the wr ite, erase, eral or wral instruction is aborted, and the conten ts of the memory are not modified. the number of clock cycles expected for ea ch instruction, and for each member of the m93cx6-a125 family, are summarized in table 5: instruction set for the m93c46 to table 7: instruction set for the m93c76 and m93c86 . for example, a write data to memory (write) instruction on the m93c56 (or m93c66) expects 20 clock cycles (for the x8 organization) from the start bit to the falling edge of chip select input (s). that is: 1 start bit + 2 op-code bits + 9 address bits + 8 data bits figure 8. write sequence with one clock glitch !) 3 !n # $ 72)4% 34!24 $ !n 'litch !n !$$2%33!.$$!4! !2%3()&4%$"9/.%")4
docid024752 rev 5 19/31 m93cx6-a125 maximum ratings 30 10 maximum ratings stressing the device outside the ratings liste d in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicat ed in the operating sections of this specification, is not im plied. exposure to absolute maximum rating conditions for extended periods may af fect device reliability. table 8. absolute maximum ratings symbol parameter min. max. unit ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec standard j-std-020d (for smal l-body, sn-pb or pb asse mbly), the st ecopack? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs directive 2011/65/eu of july 2011). c v out output range (q = v oh or hi-z) ?0.50 v cc +0.5 v v in input range ?0.50 v cc +1 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) (2) 2. positive and negative pulses applied on pin pairs, according to the aec-q100-002 (compliant with ansi/esda/jedec js-001-2012), c1 = 100 pf, r1 = 1500 , r2 = 500 ). - 4000 v
dc and ac parameters m93cx6-a125 20/31 docid024752 rev 5 11 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. figure 9. ac testing input output waveforms table 9. operating conditions (m93cx6-a125) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 125 c table 10. ac measurement conditions symbol parameter min. max. unit c l load capacitance 100 pf - input rise and fall times - 50 ns - input voltage levels 0.2 v cc to 0.8 v cc v - input timing reference voltages 0.3 v cc to 0.7 v cc v - output timing reference voltages 0.3 v cc to 0.7 v cc v table 11. input and output capacitance symbol parameter test condition (1) 1. sampled only, not 100% tested, at t a = 25 c and a frequency of 1 mhz. min max unit c out output capacitance v out = 0v - 8 pf c in input capacitance v in = 0v - 6 pf table 12. cycling performance by byte symbol parameter test condition min. max. unit ncycle write cycle endurance ta 25 c, 1.8 v < v cc < 5.5 v - 4,000,000 write cycle (1) 1. a write cycle is executed when either a write, a wr ite all, an erase or an erase all instruction is decoded. ta = 85 c, 1.8 v < v cc < 5.5 v - 1,200,000 ta = 125 c, 1.8 v < v cc < 5.5 v - 600,000 -36 9 && 9 && 9 && 9 && )nputandoutput timingreferencelevels )nputvoltagelevels -#88
docid024752 rev 5 21/31 m93cx6-a125 dc and ac parameters 30 table 13. dc characteristics symbol parameter test conditions (in addition to co nditions specified in table 9 ) min. max. unit i li input leakage current v in = v ss or v cc -2 a i lo output leakage current s = v cc , v out = v ss or v cc -2 i cc supply current (read) v cc = 1.8 v, c = 0.1 v cc /0.9 v cc , q = open, f c = 2 mhz -1 ma v cc = 2.5 v, c = 0.1 v cc /0.9 v cc , q = open, f c = 2 mhz -1 v cc = 5.5 v, f c = 2 mhz c = 0.1 v cc /0.9 v cc , q = open -1.5 i cc0 (1) supply current (write) 1.8 v v cc < 5.5 v during t w , s = v cc -1.5ma i cc1 supply current (standby mode) t = 85 c, v cc = 1.8 v, s = v cc, v in = v ss or v cc -1 a t = 85 c, v cc = 2.5 v, s = v cc, v in = v ss or v cc -2 t = 85 c, v cc = 5.5 v, s = v cc, v in = v ss or v cc -3 t = 125 c, v cc = 1.8 v, s = v cc, v in = v ss or v cc -15 t = 125 c, v cc = 2.5 v, s = v cc, v in = v ss or v cc -15 t = 125 c, v cc = 5.5 v, s = v cc, v in = v ss or v cc -15 v il input low voltage (d, c, s) 1.8 v v cc < 2.5 v ?0.45 0.25 v cc v 2.5 v v cc < 5.5 v ?0.45 0.3 v cc v ih input high voltage (d, c, s) 1.8 v v cc < 2.5 v 0.75 v cc v cc +1 v 2.5 v v cc < 5.5 v 0.7 v cc v cc +1 v ol output low voltage v cc = 1.8 v, i ol = 1 ma - 0.3 v v cc 2.5 v, i ol = 2.1 ma - 0.4 v oh output high voltage v cc = 1.8 v, i oh = 1 ma 0.8 v cc - v v cc 2.5 v, i oh = -2.1 ma 0.8 v cc - v res internal reset threshold voltage - 0.5 1.5 v 1. average value during the write cycle (t w )
dc and ac parameters m93cx6-a125 22/31 docid024752 rev 5 table 14. ac characteristics test conditions specified in table 9 and table 10 symbol alt. parameter min. max. unit f c f sk clock frequency d.c. 2 mhz t slch chip select low to clock high 50 - ns t shch t css chip select set-up time 50 - ns t slsh (1) 1. chip select input (s) must be brought low for a minimum of t slsh between consecutive instruction cycles. t cs chip select low to chip select high 200 - ns t chcl (2) 2. t chcl + t clch 1 / f c . t skh clock high time 200 - ns t clch (2) t skl clock low time 200 - ns t dvch t dis data in set-up time 50 - ns t chdx t dih data in hold time 50 - ns t clsh t sks clock set-up time (relative to s) 50 - ns t clsl t csh chip select hold time 0 - ns t shqv t sv chip select to ready/busy status - 200 ns t slqz (3) 3. value defined from characteriza tion, not tested in production. t df chip select low to output hi-z (v cc >2.5 v) - 100 ns chip select low to output hi-z (v cc <2.5 v) - 200 ns t chql t pd0 delay to output low - 200 ns t chqv t pd1 delay to output valid - 200 ns t w t wp erase or write cycle time - 4 ms
docid024752 rev 5 23/31 m93cx6-a125 dc and ac parameters 30 figure 10. synchronous timing (start and op-code input) figure 11. synchronous timing (read) figure 12. synchronous timing (write) ai # 23&2'( 23&2'( 67$57 3 $ 23&2'(,1387 67$57 w'9&+ w6+&+ w&/6+ w&+&/ w&/&+ w&+'; $,& & ' 4 $''5(66,1387 +l= w'9&+ w&/6/ $ 6 '$7$287387 w&+49 w&+'; w&+4/ $q w6/6+ w6/4= 44 4 ai # $ 1 $''5(66'$7$,1387 +l= w'9&+ w6/&+ $' 3 :5,7(&<&/( w6/6+ w&+'; $q w&/6/ w6/4= %86< w6+49 w: 5($'<
package mechanical data m93cx6-a125 24/31 docid024752 rev 5 12 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their le vel of environmental compliance. ecopack? specifications, grade definitions a nd product status are available at: www.st.com . ecopack? is an st trademark.
docid024752 rev 5 25/31 m93cx6-a125 package mechanical data 30 figure 13. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 15. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a - - 1.75 - - 0.0689 a1 - 0.1 0.25 - 0.0039 0.0098 a2 - 1.25 - - 0.0492 - b - 0.28 0.48 - 0.011 0.0189 c - 0.17 0.23 - 0.0067 0.0091 ccc - - 0.1 - - 0.0039 d 4.9 4.8 5 0.1929 0.189 0.1969 e 6 5.8 6.2 0.2362 0.2283 0.2441 e1 3.9 3.8 4 0.1535 0.1496 0.1575 e 1.27 - - 0.05 - - h - 0.25 0.5 - 0.0098 0.0197 k-08-08 l - 0.4 1.27 - 0.0157 0.05 l1 1.04 - - 0.0409 - - 62$b9 ( fff e ' f ( k[? $ n pp / $ *$8*(3/$1( h $ /
package mechanical data m93cx6-a125 26/31 docid024752 rev 5 figure 14. tssop8 ? 8 lead thin shri nk small outline, package outline 1. drawing is not to scale. table 16. tssop8 ? 8-lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a - - 1.200 - - 0.0472 a1 - 0.050 0.150 - 0.0020 0.0059 a2 1.000 0.800 1.050 0. 0394 0.0315 0.0413 b - 0.190 0.300 - 0.0075 0.0118 c - 0.090 0.200 - 0.0035 0.0079 cp - - 0.100 - - 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 - - 0.0256 - - e 6.400 6.200 6.600 0. 2520 0.2441 0.2598 e1 4.400 4.300 4.500 0. 1732 0.1693 0.1772 l 0.600 0.450 0.750 0. 0236 0.0177 0.0295 l1 1.000 - - 0.0394 - - -08-08 n8 8 76623$0b9 w > r e > ? ??
docid024752 rev 5 27/31 m93cx6-a125 package mechanical data 30 figure 15. wfdfpn8 (mlp8) ? 8-lead very thin fine pitch dual flat package no lead 2 x 3 mm, 0.5 mm, package outline 1. drawing is not to scale. 2. the central pad (the area e2 by d2 in the above illustrat ion) must be either connected to vss or left floating (not connected) in the end application. $<b0(b9 7rsylhz 3lq,'pdunlqj 6lghylhz 6hdwlqjsodqh %rwwrpylhz 'dwxp< 7huplqdowls 'hwdlo3= 6hh= 'hwdlo hhh / / / ( ( 1;e ' ' ( 1'[h . h ' $ $ # & h 'dwxp< eee ggg & & - - 3lq $ % ddd # [ ddd # [ fff # $ % h
package mechanical data m93cx6-a125 28/31 docid024752 rev 5 table 17. wfdfpn8 (mlp8) ? 8-lead very thin fine pitch dual flat package no lead 2 x 3 mm, 0.5 mm pitch, mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. min. typ. max. min. typ. max. a 0.700 0.750 0.800 0.0276 0.0295 0.0315 a1 0.025 0.045 0.065 0.0010 0.0018 0.0026 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 d 1.900 2.000 2.100 0.0748 0.0787 0.0827 e 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.500 - - 0.0197 - l1 - - 0.150 - - 0.0059 l3 0.300 - - 0.0118 - - d2 1.050 - 1.650 0.0413 - 0.0650 e2 1.050 - 1.450 0.0413 - 0.0571 k 0.400 - - 0.0157 - - l 0.300 - 0.500 0.0118 - 0.0197 nx (2) 2. nx is the number of terminals. 8 nd (3) 3. nd is the number of terminals on ?d? sides. 4 aaa 0.150 0.0059 bbb 0.100 0.0039 ccc 0.100 0.0039 ddd 0.050 0.0020 eee (4) 4. applied for exposed die paddle and terminals. ex clude embedding part of exposed die paddle from mea- suring. 0.080 0.0031
docid024752 rev 5 29/31 m93cx6-a125 part numbering 30 13 part numbering engineering samples parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st char ge. in no event, st wi ll be liable for any customer usage of these engineering samples in production. st quality has to be contacted prior to any decision to use these engineering samples to run qualification activity. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 18. ordering information scheme example: m93c 86 r mn 3 t p /k device type m93 = microwire serial eeprom device function 86 = 16 kbit (2048 x 8) 76 = 8 kbit (1024 x 8) 66 = 4 kbit (512 x 8) 56 = 2 kbit (256 x 8) 46 = 1 kbit (128 x 8) operating voltage r = v cc = 1.8 to 5.5 v package (1) 1. all packages are ecopack2 ? (rohs compliant and free of brominated, chlorinated and antimony-oxide flame retardants). mn = so8 (150 mils width) dw = tssop8 (169 mils width) mf = wfdfpn8 (2 x 3 mm) device grade 3 = device tested with high reliability certified flow (2) automotive temperature range (?40 to 125 c) 2. the high reliability cert ified flow (hrcf) is described in quality note qnee9801. please ask your nearest st sales office for a copy. packing t = tape and reel packing blank = tube packing plating technology p or g = ecopack2 ? process /k = manufacturing technology code
revision history m93cx6-a125 30/31 docid024752 rev 5 14 revision history table 19. document revision history date revision changes 07-aug-2013 1 initial release 02-dec-2013 2 document status changed from ?preliminary data? to ?production data?. updated: ? features : ?data retention? bullet ? table 9: operating conditions (m93cx6-a125) ??t slqz ? row in table 14: ac characteristics ? note (1) under table 8: absolute maximum ratings ? table 13: dc characteristics ? figure 15: wfdfpn8 (mlp8) ? 8-lead very thin fine pitch dual flat package no lead 2 x 3 mm, 0.5 mm, package outline . renamed figure 11: synchronous timing (read) and figure 12: synchronous timing (write) . 13-aug-2014 3 delete sentence: ?the vcc rise time must not vary faster than 1 v/ s.? inside section 3.1.2 updated packing inside chapter table 18. 02-sept-2014 4 updated ecopack ? to ecopack2 ? updated v ih value inside table 13: dc characteristics . added note 2. in figure 15. updated table 18: ordering information scheme 16-jan-2015 5 updated note 2. in table 8: absolute maximum ratings updated figure 15: wfdfpn8 (mlp8) ? 8-lead very thin fine pitch dual flat package no lead 2 x 3 mm, 0.5 mm, package outline updated table 17: wfdfpn8 (mlp8) ? 8-lead very thin fine pitch dual flat package no lead 2 x 3 mm, 0.5 mm pitch, mechanical data added paragraph: engineering samples on page 29
docid024752 rev 5 31/31 m93cx6-a125 31 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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