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low skew, 1-to-12 lvcmos /lvttl clock multiplier/ zero delay buffer ICS87972I-147 idt? / ics? lvcmos clock multiplier/zero delay buffer 1 ics87972dyi-147 rev. a june 5, 2008 general description the ICS87972I-147 is a low skew, lvcmos/lvttl clock generator and a member of the hiperclocks? family of high performance clock solutions from ics. the ICS87972I-147 has three selectable inputs and provides 14 lvcmos/lvttl outputs. the ICS87972I-147 is a highly flexible device. using the crystal oscillator input, it can be used to generate clocks for a system. all of these clocks can be the same frequency or the device can be configured to generate up to three different frequencies among the three output banks. using one of the single ended inputs, the ICS87972I-147 can be used as a zero delay buffer/multiplier/ divider in clock distribution applications. the three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. in addition, 2 outputs in bank c (qc2, qc3) can be select- ed to be inverting or non-inverting. the output frequency range is 10mhz to 150mhz. input frequency range is 6mhz to 150mhz. the ICS87972I-147 also has a qsync output which can be used or system synchronization purposes. it monitors bank a and bank c outputs and goes low one period of the faster clock prior to coincident rising edges of bank a and bank c clocks. qsync then goes high again when the coincident rising edges of bank a and bank c occur. this feature is used primarily in applications where bank a and bank c are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. example applications: 1. system clock generator: use a 16.66 mhz crystal to generate eight 33.33mhz copies for pci and four 100mhz copies for the cpu or pci-x. 2. line card multiplier: multiply 19.44mhz from a back plane to 77.76mhz for the line card asics and serdes. 3. zero delay buffer for synchronous memory: fan out up to twelve 100mhz copies from a memory controller reference clock to the memory chips on a memory module with zero delay. features ? fully integrated pll ? fourteen lvcmos/lvttl outputs; (12)clocks, (1)feedback, (1)sync ? selectable crystal oscillator interface or lvcmos/lvttl reference clock inputs ? clk0, clk1 can accept the following input levels: lvcmos or lvttl ? output frequency range: 10mhz to 150mhz ? vco range: 240mhz to 500mhz ? output skew: 200ps (maximum) ? cycle-to-cycle jitter, (all banks 4) : 55ps (maximum) ? full 3.3v supply voltage ? -40c to 85c ambient operating temperature ? compatible with powerpc? and pentium? microprocessors ? available in both standard (rohs 5) and lead-free (rohs 6) packages. hiperclocks? ic s 1 2 3 4 5 6 7 8 9 10 11 12 13 40 41 42 43 44 45 46 47 48 49 50 51 52 21 22 23 24 25 26 20 19 18 17 16 15 14 32 33 34 35 36 37 38 39 31 30 29 28 27 fsel_b1 fsel_b0 fsel_a1 fsel_a0 qa3 v ddo qa2 gndo qa1 v ddo qa0 gndo vco_sel fsel_fb1 qsync gndo qc0 v ddo inv_clk qc1 fsel_c0 fsel_c1 qc2 v ddo qc3 gndo gndi v dda nmr/oe frz_clk frz_data fsel_fb2 pll_sel ref_sel clk_sel clk0 clk1 xtal1 xtal2 gndo qb0 v ddo qb1 gndo qb2 v ddo qb3 fsel_fb0 ext_fb gndo qfb v dd pin assignment ICS87972I-147 52-lead lqfp 10mm x 10mm x 1.4mm package body y package top view
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 2 ics87972dyi-147 rev. a june 5, 2008 block diagram sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz d q d q d q d q d q d q qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 qfb qsync xtal1 xtal2 vco_sel pll_sel ref_sel clk_sel ext_fb clk0 clk1 pullup pullup pullup pullup pullup pullup pullup fsel_fb2 pullup nmr/oe pullup fsel_a[0:1] pullup fsel_b[0:1] pullup fsel_c[0:1] pullup fsel_fb[0:2] pullup frz_clk pullup frz_data pullup inv_clk pullup 12 0 1 2 0 1 1 0 0 1 phase detector lpf vco power-on reset 2 3 2 2 output disable circuitry data generator sync pulse 4, 6, 8, 12 4, 6, 8, 10 2, 4, 6, 8 4, 6, 8, 10
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 3 ics87972dyi-147 rev. a june 5, 2008 simplified block diagram 0 1 1 0 0 1 1 2 sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz sync frz o utput d isable c ircuitry 0 1 0 1 pll vco range 240mhz - 500mhz sync frz 3 2 2 2 inv_clk fsel_a[0:1] fsel_b[0:1] fsel_c[0:1] fsel_fb[0:2] 0 0 4 0 1 6 1 0 8 1 1 12 fsel_ a1 a0 qax 0 0 4 0 1 6 1 0 8 1 1 10 fsel_ b1 b0 qbx 0 0 0 4 0 0 1 6 0 1 0 8 0 1 1 10 1 0 0 8 1 0 1 12 1 1 0 16 1 1 1 20 fsel_ fb2 fb1 fb0 qfb 0 0 2 0 1 4 1 0 6 1 1 8 fsel_ c1 c0 qcx nmr/oe xtal1 xtal2 vco_sel pll_sel ref_sel ext_fb clk0 clk1 pullup pullup pullup pullup pullup clk_sel pullup pullup qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 qfb qsync frz_clk pullup frz_data pullup
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 4 ics87972dyi-147 rev. a june 5, 2008 table 1. pin descriptions note: pullup refers to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1 gndi power power supply ground. 2 nmr/oe input pullup master reset and output enable. when high, enables the outputs. when low, resets the outputs to hi-z and resets output divide circuitry. enables and disables all outputs. lvcmos / lvttl interface levels. 3 frz_clk input pullup clock input for freeze circ uitry. lvcmos / lvttl interface levels. 4 frz_data input pullup configuration data input for freeze circuitry. lvcmos / lvttl interface levels. 5, 26, 27 fsel_fb2, fsel_fb1, fsel_fb0 input pullup select pins control feedback divide va lue. lvcmos / lvttl interface levels. see table 3b. 6 pll_sel input pullup selects between the p ll and reference clocks as the in put to the outp ut dividers. when high, selects pll. when low, by passes the pll and reference clocks. lvcmos / lvttl interface levels. 7 ref_sel input pullup selects between crystal and reference cloc k. when low, sele cts clk0 or clk1. when high, selects crystal inputs. lvcmos / lvttl interface levels. 8 clk_sel input pullup clock select input. when low, selects clk0. when high, selects clk1. lvcmos / lvttl interface levels. 9, 10 clk0, clk1 input pullup single-ended referenc e clock inputs. lvcmos/lvttl interface levels. 11, 12 xtal_1, xtal_2 input crystal oscillator interface. xtal _1 is the input. xtal_2 is the output. 13 v dda power analog supply pin. 14 inv_clk input pullup inverted clock select for qc2 and qc3 outputs. lvcmos / lvttl interface levels. 15, 24, 30, 35, 39, 47, 51 gndo power power supply ground. 16, 18, 21, 23 qc3, qc2, qc1, qc0 output single-ended bank c clock output s. lvcmos/ lvttl interface levels. 17, 22, 33, 37, 45, 49 v ddo power output power supply pins. 19, 20 fsel_c1, fsel_c0 input pullup select pins for bank c outputs. lv cmos / lvttl interface levels. see table 3a. 25 qysnc output synchronization output for bank a and bank c. refer to figure 1, timing diagrams. lvcmos / lvttl interface levels. 28 v dd power power supply pin. 29 qfb output single-ended feedback clock out put. lvcmos / lvttl interface levels. 31 ext_fb input pullup external feedback. lvcmos / lvttl interface levels. 32, 34, 36, 38 qb3, qb2, qb1, qb0 output single-ended bank b clock outputs. lvcmos/ lvttl interface levels. 40, 41 fsel_b1, fsel_b0 input pullup select pins for bank b outputs. lv cmos / lvttl interface levels. see table 3a. 42, 43 fsel_a1, fsel_a0 input pullup select pins for bank a outputs. lv cmos / lvttl interface levels. see table 3a. 44, 46 48, 50 qa3, qa2, qa1, qa0 output single-ended bank a clock outputs. lvcmos/ lvttl interface levels. 52 vco_sel input pullup selects vco. when high, selects vco 1. when low, selects vco 2. lvcmos / lvttl interface levels.
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 5 ics87972dyi-147 rev. a june 5, 2008 table 2. pin characteristics function tables table 3a. output bank configuration select function table table 3b. feedback configuration select function table table 3c. control input select function table symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4pf r pullup input pullup resistor 51 k ? c pd power dissipation capacitance (per output) v dd, v dda, v ddo = 3.465v 18 pf r out output impedance 5 7 12 ? inputs outputs inputs outputs inputs outputs fsel_a1 fsel_a0 qa fsel_b1 f sel_b0 qb fsel_c1 fsel_c0 qc 0 0 4 0 0 4 0 0 2 0 1 6 0 1 6 0 1 4 1 0 8 1 0 8 1 0 6 11121110118 inputs outputs fsel_fb2 fsel_fb1 fsel_fb0 qfb 000 4 001 6 010 8 011 10 100 8 101 12 110 16 111 20 control pin logic 0 logic 1 vco_sel vco/2 vco ref_sel clk0 or clk1 xtal clk_sel clk0 clk1 pll_sel bypass pll enable pll nmr/oe master reset/output hi-z enable outputs inv_clk non-inverted qc2, qc3 inverted qc2, qc3
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 6 ics87972dyi-147 rev. a june 5, 2008 figure 1. timing diagrams fvco qa qc qsync qa qa(4) qc qc(2) qsync qsync qa(8) qc(2) qsync qa(8) qc(2) qsync qc(8) qa(6) qsync qc(2) qa(12) qsync 1:1 mode 2:1 mode 3:2 mode 3:1 mode 4:1 mode 4:3 mode 6:1 mode
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 7 ics87972dyi-147 rev. a june 5, 2008 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v dda = v ddo = 3.3v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = v dda = v ddo = 3.3v 5%, t a = -40c to 85c note 1: outputs terminated with 50 ? to v ddo /2. see parameter measurement information section. load test circuit diagram. item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 42.3 c/w (0 lfpm) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current 250 ma i dda analog supply current 20 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage vco_sel, pll_sel, ref_sel, clk_sel, ext_fb, fsel_fb[0:2], fsel_a[0:1], fsel_b[0:1], fsel_c[0:1], frz_data -0.3 0.8 v clk0, clk1, inv_clk, frz_clk -0.3 1.3 v i in input current 120 a v oh output high voltage; note 1 i oh = -20ma 2.4 v v ol output low voltage; note 1 i ol = 20ma 0.5 v
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 8 ics87972dyi-147 rev. a june 5, 2008 table 5. input frequency characteristics, v dd = v dda = v ddo = 3.3v 5%, t a = -40c to 85c note 1: input frequency depends on the feedback divide ratio to ensure "clock * feedback divide" is in the vco range of 240mhz to 500mhz. table 6. crystal characteristics ac electrical characteristics table 7. ac characteristics, v dd = v dda = v ddo = 3.3v 5%, t a = -40c to 85c note 1: defined as the time difference between the input refere nce clock and the average feedback input signal when the pll is locked and the input reference frequency is stable. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: these parameters are guaranteed by characterization. not tested in production. symbol parameter test conditions minimum typical maximum units f in input frequency clk0, clk1; note 1 150 mhz xtal1, xtal 12 40 mhz frz_clk 20 mhz parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 12 40 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf parameter symbol test conditi ons minimum typical maximum units f max output frequency 2 150 mhz 4 125 mhz 6 83.33 mhz 8 62.5 mhz t(?) static phase offset; note 1 clk0 qfb 8, in frequency = 50mhz -10 145 300 ps clk1 -65 90 245 ps t sk(o) output skew; note 2, 3 200 ps tjit(cc) cycle-to-cycl e jitter; note 3 all banks 4 55 ps f vco pll vco lock range 240 500 mhz t lock pll lock time; note 4 10 ms t r / t f output rise/fall time 0.8v to 2v 0.15 0.7 ns odc output duty cycle 45 55 % t pzl, t pzh output enable time; note 4 10 ns t plzl, t phz output disable time; note 4 8 ns
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 9 ics87972dyi-147 rev. a june 5, 2008 parameter measureme nt information 3.3v core/3.3v lvcmos output load ac test circuit cycle-to-cycle jitter static phase offset output skew output duty cycle/pulse width period output rise/fall time scope qx lvcmos gnd v dd, 1.65v5% -1.65v5% v ddo v dda, ? ? ? ? v ddo 2 v ddo 2 v ddo 2 t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles qa[0:3], qb[0:3], qc[0:3], qsync, qfb ? ? (?) v dd 2 v dd 2 t (?) mean = static phase offset where t (?) is any random sample, and t (?) mean is the average of the sampled cycles measured on controlled edges clk0, clk1 ext_fb t sk(o) qx qy t period t pw t period odc = v ddo 2 x 100% t pw qa[0:3], qb[0:3], qc[0:3], qsync, qfb 0.8v 2v 2v 0.8v t r t f qa[0:3], qb[0:3], qc[0:3], qsync, qfb
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 10 ics87972dyi-147 rev. a june 5, 2008 application information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perform- ance, power supply isolation is required. the ICS87972I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd, v dda and v ddo should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 2 illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v dda pin. figure 2. power supply filtering recommendations for unused input and output pins inputs: crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. clk inputs for applications not requiring the use of the clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk to ground. lvcmos control pins all control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs all unused lvcmos output can be le ft floating. there should be no trace attached. v dd v dda 3.3v 10 ? 10f .01f .01f
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 11 ics87972dyi-147 rev. a june 5, 2008 crystal input interface the ICS87972I-147 has been characterized with 18 pf parallel resonant crystals. external capacitors are not required for this crystal interface. while layout the pc board, it is recommended to have spare footprints capacitor c1 and c2. if required, the spare c1 and c2 footprints can be used for fine tuned further for more accurate frequency. the possible c1 and c2 value are ranged from 2pf ? 25pf. the suggest footprint size is 0402 or 0603. figure 3. crystal input interface lvcmos to xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 4. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be re duced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configurat ion requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . figure 4. general diagram for lvcmos driver to xtal input interface xtal_in xtal_out x1 18pf parallel crystal c1 spare c2 spare xtal_in xtal_out ro rs zo = ro + rs 50 ? 0.1f r1 r2 v cc v cc
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 12 ics87972dyi-147 rev. a june 5, 2008 using the output freeze circuitry o verview to enable low power states within a system, each output of ICS87972I-147 (except qc0 and qfb) can be individually frozen (stopped in the logic ?0? state) using a simple serial interface to a 12 bit shift register. a serial interface was chosen to eliminate the need for each output to have its own output enable pin, which would dramatically increase pin count and package cost. common sources in a system that can be us ed to drive th e ICS87972I-147 serial interface are fpga?s and asics. p rotocol the serial interface consists of two pins, frz_data (freeze data) and frz_clk (freeze clock). each of the outputs which can be frozen has its own freeze enable bit in the 12 bit shift register. the sequence is started by supplying a logic ?0? start bit followed by 12nrz freeze enable bits. the period of each frz_data bit equals the period of the frz_clk signal. the frz_data serial transmission should be timed so the ICS87972I-147 can sample each frz_data bit with the rising edge of the frz_clk signal. to place an output in the freeze state, a logic ?0? must be written to the respective freeze enable bit in the shift register. to unfreeze an output, a logic ?1? must be written to the respective freeze enable bit. outputs will not become enable d/disabled until all 12 data bits are shifted into the shift register. when all 12 data bits are shifted in the register, the next rising edge of frz_clk will enable or disable the outputs. if the bit that is following the 12th bit in the register is a logic ?0?, it is used for the start bit of the next cycle; otherwise, the device will wait and w on?t start the next cycle until it sees a logic ?0? bit. freezing and unfreezing of the output clock is synchronous (see the timing diagram below). when going into a frozen state, the output clock will go low at the time it would normally go low, and the freeze logic will keep the output low until unfrozen. likewise, when coming out of the frozen state, the output will go high only when it would normally go high. this logic, therefore, prevents runt pulses when going into and out of the frozen state. frz latched frz clocked qx f reeze internal qx internal qx out frz_clk frz_data start bit qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc1 qc2 qc3 qsync figure 5b. output disable timing diagram figure 5a. freeze data input protocol
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 13 ics87972dyi-147 rev. a june 5, 2008 reliability information table 8. ja vs. air flow table for a 52 lead lqfp transistor count the transistor count for ICS87972I-147: 8364 pin compatible with mpc972 ja by velocity linear feet per minute 0200500 single-layer pcb, jedec standard te st boards 58.0c/w 47.1c/w 42.0c/w multi-layer pcb, jedec standard test boards 42.3c/w 36.4c/w 34.0c/w note: most modern pcb designs use multi-layered boards . the data in the second row pertains to most designs.
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 14 ics87972dyi-147 rev. a june 5, 2008 package outline and package dimensions package outline - y suffix for 52 lead lqfp table 9. package dimensions for 52 lead lqfp reference document: jedec publication 95, ms-026 jedec variation: bcc all dimensions in millimeters symbol minimum nominal maximum n 52 a 1.60 a1 0.05 0.10 0.15 a2 1.35 1.40 1.45 b 0.22 0.38 c 0.09 0.20 d & e 12.00 basic d1 & e1 10.00 basic d2 & e2 7.80 ref. e 0.65 basic l 0.45 0.60 0.75 0 7 ccc 0.10
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 15 ics87972dyi-147 rev. a june 5, 2008 ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 87972dyi-147 ics87972dyi-147 52 lead lqfp tray -40 c to 85 c 87972dyi-147t ics87972dyi-147 52 lead lqfp 1000 tape & reel -40 c to 85 c 87972dyi-147lf ics87972di147l ?lead-free? 52 lead lqfp tray -40 c to 85 c 87972dyi-147lft ics87972di147l ?lead-free? 52 lead lqfp 1000 tape & reel -40 c to 85 c while the information presented herein has been checked for both a ccuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other ext raordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support device s or critical medical instruments.
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer idt? / ics? lvcmos clock multiplier/zero delay buffer 16 ics87972dyi-147 rev. a june 5, 2008 revision history sheet rev table page description of change date a t9 t10 1 10 11 14 15 features section - added leaf-free bullet. added recommendations for unused input/output pins section. added lvcmos to xtal interface section. package dimensions table - added l and dimensions. ordering information table - added 52 lead lqfp ordering information; corrected non-lf marking from ics87972dyi147 to ics87972dyi-147. 6/5/08
ICS87972I-147 low skew, 1-to-12, lvcmos/lvttl clock multiplier/zero delay buffer www.idt.com ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) contact information: www.idt.com

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