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? semiconductor components industries, llc, 2015 may, 2015 ? rev. 9 1 publication order number: ncv7420/d ncv7420 lin transceiver with 3.3v or 5 v voltage regulator general description the ncv7420 is a fully featured local interconnect network (lin) transceiver designed to interface between a lin protocol controller and the physical bus. the transceiver is implemented in i3t technology enabling both high?voltage analog circuitry and digital functionality to co?exist on the same chip. the ncv7420 lin device is a member of the in?vehicle networking (ivn) transceiver family of on semiconductor that integrates a lin v2.0/2.1 physical transceiver and either a 3.3 v or a 5 v voltage regulator. the lin bus is designed to communicate low rate data from control devices such as door locks, mirrors, car seats, and sunroofs at the lowest possible cost. the bus is designed to eliminate as much wiring as possible and is implemented using a single wire in each node. each node has a slave mcu?state machine that recognizes and translates the instructions specific to that function. the main attraction of the lin bus is that all the functions are not time critical and usually relate to passenger comfort. key features lin?bus transceiver ? lin compliant to specification revision 2.0 and 2.1 (backward compatible to version 1.3) and j2602 ? i3t high voltage technology ? bus voltage 45 v ? transmission rate up to 20 kbaud protection ? thermal shutdown ? indefinite short?circuit protection on pins lin and wake towards supply and ground ? load dump protection (45 v) ? bus pins protected against transients in an automotive environment ? system esd protection level for lin, wake and v bb up to 12 kv voltage regulator ? output voltage 5 v / ~50 ma or 3.3 v / ~50 ma ? wake?up input ? enable inputs for standby and sleep mode ? inh output for auxiliary purposes (switching of an external pull?up or resistive divider towards battery, control of an external voltage regulator etc.) emi compatibility ? integrated slope control ? meets most demanding ems/eme requirements modes ? normal mode: lin communication in either low (up to 10 kbaud) or normal slope ? sleep mode: v cc is switched ?off? and no communication on lin bus ? standby mode: v cc is switched ?on? but there is no communication on lin bus ? wake?up bringing the component from sleep mode into standby mode is possible either by lin command or digital input signal on wake pin. wake?up from lin bus can also be detected and flagged when the chip is already in standby mode. quality ? ncv prefix for automotive and other applications requiring unique site and control change require? ments; aec?q100 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant www. onsemi.com see detailed ordering and shipping information in the package dimensions section on page 19 of this data sheet. ordering information 1 14 soic?14 d suffix case 751ap pin configuration 1 2 3 4 14 13 12 11 gnd gnd txd rxd gnd lin ncv7420 5 6 7 10 9 8 wake otp_zap inh test en stb v cc v bb
ncv7420 www. onsemi.com 2 marking diagram ncv7420?x awlywwg 1 14 ncv7420 = specific device code ?x = ?3 = ncv7420d23g = ?4 = NCV7420D24G = ?5 = ncv7420d25g = ?6 = ncv7420d26g a = assembly location wl = wafer lot y = year ww = work week g = pb?free package table 1. key technical characteristics ? 3.3 v version symbol parameter min typ max unit v bb nominal battery operating voltage (note 1) 5 12 26 v load dump protection (note 2) 45 i bb_slp supply current in sleep mode 20 a v cc_out (note 4) regulated v cc output, v cc load 1 ma?30 ma 3.23 3.30 3.37 v regulated v cc output, v cc load 0 ma?50 ma 3.19 3.30 3.41 i out_max maximum v cc output current (note 3) 50 ma v wake operating dc voltage on wake pin 0 v bb v maximum rating voltage on wake pin ?45 45 t jsd junction thermal shutdown temperature 165 195 c t j operating junction temperature ?40 +150 c table 2. key technical characteristics ? 5 v version symbol parameter min typ max unit v bb nominal battery operating voltage (note 1) 6 12 26 v load dump protection 45 i bb_slp supply current in sleep mode 20 a v cc_out (note 4) regulated v cc output, v cc load 1 ma?30 ma 4.9 5.0 5.1 v regulated v cc output, v cc load 0 ma?50 ma 4.83 5.0 5.17 i out_max maximum v cc output current (note 3) 50 ma v wake operating dc voltage on wake pin 0 v bb v maximum rating voltage on wake pin ?45 45 t jsd junction thermal shutdown temperature 165 195 c t j operating junction temperature ?40 +150 c 1. below 5 v on v bb in normal mode, the bus will either stay recessive or comply with the voltage level specifications and transition time specifications as required by sae j2602. it is ensured by the battery monitoring circuit. 2. the applied transients shall be in accordance with iso 7637 part 1, test pulse 5. the device complies with functional class c ; class a can be reached depending on the application and external conditions. 3. thermal aspects of the entire end?application have to be taken into account in order to avoid thermal shutdown of ncv7420. 4. v cc voltage regulator output must be properly decoupled by external capacitor of min. 8 f with esr < 1 to ensure stability. table 3. thermal characteristics symbol parameter conditions value unit r ja1 thermal resistance junction?to?ambient, 1s0p pcb (note 5) free air 140 k/w r ja 2 thermal resistance junction?to?ambient, 2s2p pcb (note 6) free air 80 k/w 5. test board according to eia/jedec standard jesd51?3, signal layer with 20% trace coverage 6. test board according to eia/jedec standard jesd51?7, signal layers with 20% trace coverage
ncv7420 www. onsemi.com 3 figure 1. block diagram stb txd en rxd wake control logic ncv7420 lin timeout driver & slope control thermal shutdown osc inh test otp_zap por v?reg band? gap receiver gnd normal mode standby sleep v bb v cc v bb v bb v cc v bb v cc v cc v cc typical application application schematic the emc immunity of the master?mode device can be further enhanced by adding a capacitor between the lin output and ground. the optimum value of this capacitor is determined by the length and capacitance of the lin bus, the number and capacitance of slave devices, the pull?up resistance of all devices (master & slave), and the required time constant of the system, respectively. v cc voltage must be properly stabilized by external capacitor: capacitor of min. 8 f (esr < 1 ).
ncv7420 www. onsemi.com 4 figure 2. typical application diagram kl30 lin?bus kl31 lin master node 1 nf 1kw gnd ncv7420 micro controller gnd inh v bb vbat gnd 10nf wake lin slave node 220pf gnd micro controller vbat gnd wake 10uf v cc v cc 10uf 100nf test otp_zap 10nf gnd inh v bb v cc test otp_zap lin wake 10uf 100nf v cc lin wake en stb txd rxd ncv7420 en stb txd rxd 10uf table 4. pin description pin name description 1 v bb battery supply input 2 lin lin bus output/input 3 gnd ground 4 gnd ground 5 wake high voltage digital input pin to switch the part from sleep? to standby mode 6 inh inhibit output 7 otp_zap supply for programming of trimming bits at factory testing, should be grounded in the application 8 test digital input for factory testing, should be grounded in the application 9 en enable input, transceiver in normal operation mode when high 10 stb standby mode control input 11 gnd ground 12 txd transmit data input, low in dominant state 13 rxd receive data output; low in dominant state; push?pull output 14 v cc supply voltage (output) overall functional description lin is a serial communication protocol that efficiently supports the control of mechatronic nodes in distributed automotive applications. the domain is class?a multiplex buses with a single master node and a set of slave nodes. ncv7420 is designed as a master or slave node for the lin communication interface with an integrated 3.3 v or 5 v voltage regulator having a current capability up to 50 ma for supplying any external components (microcontroller). ncv7420 contains the lin transmitter, lin receiver, voltage regulator, power?on?reset (por) circuits and thermal shutdown (tsd). the lin transmitter is optimized for the maximum specified transmission speed of 20 kbaud with emc performance due to reduced slew rate of the lin output. the junction temperature is monitored via a thermal shutdown circuit that switches the lin transmitter and voltage regulator off when temperature exceeds the tsd trigger level. ncv7420 has four operating states (normal mode, low slope mode, standby mode, and sleep mode) that are determined by the input signals en, wake, stb, and txd. operating states ncv7420 provides four operating states, two modes for normal operation with communication, one standby without communication and one low power mode with very low current consumption. see figure 3.
ncv7420 www. onsemi.com 5 figure 3. state diagram en goes from 0 to 1 while txd = 0, en goes from 1 to 0 en goes from 1 to 0 en goes from 0 to 1 while txd = 1, en goes from 1 to 0 standby mode normal mode (normal slope) sleep mode normal mode (low slope) power off from any mode local wake?up or lin wake?up note: lin transmitter is ?off? when en goes from 1 to 0 ?v cc : ?on? ?lin tx: ?off? ?term: ?current source? ?inh: ?floating? ?rxd: pull?up to v cc /low ?v cc : ?on? ?lin tx: ?on? ?term: 30 k ?inh: ?high?/?floating? ?rxd: lin data (push?pull) ?v cc : ?off? ?lin tx: ?off? ?term: ?current source? ?inh: ?floating? ?rxd: pull?up to v cc ?v cc : ?on? ?lin tx: ?on? ?term: 30 k ?inh: ?high?/?floating? ?rxd: lin data (push?pull) while stb = 0 and v bb > v bb_uv_th power up v bb v bb > v bb_uv_th v bb < v bb_uv_th v bb < porl_v bb while stb = 1 or v bb < v bb_uv_th and v cc > v cc_uv_th and v bb > v bb_uv_th while stb = 0 and v bb > v bb_uv_th and v cc > v cc_uv_th , v bb > v bb_uv_th while stb = 1 or v bb < v bb_uv_th table 5. mode selection mode v cc rxd inh lin 30 k on lin note normal ? slope on low = dominant state high = recessive state high if stb=high during state transition; floating otherwise normal slope on (note 7) normal ? low slope on low = dominant state high = recessive state high if stb=high during state transition; floating otherwise low slope on (note 8) standby on low after lin wake?up, high otherwise floating off off (notes 9 and 10) sleep off clamped to v cc floating off off 7. the normal slope mode is entered when pin en goes high while txd is in high state during en transition. 8. the low slope mode is entered when pin en goes high while txd is in low state during en transition. lin transmitter gets on o nly after txd returns to high after the state transition. 9. the standby mode is entered automatically after power?up. 10. in standby mode, rxd high state is achieved by internal pull-up resistor to v cc . normal slope mode in normal slope mode the transceiver can transmit and receive data via lin bus with speed up to 20 kbaud. the transmit data stream of the lin protocol is present on the txd pin and converted by the transmitter into a lin bus signal with controlled slew rate to minimize emc emission. the receiver consists of the comparator that has a threshold with hysteresis in respect to the supply voltage and an input filter to remove bus noise. the lin output is pulled high via an internal 30 k pull-up resistor. for master applications it is needed to put an external 1 k resistor with a serial diode between lin and v bb (or inh). see figure 2. the mode selection is done by en=high when txd pin is high. if stb pin is high during the standby-to-normal slope mode transition, inh pin is pulled high. otherwise, it stays floating. low slope mode in low slope mode the slew rate of the signal on the lin bus is reduced (rising and falling edges of the lin bus signal are longer). this further reduces the emc emission. as a consequence the maximum speed on the lin bus is reduced up to 10 kbaud. this mode is suited for applications where the communication speed is not critical. the mode selection is done by en=high when txd pin is low. in order not to transmit immediately a dominant state on the bus (because
ncv7420 www. onsemi.com 6 txd=low), t he lin transmitter is enabled only after txd returns to high. if stb pin is high during the standby?to?low slope mode transition, inh pin is pulled high. otherwise, it stays floating. standby mode the standby mode is always entered after power?up of the ncv7420. it can also be entered from normal mode when the en pin is low and the standby pin is high. from sleep mode it can be entered after a local wake?up or lin wake?up. in standby mode the v cc voltage regulator for supplying external components (e.g. a microcontroller) stays active. also the lin receiver stays active to be able to detect a remote wake?up via bus. the lin transmitter is disabled and the slave internal termination resistor of 30 k between lin and v bb is disconnected in order to minimize current consumption. only a pull?up current source between v bb and lin is active. sleep mode the sleep mode provides extreme low current consumption. this mode is entered when both en and stb pins are low coming from normal mode. the internal termination resistor of 30 k between lin and v bb is disconnected and also the v cc regulator is switched off to minimize current consumption. wake?up ncv7420 has two possibilities to wake?up from sleep or standby mode (see figure 3): ? local wake?up: enables the transition from sleep mode to standby mode ? remote wake?up via lin: enables the transition from sleep? to standby mode and can be also detected when already in standby mode. a local wake?up is only detected in sleep mode if a transition from low to high or from high to low is seen on the wake pin. wake t v bb detection of local wake?up sleep mode standby mode 50% v bb typ. wake t v bb detection of local wake?up sleep mode standby mode 50% v bb typ. figure 4. local wake?up signal a remote wake?up is only detected if a combination of (1) a falling edge at the lin pin (transition from recessive to dominant) is followed by (2) a dominant level maintained for a time period > t wake and (3) again a rising edge at pin lin (transition from dominant to recessive) happens. lin recessive level lin t t wake detection of remote wake?up v bb sleep mode standby mode lin dominant level figure 5. remote wake?up behavior 40% v bb 60% v bb the wake?up source is distinguished by pin rxd in the standby mode: ? rxd remains high after power?up or local wake?up. ? rxd is kept low until normal mode is entered after a remote wake?up (lin).
ncv7420 www. onsemi.com 7 figure 6. operating modes transitions en stb txd power off standby normal normal slope normal low slope standby sleep wake?up (local or lin) standby power off v cc v bb porl_v bb v bb_uv_th
ncv7420 www. onsemi.com 8 electrical characteristics definitions all voltages are referenced to gnd (pin 11). positive currents flow into the ic. table 6. absolute maximum ratings ? 3.3 v and 5 v versions symbol parameter min max unit v bb battery voltage on pin v bb (note 11) ?0.3 +45 v v cc dc voltage on pin v cc 0 +7 v i vcc current delivered by the v cc regulator 50 ma v lin lin bus voltage (note 12) ?45 +45 v v inh dc voltage on inhibit pin ?0.3 v bb + 0.3 v v wake dc voltage on wake pin ?45 45 v v dig_in dc input voltage on pins txd, rxd, en, stb ?0.3 v cc + 0.3 v t j maximum junction temperature ?40 +165 c v esd electrostatic discharge voltage on all pins; hbm (note 13) ?2 +2 kv electrostatic discharge voltage on lin, inh, wake and v bb towards gnd; hbm (note 13) ?4 +4 kv electrostatic discharge on lin, wake and v bb ; system hbm (note 14) ?8 +8 kv electrostatic discharge voltage on all pins; cdm (note 16) ?500 +500 v v esd (emc/esd improved versions) electrostatic discharge voltage on all pins; hbm (note 13) ?4 +4 kv electrostatic discharge voltage on lin, inh, wake and v bb towards gnd; hbm (note 13) ?6 +6 kv electrostatic discharge on lin, wake and v bb ; system hbm (note 15) ?12 +12 kv electrostatic discharge voltage on all pins; cdm (note 16) ?750 +750 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 11. the applied transients shall be in accordance with iso 7637 part 1, test pulses 1, 2, 3a, 3b, and 5. the device complies wit h functional class c; class a can be reached depending on the application and external components. 12. the applied transients shall be in accordance with iso 7637 part 1, test pulses 1, 2, 3a, and 3b. the device complies with f unctional class c; class a can be reached depending on the application and external components. 13. equivalent to discharging a 100 pf capacitor through a 1500 resistor. 14. equivalent to discharging a 150 pf capacitor through a 330 resistor conform to iec standard 61000?4?2. lin bus filter 220 pf, v bb blocking capacitor 100 nf, 3k3/10n r/c network on wake. 15. equivalent to discharging a 150 pf capacitor through a 330 resistor conform to iec standard 61000?4?2. no filter on lin, v bb blocking capacitor 100 nf, 3k3/10n r/c network on wake. 16. charged device model according esd-stm5.3.1.
ncv7420 www. onsemi.com 9 table 7. dc characteristics ? 3.3 v version (v bb = 5 v to 26 v; t j = ?40 c to +150 c; bus load = 500 (v bb to lin); unless otherwise specified.) symbol parameter conditions min typ max unit supply ? pin v bb i bb_on supply current normal mode; lin recessive 1.6 ma i bb_stb supply current standby mode, v bb = 5?18 v, t j < 105 c 70 a i bb_slp supply current sleep mode, v bb = 5?18 v, t j < 105 c 20 a voltage regulator ? pin v cc v cc_out regulator output voltage v cc load 1 ma ? 30 ma 3.23 3.30 3.37 v v cc load 0 ma ? 50 ma 3.19 3.30 3.41 i out_max_abs absolute maximum output current thermal shutdown must be taken into account 50 ma i out_lim overcurrent limitation 50 100 170 ma v cc_out line regulation (note 22) v bb 5?26 v, i out = 5 ma, t j = 25 c 0.5 mv load regulation (note 22) i out 1?50 ma, v bb = 14 v, t j = 25 c 45 mv v do dropout voltage (v bb ?v cc_out ) figure 11, (notes 21, 22) i out = 1 ma, t j = 25 c 13 mv i out = 10 ma, t j = 25 c 134 mv i out = 50 ma, t j = 25 c 732 mv lin transmitter ? pin lin v lin_dom_losup lin dominant output voltage txd = low; v bb = 7.3 v 1.2 v v lin_dom_hisup lin dominant output voltage txd = low; v bb = 18 v 2.0 v v lin_rec lin recessive output voltage (note 17) txd = high; i lin = 10 a v bb ? 1.5 v bb v i lin_lim short circuit current limitation v lin = v bb_max 40 200 ma r slave internal pull?up resistance 20 33 47 k c lin capacitance on pin lin (note 19) 15 25 pf lin receiver ? pin lin v bus_dom bus voltage for dominant state 0.4 v bb v bus_rec bus voltage for recessive state 0.6 v bb v rec_dom receiver threshold lin bus recessive dominant 0.4 0.6 v bb v rec_rec receiver threshold lin bus dominant recessive 0.4 0.6 v bb v rec_cnt receiver centre voltage (vrec_dom + vrec_rec) / 2 0.475 0.525 v bb v rec_hys receiver hysteresis (vrec_rec ? vrec_dom) 0.05 0.175 v bb i lin_off_dom lin output current bus in dominant state driver off; v bb = 12 v, v lin = 0 v ?1 ma i lin_off_rec lin output current bus in recessive state driver off; v bb < 18 v v bb < v lin < 18 v 1 a i lin_no_gnd communication not affected v bb = gnd = 12 v; 0 < v lin < 18 v ?1 1 ma 17. the voltage drop in normal mode between lin and v bb pin is the sum of the diode drop and the drop at serial pull?up resistor. the drop at the switch is negligible. see figure 1. 18. by one of the trimming bits, following reconfiguration can be done during chip?level testing in order to fit the ncv7420?3 i nto different interface: pins txd and en will have typ. 10 k pull?down resistor to ground and pin wake will have typ. 10 a pull?up current source. 19. guaranteed by design. not tested. 20. v bb undervoltage threshold is always higher than v bb por low level (v bb_uv_th > porl_v bb ) 21. measured at output voltage v cc_out = (v cc_out @v bb = 5 v) ? 2%. 22. values based on design and characterization. not tested in production.
ncv7420 www. onsemi.com 10 table 7. dc characteristics ? 3.3 v version (v bb = 5 v to 26 v; t j = ?40 c to +150 c; bus load = 500 (v bb to lin); unless otherwise specified.) symbol unit max typ min conditions parameter lin receiver ? pin lin i lin_no_vbb lin bus remains operational v bb = gnd = 0 v; 0 < v lin < 18 v 5 a pin wake v wake_th threshold voltage 0.35 0.65 v bb i leak input leakage current (note 18) v wake = 0 v; v bb = 18 v ?1 ?0.5 1 a t wake_min debounce time sleep mode; rising and falling edge 8 54 s pins txd and stb v il low level input voltage 0.8 v v ih high level input voltage 2.0 v r pu pull?up resistance to v cc (note 18) 50 200 k pin inh delta_v h high level voltage drop i inh = 15 ma 0.35 0.75 v i leak leakage current sleep mode; v inh = 0 v ?1 1 a pin en v il low level input voltage 0.8 v v ih high level input voltage 2.0 v r pd pull?down resistance to ground (note 18) 50 200 k pin rxd v ol low level output voltage i sink = 2 ma 0.65 v v oh high level output voltage (in normal mode) normal mode, i source = ?2 ma v cc ? 0.65 v v r pu pull?up resistance to v cc (in standby and sleep mode) standby mode, sleep mode 5 10 15 k por and voltage monitor v bb_uv_th v bb undervoltage threshold (note 20) 3 4.2 4.75 v porl_v bb v bb por low level comparator ncv7420d23 2.5 4.2 v ncv7420d24 1.7 3.8 v v cc_uv_th v cc undervoltage threshold 2 3 v thermal shutdown t jsd thermal shutdown junction temperature for shutdown 165 195 c t jsd_hyst thermal shutdown hysteresis 9 18 c 17. the voltage drop in normal mode between lin and v bb pin is the sum of the diode drop and the drop at serial pull?up resistor. the drop at the switch is negligible. see figure 1. 18. by one of the trimming bits, following reconfiguration can be done during chip?level testing in order to fit the ncv7420?3 i nto different interface: pins txd and en will have typ. 10 k pull?down resistor to ground and pin wake will have typ. 10 a pull?up current source. 19. guaranteed by design. not tested. 20. v bb undervoltage threshold is always higher than v bb por low level (v bb_uv_th > porl_v bb ) 21. measured at output voltage v cc_out = (v cc_out @v bb = 5 v) ? 2%. 22. values based on design and characterization. not tested in production.
ncv7420 www. onsemi.com 11 table 8. dc characteristics ? 5 v version (v bb = 6 v to 26 v; t j = ?40 c to +150 c; bus load = 500 (v bb to lin); unless otherwise specified.) symbol parameter conditions min typ max unit supply ? pin v bb i bb_on supply current normal mode; lin recessive 1.6 ma i bb_stb supply current standby mode, v bb = 6?18 v, t j < 105 c 70 a i bb_slp supply current sleep mode, v bb = 6?18 v, t j < 105 c 20 a voltage regulator ? pin v cc v cc_out regulator output voltage v cc load 1 ma ? 30 ma 4.9 5.0 5.1 v v cc load 0 ma ? 50 ma 4.83 5.0 5.17 i out_max_abs absolute maximum output current thermal shutdown must be taken into account 50 ma i out_lim overcurrent limitation 50 100 170 ma v cc_out line regulation (note 28) v bb 6?26 v, i out = 5 ma, t j = 25 c 0.9 mv load regulation (note 28) i out 1?50 ma, v bb = 14 v, t j = 25 c 74 mv v do dropout voltage (v bb ?v cc_out ) figure 19 (notes 27, 28) i out = 1 ma, t j = 25 c 13 mv i out = 10 ma, t j = 25 c 136 mv i out = 50 ma, t j = 25 c 794 mv lin transmitter ? pin lin v lin_dom_losup lin dominant output voltage txd = low; v bb = 7.3 v 1.2 v v lin_dom_hisup lin dominant output voltage txd = low; v bb = 18 v 2.0 v v lin_rec lin recessive output voltage (note 23) txd = high; i lin = 10 a v bb ? 1.5 v bb v i lin_lim short circuit current limitation v lin = v bb_max 40 200 ma r slave internal pull?up resistance 20 33 47 k c lin capacitance on pin lin (note 25) 15 25 pf lin receiver ? pin lin symbol parameter conditions min typ max unit v bus_dom bus voltage for dominant state 0.4 v bb v bus_rec bus voltage for recessive state 0.6 v bb v rec_dom receiver threshold lin bus recessive dominant 0.4 0.6 v bb v rec_rec receiver threshold lin bus dominant recessive 0.4 0.6 v bb v rec_cnt receiver center voltage (vrec_dom + vrec_rec) / 2 0.475 0.525 v bb v rec_hys receiver hysteresis (vrec_rec ? vrec_dom) 0.05 0.175 v bb i lin_off_dom lin output current bus in dominant state driver off; v bb = 12 v; v lin = 0 v ?1 ma i lin_off_rec lin output current bus in recessive state driver off; v bb < 18 v v bb < v lin < 18 v 1 a 23. the voltage drop in normal mode between lin and v bb pin is the sum of the diode drop and the drop at serial pull?up resistor. the drop at the switch is negligible. see figure 1. 24. by one of the trimming bits, following reconfiguration can be done during chip?level testing in order to fit the ncv7420?5 i nto different interface: pins txd and en will have typ. 10 k pull?down resistor to ground and pin wake will have typ. 10 a pull?up current source. 25. guaranteed by design. not tested. 26. v bb undervoltage threshold is always higher than v bb por low level (v bb_uv_th > porl_v bb ) 27. measured at output voltage v cc_out = (v cc_out @v bb = 6 v) ? 2%. 28. values based on design and characterization. not tested in production.
ncv7420 www. onsemi.com 12 table 8. dc characteristics ? 5 v version (v bb = 6 v to 26 v; t j = ?40 c to +150 c; bus load = 500 (v bb to lin); unless otherwise specified.) symbol unit max typ min conditions parameter lin receiver ? pin lin i lin_no_gnd communication not affected v bb = gnd = 12 v; 0 < v lin < 18 v ?1 1 ma i lin_no_vbb lin bus remains operational v bb = gnd = 0 v; 0 < v lin < 18 v 5 a pin wake v wake_th threshold voltage 0.35 0.65 v bb i leak input leakage current (note 24) v wake = 0 v; v bb = 18 v ?1 ?0.5 1 a t wake_min debounce time sleep mode; rising and falling edge 8 54 s pins txd and stb v il low level input voltage 0.8 v v ih high level input voltage 2.0 v r pu pull?up resistance to v cc (note 24) 50 200 k pin inh delta_v h high level voltage drop i inh = 15 ma 0.35 0.75 v i leak leakage current sleep mode; v inh = 0 v ?1 1 a pin en v il low level input voltage 0.8 v v ih high level input voltage 2.0 v r pd pull?down resistance to ground (note 24) 50 200 k pin rxd v ol low level output voltage i sink = 2 ma 0.65 v v oh high level output voltage (in normal mode) normal mode, i source = ?2 ma v cc ? 0.65 v v r pu pull?up resistance to v cc (in standby and sleep mode) standby mode, sleep mode 5 10 15 k por and voltage monitor v bb_uv_th v bb undervoltage threshold (note 26) 3 4.2 4.75 v porl_v bb v bb por low level comparator ncv7420d25 2.5 4.2 v ncv7420d26 1.7 3.8 v v cc_uv_th v cc undervoltage threshold 3 4.5 v thermal shutdown t jsd thermal shutdown junction temperature for shutdown 165 195 c t jsd_hyst thermal shutdown hysteresis 9 18 c 23. the voltage drop in normal mode between lin and v bb pin is the sum of the diode drop and the drop at serial pull?up resistor. the drop at the switch is negligible. see figure 1. 24. by one of the trimming bits, following reconfiguration can be done during chip?level testing in order to fit the ncv7420?5 i nto different interface: pins txd and en will have typ. 10 k pull?down resistor to ground and pin wake will have typ. 10 a pull?up current source. 25. guaranteed by design. not tested. 26. v bb undervoltage threshold is always higher than v bb por low level (v bb_uv_th > porl_v bb ) 27. measured at output voltage v cc_out = (v cc_out @v bb = 6 v) ? 2%. 28. values based on design and characterization. not tested in production.
ncv7420 www. onsemi.com 13 ac characteristics ? 3.3 v and 5 v versions ? (v bb = 7 v to 18 v; t j = ?40 c to +150 c; unless otherwise specified.) table 9. ac characteristics lin transmitter ? pin lin symbol parameter conditions min typ max unit d1 duty cycle 1 = t bus_rec(min) / (2 x t bit ) see figure 23 normal slope mode th rec(max) = 0.744 x v bb th dom(max) = 0.581 x v bb t bit = 50 s v bb = 7 v to 18 v 0.396 0.5 d2 duty cycle 2 = t bus_rec(max) / (2 x t bit ) see figure 23 normal slope mode th rec(min) = 0.422 x v bb th dom(min) = 0.284 x v bb t bit = 50 s v bb = 7.6 v to 18 v 0.5 0.581 d3 duty cycle 3 = t bus_rec(min) / (2 x t bit ) see figure 23 normal slope mode th rec(max) = 0.778 x v bb th dom(max) = 0.616 x v bb t bit = 96 s v bb = 7 v to 18 v 0.417 0.5 d4 duty cycle 4 = t bus_rec(max) / (2 x t bit ) see figure 23 normal slope mode th rec(min) = 0.389 x v bb th dom(min) = 0.251 x v bb t bit = 96 s v bb = 7.6 v to 18 v 0.5 0.590 t trx_prop_down propagation delay of txd to lin. txd high to low (note 29) 6 s t trx_prop_up propagation delay of txd to lin. txd low to high (note 29) 6 s t fall_norm lin falling edge normal slope mode; v bb = 12 v; l1, l2 (note 30) 22.5 s t rise_norm lin rising edge normal slope mode; v bb = 12 v; l1, l2 (note 30) 22.5 s t sym_norm lin slope symmetry normal slope mode; v bb = 12 v; l1, l2 (note 30) ?4 4 s t fall_norm lin falling edge normal slope mode; v bb = 12 v; l3 (note 30) 27 s t rise_norm lin rising edge normal slope mode; v bb = 12 v; l3 (note 30) 27 s t sym_norm lin slope symmetry normal slope mode; v bb = 12 v; l3 (note 30) ?5 5 s t fall_low lin falling edge low slope mode (note 31); v bb = 12 v; l3 (note 30) 62 s t rise_low lin rising edge low slope mode (note 31); v bb = 12 v; l3 (note 30) 62 s t wake dominant timeout for wake?up via lin bus 30 150 s t dom txd dominant timeout txd = low 6 20 ms 29. values based on design and characterization. not tested in production. 30. the ac parameters are specified for following rc loads on the lin bus: l1 = 1 k / 1 nf; l2 = 660 / 6.8 nf; l3 = 500 / 10 nf. 31. low slope mode is not compliant to the lin standard.
ncv7420 www. onsemi.com 14 regulator typical performance characteristics ? 3.3 v version load transient responses figure 7. load transient response (i cc 100 a to 50 ma) figure 8. load transient response (i cc 1 ma to 50 ma) time (500 s/div) time (500 s/div) 1 50 load current (ma) load current (ma) 0.1 50 v cc (20 mv/div) v cc (20 mv/div) t rise , t fall = 10 s v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r t rise , t fall = 10 s v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r line transient responses figure 9. line transient response (v bb 5 v to 26 v) figure 10. line transient response (v bb 5 v to 26 v) time (2 ms/div) time (1 ms/div) 10 30 input voltage (v) input voltage (v) 10 30 v cc (50 mv/div) v cc (20 mv/div) t rise , t fall = 10 s 0 20 0 20 i cc = 5 ma c vcc = 10 f t rise , t fall = 10 s i cc = 100 a c vcc = 10 f
ncv7420 www. onsemi.com 15 regulator typical performance characteristics ? 3.3 v version static characteristics figure 11. dropout voltage vs. temperature figure 12. output voltage vs. output current temperature ( c) i cc output current (ma) 125 100 75 50 25 0 ?25 ?50 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 45 35 30 20 15 10 5 0 3.24 3.25 3.26 3.27 3.28 3.29 3.31 3.32 dropout voltage (v) v cc output voltage (v) 150 c vcc = 10 f x7r 50 ma 25 ma 10 ma 25 40 50 3.30 ?40 c 25 c 85 c 135 c 150 c v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r (porl_vbb reached at low temperatures) figure 13. ground current vs. output current figure 14. output voltage vs. temperature i cc output current (ma) temperature ( c) 45 35 30 25 20 10 5 0 0 20 60 80 100 140 160 200 125 100 75 50 25 0 ?25 ?50 3.24 3.25 3.26 3.27 3.28 3.30 3.31 3.32 i bb ?i cc ( a) v cc output voltage (v) 15 40 50 40 120 180 v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r standby mode t = 25 c 150 3.29 50 ma 25 ma 10 ma 1 ma v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r
ncv7420 www. onsemi.com 16 regulator typical performance characteristics ? 5 v version load transient responses figure 15. load transient response (i cc 100 a to 50 ma) figure 16. load transient response (i cc 1 ma to 50 ma) time (500 s/div) time (500 s/div) 1 50 load current (ma) load current (ma) 0.1 50 v cc (50 mv/div) v cc (50 mv/div) t rise , t fall = 10 s v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r t rise , t fall = 10 s v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r line transient responses figure 17. line transient response (v bb 6 v to 26 v) figure 18. line transient response (v bb 6 v to 26 v) time (2 ms/div) time (1 ms/div) 10 30 input voltage (v) input voltage (v) 10 30 v cc (50 mv/div) v cc (20 mv/div) t rise , t fall = 10 s 0 20 0 20 i cc = 5 ma c vcc = 10 f t rise , t fall = 10 s i cc = 100 a c vcc = 10 f
ncv7420 www. onsemi.com 17 regulator typical performance characteristics ? 5 v version static characteristics figure 19. dropout voltage vs. temperature figure 20. output voltage vs. output current temperature ( c) i cc output current (ma) 125 100 75 50 25 0 ?25 ?50 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 45 35 30 20 15 10 5 0 4.93 4.94 4.95 4.97 4.98 4.99 5.02 5.03 dropout voltage (v) v cc output voltage (v) 150 c vcc = 10 f x7r 50 ma 25 ma 10 ma 25 40 50 5.00 ?40 c 25 c 85 c 135 c 150 c v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r 4.96 5.01 figure 21. ground current vs. output current figure 22. output voltage vs. temperature i cc output current (ma) temperature ( c) 45 35 30 25 20 10 5 0 0 20 60 80 100 140 160 200 125 100 75 50 25 0 ?25 ?50 4.93 4.94 4.95 4.97 4.98 5.00 5.02 5.03 i bb ?i cc ( a) v cc output voltage (v) 15 40 50 40 120 180 v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r standby mode t = 25 c 150 4.99 50 ma 25 ma 10 ma 1 ma v bb = 14 v c vbb = 10 f + 100 nf c vcc = 10 f x7r 4.96 5.01
ncv7420 www. onsemi.com 18 t bus_dom(min) lin t th rec(max) th rec(min) th dom(max) th dom(min) t bus_dom(max) t bus_rec(max) t bus_rec(min) t bit t bit 50% thresholds of receiving node 1 thresholds of receiving node 2 txd t figure 23. lin transmitter duty cycle figure 24. lin transmitter timing 50% txd lin t t t trx_prop_up t trx_prop_down t bit t bit 60% v bb 40% v bb v bb lin t 60% 40% 60% 40% 100% 0% figure 25. lin transmitter rising and falling times t rise t fall
ncv7420 www. onsemi.com 19 table 10. ac characteristics lin receiver symbol pin lin parameter conditions min typ max unit t rec_prop_down propagation delay of receiver falling edge 0.1 6 s t rec_prop_up propagation delay of receiver rising edge 0.1 6 s t rec_sym propagation delay symmetry t rec_prop_down ? t rec_prop_up ?2 2 s figure 26. lin receiver timing 50% t rec_prop_up rxd t lin t t rec_prop_down v bb 60% v bb 40% v bb ordering information part number description temperature range package shipping ? ncv7420d23g lin transceiver + 3.3 v vreg. ?40 c to 125 c soic?14 (pb?free) 55 / tube/rail ncv7420d23r2g lin transceiver + 3.3 v vreg. 3000 / tape & reel NCV7420D24G emc/esd improved lin transceiver + 3.3 v vreg. 55 / tube/rail ncv7420d24r2g emc/esd improved lin transceiver + 3.3 v vreg. 3000 / tape & reel ncv7420d25g lin transceiver + 5 v vreg. 55 / tube/rail ncv7420d25r2g lin transceiver + 5 v vreg. 3000 / tape & reel ncv7420d26g emc/esd improved lin transceiver + 5 v vreg. 55 / tube/rail ncv7420d26r2g emc/esd improved lin transceiver + 5 v vreg. 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv7420 www. onsemi.com 20 package dimensions soic 14 case 751ap issue b 7.00 14x 0.76 14x 1.52 1.27 dimensions: millimeters 1 pitch *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* recommended notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.004 mm in excess of maximum material condition. 4. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006 mm per side. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.010 mm per side. 5. the package top may be smaller than the package bot- tom. dimensions d and e1 are determined at the outer- most extremes of the plastic body at datum h. 6. dimensions a and b are to be determined at datum h. 7. dimensions b and c apply to the flat section of the lead between 0.10 to 0.25 from the lead tip. 8. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. 17 14 8 seating plane detail a 0.10 c a1 dim min max millimeters h 0.25 0.41 a --- 1.75 b 0.31 0.51 l 0.40 1.27 e 1.27 bsc c 0.10 0.25 a1 0.10 0.25 l2 m 0.25 a-b b 14x c d a b c top view side view 0.25 bsc e1 3.90 bsc e 6.00 bsc d e d 0.20 c 0.10 c 2x 2x note 6 notes 4&5 notes 4&5 side view end view e e1 d 0.10 c d d notes 3&7 note 6 note 8 a a2 a2 1.25 --- d 8.65 bsc h seating plane detail a l c l2 h 45 chamfer c note 7 p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncv7420/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.

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