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mic24046 pin - programmable, 4.5v ? 19v, 5a step - down converter micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com october 14 , 2015 revision 1. 1 general description the mic24046 is a pin - programmable, high C efficiency, wide input range, 5a synchronous step - down regulator. the mic24046 is perfectly suited for multiple - voltage rail application environments typically found in computing and telecommunication systems . it can be programmed by pin strapping various parameters , such as output voltage, switching frequency, and current - limit val ues . the pin - selectable switching frequency, valley - current mode control technique, high C performance error amplifier, and external compen sation allow for the best trade - offs between high efficiency and the smallest possible solution size. the mic24046 is a vailable in a thermally C efficient, space - saving , 20 C pin 3mm 3mm qfn package with an operating junction temperature range of C 40 c to +125 c. datasheets and support documentation are available on micrels website at : www.micrel.com . features ? 4.5 v to 19 v input voltage range ? 5a (maximum) output current ? high efficiency (>90%) ? pin - selectable output voltage s: ? 0. 7v , 0.8v, 0.9v, 1.0v, 1.2v, 1.5v, 1.8v, 2.5v, and 3.3v ? 1% output voltage accuracy ? supports safe start - up with pre - biased output ? pin - selectable current limit and switching frequency ? internal soft - start and thermal shutdown protection ? hiccup - mode s hort - circuit protection ? available in a 20 - pin 3 mm 3 mm qfn package ? C 40c to +125c junction temperature range applications ? servers, data storage, routers, and base stations ? fpgas, dsp, and low - voltage asic power typical application mic24046 12v in 5a dc/dc converter downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 2 revision 1. 1 ordering information part number junction temperature range package lead finish mic24046yfl C 40c to +125c 20 C pin 3 mm 3 mm qfn pb-free pin configuration 20 C pin 3mm 3mm qfn (fl) (top view) pin description pin number pin name pin function 1 ? 2 vin input voltage for the buck converter power stage: these pins are the drain terminal of the inter nal high - side n - channel mosfet. a 10 f minimum ceramic capacitor should be connected from vin to pgnd as close as possible to the device. a combination of multiple ceramic capacitors of different sizes is recommended. 3 ? 4, 13 pgnd low - side mosfet source terminal and low - side driver return: connect the ceramic input capacitors to pgnd as close as possible to the dev ice. 5 ? 6 lx switch node: drain (low - side mosfet) and source (high - side mosfet) connection of the internal power n - channel fets. the external inductor (switched side) and bootstrap capacitor (bottom terminal) must be connected to these pins. 7 bst bootstrap: supply voltage for the driver of the high - side n - channel power mosfet. connect the bootstrap capacitor (top terminal) to this pin. 8 pg power good (output): when the output voltage is within 92.5% of the nominal set point, this pin w ill go from logic low to logic high through an external pull - up resistor. this pin is the drain connection of an internal n - channel fet . 9 voset0 three - state pin (low, high, and high - z) for output voltage programming : together with voset1, voset0 defines nine logi c values corresponding to nine output voltage selections. 10 voset1 three - state pin ( low, high, and high - z) for output voltage programming: together with voset0, voset1 defines nine logic values corresponding to nine output voltage selections. downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 3 revision 1. 1 pin description (continued) pin number pin name pin function 11 ilim three - state ( low, high , and high -z ) current - limit selection pin . 12 freq three - state (low, high , and high - z) switching frequency selection pin . 14 a gnd analog ground: quiet ground for the analog circuitry of the internal regulator and return termina l for the external compensation network. 15 comp transconductance error amplifier output : connect a compensation network from this pin to agnd . 16 outsns output sensing : connect this pin directly to the buck converter output voltage. this pin is the top side terminal of the internal feedback divider. 17 en/dly precision enable/turn - on delay input. the en/dly pin is first compared against a 507 mv threshold to turn - on the on - board ldo regulator. the en/dly pin is then compared against a 1.21v (typical) threshold to initiate output power delivery. a 150mv typical hysteresis prevents chatteri ng when power delivery is started. a 2a (typical) current source pulls up the en/dly pin. turn - on delay can be achieved by connecting a capacitor from en/dly to ground, while using an open - drain output to drive the en/dly pin. 18 vdda output of the internal linear regulator and internal supply for analog control. a 1f minimum c eramic capacitor should be connected from this pin to agnd; 2.2f nominal value recommended. 19 vddp internal supp ly rail for the mosfet drivers ( fed by the vdda pin ): an internal resistor (10?) between pins vddp and vdda is provided in the regulator in order to implement an rc filter fo r switching noise suppression. a 1f minimum ceramic capacitor should be connected from this pin to pgnd; 2.2f nominal value recommended. 20 vinldo input o f the internal linear regulator: this pin is typically connected to the input voltage of the buck converter stage (vin). if vinldo and vin are connected to different voltage rails, indi vidually bypass vinldo to ground with a 100nf ceramic capacitor. pgnd_ep pgn d pgnd exposed pad: electrically connected to pgnd pins. connect with thermal vias to the ground plane to ensure adequate heat - sinking. follow recommendations as illustrated in the pcb layout recommendations section vin_ep vin vin exposed pad : electrically connected to vin pins. if an input power distribution plane is available, connect with thermal vias to that plane to improve heat - sinking. follow recommendations as illustrated in the pcb layout recommendations section lx_ep lx lx exposed pad: electrically connected to lx pins. follow recommendations as illustrated in the pcb layout recommendations section downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 4 revision 1. 1 absolute maximum ratings ( 1 ) v vin , v vinldo to agnd ................................... ? 0.3v to + 20 v v vddp , v vdda t o agnd ..................................... ? 0.3v to +6v v vinldo to v vdda ............................................. ? 0.3v to +20 v v vddp to v vdda ............................................... ? 0.3v to +0.3v v vosetx , v freq , v ilim , t o a gnd ......................... ? 0.3v to +6v v bst to v lx ....................................................... ? 0.3v to + 6v v bst to agnd ................................................ ? 0.3v to +26 v v en/dly to a gnd ........................ ? 0.3v to v vdda + 0.3v, +6v v pg to a gnd ................................................... ? 0.3v to +6v v comp , v outsns to a gnd ........... ? 0.3v to v vdda + 0.3v, +6v a gnd to pgnd ............................................ ? 0.3v to +0.3v junction temperature .............................................. +150 c storage temperature (t s ) ......................... ? 65 c to +150 c lead temperature (soldering, 10s) ............................ 260 c esd ratin g ( 4 ) hbm ......................................................................... 2kv mm ......................................................................... 150v operating ratings ( 2 ) supply voltage ( v vin , v vi nldo ) ........................... 4.5 v to 19 v externally applied analog and drivers supply voltage (v vinldo = v vdda = v vddp ) .................................. 4.5 v to 5.5 v enable voltage ( v en/dly ) .................................... 0v to v vdda power - good (pg) pull - up voltage (v pu_pg ) ........ 0v to 5.5v output current ................................................................ . 5a junction temperature (t j ) ........................ ? 40 c to +125 c junction to ambient thermal resistance 20 - pin 3mm 3mm qfn ( ja ) ( 3 ) ........................ 29 c/w electrical characteristics ( 5 ) v vi n = v vi nldo = 12 v; c vdda = 2.2 f, c vddp = 2.2 f, t a = 25 c, unless otherwise noted. bold values indicate ? 40 c t j +125 c. symbol parameter test conditions min . typ . max . units vin supply vin input range 4.5 19 v ivin q disable current en/dly = 0v 0.2 2 a ivin ldo q disable current en/dly = 0v t a = t j = 25c 35 42 a ? 40c t j +125c 56 ivinop operating current en/dly > 1.28v , outsns = 1.15 v out(nom) , n o switching , t a = t j = 25c 0.45 0.75 ma ivinldo op operating current en/dly > 1.28v , outsns = 1.15 v out(nom) , n o switching , t a = t j = 25c 5. 6 7 ma vdda 5v supply vdda operating voltage en/dly > 0.58v , i (vdda) = 0ma to 10ma 4.8 5.1 5.4 v dropout operation v inldo = 4 .5 v, en/dly > 0.58v , i (vdda) = 10ma 3.6 3. 75 v vdda undervoltage lockout uvlo_r vdda uvlo rising v vd da rising, en/dl y > 1.28v 3.1 3. 5 3.9 v uvlo_f vdda uvlo falling v vd da falling, en/dly > 1.28v 2.87 3. 2 3.45 v uvlo_h vdda uvlo hysteresis 300 mv notes: 1. exceeding the absolute maximum ratings may damage the device. 2. the device is not guaranteed to function outside operating range. 3. ja is measured on the mic24046 evaluation board . 4. devices are esd sensitive. handling precautions recommended. human body model, 1.5k ? in series with 100pf. 5. specification for packaged product only. downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 5 revision 1. 1 electrical characteristics ( 5 ) (continued) v vi n = v vi nldo = 12 v; c vdda = 2.2 f, c vddp = 2.2 f, t a = 25c, unless otherwise noted. bold values indicate ? 40c t j +125c . symbol parameter test conditions min . typ . max . units en/dly control en_ldo_r ldo enable threshold turns on vdda ldo 507 580 mv en_ldo_f ldo disable threshold turns off vdda ldo 460 491 mv en_ldo_h ldo threshold hysteresis 16 mv en_r en/dly rising threshold initiates power - stage operation 1.14 1.21 1.28 v en_f en/dly falling threshold stops power - stage operation 1.0 6 v en_h en /dly hysteresis 150 mv en_i en /dly pull- up current t a = t j = 25c 1 2 3 a switching frequency f sz programmable frequency (high z) freq = high z (open) 360 400 440 khz f s0 programmable frequency 0 freq = low (gnd) 500 5 65 630 khz f s1 programmable frequency 1 freq = high (vdda) 700 790 880 khz over current protection i lim_hs0 hs current limit 0 i lim = low (gnd) 6.0 7.1 8.1 a i lim_hs1 hs current limit 1 i lim = high (vdda) 8.1 9.3 10.3 a i lim_hsz hs current limit high z i lim = high z (open) 9.3 10.5 11. 9 a leb top fet current - limit leading edge - blanking time 108 ns i lim_ls0 ls current limit 0 i lim = low (gnd) 3.0 4. 6 6. 3 a i lim_ls1 ls current limit 1 i lim = high (vdda) 4.0 6.2 7. 9 a i lim _ lsz ls current limit hi z i lim = high z (o pen) 5.0 6.8 8.6 a in hicc _ de oc events count for hiccup number of subsequent cycles in current limit before entering hiccup overload protection . 15 clock c ycles t hicc _ wait hiccup wait time duration of the high - z state on lx before new soft -start. 3 x soft-start time power switches r bottom bottom fet on resistance v v in = v vi nldo = v v ddp = v v dda = 5v , v bst -v lx = 5v , t a = t j = 25c 16 21 m? r top top fet on resistance v vi n = v vi nldo = v vd dp = v vd da = 5v, v bst -v lx = 5v , t a = t j = 25c 38 50 m? pulse- width modulation (pwm) t on(min) minimum lx on time t a = t j = 25c 26 ns t off(min) minimum lx off time v vi n = v vi nldo = v vd da = 5v, v outsns = 3v , freq = open (400 khz setting), v v oset0 = v v oset1 = 0v (3.3v setting), t a = t j = 25c 90 1 35 190 ns d min min imum duty cycle v outsns >1.1 v out(nom) 0 % downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 6 revision 1. 1 electrical characteristics ( 5 ) (continued) v vi n = v vi nldo = 12 v; c vdda = 2.2 f, c vddp = 2.2 f, t a = 25c, unless otherwise noted. bold values indicate ? 40c t j +125c . symbol parameter test conditions min . typ . max . units gm error amplifier gm ea error- amplifier transconduct ance 1. 5 m mho a ea error- amplifier dc gain 50000 v/v i sr_snk error- amplifier source/sink current ? 4 00 +4 00 a comp_h comp output swing high 2.4 v comp_l comp output swing low 0.8 v gm ps com p- to - inductor current transconduct ance v out = 1.2v, i out = 4a 12.5 a/v output voltage dc accuracy outerr12 output voltage accuracy for ranges 1 and 2 4.75 v v in 19v, v out = 0.7v to 1.8v t a = t j = ? 40c to 125c, i out = 0a ? 1 1 % outerr3 output voltage accuracy for range 3 4.75 v v in 19v, v out = 2.49v to 3.3v t a = t j = ? 40c to 125c, i out = 0a ? 1.5 1.5 % loadreg load regulation i out = 0a to 5 a 0.25 % linereg line regulation 6v< v in < 19v, i out = 2a 0.1 % internal soft - start ss_sr reference soft - start slew rate v out = 0.7v, 0.8v, 0.9v, 1.0v, 1.2v 0.45 v/ms power good (pg) pg_v ol pg low voltage i (pg) =4ma 0.18 0.4 v pg_i leak pg leakage current v pg =5v -1 0.02 1 a pg_r pg rise threshold v out rising 90 92.5 95 % pg_f pg fall threshold v out falling 87.5 90 92.5 % pg_r_dly p g rise delay v out rising 0. 45 ms pg_f_dly p g fall delay v out falling 70 s thermal shutdown t shdn thermal shutdown 160 c t shdn_hyst thermal - shutdown hysteresis 25 c efficiency efficiency v in = 12v, v out = 0.9v, i out = 2a f s = f sz = 400khz, l = 1.2h, t a = 25c 82.3 % downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 7 revision 1. 1 typical characteristics v vi n = v vi nldo = 12 v; c vdda = 2.2 f, c vddp = 2.2 f, t a = 25c, unless otherwise noted. 10 11 12 13 14 15 16 17 18 19 20 4 6 8 10 12 14 16 18 20 operating current (ma) input voltage (v) operating current (i q ) vs. input voltage switching v out = 1.0v i out = 0a f = 790khz f = 565khz f = 400khz 4.1 4.3 4.5 4.7 4.9 5.1 5.3 4 6 8 10 12 14 16 18 20 vdd voltage (v) input voltage (v) vdd voltage vs. input voltage i vdda = 0ma i vdda = 10ma 3 4 5 6 7 8 9 10 4 6 8 10 12 14 16 18 20 low - side current limit (a) input voltage (v) low - side current limit vs. input voltage v out = 1.2v l = 2.2h i lim = hi -z i lim = vdda i lim = gnd 0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 4 6 8 10 12 14 16 18 20 enable threshold (v) input voltage (v) enable threshold vs. input voltage enable rising enable falling 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 4 6 8 10 12 14 16 18 20 en/dly (a) input voltage (v) en/dly pull - up current vs. input voltage en/dly = 0v 10 11 12 13 14 15 16 17 18 19 20 -40 -20 0 20 40 60 80 100 120 140 operating current (ma) temperature ( c) operating current (i q ) vs. temperature switching v in = 12v v out = 1.0v i out = 0a f = 790khz f = 565khz f = 400khz 5 15 25 35 45 55 65 -40 -20 0 20 40 60 80 100 120 140 fet on resistance (m ? ) temperature ( c) fet on resistance vs. temperature v in = 12v r top r bottom 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -40 -20 0 20 40 60 80 100 120 140 ea transconductance (ms) temperature ( c) ea transconductance vs. temperature v in = 12v v out = 1.0v -800 -600 -400 -200 0 200 400 600 800 -40 -20 0 20 40 60 80 100 120 140 ea output current (a) temperature ( c) ea output current vs. temperature v in = 12v sinking sourcing downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 8 revision 1. 1 typical characteristics (continued) v vin = v vinldo = 12 v; c vdda = 2.2 f, c vddp = 2.2 f, t a = 25c, unless otherwise noted. 40 50 60 70 80 90 100 0 1 2 3 4 5 6 efficiency (%) output current (a) efficiency (vin = 12v) vs. output current v in = 12v l = 2.2h v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v v out = 1.0v v out = 0.9v v out = 0.8v v out = 0.7v 40 50 60 70 80 90 100 0 1 2 3 4 5 6 efficiency (%) output current (a) efficiency (vin = 5.0v) vs. output current v in = 5.0v l = 2.2h v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v v out = 1.0v v out = 0.9v v out = 0.8v v out = 0.7v 0.88 0.885 0.89 0.895 0.9 0.905 0.91 0 1 2 3 4 5 output voltage (v) output current (a) output voltage (v out = 0.9v) vs. output current v in = 12v v out = 0.9v 0.98 0.985 0.99 0.995 1 1.005 1.01 0 1 2 3 4 5 output voltage (v) output current (a) output voltage (v out = 1.0v) vs. output current v in = 12v v out = 1.0v 1.18 1.185 1.19 1.195 1.2 1.205 1.21 0 1 2 3 4 5 output voltage (v) output current (a) output voltage (v out = 1.2v) vs. output current v in = 12v v out = 1.2v 1.48 1.485 1.49 1.495 1.5 1.505 1.51 1.515 1.52 0 1 2 3 4 5 output voltage (v) output current (a) output voltage (v out = 1.5v) vs. output current v in = 12v v out = 1.5v 1.78 1.785 1.79 1.795 1.8 1.805 1.81 1.815 1.82 0 1 2 3 4 5 output voltage (v) output current (a) output voltage (v out = 1.8v) vs. output current v in = 12v v out = 1.8v 2.45 2.46 2.47 2.48 2.49 2.5 2.51 2.52 0 1 2 3 4 5 output voltage (v) output current (a) output voltage (v out = 2.5v) vs. output current v in = 12v v out = 2.5v (2.49v) 3.26 3.27 3.28 3.29 3.3 3.31 3.32 3.33 0 1 2 3 4 5 output voltage (v) output current (a) output voltage (v out = 3.3v) vs. output current v in = 12v v out = 3.3v downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 9 revision 1. 1 functional characteristics v vi n = v vi nldo = 12 v; c vdda = 2.2 f, c vddp = 2.2 f, t a = 25 c, unless otherwise noted. downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 10 revision 1. 1 functional characteristics (continued) v vi n = v vi nldo = 12 v; c vdda = 2.2 f, c vddp = 2.2 f, t a = 25 c, unless otherwise noted. downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 11 revision 1. 1 functional characteristics (continued) v vin = v vinldo = 12 v; c vdda = 2.2 f, c vddp = 2.2 f, t a = 25c, unless otherwise noted. downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 12 revision 1. 1 functional diagram downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 13 revision 1. 1 functional description the mic24046 is a pin - programmable, 5a valley current - mode controlled regulator featuring an input voltage range from 4.5v to 19v. the mic24046 requires a minimal amount of external components. only the inductor, supply decoupling capacitors , and compensation network are external. the flexibility in the external compensation design allows the user to optimize the ir design across the entire input voltage and selectable output voltages range. theory of operation valley - current - mode control is a fixed - frequency, leading - e dge modulated pwm current - mode control. differing from the peak - current - mode, the valley - current - mode clock marks the turn - off of the high - side switch. upon this instant, the mic24046 low - side switch current level is compared against the reference current signal from the error amplifier. when the falling low - side switch current signal drops below the current reference signal, the high side switch is turned on. as a result, the inductor valley current is regulated to a level dictated by the output of the error amplifier. as shown in the , compensation design sub - section within the application information section , the feedback loop includes an internal programmable reference ( ref dac ) and output voltage sensing attenuator ( r2/r1 ), which removes the need for external feedback components and improves regulation accuracy. output voltage feedback is achieved by connecting outsns directly to the output. the high - performance transconductance error amplifier drives an external compensation network at the comp pin. the comp pin voltage represents the reference current signal. the comp pin voltage is fed to the valley - current - mode modulator, which also adds slope compensation to guarantee current - loop stability. valley - current - mode control requires slope compensation at duty c ycles less than 50% for current - loop stability. the slope compensation circuit is internal, and it is automatically adapted in amplitude depending upon the frequency, out put voltage range, and voltage di fferential (v vin ? v outsns ) . the i nternal low -r ds(on) power mosfets, associated adaptive gate driver , and internal bootstrap diode complete the power train. overcurrent protection and thermal shutdown protect the mic24046 from faults or abnormal operating conditions. inter nal ldo, supply rails (vin, vinldo, vdda, vddp) vin represent s the power train input. these pins are the drain connection of the internal high - side mosfet and should be bypassed to gnd with a n x5r or x7r 10 f (minimum) ceramic capacitor, placed as close as possible to the ic. a combination of ceramic capacitors of different sizes is recommended. an internal ldo (input = vinldo) provides a clean voltage supply (5.1v typ.) for the analog circuits at pin vdda. the internal ldo is typically powered from the same power rail fe e d a s vin; however , vinldo can also be higher or lower than vin , and can be connected to any other voltage within its recommended limits. vinldo and vdda should be locally bypassed (see pin description ) . a small series resistor (typically 2 ? - 10 ? ) can be used in combination with the vinldo bypass capacitor to implement a rc filter for suppression of la rge high - frequency switching noise. the internal ldo is enabled when the voltage at the en/dly pin exceeds about 0. 51 v, and regulation takes place as soon as enough voltage has established between the vinldo and vdda pins. if an external 5v10% is availabl e, it is possible to bypass the internal ldo by connecting vinldo, vdda and vddp together at the external 5v rail, thus improving overall efficiency. an internal under voltage lock - out circuit (uvlo) monitors the level of vdda. vddp is the power supply rail for the gate drivers and bootstrap circuit. this pin is subject to high - current spike with high - frequency content. to prevent these from polluting the analog vdda supply, a separate capacitor is needed for vddp pin bypassing. an internal 10 re sistor is provided between vdda and vddp allowing a switching noise attenuation rc filter with the minimum amount of external components to be implemented . it is possible ? although typically not necessary ? to lower the rc time constant by connecting an external resistor between vdda and vddp. pin - strapping programmability (voset0, voset1, freq, ilim) the mic24046 uses pin - strapping to set the output voltage ( pins voset0, voset1), switching frequency ( pin freq) , and current limit ( pin ili m). no external passives are needed, such that external component count is minimized. each pin is a three - state input (connect to gnd for low logic level , connect to vdda for high logic level or leave unconnected for high - z). the logic level of the pins is read and frozen in the internal configuration logic immediately after the vdda rail has come up and stabilized. after this instant, any change of the input logic level on the pins will have no effect until the vdda power is cycled again. the values corres ponding to each particular pin - strapping configuration are detailed in the application information section . downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 14 revision 1. 1 enable/delay (en/dly) en/dly is a dual - threshold pin that turns the internal ldo on and off, and starts/stops the power delivery to the output. this is shown i n figure 1 : figur e 1 . en/dly pin functionality the threshold for power delivery (en_r) is a precise 1.21v 70mv. a 150mv typical hysteresis prevents chattering due to switching noise and/or slow edges. a 2a typical pull - up current with 1a accuracy permits the implementation of a start - up delay by means of an external capacitor. in this case, it is necessary to use an open - drain driver to disable the mic24046 while maintaining the start - up delay functi on. power - good (pg) pg is an open - drain output that requires an external pull - up resistor to a pull - up voltage (v pu_pg ) less than 5.5v for being asserted to a logic high level . pg is asserted with a typical delay of 0. 4 5ms when the output voltage (outsns) reaches 92.5% of its target regulation voltage. pg is de - asserted with a typical delay of 70 s when the output voltage falls below 90% of its target regulation voltage. the pg falling delay acts as a de - glitch timer against very short spikes. the pg output is always immediately de - asserted w hen the en/dly pin is below the power delivery enable threshold (en_r/en_f). the pull - up resistor should be large enough to limit the pg pin current to below 2ma . induct or (lx) and bootstrap (bst) the external inductor is connected to lx. the high - side mosfet driver circuit is powered between bst and lx by means of an external capacitor (typically 100nf) that is replenished from rail vddp during the low - side mosfet on - time. the bootstrap diode is internal. output sensing (outs ns) and compensation (comp) outsns should be connected exactly to the desired point - of - load regulation avoiding parasitic resistive drops. the impedance seen into outsns is high (tens of k or more, depending on the selected output voltage value ), therefore its loading effect is typically negligible. outsns is also used by the slope compensation generator. comp is the connection for the external compensation network. comp is driven by the output of the transconductance error amplifier. care must be taken to return the compensation network ground directly to agnd . soft - start the mic24046 internal reference is ramped up at a 0.45 v/ms rate. note that this is the internal reference soft - start slew rate and that the actual slew rate seen at the output should take into account the internal divider attenuation as detailed in the application information section. switching frequency (freq) the mic24046 features three different se lectable switching frequencies: 400khz, 565khz, and 790khz . pre - biased output start -up the mic24046 is designed to achieve safe start - up into a pre - biased output without discharging the output capacitors. thermal shutdown the mic24046 has thermal - shutdown protection that prevents operation at excessive temperature. the thermal - shutdown threshold is typically set at 160 c with a hysteresis of 25c. overc urrent protection (ilim) and hiccup mode short - circuit protection the mic24046 features instantaneous cycle - by - cycle current limit with current sensing on both low - side and high - side switches . it also offers a hiccup mode for prol onged overloads or short - circuit conditions. low - side cycle - by - cycle protection detects the current level of the inductor current during the low - side mosfet on time. the high - side mosfet turn - on is inhibited as long as the low - side mosfet current limit is above the current - limit threshold level. the inductor current will continue decaying until the current falls below the threshold, where the high - side mosfet will be enabled again according to the duty cycle requirement from the pwm modulator. the mechanism is illustrated in figure 2 . downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 15 revision 1. 1 figure 2 . low - side cycle - by - cycle current - limit action the low - side current limit has three different programmable levels ( for 3a, 4a, and 5a loads) , in order to fit different application re quirements . s ince the low - side current limit acts on the valley current, the dc output current level (i out ) where the low - side cycle - by - cycle current limit is engaged will be higher than the current limit v alue by an amount equal to il pp /2 , where il pp is the peak - to - peak inductor ripple current. the high - side current limit is approximately 1. 4 ? 1.5 times great er than the low - side current limit (typical values) . the high - side cycle - by - cycle current limit immediately truncates the high - side on time without waiting for the off clocking event. a leading edge blanking (leb) timer (108ns, typical ) is provided on the high - side cycle - by - cycle current limit to mask the switching noise and to prevent false ly triggering the protection. h igh - side cycle - by - cycle current limit action cannot take place b efore the leb timer expire s. hiccup mode protection reduces power dissipation in permanent short - circuit conditions. on each clock cycle where a low - side cycle - by - cycle current - limit event is detected, a 4- bit up/down counter is incremented. on each clock cycle , without a concurrent low - side current limit event, the counter is decremented or left at zero . the counter cannot wrap - around below 0000 and above 1111. hi gh - side current limit events do not increment the counter . o nly detections from low - side current limit event s trigger the counter . if the counter reaches 1111 ( or 15 events), the high - and low - side mosfets become t ri - stated , and power delivery to the output is inhibited for the duration of three times the soft - start time. this digital integration mechanism provides immunity to momentary overloading of the output. after the wait time, the mic24046 retries entering operation and initiates a new soft - start sequence. figure 3 illustrates the hiccup mode shor t- circuit protection logic flow. note tha t hiccup mode short - circuit protection is active at all times, including the soft - start ramp. downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 16 revision 1. 1 figure 3 . hiccup mode short - circuit protection logic downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 17 revision 1. 1 application information programming start - up delay and external uvlo the en/dly pin allows programming of an external start - up delay. in this case, the driver for the en/dly pin should be an open - drain /open - collector type as shown in figure 4 : figure 4 . programmable start- up delay function the start - up delay is the delay time from the off falling edge to the assertion of the enable power delivery signal and can be calculated as shown in equation 1 : i_ en c r_ en t dly dly _ su = eq. 1 where: en_r = 1.21v en_i = 2a c dly = d elay programming external capacitor the en/dly pin can also be used to program an uvlo threshold for power delivery by means of an external resistor divider, as described in the following figure 5 . figure 5 . programmable external uvlo function the programmed v in uvlo threshold v in_rise is given by: 2r i_ en 1r 2r 1 r_ en v rise _in ? ?? ? ?? ? + = eq. 2 where: en_r = 1.21v en_i = 2a r1 and r2 = external resistors. to desensitize the v in uvlo threshold against variations of the pull - up current en_i, it is recommended to run the r1 ? r2 voltage divider at a significantly higher current level than the en_i current. the corresponding v in uvlo hysteresis vin_hys is calculated as follows : ?? ? ?? ? + ? = 1r 2r 1 mv 150 v hys _in eq. 3 similar calculations also apply to the internal ldo activation threshold. setting the switching frequency the mic24046 switching frequency can be programmed using freq as shown in table 1 : table 1 . switching frequency settings freq frequency hi -z (open) 400khz 0 (gnd) 565 khz 1 (vdda) 79 0khz downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 18 revision 1. 1 setting the output voltage the mic24046 output voltage can be programmed by setting pins voset0 and voset1 , as shown in table 2 . table 2 . output voltage settings voset1 voset0 output voltage 0 (gnd) 0 (gnd) 3.3v 0 (gnd) 1 (vdda) 2.5 v (2.49v) 1 (vdda) 0 (gnd) 1.8v 1 (vdda) 1 (vdda) 1.5v 0 (gnd) hi -z ( open ) 1.2v hi -z ( open ) 0 (gnd) 1.0v 1 (vdda) hi -z ( open ) 0.9v hi -z ( open ) 1 (vdda) 0.8v hi -z ( open ) hi -z ( open ) 0.7v to achieve accurate output voltage regulation, the outsns pin (internal feedback divider top terminal) should be kelvin - connected as close as possible to the point - of - regulation top terminal. s ince both the internal reference and the internal feedback divider s bottom terminal refer to agnd, it is important to minimize voltage drops between the agnd and the point - of - regulation return terminal. setting the current limit the mic24046 valley - mode current limit on the low - side mosfet can be programmed by means of ilim as shown in table 3 . table 3 . current - limit setting ilim low - side valley current limit (typical value) rated output current 0 (gnd) 4. 6 a 3a 1 (vdda) 6.2 a 4a hi - z (open) 6.8 a 5a n ote that the programmed current - limit value s act as pulse - by - pulse current - limit thresholds on the valley inductor current. if the inductor current has not decayed below the threshold at the time the pwm requires a new on time, the high - side mosfet turn -o n is either delayed until the valley current recovers below the threshold or skipped. each time the high - side mosfet turn - on is skipped, a 4 - bit up - down counter is incremented. when the counter reaches the configuration 1111, a hiccup sequence is invoked in order to reduce power dissipation under prolonged short - circuit conditions. the highest current - limit setting ( 6.8 a) is intended to comfortably accommodate a 5a application. ensure the value of the operating junction temperature does not exceed the maxim um rating in high output power applications. inductor selection and slope compensation when selecting an inductor, it is important to consider the following factors: ? inductance ? rated current value ? size requirements ? dc resistance (dcr) ? core losses the inductance value is critical to the operation of mic24046 . since the mic24046 is a valley current - mode regulator, it needs a slope compensation for the stable current loop operation where duty cycles are below 50%. slope compensation is internally programmed according to the frequency and output voltage selection, assuming there is a minimum inductance value for the given operating condition. table 4 lists the assumed minimum inductor values recommended for stable current loop operation. note that the minimum suggested inductance values should be met when taking into account inductor tolerance and its change with current level. table 4 . recommended inductance values at v in = 12v v out selection frequency minimum inductance 0.7v, 0.8v, 0.9v, 1.0v, 1.2v 400khz 0.97 565khz 0.68 790khz 0.49 1.5v, 1.8v 400khz 1.51 565khz 1.06 790khz 0.76 2.49v, 3.3v 400khz 2.42 565khz 1.70 790khz 1.21 the slope compensation is also internally adapted to the input - output voltage differential . in practical implementations of valley - current - mode control, slope compensation is also added to any duty cycle larger than 50% as part of improv ing current loop stability and noise immunity for all input and output voltage ranges. consequently, the mic24046 adds internal slope compensation signal up to 60% duty cycle. a bove this , no slope co mpensation is added. for this reason, the pwm modulator gain exhibits an abrupt change when the duty cycle exceeds 60%, possibly leading to some increase in jitter and noise susceptibility. downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 19 revision 1. 1 if operation around and above 60% duty cycle is considered, a more conservative design of the compensation loop might help in reducing jitter and noise sensitivity. inductor current ratings are generally stated as permissible dc curren t and saturation current. permissible dc current can be rated for a 20c to 40c temperature rise. saturation current can be rated for a 10% to 30% loss in inductance. en sure that the nominal current of the application is well within the permissible dc curr ent ratings of the inductor , depending on the allowed temperature rise. note that the inductor permissible dc current rating typically does not include inductor core losses. these are very important contributo rs of total inductor core loss and temperatur e increase in high - frequency dc/dc converters because core losses increase rapidly with the excitation frequency. when saturation current is specified, make sure that there are enough design margin s so the peak current does not cause the inductor to enter d eep saturation. p ay attention to the inductor saturation characteristic in current limit. the inductor should not heavily saturate , even in current limit operation . if there is heavy saturation, the current may instantaneously run away and reach potentially destructive levels. typically, ferrite - core inductors exhibit an abrupt saturation characteristic, while powdered - iron or composite inductors have a soft - saturation characteristic. peak current can be calculated with equation 4 . ?? ? ?? ? ?? ? ?? ? ? + = l f 2 /v v 1 v i i in o o o peak l, eq. 4 as shown in equation 4, the peak inductor current is inversely proportional to the switching frequency and the inductance. the lower the switching frequency or inductance, the higher the peak current. as input voltage incr eases, the peak current also increases. output capacitor selection two main requirements determine the size and characteristics of the output capacitor c o : ? steady - state ripple ? maximum voltage deviation during load transient for steady - state ripple calculation, the esr and the capacitive ripple both contribute to the total ripple amplitude. from the switching frequency, input voltage, output voltage setting, and load current , the peak - to - peak inductor current ripple and the peak inductor current can be cal culated as: ? ?? ? ? ?? ? ? = ? l /v v 1 v i s in o o l_pp f eq. 5 2 i i i l_pp o peak l, ? + = eq. 6 the capacitive ripple v r, c and the esr ripple v r, esr are given by: o s l_pp c r, c f 8 i v ? = ? eq. 7 l_pp esr r, i esr v ? = ? eq. 8 the total peak - to - peak output ripple is then conservatively estimated as: esr r, c r, r v v v ?+ ?? ? eq. 9 t he output capacitor value and esr should be chosen so v r is within specifications. capacitor tolerance should be considered for worst case calculations. in the case of ceramic output capacitors, factor into account the decrease of effective capacitance versus applied dc bias. the worst - case load transient for output capacitor calculation is an instantaneous 100% to 0% load release when the inductor current is at its peak value. in this case, all the energy stored in the inductor is absorbed by the output capacitor while the converter stops switching and keeps the low - side fet on. the peak output voltage overshoot ( v out ) happens when the inductor current has decayed to zero . this can be calculated with equation 10 : o 2 o 2 o o v i c l v v peak l, ? + = eq. 10 equation 11 calculates the minimum output capacitance value (c o(min) ) needed to limit the output overshoot below v out . downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 20 revision 1. 1 ( ) 2 o 2 o o 2 peak l, o(min) v v v i l c ? + = eq. 11 the result from the minimum output capacitance value for load transient is the most stringent requirement found for capacitor value in most applications. low equivalent series resistance (esr) ceramic output capacitors with x5r or x7r temperature characteristics are recommended. for low output voltage applications with demanding load transient requirements, us ing a combination of polarized and ceramic output capacitors may be most convenient for smallest solution size. input capacitor selection two main requirements determine the size and characteristics of the input capacitor: ? steady - state ripple ? rms current the buck converter input current is a pulse train with very fast rising and falling times so low - esr ceramic capacitors are recommended for input filtering, because of their good high - frequency characteristics. for ideal input filtering (assuming a dc input current feeding the filtered buck power stage), and by neglecting the capacitor esr contribution to the input ripple (typically possible for ceramic input capacitors), the minimum capacitance value c in(min) needed for a given input peak - to - peak ripple vo ltage v r, in can be estimated as shown in equation 12 : s in,r o ) min (in f v )d 1( d i c ? ? = eq. 12 where: d is the duty cycle at the given operating point. the rms current i in,rms of the input capacitor is estimated as in equation 13 : d)- (1 d i i o rms in, = eq. 13 note that for a given output current i o, the w orst case values are obtained at d = 0.5. multiple input capacitors can be used to reduce input ripple amplitude and/or individual capacitor rms current. compensation design as a simple first - order approximation, the valley - current - mode - controlled buck power stage can be modeled as a voltage - controlled current - source feeding the output capacitor and load. the inductor current state - variable is removed and t he power - stage transfer function from comp to the inductor current is modeled as a transconductance (gm ps ). the simplified model of the control loop is shown in figure 6 . the power - stage transconductance gm ps shows some dependence on current levels and it is also somewhat affected by process variations, therefore some design margin is recommended against the typical value gm ps = 12.5 a/v (see electrical characteristics(5 ) ). figure 6 . simplified small - signal model of the voltage regulation loop this simplified approach disregards all issues related to the inner current loop, like its stability and bandwidth. this approximation is good enough for most operati ng scenarios, where the voltage - loop bandwidth is not pushed to aggressively high frequencies. based on the model shown in figure 6 , the control - to - output transfer function is: ? ?? ? ? ?? ? + ? ?? ? ? ?? ? + = = p z l ps )s(c )s(o )s( co 2 s 1 2 s 1 r gm v v g f f eq. 14 w here : f z and f p = t he frequencies associated with the output capacitor esr zero and with the load pole , respectively: esr c 2 1 o z = f eq. 15 ) r esr ( c 2 1 l o p + = f eq. 16 downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 21 revision 1. 1 the mic24046 uses a transconductance (gm ea = 1. 5 ma/ v ) error amplifier. frequency compensation is implemented with a type - ii network (r c1 , c c1 , and c c2 ) connected from comp to agnd. the compensator transfer function consists of an integrator for zero dc ( voltage regulation error), a zero to boost the phase margin of the overall loop gain around the cro ssover frequency , and an additional pole that can be used to cancel the output capacitor esr zero , or to further attenuate switching frequency ripple. in both cases, the additional pole makes the regulation loop less susceptible to switching frequency nois e. the additional pole is created by capacitor c c2 . equation 17 details the compensator transfer function h c(s) (from outsns to comp) . ( ) ( ) ? ?? ? ? ?? ? + + + + + ?= 2c 1c 2c 1c 1c 1c 1c 2c 1c ea )s(c c c c c r s 1 c r s 1 c c s 1 gm 2r 1r 1r h eq. 17 the overall voltage loop gain t v(s) is the product of the control - to - output and the compensator transfer functions: )s(c )s( co )s(v h g t = eq. 18 the value of the attenuation ratio r1/(r1 + r2) depends on the output voltage selection , and can be retrieved as illustrated in table 5 : table 5 . internal feedback divider attenuation values v o range r1/(r1 + r2) a ( a = 1 + r2/r1 ) 0.7v ? 1.2 v 1 1 1.5v ? 1.8 v 0.5 2 2.5v(2.49v) ? 3.3 v 0.333 3 the compensation design process is as follows : 1. set the t v(s) loop gain crossover frequency f xo in the range f s /20 to f s /10 . lower values of f xo allow a more predictable and robust phase margin. higher values of f xo would involve additional considerations about the current loop bandwidth in order to achieve a robust phase margin . taking a more conservative approach is highly recommended . 20 s xo f f eq. 19 2. select r c1 to achieve the target crossover frequency f xo of the overall voltage loop. this typically happens where the power stage transfer function g co(s) i s rolling off at - 20 db/dec. the compensato r transfer function h c(s) is in the so - called mid - band gain region where c c1 can be considered a dc - blocking short circuit while c c2 can still be considered as an open circuit, as calculated in equation 20: ps ea xo o 1c gm gm c 2 1r 2r 1r r ? ? ?? ? ?? ? + = f eq. 20 3. select capacitor c c1 to place the compensator zero at the load pole. the load pole moves around with load variations, so to calculate the load pole use as a load resistance r l the value determined by the nominal output curren t i o of the application, as shown in equation 21 and equation 22 : o o l i v r = eq. 21 1c l o 1c r ) r esr ( c c + = eq. 22 4. select capacitor c c2 to place the compensator pole at the point where the frequency of the output capacitor esr is zero , or at 5 f xo , whichever is lower. the c c2 is intended for plac ing the compensator pole at the frequency of the output capacitor esr zero, and/or achieve additional switching ripple/noise atte nuation. if the output capacitor is a polarized one, its esr zero will typically occur at low enough frequencies to cause the loop gain to flatten out and not roll - off at a - 20db / decade slope around or just after the crossover frequency f xo . this causes undesirable scarce compensation design robustness and switching noise susceptibility. the compensator pole is then used to cancel the output capacitor esr zero , and achieve a well - behaved roll - off of the loop gain above the crossover frequency. if the output capacitor s are only ceramic , then the esr zero es frequencies could be very high . i n many cases , the frequencies could even be above the switching frequency itself. loop gain roll - off a t ? 20db/decade well beyond the crossover frequency is ensured, but even in this case , it is good practice to still make use of the compensator pole to further attenuate switching noise, while conserving phase margin at the crossover downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 22 revision 1. 1 frequency. for example, setting the compensator pole at 5 f xo , will limit its associated phase loss at the crossover frequency to about 11 . placement at even higher frequencies n f xo ( n > 5 ) will reduce phase loss even further, at the expense of less noise/ripple attenuation at the switching frequency. some attenuation of the switching frequency noise /ripple is achieved as long as n f xo < f s . for polarized output capacitor, compensator pole placement at the esr zero frequency is achieved shown in equation 23 : 1c o 1c 2c c 1 esr c r 1 c ? = eq. 23 for ceramic output capacitor, compensator pole placement at n f xo (n 5, n f xo < f s ) is achieved as detailed in equation 24 : 1c xo 1c 2c c 1 n r 2 1 c ? = f eq. 24 output voltage soft - start rate the mic24046 features internal analog soft - start, such that the output voltage can be smoothly increased to the target regulation voltage. the soft - start rate given in the electrical characteristics is referred to the error amplifier reference, and therefore the effective soft - start rate value seen at the output of the module has to be scaled according to the internal feedback divider attenuation values listed in table 5 . to calculate the effective output voltage soft - start slew rate ss_sr out based on the particular output voltage setting and the reference soft - start slew rate ss_sr, use the following formula: sr _ ss a sr _ ss out ? = eq. 25 w here : t he value of a (amplification, a =1 + r2/r1) i s given in the right column of table 5 . downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 23 revision 1. 1 typical application schematic bill of materials item part number manufacturer description qty . c1 grm31cr61e226me15 murata ( 6 ) x5r, 22f 25v 20% , s ize 1206 capacitor 1 c 2, c7 grm155r71e104ke14 murata x7r, 100nf 25v 10%, s ize 0402 capacitor 2 c3, c4 grm31cr60j107me39 murata x5r, 100uf 6.3v 20%, s ize 1206 capacitor c5 , c6 grm155r61c225ke11 murata x5r, 2.2f 16v 10%, s ize 0402 capacitor 2 c8 grm1555c1h470ja01 murata c0g, 47pf 50v 5%, s ize 0402 capacitor 1 c9 grm155r71e103ka01 murata x7r, 10nf 25v 10%, s ize 0402 capacitor 1 r1 rc0402 - 2551f any chip, 2.55k 1%, s ize 0402 resistor 1 r2 rc0402 - 103j any chip, 10k 5 %, s ize 0402 resistor 1 l1 xal4020 - 152me coilcraft ( 7 ) smt, 1.5h, i sat = 7.1a i rms = 5.2a inductor 1 u1 mic24046yfl micrel, inc. ( 8 ) pin- programmable, 4.5v ? 19v, 5a step - down converter 1 notes: 6. murata : www.murata.com . 7. coilcraft : www.coilcraft.com . 8. micrel, inc.: www.micrel.com . downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 24 revision 1. 1 pcb layout recommendations top layer layer 1 downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 25 revision 1. 1 pcb layout recommendations (continued) layer 2 bottom layer downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 26 revision 1. 1 package information and recommended land pattern ( 9 ) 20 -pin 3mm 3mm qfn ( fl ) note: 9. package information is correct as of the publication date. for updat es and most current information, go to www.micrel.com . downloaded from: http:///
micrel, inc. mic24046 october 14 , 2015 27 revision 1. 1 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.com micrel, inc. is a leading global manufacturer of ic solutions for the worldwide high performance l inear and power, lan, and t iming & communications markets. the companys products include advanced mixed - signal, analog & power semiconductors; high - performance communication, clock management, mems - based clock oscillators & crystal - less clock generators, ethernet switches, and physical layer transceiver ics. company customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and comp uter products. corporation headquarters and state - of - the - art wafer fabrication facilities are locat ed in san jose, ca, with regional sales and support offices and advanced technology design centers situated throughout the americas, europe, and asia. additionally, the company maintains an extensive network of distributors and reps worldwide. micrel mak es no representations or warranties with respect to the accuracy or completeness of the inf ormation furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the righ t to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrels term s and conditions of sale for such products, micrel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of mi crel products including liability or warranties relating to fitness for a particul ar purpose, merchantability, or infringement of any patent, copyright , or other intellectual property right. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or sy stems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or s ystems is a purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from suc h use or sale. ? 20 15 micrel, incorporated. downloaded from: http:///

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