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| 8 bit microcontroller tlcs-870/c series TMP86P820UG
TMP86P820UG the information contained herein is su bject to change without notice. 021023 _ d toshiba is continually working to improve the qual ity and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fa il due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products , to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that to shiba products are used within specified operating ranges as set forth in the most re cent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc. 021023_a the toshiba products listed in this document are inte nded for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instrument s, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer's own risk. 021023_b the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_q the information contained he rein is presented only as a guide for the applications of our products. no responsibility is assumed by tosh iba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. 021023_c the products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_f for a discussion of how the reliability of microcontro llers can be predicted, please refer to section 1.3 of the chapter entitled quality and reli ability assurance/hand ling precautions. 030619_s ? 200 7 toshiba corporation all rights reserved TMP86P820UG the functional differences on products basi s: tmp86cm29l, tm p86cx29b, tmp86ch21 and tmp86cx20 note 1: uart and sio can not use function sync hronously because each f unction pins are shared. note 2: with tmp86ch21aug the operating temperature (topr) is -20 to 85 when the supply voltage vdd is less than 2.0v. note 3: tmp86c820/420 don?t have the timer/counter-6 input/output and uart input/output. note 4: the electrial characteristics of tmp86cm29lug ar e different from that of tmp86c829/ch29/cm29b, tmp86ch21/ ch21a and tmp86c420/c820. for details, please refer to "e lectrical characteristics" in data sheet of tmp86cm29lug. note 5: the operating temperature (topr) of ad characteri stics of all products (tmp86c420/c820/ch21/ch21a/c829b/ch29b/ cm29b/cm29l) is -10 to 85 when the supply voltage vdd is less than 2. 0v. for details, please refer to "ad conver- sion characteristics" in data sheet of each product. note 6: the characteristic of power supply current differs in each product. for details , please refer to "electirical characteri stics" in data sheet of each product. products name tmp86cm29l tmp86c829b tmp86ch29b tmp86cm29b tmp86ch21 tmp86ch21a tmp86c420 tmp86c820 rom 32 k bytes c829: 8k bytes ch29: 16k bytes cm29: 32k bytes 16k bytes c420: 4k bytes c820: 8k bytes ram 1.5k bytes c829: 512bytes ch29: 1.5k bytes cm29: 1.5k bytes 512bytes 256bytes i/o port 39 pins minumum command execution time 0.25 sec at 16mhz supply voltage 1.8v to 3.6v at 8.0mhz/ 32.768khz 2.7v to 3.6v at 16mhz/ 32.768khz (note4) 1.8v to 5.5v at 4.2mhz/32.768khz 2.7v to 5.5v at 8.0mhz/32.768khz 4.5v to 5.5v at 16mhz/32.768khz 18-bit timer counter 1ch (ecin input is both edge or single edge) 1ch (ecin input is single edge) 8-bit timer counter 4ch 2ch time base timer 1ch watch dog timer 1ch uart/sio 1ch (note1) n.a. sio n.a 1ch key-on wakeup 4ch a/d converter 10-bit a/d: 8ch 8-bit a/d: 8ch lcd driver 32seg x 4com operating temperature -40 to 85 -40 to 85 (note2) -40 to 85 package(body size) lqfp64(10x10mm) qfp64(14x14mm) lqfp64(10x10mm) package (p-qfp64-1010-0.80c) n.a tmp86c829bfg tmp86ch29bfg tmp86cm29bfg tmp86ch21fg tmp86c420fg tmp86c820fg package (p-lqfp64-1010-0.50e) n.a tmp86c829bug tmp86ch29bug tmp86cm29bug tmp86ch21ug tmp86c420ug tmp86c820ug package (p-lqfp64-1010-0.50d) tmp86cm29lug n.a. tmp86ch21aug n.a. TMP86P820UG the functional differ ences on products basis: tmp86c829b/ch29b/cm29b/pm29a/ pm29b/fm29/cm29l. note 1: uart and sio can not use function sync hronously because each f unction pins are shared. note 2: an emulation chip (tmp86c929axb) can?t emulate the flash memory functions, cpu wait and serial prom mode. therefore, if the software which incl udes flash memory function or cpu wait is executed in tmp86c929axb, the opera- tion might be different from tmp86fm29/cm29l. note 3: the operating temperature (topr) of ad characteri stics of all products (tmp86c829b/ch29b/cm29b/pm29a/pm29b/ fm29/cm29l) is -10 to 85 when the supply voltage vdd is less than 2.0v . for details, please re fer to "ad conversion characteristics" in data sheet of each product. note 4: the typical value of high and low fr equency feedback resistor in tmp86fm29/cm29l are different from that of the other products. for details, please refer to "input/out put circuitry" in data sheet of each product. note 5: the characteristic of power supply current differs in each product. for details , please refer to "electirical characteri stics" in data sheet of each product. note 6: the recommended operating condition of serial prom mode in tmp86fm29 is different from mcu mode. fore details, please refer to "electirical characteri stics" in data sheet of each product. products name tmp86c829b tmp86ch29b tmp86cm29b tmp86pm29a tmp86pm29b tmp86fm29 tmp86cm29l rom 8k bytes (mask) 16k bytes (mask) 32k bytes (mask) 32k bytes (otp) 32k bytes (flash) 32k bytes (mask) ram 512 bytes 1.5k bytes dbr 128 bytes (flash memory control/status registers TMP86P820UG note 1: tmp86fm29 has a cpu wait functi on which is a warming up (cpu halt) of cpu for stabilizing of power supply of flash memory. even though tmp86cm29l doesn?t have a flash memory, the cpu wait function is inserted to keep the compatibility with flash product (tmp86fm29) . during the cpu wait period except reset, cpu is halted but peripheral functions are not halted. therefore, if the interrupt occurs during the cpu wait period, the interrupt latch (il) is set and when imf has been set to "1 ", the interrupt service routine might be executed after cpu wait period . for details, please refer to "flash memory" in tmp86fm29 data sheet. tmp86fm29 (flash product) should be used as non-volatile product to confirm the software of tmp86cm29l because of the above reason. and tmp86pm29a/pm29b (otp pr oduct) should be used as non-volatile product to confirm the software of tmp86c829b/ch29b/cm29b. note 1: tmp86fm29/cm29l can't use lcd panel which is driven by 5v because the maximum recommended voltage is 3.6v. therefore, the voltage level of v3 pin always should be under 3.6v. note 2: the operating temperature of tmp86fm29/cm29l in type-1 and type-2 is -10 TMP86P820UG revision history date revision 2006/12/21 1 first release 2007/1/18 2 contents revised 2007/6/29 3 contents revised 2008/8/29 4 contents revised caution in setting the ua rt noise rejection time when uart is used, settings of rxdnc are limited depend ing on the transfer clock specified by brg. the com- bination "o" is available but please do not select the combination "?". the transfer clock generated by timer/counter in terrupt is calculated by the following equation : transfer clock [hz] = time r/counter source clock [hz] ttreg set value brg setting transfer clock [hz] rxdnc setting 00 (no noise rejection) 01 (reject pulses shorter than 31/fc[s] as noise) 10 (reject pulses shorter than 63/fc[s] as noise) 11 (reject pulses shorter than 127/fc[s] as noise) 000 fc/13 o o o ? 110 (when the transfer clock gen- erated by timer/counter inter- rupt is the same as the right side column) fc/8 o ? ? ? fc/16 o o ? ? fc/32ooo ? the setting except the a b o v eoooo i table of contents TMP86P820UG 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. operational description 2.1 cpu core functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 memory address map ............................................................................................................................... 9 2.1.2 program memory (otp) ........................................................................................................................... 9 2.1.3 data memory (ram) ................................................................................................................................. 9 2.2 system clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 clock generator ...................................................................................................................................... 10 2.2.2 timing generator .................................................................................................................................... 12 2.2.2.1 configuration of timing generator 2.2.2.2 machine cycle 2.2.3 operation mode control circuit .............................................................................................................. 13 2.2.3.1 single-clock mode 2.2.3.2 dual-clock mode 2.2.3.3 stop mode 2.2.4 operating mode control ......................................................................................................................... 18 2.2.4.1 stop mode 2.2.4.2 idle1/2 mode and sleep1/2 mode 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) 2.2.4.4 slow mode 2.3 reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.1 external reset input ............................................................................................................................... 31 2.3.2 address trap reset ............................................................................................................................... ... 32 2.3.3 watchdog timer reset .............................................................................................................................. 32 2.3.4 system clock reset ............................................................................................................................... ... 32 3. interrupt control circuit 3.1 interrupt latches (il15 to il2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2 interrupt enable register (eir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.1 interrupt master enable flag (imf) .......................................................................................................... 36 3.2.2 individual interrupt enable flags (ef15 to ef4) ...................................................................................... 36 3.3 interrupt source selector (intsel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.4 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.4.1 interrupt acceptance processing is packaged as follows. ....................................................................... 39 3.4.2 saving/restoring general-purpose registers ............................................................................................ 40 3.4.2.1 using push and pop instructions ii 3.4.2.2 using data transfer instructions 3.4.3 interrupt return ........................................................................................................................................ 41 3.5 software interrupt (intsw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.1 address error detection .......................................................................................................................... 42 3.5.2 debugging .............................................................................................................................................. 42 3.6 undefined instruction interrupt (intundef) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.7 address trap interrupt (intatrap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.8 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4. special function r egister (sfr) 4.1 sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2 dbr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5. i/o ports 5.1 port p1 (p17 to p10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2 port p2 (p22 to p20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3 port p3 (p33 to p30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.4 port p5 (p57 to p50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.5 port p6 (p67 to p60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.6 port p7 (p77 to p70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6. time base timer (tbt) 6.1 time base timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.1.1 configuration .......................................................................................................................................... 59 6.1.2 control .................................................................................................................................................... 59 6.1.3 function .................................................................................................................................................. 60 6.2 divider output (dvo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.2.1 configuration .......................................................................................................................................... 61 6.2.2 control .................................................................................................................................................... 61 7. watchdog timer (wdt) 7.1 watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.2 watchdog timer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.2.1 malfunction detection methods using the watchdog timer ................................................................... 64 7.2.2 watchdog timer enable ......................................................................................................................... 65 7.2.3 watchdog timer disable ........................................................................................................................ 66 7.2.4 watchdog timer interrupt (intwdt) ...................................................................................................... 66 7.2.5 watchdog timer reset ........................................................................................................................... 67 7.3 address trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.3.1 selection of address trap in internal ram (atas) ................................................................................ 68 7.3.2 selection of operation at address trap (atout) .................................................................................. 68 7.3.3 address trap interrupt (intatrap) ....................................................................................................... 68 7.3.4 address trap reset ............................................................................................................................... . 69 8. 18-bit timer/counter (tc1) iii 8.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.3.1 timer mode ............................................................................................................................................. 75 8.3.2 event counter mode ............................................................................................................................... 75 8.3.3 pulse width measurement mode ............................................................................................................ 76 8.3.4 frequency measurement mode .............................................................................................................. 77 9. 8-bit timercounter (tc3, tc4) 9.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.3.1 8-bit timer mode (tc3 and 4) ................................................................................................................ 85 9.3.2 8-bit event counter mode (tc3, 4) ........................................................................................................ 86 9.3.3 8-bit programmable divider ou tput (pdo) mode (tc3, 4) ..................................................................... 86 9.3.4 8-bit pulse width modulation (pwm) output mode (tc3, 4) .................................................................. 89 9.3.5 16-bit timer mode (tc3 and 4) .............................................................................................................. 91 9.3.6 16-bit event counter mode (tc3 and 4) ................................................................................................ 92 9.3.7 16-bit pulse width modulation (pwm) output mode (tc3 and 4) .......................................................... 92 9.3.8 16-bit programmable pulse generate (ppg) output mode (tc3 and 4) ............................................... 95 9.3.9 warm-up counter mode ......................................................................................................................... 97 9.3.9.1 low-frequency warm-up counter mode (normal1 normal2 slow2 slow1) 9.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) 10. synchronous serial interface (sio) 10.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.3 serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.3.1 clock source ............................................................................................................................... ........ 101 10.3.1.1 internal clock 10.3.1.2 external clock 10.3.2 shift edge ............................................................................................................................... ............. 103 10.3.2.1 leading edge 10.3.2.2 trailing edge 10.4 number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.5 number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.6 transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.6.1 4-bit and 8-bit transfer modes ............................................................................................................. 104 10.6.2 4-bit and 8-bit receive modes ............................................................................................................. 106 10.6.3 8-bit transfer / receive mode ............................................................................................................... 107 11. 8-bit ad converter (adc) 11.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 11.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.3.1 ad conveter operation ...................................................................................................................... 112 11.3.2 ad converter operation ..................................................................................................................... 112 11.3.3 stop and slow mode during ad conversion ................................................................................. 113 11.3.4 analog input voltage and ad conversion result ............................................................................... 114 11.4 precautions about ad converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.4.1 analog input pin voltage range ........................................................................................................... 115 iv 11.4.2 analog input shared pins .................................................................................................................... 115 11.4.3 noise countermeasure ........................................................................................................................ 115 12. key-on wakeup (kwu) 12.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13. lcd driver 13.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13.2.1 lcd driving methods .......................................................................................................................... 121 13.2.2 frame frequency ............................................................................................................................... .. 122 13.2.3 driving method for lcd driver ............................................................................................................ 123 13.2.3.1 when using the booster circuit (lcdcr v 16.7.1 read operation in prom mode .......................................................................................................... 149 16.7.2 program operation (high-speed) (topr = 25 5 c) ........................................................................... 150 16.8 recommended oscillating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 16.9 handling precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 17. package dimensions this is a technical docu ment that describes the operat ing functions and electrical specifications of the 8-bit microc ontroller series tlcs-870/c (lsi). vi page 1 060116ebp TMP86P820UG cmos 8-bit microcontroller ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality and reli ability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent el ectrical sensitivity and vulnerability to physical stre ss. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of sa fety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, pleas e ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling gui de for semiconductor devices,? or ?toshiba se miconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics applic ations (computer, personal eq uip- ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neithe r intended nor warranted for usage in equipment that requires extr aordinarily high quality and/or re liability or a malfunctionor failure of which may cause loss of human life or bod ily injury (?unintended usage?). unintended us age include atomic energy control instru ments, airplane or spaceship instruments, transporta tion instruments, traffic signal instrume nts, combustion control instruments, medi cal instru- ments, all types of safety dev ices, etc. unintended usage of toshiba products li sted in this document shall be made at the cust omer's own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any appl icable laws and regulations. 060106_q ? the information contained herein is present ed only as a guide for the applications of our products. no responsibility is assum ed by toshiba for any infringements of patents or other rights of the th ird parties which may result from its use. no license is gran ted by impli- cation or otherwise under any patent or patent rights of toshiba or others. 021023_c ? the products described in this document are subjec t to the foreign exchange and foreign trade laws. 021023_e ? for a discussion of how the reliability of microcontrollers c an be predicted, please refer to section 1.3 of the chapter entit led quality and reliability assurance/h andling precautions. 030619_s TMP86P820UG the TMP86P820UG is a single-chip 8-bit high-speed an d high-functionality microcomputer incorporating 8192 bytes of one-time prom. it is pin-compatible with the tmp86c820ug/tmp86c420ug (mask rom version). the TMP86P820UG can realize operations equivalent to those of the tmp86c820ug/tmp86c420ug by program- ming the on-chip prom. 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c series - instruction execution time : 0.25 s (at 16 mhz) 122 s (at 32.768 khz) - 132 types & 731 basic instructions 2. 15interrupt sources (external : 5 internal : 10) 3. input / output ports (39 pins) large current output: 4pins (typ. 20ma), led direct drive 4. prescaler - time base timer - divider output function 5. watchdog timer 6. 18-bit timer/counter : 1ch - timer mode - event counter mode - pulse width measurement mode - frequency measurement mode product no. rom (eprom) ram package maskrom mcu emulation chip TMP86P820UG 8192 bytes 256 bytes lqfp64-p-1010-0.50e tmp86c820ug/ tmp86c420ug tmp86c929axb page 2 1.1 features TMP86P820UG 7. 8-bit timer counter : 2 ch - timer, event counter, programmable divider output (pdo), pulse width modulation (pwm) output, programmable pulse generation (ppg) modes 8. 8-bit sio: 1 ch 9. 8-bit successive approximation type ad converter (with sample hold) analog inputs: 8ch 10. key-on wakeup : 4 ch 11. lcd driver/controller built-in voltage booster for lcd driver with display memory lcd direct drive capability (max 32 seg 4 com) 1/4,1/3,1/2duties or static drive are programmably selectable 12. clock operation single clock mode dual clock mode 13. low power consumption operation stop mode: oscillation stops. (battery/capacitor back-up.) slow1 mode: low power consumption operation usin g low-frequency clock.(high-frequency clock stop.) slow2 mode: low power consumption operation usin g low-frequency clock.(high-frequency clock oscillate.) idle0 mode: cpu stops, and only the time-based-tim er(tbt) on peripherals operate using high fre- quency clock. release by falling edge of th e source clock which is set by tbtcr page 3 TMP86P820UG 1.2 pin assignment figure 1-1 pin assignment vss xout test vdd (xtin) p21 (xtout) p22 reset ( int5 / stop ) p20 (ain0) p60 (ecnt/ain2) p62 (stop2/ain4) p64 ( int0 /ain3) p63 (stop3/ain5) p65 (stop4/ain6) p66 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p15(seg26/si) p17(seg24/ sck ) p50(seg23) p52(seg21) p51(seg22) p54(seg19) p53(seg20) p16(seg25/so) seg3 seg4 seg5 seg6 seg7 p77 (seg8) p76 (seg9) p75 (seg10) (ecin/ain1) p61 xin p67(ain7/stop5) avdd p10(seg31) p11(seg30) p14(seg27/int3) p12(seg29/int1) varef p13(seg28/int2) p74 (seg11) p73 (seg12) p72 (seg13) p71 (seg14) p70 (seg15) p57 (seg16) p56 (seg17) p55 (seg18) seg2 seg1 seg0 com3 com2 com1 com0 v3 v2 v1 c1 c0 ( dvo ) p30 (tc3/ pdo3/pwm3 ) p31 (tc4/ pdo4/pwm4/ppg4 ) p32 p33 page 4 1.3 block diagram TMP86P820UG 1.3 block diagram figure 1-2 block diagram page 5 TMP86P820UG 1.4 pin names and functions table 1-1 pin names and functions(1/3) pin name pin number input/output functions p17 seg24 sck 27 io o io port17 lcd segment output 24 serial clock i/o p16 seg25 so 26 io o o port16 lcd segment output 25 serial data output p15 seg26 si 25 io o i port15 lcd segment output 26 serial data input p14 seg27 int3 24 io o i port14 lcd segment output 27 external interrupt 3 input p13 seg28 int2 23 io o i port13 lcd segment output 28 external interrupt 2 input p12 seg29 int1 22 io o i port12 lcd segment output 29 external interrupt 1 input p11 seg30 21 io o port11 lcd segment output 30 p10 seg31 20 io o port10 lcd segment output 31 p22 xtout 7 io o port22 resonator connecting pins(32.768khz) for inputting external clock p21 xtin 6 io i port21 resonator connecting pins(32.768khz) for inputting external clock p20 stop int5 9 io i i port20 stop mode release signal input external interrupt 5 input p33 64 io port33 p32 pdo4/pwm4/ppg4 tc4 63 io o i port32 pdo4/pwm4/ppg4 output tc4 input p31 pdo3/pwm3 tc3 62 io o i port31 pdo3/pwm3 output tc3 input p30 dvo 61 io o port30 divider output p57 seg16 35 io o port57 lcd segment output 16 p56 seg17 34 io o port56 lcd segment output 17 p55 seg18 33 io o port55 lcd segment output 18 page 6 1.4 pin names and functions TMP86P820UG p54 seg19 32 io o port54 lcd segment output 19 p53 seg20 31 io o port53 lcd segment output 20 p52 seg21 30 io o port52 lcd segment output 21 p51 seg22 29 io o port51 lcd segment output 22 p50 seg23 28 io o port50 lcd segment output 23 p67 ain7 stop5 17 io i i port67 analog input7 stop5 input p66 ain6 stop4 16 io i i port66 analog input6 stop4 input p65 ain5 stop3 15 io i i port65 analog input5 stop3 input p64 ain4 stop2 14 io i i port64 analog input4 stop2 input p63 ain3 int0 13 io i i port63 analog input3 external interrupt 0 input p62 ain2 ecnt 12 io i i port62 analog input2 ecnt input p61 ain1 ecin 11 io i i port61 analog input1 ecin input p60 ain0 10 io i port60 analog input0 p77 seg8 43 io o port77 lcd segment output 8 p76 seg9 42 io o port76 lcd segment output 9 p75 seg10 41 io o port75 lcd segment output 10 p74 seg11 40 io o port74 lcd segment output 11 p73 seg12 39 io o port73 lcd segment output 12 p72 seg13 38 io o port72 lcd segment output 13 p71 seg14 37 io o port71 lcd segment output 14 p70 seg15 36 io o port70 lcd segment output 15 table 1-1 pin names and functions(2/3) pin name pin number input/output functions page 7 TMP86P820UG seg7 44 o lcd segment output 7 seg6 45 o lcd segment output 6 seg5 46 o lcd segment output 5 seg4 47 o lcd segment output 4 seg3 48 o lcd segment output 3 seg2 49 o lcd segment output 2 seg1 50 o lcd segment output 1 seg0 51 o lcd segment output 0 com3 52 o lcd common output 3 com2 53 o lcd common output 2 com1 54 o lcd common output 1 com0 55 o lcd common output 0 v3 56 i lcd voltage booster pin v2 57 i lcd voltage booster pin v1 58 i lcd voltage booster pin c1 59 i lcd voltage booster pin c0 60 i lcd voltage booster pin xin 2 i resonator connecting pins for high-frequency clock xout 3 o resonator connecting pins for high-frequency clock reset 8 io reset signal test 4 i test pin for out-going test. normally, be fixed to low. varef 18 i analog base voltage input pin for a/d conversion avdd 19 i analog power supply vdd 5 i power supply vss 1 i 0(gnd) table 1-1 pin names and functions(3/3) pin name pin number input/output functions page 8 1.4 pin names and functions TMP86P820UG page 9 TMP86P820UG 2. operational description 2.1 cpu core functions the cpu core consists of a cpu, a system cl ock controller, and an interrupt controller. this section provides a description of the cpu core, the program memory, the data memory, and the reset circuit. 2.1.1 memory address map the TMP86P820UG memory is composed otp, ram, dbr(data buffer registe r) and sfr(special func- tion register). they are all mapped in 64-kbyte address space. figure 2-1 shows the TMP86P820UG memory address map. figure 2-1 memory address map 2.1.2 program memory (otp) the TMP86P820UG has a 8192 bytes (address e000h to ffffh) of program memory (otp ). 2.1.3 data memory (ram) the TMP86P820UG has 256bytes (address 0040h to 0 13fh) of internal ram. the first 192 bytes (0040h to 00ffh) of the internal ram are locat ed in the direct area; instructions with shorten operations are available against such an area. sfr 0000 h 64 bytes sfr: ram: special function register includes: i/o ports peripheral control registers peripheral status registers system control registers program status word random access memory includes: data memory stack 003f h ram 0040 h 256 bytes 013f h dbr 0f80 h 128 bytes dbr: data buffer register includes: peripheral control registers peripheral status registers lcd display memory 0fff h e000 h otp: program memory otp 8192 bytes ffc0 h vector table for vector call instructions (32 bytes) ffdf h ffe0 h vector table for interrupts (32 bytes) ffff h page 10 2. operational description 2.2 system clock controller TMP86P820UG the data memory contents become un stable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. 2.2 system clock controller the system clock controller consists of a clock generator, a timing generator, and a standby controller. figure 2-2 syst em colck control 2.2.1 clock generator the clock generator generates the basic clock which pr ovides the system clocks supplied to the cpu core and peripheral hardware. it contains two oscillation ci rcuits: one for the high-frequency clock and one for the low-frequency clock. power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. the high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the xin/xout and xtin/xtout pins respectively. clock input from an exte rnal oscillator is also possible. in this case, external clock is applied to xin/xtin pin with xout/xtout pin not connected. example :clears ram to ?00h?. (TMP86P820UG) ld hl, 0040h ; start address setup ld a, h ; initial value (00h) setup ld bc, 00ffh sramclr: ld (hl), a inc hl dec bc jrs f, sramclr tbtcr syscr2 syscr1 xin xout xtin xtout fc 0036 h 0038 h 0039 h fs timing generator control register timing generator standby controller system clocks clock generator control high-frequency clock oscillator low-frequency clock oscillator clock generator system control registers page 11 TMP86P820UG figure 2-3 examples of resonator connection note:the function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. the system to require the adjustment of the oscilla tion frequency should create the program for the adjust- ment in advance. xout xin (open) xout xin xtout xtin (open) xtout xtin (a) crystal/ceramic resonator (b) external oscillator (c) crystal (d) external oscillator high-frequency clock low-frequency clock page 12 2. operational description 2.2 system clock controller TMP86P820UG 2.2.2 timing generator the timing generator generates the various system cloc ks supplied to the cpu core and peripheral hardware from the basic clock (fc or fs). the timing generator provides the following functions. 1. generation of main system clock 2. generation of divider output ( dvo ) pulses 3. generation of source clocks for time base timer 4. generation of source clocks for watchdog timer 5. generation of internal source clocks for timer/counters 6. generation of warm-up clocks for releasing stop mode 7. lcd 2.2.2.1 configuration of timing generator the timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. an input clock to the 7th stage of the divider depends on the operating mode, syscr2 page 13 TMP86P820UG note 1: in single clock mode, do not set dv7ck to ?1?. note 2: do not set ?1? on dv7ck while the low-frequency clock is not operated stably. note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don?t care note 4: in slow1/2 and sleep1/2 modes, the dv7ck setting is ineffective, and fs is input to the 7th stage of the divider. note 5: when stop mode is entered from normal1/2 mode, the dv 7ck setting is ineffective during the warm-up period after release of stop mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 machine cycle instruction execution and peripheral hardware operat ion are synchronized with the main system clock. the minimum instruction execution uni t is called an ?machine cycle?. th ere are a total of 10 different types of instructions for the tlcs-870/c series: ra nging from 1-cycle instructions which require one machine cycle for execution to 10-cyc le instructions which require 10 machine cycles fo r execution. a machine cycle consists of 4 states (s0 to s3), and each state consists of one main system clock. figure 2-5 machine cycle 2.2.3 operation mode control circuit the operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low- frequency clocks, and switches the main system clock. there are three operating modes: single clock mode, dual clock mode and stop mode. these modes are cont rolled by the system cont rol registers (syscr1 and syscr2). figure 2-6 shows the operating mode transition diagram. 2.2.3.1 single-clock mode only the oscillation circuit for the high-frequenc y clock is used, and p21 (xtin) and p22 (xtout) pins are used as input/output ports . the main-system clock is obtained from the high-frequency clock. in the single-clock mode, the machine cycle time is 4/fc [s]. (1) normal1 mode in this mode, both the cpu core and on-chip pe ripherals operate using the high-frequency clock. the TMP86P820UG is placed in this mode after reset. timing generator control register tbtcr (0036h) 76543210 (dvoen) (dvock) dv7ck (tbten) (tbtck) (initial value: 0000 0000) dv7ck selection of input to the 7th stage of the divider 0: fc/2 8 [hz] 1: fs r/w main system clock state machine cycle s3 s2 s1 s0 s3 s2 s1 s0 1/fc or 1/fs [s] page 14 2. operational description 2.2 system clock controller TMP86P820UG (2) idle1 mode in this mode, the internal oscillation circuit remains active. the cpu and the watchdog timer are halted; however on-chip peripherals remain active (operate using the high-frequency clock). idle1 mode is started by syscr2 page 15 TMP86P820UG switching back and forth between slow1 and slow2 modes are performed by syscr2 page 16 2. operational description 2.2 system clock controller TMP86P820UG note 1: normal1 and normal2 modes are generically called no rmal; slow1 and slow2 are called slow; idle0, idle1 and idle2 are called idle; sleep0, sleep1 and sleep2 are called sleep. note 2: the mode is released by fa lling edge of tbtcr page 17 TMP86P820UG note 1: always set retm to ?0? when transiting from normal mode to stop mode. always set retm to ?1? when transiting from slow mode to stop mode. note 2: when stop mode is released with reset pin input, a return is made to normal1 regardless of the retm contents. note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *; don?t care note 4: bits 1 and 0 in syscr1 are read as undefined data when a read instruction is executed. note 5: as the hardware becomes stop mode under outen = ?0?, input value is fixed to ?0?; therefore it may cause external interrupt request on account of falling edge. note 6: when the key-on wakeup is used, relm should be set to "1". note 7: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. note 8: the warmig-up time should be set correctly for using oscillator. note 1: a reset is applied if both xen and xten are cleared to ?0?, xen is cleared to ?0? when sysck = ?0?, or xten is cleared to ?0? when sysck = ?1?. note 2: *: don?t care, tg: timing generator, *; don?t care note 3: bits 3, 1 and 0 in syscr2 are always read as undefined value. note 4: do not set idle and tghalt to ?1? simultaneously. note 5: because returning from idle0/sleep0 to normal1/slow 1 is executed by the asynchronous internal clock, the period of idle0/sleep0 mode might be shorter than the period setting by tbtcr page 18 2. operational description 2.2 system clock controller TMP86P820UG 2.2.4 operating mode control 2.2.4.1 stop mode stop mode is controlled by the system control register 1, the stop pin input and key-on wakeup input (stop5 to stop2) which is controlled by the stop mode release control register (stopcr). the stop pin is also used both as a port p20 and an int5 (external interrupt input 5) pin. stop mode is started by setting syscr1 page 19 TMP86P820UG figure 2-7 level-s ensitive release mode note 1: even if the stop pin input is low after warm-up start, the stop mode is not restarted. note 2: in this case of changing to the level-s ensitive mode from the edge-s ensitive mode, the release mode is not switched until a rising edge of the stop pin input is detected. (2) edge-sensitive release mode (relm = ?0?) in this mode, stop mode is released by a rising edge of the stop pin input. this is used in appli- cations where a relatively short pr ogram is executed repeat edly at periodic intervals. this periodic signal (for example, a clock from a low-power consumption oscillator) is input to the stop pin. in the edge-sensitive release mode, stop mode is started even when the stop pin input is high level. do not use any stop5 to stop2 pin input for releasing stop mode in edge-sensitive release mode. figure 2-8 edge-sensitive release mode example 2 :starting stop mode from normal mode with an int5 interrupt. pint5: test (p2prd). 0 ; to reject noise, stop mode does not start if jrs f, sint5 port p20 is at high ld (syscr1), 01010000b ; sets up the level-sensitive release mode. di ; imf 0 set (syscr1). 7 ; starts stop mode sint5: reti example :starting stop mode from normal mode di ; imf 0 ld (syscr1), 10010000b ; starts after specified to the edge-sensitive release mode v ih normal operation warm up stop operation confirm by program that the stop pin input is low and start stop mode. always released if the stop pin input is high. stop pin xout pin stop mode is released by the hardware. normal operation normal operation normal operation v ih stop mode is released by the hardware at the rising edge of stop pin input. warm up stop mode started by the program. stop operation stop operation stop pin xout pin page 20 2. operational description 2.2 system clock controller TMP86P820UG stop mode is released by the following sequence. 1. in the dual-clock mode, when returning to normal2, both the high-frequency and low- frequency clock oscillators are turned on; when returning to slow1 mode, only the low- frequency clock oscillator is turned on. in the single-clock mode, only the high-frequency clock oscillator is turned on. 2. a warm-up period is inserted to allow oscillation time to stabilize. during warm up, all internal operations remain halted. four differ ent warm-up times can be selected with the syscr1 page 21 TMP86P820UG figure 2-9 stop mode start/release instruction address a + 4 0 instruction address a + 3 turn on turn on warm up 0 n halt set (syscr1). 7 turn off (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) a + 6 a + 5 a + 4 a + 3 a + 2 n + 2 n + 3 n + 4 a + 3 n + 1 instruction address a + 2 2 1 0 3 (b) stop mode release count up turn off halt oscillator circuit program counter instruction execution divider main system clock oscillator circuit stop pin input program counter instruction execution divider main system clock page 22 2. operational description 2.2 system clock controller TMP86P820UG 2.2.4.2 idle1/2 mode and sleep1/2 mode idle1/2 and sleep1/2 modes are controlled by the system control register 2 (syscr2) and maskable interrupts. the following status is maintained during these modes. 1. operation of the cpu and watchdog timer (wdt) is halted. on-chip peripherals continue to operate. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. the program counter holds the address 2 ahead of th e instruction which starts these modes. figure 2-10 idle1/ 2 and sleep1/2 modes reset reset input ?0? ?1? (interrupt release mode) yes no no cpu and wdt are halted interrupt request imf interrupt processing normal release mode yes starting idle1/2 and sleep1/2 modes by instruction execution of the instruc- tion which follows the idle1/2 and sleep1/2 modes start instruction page 23 TMP86P820UG ? start the idle1/2 and sleep1/2 modes after imf is set to "0", set the individual inte rrupt enable flag (ef) which releases idle1/2 and sleep1/2 modes. to start idle1/2 and sl eep1/2 modes, set syscr2 page 24 2. operational description 2.2 system clock controller TMP86P820UG figure 2-11 idle1/2 and sleep1/2 modes start/release halt halt halt halt operate instruction address a + 2 a + 3 a + 2 a + 4 a + 3 a + 3 halt set (syscr2). 4 operate operate operate acceptance of interrupt ?r:wnormal release mode ?s:winterrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer (a) idle1/2 and sleep1/2 modes start (example: star ting with the set instruction located at address a) (b) idle1/2 and sleep1/2 modes release page 25 TMP86P820UG 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) idle0 and sleep0 modes are controlled by the system control register 2 (syscr2) and the time base timer control register (tbtcr). the following stat us is maintained during idle0 and sleep0 modes. 1. timing generator stops feeding clock to peripherals except tbt. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before idle0 and sleep0 modes were entered. 3. the program counter holds the address 2 ahead of the instru ction which starts idle0 and sleep0 modes. note: before starting idle0 or sleep0 mode, be sure to stop (disable) peripherals. figure 2-12 idle 0 and sleep0 modes yes (normal release mode) yes (interrupt release mode) no yes reset input cpu and wdt are halted reset tbt source clock falling edge tbtcr page 26 2. operational description 2.2 system clock controller TMP86P820UG ? start the idle0 and sleep0 modes stop (disable) peripherals such as a timer counter. to start idle0 and sleep0 modes, set syscr2 page 27 TMP86P820UG figure 2-13 idle0 and slee p0 modes start/release halt halt operate instruction address a + 2 halt operate set (syscr2). 2 halt operate acceptance of interrupt halt ?r:wnormal release mode ?s:winterrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock tbt clock tbt clock program counter instruction execution watchdog timer main system clock program counter instruction execution watchdog timer a + 3 a + 2 a + 4 a + 3 a + 3 (a) idle0 and sleep0 modes start (example: starting with the set instruction located at address a (b) idle and sleep0 modes release page 28 2. operational description 2.2 system clock controller TMP86P820UG 2.2.4.4 slow mode slow mode is controlled by the sy stem control register 2 (syscr2). the following is the methods to switch the mode with the warm-up counter. (1) switching from normal2 mode to slow1 mode first, set syscr2 page 29 TMP86P820UG (2) switching from slow1 mode to normal2 mode note: after sysck is cleared to ?0?, executing the in structions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. first, set syscr2 page 30 2. operational description 2.2 system clock controller TMP86P820UG figure 2-14 switching between the normal2 and slow modes set (syscr2). 7 normal2 mode clr (syscr2). 7 set (syscr2). 5 normal2 mode turn off (a) switching to the slow mode slow1 mode slow2 mode clr (syscr2). 5 (b) switching to the normal2 mode high- frequency clock low- frequency clock main system clock instruction execution sysck xen high- frequency clock low- frequency clock main system clock instruction execution sysck xen slow1 mode warm up during slow2 mode page 31 TMP86P820UG 2.3 reset circuit the TMP86P820UG has four types of reset generation proced ures: an external reset input , an address trap reset, a watchdog timer reset and a system clock re set. of these reset, the address trap reset, the watchdog timer and the sys- tem clock reset are a malfunction reset. when the malfunction reset request is detected, reset occurs during the max- imum 24/fc[s] (the reset pin outputs "l" level). the malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial- ized when power is turned on. therefore, reset may occur during maximum 24/fc[s] (1.5 s at 16.0 mhz) when power is turned on. reset pin outputs "l" level during maximum 24/fc[s] (1.5 s at 16.0mhz). table 2-3 shows on-chip hardware initialization by reset action. 2.3.1 external reset input the reset pin contains a schmitt trigger (hysteresis) with an internal pull-up resistor. when the reset pin is held at ?l? level for at least 3 machin e cycles (12/fc [s]) wi th the power supply volt- age within the operating voltage range and oscillation stab le, a reset is applied and the internal state is initial- ized. when the reset pin input goes high, the reset operation is rele ased and the program execution starts at the vector address stored at addresses fffeh to ffffh. figure 2-15 reset circuit table 2-3 initializing internal status by reset action on-chip hardware initial value on-chip hardware initial value program counter (pc) (fffeh) prescaler and divider of timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l, ix, iy) not initialized jump status flag (jf) not initialized watchdog timer enable zero flag (zf) not initialized output latches of i/o ports refer to i/o port circuitry carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 interrupt individual enable flags (ef) 0 control registers refer to each of control register interrupt latches (il) 0 lcd data buffer not initialized ram not initialized internal reset reset vdd malfunction reset output circuit watchdog timer reset address trap reset system clock reset page 32 2. operational description 2.3 reset circuit TMP86P820UG 2.3.2 address trap reset if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (when wdtcr1 page 33 TMP86P820UG page 34 2. operational description 2.3 reset circuit TMP86P820UG page 35 TMP86P820UG 3. interrupt control circuit the TMP86P820UG has a total of 15 interrupt sources excl uding reset, of which 1 source levels are multiplexed. interrupts can be nested with priorities. four of the internal interrupt sour ces are non-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il) , which hold interrupt requests, and independent vectors. the interrupt latch is set to ?1? by th e generation of its interrupt request wh ich requests the cpu to accept its inter- rupts. interrupts are enabled or disabled by software using the interrupt master enable fl ag (imf) and in terrupt enable flag (ef). if more than one interrupts are generated simultaneously, interrup ts are accepted in order which is domi- nated by hardware. however, there are no prioritized interrupt factors among non-maskable interrupts. note 1: the intsel register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 inte r- rupt source selector (intsel)). note 2: to use the address trap interrupt (intatrap), clear wdtcr1 page 36 3. interrupt control circuit 3.2 interrupt enable register (eir) TMP86P820UG note: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf new ly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0 " automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple inte rrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". 3.2 interrupt enab le register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except fo r the non-maskable interrupts (software interrupt, undefined instruction interr upt, address trap interrupt and watchdog interrupt). non- maskable interrupt is accepted regardless of the contents of the eir. the eir consists of an interrupt mast er enable flag (imf) and the individua l interrupt enable flags (ef). these registers are located on address 003ah and 003bh in sfr area, and they can be read and written by an instructions (including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 interrupt ma ster enable flag (imf) the interrupt enable register (imf ) enables and disables the acceptance of the whole maskable interrupt. while imf = ?0?, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (ef). by setting imf to ?1?, the interrupt becomes acceptable if the individuals are enabled. when an interrupt is accepted, imf is cleared to ?0? after the latest status on imf is stacked. thus the maskable inter- rupts which follow are disabled. by executing return interrupt instruction [reti/retn], the stacked data, which was the status before interrup t acceptance, is loaded on imf again. the imf is located on bit0 in eirl (address: 003ah in sfr), and can be read and written by an instruction. the imf is normally set and cl eared by [ei] and [di] instruction respectively. during reset, the imf is initial- ized to ?0?. 3.2.2 individual interrupt enable flags (ef15 to ef4) each of these flags enables and disables the acceptan ce of its maskable interrupt . setting the corresponding bit of an individual interrupt enable flag to ?1? enables acceptan ce of its interrupt, and setting the bit to ?0? dis- ables acceptance. during reset, all the individual interrupt enable flags (ef15 to ef4) ar e initialized to ?0? and all maskable interrupts are not accepted until they are set to ?1?. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf become s "0" automatically, clearing imf need not execute nor- mally on interrupt service routine. however, if using mult iple interrupt on interrupt service routine, manipulat- ing ef or il should be executed before setting imf="1". example 1 :clears interrupt latches di ; imf 0 ldw (ill), 111010000011 1111b ; il12, il10 to il6 0 ei ; imf 1 example 2 :reads interrupt latchess ld wa, (ill) ; w ilh, a ill example 3 :tests interrupt latches test (ill). 7 ; if il7 = 1 then jump jr f, sset page 37 TMP86P820UG example 1 :enables interrupts individually and sets imf di ; imf 0 ldw : (eirl), 1110100010100000b ; ef15 to ef13, ef11, ef7, ef5 1 note: imf should not be set. : ei ; imf 1 example 2 :c compiler description example unsigned int _io (3ah) eirl; /* 3ah shows eirl address */ _di(); eirl = 10100000b; : _ei(); page 38 3. interrupt control circuit 3.2 interrupt enable register (eir) TMP86P820UG note 1: to clear any one of bits il7 to il4, be sure to write "1" into il2 and il3. note 2: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". note 3: do not clear il with read-modify-w rite instructions such as bit operations. note 1: *: don?t care note 2: do not set imf and the interrupt enable flag (ef15 to ef4) to ?1? at the same time. note 3: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". interrupt latches (initial value: 00000000 000000**) ilh,ill (003dh, 003ch) 1514131211109876543210 il15 il14 il13 il12 il11 il10 il9 il8 il7 il6 il5 il4 il3 il2 ilh (003dh) ill (003ch) il15 to il2 interrupt latches at rd 0: no interrupt request 1: interrupt request at wr 0: clears the interrupt request 1: (interrupt latch is not set.) r/w interrupt enable registers (initial value: 00000000 0000***0) eirh,eirl (003bh, 003ah) 1514131211109876543210 ef15 ef14 ef13 ef12 ef11 ef10 ef9 ef8 ef7 ef6 ef5 ef4 imf eirh (003bh) eirl (003ah) ef15 to ef4 individual-interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. r/w imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts enables the acceptance of all maskable interrupts page 39 TMP86P820UG 3.3 interrupt sour ce selector (intsel) each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the intsel register. the interrupt controller does not hold interrupt requests corresponding to interrupt sour ces that are not selected in the intsel register. th erefore, the intsel reg- ister must be set appropriately befo re interrupt requests are generated. the following interrupt sources share their interrupt sour ce level; the source is selected onnthe register intsel. 1. int3 and inttc3 share the interrupt source level whose priority is 15. 3.4 interrupt sequence an interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to ?0? by resetting or an instruct ion. interrupt acceptance sequence requires 8 machine cycles (2 s @16 mhz) after the completion of the current instruction. the interrupt service task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). figure 3-1 shows the timing chart of interrupt acceptance processing. 3.4.1 interrupt acceptance proc essing is packaged as follows. a. the interrupt master enab le flag (imf) is cleared to ?0? in or der to disable the acceptance of any fol- lowing interrupt. b. the interrupt latch (il) for the interrupt source accepted is cleared to ?0?. c. the contents of the program coun ter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the st ack in sequence of psw + imf, pch, pcl. mean- while, the stack pointer (s p) is decremented by 3. d. the entry address (interrupt vect or) of the corresponding interrupt service program, loaded on the vec- tor table, is transferred to the program counter. e. the instruction stored at the entry address of the inte rrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of imf are also saved. interrupt sour ce selector intsel (003eh) 76543210 ------il14er-(initial value: **** **0*) il14er selects int3 or inttc3 0: int3 1: inttc3 r/w a b a c + 1 execute instruction sp pc execute instruction n n ? 2 n - 3 n ? 2n ? 1 n ? 1 n a + 2 a + 1 c + 2 b + 3 b + 2 b + 1 a + 1 a a ? 1 execute reti instruction interrupt acceptance execute instruction interrupt service task 1-machine cycle interrupt request interrupt latch (il) imf page 40 3. interrupt control circuit 3.4 interrupt sequence TMP86P820UG note 1: a: return address entry address, b: entry address, c: address which reti instruction is stored note 2: on condition that interrupt is enabled, it takes 38/fc [s ] or 38/fs [s] at maximum (if the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. figure 3-1 timing chart of interrupt acceptance/return in terrupt instruction example: correspondence be tween vector table address for inttbt and the entry address of the interrupt service program figure 3-2 vector table address,entry address a maskable interrupt is not accepted until the imf is set to ?1? even if th e maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt service, the imf is set to ?1? in the interrupt service program. in this case, acceptable interrupt sources are selectively en abled by the individual interrupt enable flags. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to ?1?. as for non-maskable interr upt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.4.2 saving/restoring general-purpose registers during interrupt acceptance processing , the program counter (pc) and the program status word (psw, includes imf) are automati cally saved on the stack, but the accumulato r and others are not. these registers are saved by software if necessary. when multiple interrupt se rvices are nested, it is also necessary to avoid using the same data memory area for saving registers. the fo llowing methods are used to save/restore the general- purpose registers. 3.4.2.1 using push and pop instructions if only a specific register is saved or interrupts of the same source are nested , general-purpose registers can be saved/restored using the push/pop instructions. example :save/store register us ing push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return d2h 03h d203h d204h 06h vector table address entry address 0fh vector interrupt service program fff2h fff3h page 41 TMP86P820UG figure 3-3 save/store register using push and pop instructions 3.4.2.2 using data transfer instructions to save only a specific register wi thout nested interrupts, data tran sfer instructions are available. figure 3-4 saving/restoring general-purpose r egisters under interrupt processing 3.4.3 interrupt return interrupt return instructions [reti]/[retn] perform as follows. example :save/store register us ing data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return [reti]/[retn] interrupt return 1. program counter (pc) and program status word (psw, includes imf) are restored from the stack. 2. stack pointer (sp) is incremented by 3. pcl pch psw at acceptance of an interrupt at execution of push instruction at execution of reti instruction at execution of pop instruction b-4 b-3 b-2 b-1 b pcl pch psw pcl pch psw sp address (example) sp sp sp a w b-5 interrupt acceptance interrupt service task restoring registers saving registers interrupt return saving/restoring general-purpose registers using push/pop data transfer instruction main task page 42 3. interrupt control circuit 3.5 software interrupt (intsw) TMP86P820UG as for address trap interrupt (intatrap), it is requir ed to alter stacked data for program counter (pc) to restarting address, during interrupt service program. note:if [retn] is executed with the above data unaltered, the program returns to the address trap area and intatrap occurs again.when interrupt acceptance pr ocessing has completed, stacked data for pcl and pch are located on address (sp + 1) and (sp + 2) respectively. interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next inter- rupt can be accepted immediately after the interrupt retu rn instruction is executed. note 1: it is recommended that stack pointer be return to rate before intatrap (increment 3 times), if return inter- rupt instruction [retn] is not utilized during inte rrupt service program under intatrap (such as example 2). note 2: when the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.5 software interrupt (intsw) executing the swi instruction generates a software interr upt and immediately starts interrupt processing (intsw is highest prioritized interrupt). use the swi instruction only for detection of the address error or for debugging. 3.5.1 address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address during single chip mode. code ffh is th e swi instruction, so a software interrupt is gener- ated and an address error is detect ed. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram, dbr or sfr areas. 3.5.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. example 1 :returning from address trap interrupt (intatrap) service program pintxx: pop wa ; recover sp by 2 ld wa, return address ; push wa ; alter stacked data (interrupt processing) retn ; return example 2 :restarting without returning interrupt (in this case, psw (includes imf) befo re interrupt acceptance is discarded.) pintxx: inc sp ; recover sp by 3 inc sp ; inc sp ; (interrupt processing) ld eirl, data ; set imf to ?1? or clear it to ?0? jp restart address ; jump into restarting address page 43 TMP86P820UG 3.6 undefined instruct ion interrupt (intundef) taking code which is not defined as authorized instru ction for instruction causes intundef. intundef is gen- erated when the cpu fetches such a co de and tries to execute it. intundef is accepted even if non-maskable inter- rupt is in process. contemporary process is broken and intundef interrupt process starts, soon after it is requested. note: the undefined instruction interrupt (intundef) forces cpu to jump into vector address, as software interrupt (swi) does. 3.7 address trap interrupt (intatrap) fetching instruction from unauthorized area for instructio ns (address trapped area) cause s reset output or address trap interrupt (intatrap). intatrap is accepted even if non-maskable interrupt is in process. contemporary pro- cess is broken and intatrap interrupt pro cess starts, soon afte r it is requested. note: the operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (wdtcr). 3.8 external interrupts the TMP86P820UG has 5 external interrupt inputs. these inputs are equipped with digital noise reject circuits (pulse inputs of less than a certa in time are elimin ated as noise). edge selection is also possible with int1 to int3. the int0 /p63 pin can be configured as either an external inter- rupt input pin or an input/output port, and is configured as an input port during reset. edge selection, noise reject control and int0 /p63 pin function selection are performed by the external interrupt control register (eintcr). source pin enable conditions release edge digital noise reject int0 int0 imf ? ef4 ? int0en=1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s ] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int1 int1 imf ? ef5 = 1 falling edge or rising edge pulses of less than 15/fc or 63/fc [s] are elimi- nated as noise. pulses of 49/fc or 193/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int2 int2 imf ? ef7 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int3 int3 imf ? ef14 = 1 and il14er=0 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int5 int5 imf ? ef15 = 1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s ] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. page 44 3. interrupt control circuit 3.8 external interrupts TMP86P820UG note 1: in normal1/2 or idle1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "si g- nal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. note 2: when int0en = "0", il4 is not set even if a falling edge is detected on the int0 pin input. note 3: when a pin with more than one function is used as an out put and a change occurs in data or input/output status, an inter - rupt request signal is generated in a pseudo manner. in this ca se, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. page 45 TMP86P820UG note 1: fc: high-frequency clock [hz], *: don?t care note 2: when the system clock frequency is switched between high and low or when the external interrupt control register (eintcr) is overwritten, the noise canceller may not operat e normally. it is recommended that external interrupts are dis- abled using the interrupt enable register (eir). note 3: the maximum time from modifying int1 nc until a noise reject time is changed is 2 6 /fc. external interrupt control register eintcr76543210 (0037h) int1nc int0en - - int3es int2es int1es (initial value: 00** 000*) int1nc noise reject time select 0: pulses of less than 63/fc [s] are eliminated as noise 1: pulses of less than 15/fc [s] are eliminated as noise r/w int0en p63/ int0 pin configuration 0: p63 input/output port 1: int0 pin (port p63 should be set to an input mode) r/w int3 es int3 edge select 0: rising edge 1: falling edge r/w int2 es int2 edge select 0: rising edge 1: falling edge r/w int1 es int1 edge select 0: rising edge 1: falling edge r/w page 46 3. interrupt control circuit 3.8 external interrupts TMP86P820UG page 47 TMP86P820UG 4. special function register (sfr) the TMP86P820UG adopts the memory mapped i/o system, and all peripheral control and data transfers are per- formed through the special function register (sfr) or the data buffer register (dbr). the sfr is mapped on address 0000h to 003fh, dbr is mapped on address 0f80h to 0fffh. this chapter shows the arrangement of the special functi on register (sfr) and data buffer register (dbr) for TMP86P820UG. 4.1 sfr address read write 0000h reserved 0001h p1dr 0002h p2dr 0003h p3dr 0004h p3outcr 0005h p5dr 0006h p6dr 0007h p7dr 0008h p1prd - 0009h p2prd - 000ah p3prd - 000bh p5prd - 000ch p6cr 000dh p7prd - 000eh adccr1 000fh adccr2 0010h treg1al 0011h treg1am 0012h treg1ah 0013h treg1b 0014h tc1cr1 0015h tc1cr2 0016h tc1sr - 0017h reserved 0018h tc3cr 0019h tc4cr 001ah reserved 001bh reserved 001ch ttreg3 001dh ttreg4 001eh reserved 001fh reserved 0020h adcdr1 - 0021h adcdr2 - 0022h reserved 0023h reserved 0024h reserved 0025h reserved page 48 4. special function register (sfr) 4.1 sfr TMP86P820UG note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). 0026h reserved 0027h reserved 0028h lcdcr 0029h p1lcr 002ah p5lcr 002bh p7lcr 002ch pwreg3 002dh pwreg4 002eh reserved 002fh reserved 0030h reserved 0031h reserved 0032h reserved 0033h reserved 0034h - wdtcr1 0035h - wdtcr2 0036h tbtcr 0037h eintcr 0038h syscr1 0039h syscr2 003ah eirl 003bh eirh 003ch ill 003dh ilh 003eh intsel 003fh psw address read write page 49 TMP86P820UG 4.2 dbr note 1: do not access reserved areas by the program. address read write 0f80h seg1/0 0f81h seg3/2 0f82h seg5/4 0f83h seg7/6 0f84h seg9/8 0f85h seg11/10 0f86h seg13/12 0f87h seg15/14 0f88h seg17/16 0f89h seg19/18 0f8ah seg21/20 0f8bh seg23/22 0f8ch seg25/24 0f8dh seg27/26 0f8eh seg29/28 0f8fh seg31/30 0f90h siobr0 0f91h siobr1 0f92h siobr2 0f93h siobr3 0f94h siobr4 0f95h siobr5 0f96h siobr6 0f97h siobr7 0f98h - siocr1 0f99h siosr siocr2 0f9ah - stopcr 0f9bh reserved 0f9ch reserved 0f9dh reserved 0f9eh reserved 0f9fh reserved address read write 0fa0h reserved : : : : 0fbfh reserved address read write 0fc0h reserved : : : : 0fdfh reserved address read write 0fe0h reserved : : : : 0fffh reserved page 50 4. special function register (sfr) 4.2 dbr TMP86P820UG note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). page 51 TMP86P820UG 5. i/o ports the TMP86P820UG have 6 parallel input/o utput ports (39 pins) as follows. each output port contains a latch, which holds the output data. all input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing. figure 5-1 shows input/output timing examples. external data is read from an i/o port in the s1 state of the read cycle during execution of the read instruction. this timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro- gram. output data changes in the s2 state of the write cycle du ring execution of the instruct ion which writes to an i/o port. note: the positions of the read and write c ycles may vary, depending on the instruction. figure 5-1 input/output timing (example) primary function secondary functions port p1 8-bit i/o port external interrupt input, serial interface input/output, and segment output. port p2 3-bit i/o port low-frequency resonator connections, exte rnal interrupt input, stop mode release signal input. port p3 4-bit i/o port timer/counter input/output and divider output. port p5 8-bit i/o port segment output. port p6 8-bit i/o port analog input, external interrupt input, timer/counter input and stop mode release signal input. port p7 8-bit i/o port segment output. instruction execution cycle input strobe data input ex: ld a, (x) fetch cycle fetch cycle read cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 instruction execution cycle output strobe old new data output ex: ld (x), a fetch cycle fetch cycle write cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 (a) input timing (b) output timing page 52 5. i/o ports 5.1 port p1 (p17 to p10) TMP86P820UG 5.1 port p1 (p17 to p10) port p1 is an 8-bit i nput/output port which is al so used as an external interrup t input, serial interface input/output, and segment output of lcd. when used as a segment pins of lcd, the respective bit of p1lcr should be set to ?1?. when used as an input port or a secondary function (e xcept for segment) pins, the respective output latch (p1dr) should be set to ?1? and its corresponding p1lcr bit should be set to ?0?. when used as an output port, the respec- tive p1lcr bit should be set to ?0?. during reset, the output latch is initialized to ?1?. p1 port output latch (p1dr) and p1 port terminal input (p1prd) are located on their respective address. when read the output latch data, the p1dr register should be read and when read the terminal input data, the p1prd register should be read. if the terminal input data which is configured as lcd segment output is read, unstable data is read. figure 5-2 port 1 p1dr (0001h) r/w 76543210 p17 seg24 sck p16 seg25 so p15 seg26 si p14 seg27 int3 p13 seg28 int2 p12 seg29 int1 p11 seg30 p10 seg31 (initial value: 1111 1111) p1lcr (0029h) 76543210 (initial value: 0000 0000) p1lcr port p1/segment output control (set for each bit individually) 0: p1 input/output port or secondary function (expect for segment) 1: segment output r/w p1prd (0008h) read only 76543210 p17 p16 p15 p14 p13 p12 p11 p10 output latch p1lcri data output (p1dr) output latch data (p1dr) lcd data output control input terminal input (p1prd) stop outen control output p1lcri input p1i note: i = 7 to 0 dq dq page 53 TMP86P820UG 5.2 port p2 (p22 to p20) port p2 is a 3-bit input/output port. it is also used as an external interr upt, a stop mode release signal input, and low-frequency crys tal oscillator con- nection pins. when used as an input port or a secondary function pins, respective output latch (p2dr) should be set to ?1?. during reset, the output latch is initialized to ?1?. a low-frequency crystal osci llator (32.768 khz) is connected to pins p21 (xtin) and p22 (xtout) in the dual- clock mode. in the single-clock mode, pins p21 and p22 can be used as normal input/output ports. it is recommended that pin p20 should be used as an exte rnal interrupt input, a stop mode release signal input, or an input port. if it is used as an output port, the in terrupt latch is set on the falling edge of the output pulse. p2 port output latch (p2dr) and p2 port terminal input (p2prd) are located on their respective address. when read the output latch data, the p2dr register should be read and when read the terminal input data, the p2prd register should be read. if a read instruction is executed for port p2, r ead data of bits 7 to 3 are unstable. figure 5-3 port 2 note: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. p2dr (0002h) r/w 76543210 p22 xtout p21 xtin p20 int5 stop (initial value: **** *111) p2prd (0009h) read only 76543210 p22 p21 p20 output latch output latch output latch data input (p20prd) data input (p21) data output (p21) data output (p20) data input (p20) control input data input (p21prd) data input (p22) data input (p22prd) data output (p22) stop outen xten fs p22 (xtout) p21 (xtin) p20 (int5, stop) osc. enable dq dq dq page 54 5. i/o ports 5.3 port p3 (p33 to p30) TMP86P820UG 5.3 port p3 (p33 to p30) port p3 is a 4-bit input/output port. it is also used as a timer/counter input/output, divider output. when used as a timer/counter output or divider output, respective output latch (p3dr) should be set to ?1?. it can be selected whether ou tput circuit of p3 port is c-mos output or a sink open drain individually, by setting p3outcr. when a corresponding bit of p3 outcr is ?0?, the output circuit is selected to a sink open drain and when a corresponding bit of p3outcr is ?1?, the output circuit is selected to a c-mos output. when used as an input port or timer/counter input, respective output control (p3outcr) should be set to ?0? after p3dr is set to ?1?. during reset, the p3dr is initialized to ?1?, and the p3outcr is initialized to ?0?. p3 port output latch (p3dr) and p3 port terminal input (p3prd) are located on their respective address. when read the output latch data, the p3dr should be r ead and when read the termin al input data, the p3prd reg- ister should be read. if a read instruction is execute d for port p3, read data of bits 7 to 4 are unstable. figure 5-4 port 3 p3dr (0003h) r/w 76543210 p33 p32 pwm4 pdo4 ppg4 tc4 p31 pwm3 pdo3 tc3 p30 dvo (initial value: **** 1111) p3outcr (0004h) 76543210 (initial value: **** 0000) p3outcr port p3 output circuit control (set for each bit individually) 0: sink open-drain output 1: c-mos output r/w p3prd (000ah) read only 76543210 p33 p32 p31 p30 data input (p3prd) data output (p3dr) control output stop outen p3outcri p3outcri input data input (p3dr) control input p3i note: i = 3 to 0 d q d q page 55 TMP86P820UG 5.4 port p5 (p57 to p50) port p5 is an 8-bit input/output port which is also used as a segment pins of lcd. when used as input port, the respective output latch (p5dr) should be set to ?1?. during reset, the output latch is initialized to ?1?. when used as a segment pins of lcd, the respective bit of p5lcr should be set to ?1?. when used as an output port, the respective p5lcr bit should be set to ?0?. p5 port output latch (p5dr) and p5 port terminal input (p5prd) are located on their respective address. when read the output latch data, the p5dr register should be read and when read the terminal input data, the p5prd register should be read. if the terminal input data which is configured as lcd segment output is read, unsta- ble data is read. figure 5-5 port 5 p5dr (0005h) r/w 76543210 p57 seg16 p56 seg17 p55 seg18 p54 seg19 p53 seg20 p52 seg21 p51 seg22 p50 seg23 (initial value: 1111 1111) p5lcr (002ah) 76543210 (initial value: 0000 0000) p5lcr port p5/segment output control (set for each bit individually) 0: p5 input/output port 1: lcd segment output r/w p5prd (000bh) read only 76543210 p57 p56 p55 p54 p53 p52 p51 p50 output latch p5lcri data output (p5dr) data input (p5dr) data input (p5prd) lcd data output stop outen p5lcri input p5i note: i = 7 to 0 dq dq page 56 5. i/o ports 5.5 port p6 (p67 to p60) TMP86P820UG 5.5 port p6 (p67 to p60) port p6 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. port p6 is also used as an analog input, key-on wake-up input, timer/counter input and external interrupt input. input/output modes is specified by the p6 control register (p6cr), the p6 output latch (p6dr), and ad ccr1 page 57 TMP86P820UG read-modify-write instruction writes the all data of 8-bit af ter data is read and modified. because a bit setting input mode read data of terminal, the output latch is changed by t hese instruction. so p6 port can not input data. 5.6 port p7 (p77 to p70) port p7 is an 8-bit input/output port which is also used as a segment pins of lcd. when used as input port, the respective output latch (p7dr) should be set to ?1?. during reset, the output latch is initialized to ?1?. when used as a segment pins of lcd, the respective bi t of p7lcr should be set to ?1? and its corresponding p7lcr bit should be set to ?0?. when used as an output port, the respective p7lcr bit should be set to ?0?. p7 port output latch (p7dr) and p7 port terminal input (p7prd) are located on their respective address. when read the output latch data, the p7dr register should be read and when read the terminal input data, the p7prd register should be read. if the terminal input data which is configured as lcd segment output is read, unsta- ble data is read. figure 5-7 port 7 p7dr (0007h) r/w 76543210 p77 seg8 p76 seg9 p75 seg10 p74 seg11 p73 seg12 p72 seg13 p71 seg14 p70 seg15 (initial value: 1111 1111) p7lcr (002bh) 76543210 (initial value: 0000 0000) p7lcr port p7/segment output control (set for each bit individually) 0: p7 input/output port 1: segment output r/w p7prd (000dh) read only 76543210 p77 p76 p75 p74 p73 p72 p71 p70 output latch p7lcri data output (p7dr) data input (p7dr) data input (p7prd) lcd data output stop outen p7lcri input p7i note: i = 7 to 0 p7lcri dq dq page 58 5. i/o ports 5.6 port p7 (p77 to p70) TMP86P820UG page 59 TMP86P820UG 6. time base timer (tbt) the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). 6.1 time base timer 6.1.1 configuration figure 6-1 time base timer configuration 6.1.2 control time base timer is controlled by time base timer control register (tbtcr). note 1: fc; high-frequency clock [hz], fs ; low-frequency clock [hz], *; don't care time base timer control register 7 6543210 tbtcr (0036h) (dvoen) (dvock) (dv7ck) tbten tbtck (initial value: 0000 0000) tbten time base timer enable / disable 0: disable 1: enable tbtck time base timer interrupt frequency select : [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 23 fs/2 15 fs/2 15 001 fc/2 21 fs/2 13 fs/2 13 010 fc/2 16 fs/2 8 ? 011 fc/2 14 fs/2 6 ? 100 fc/2 13 fs/2 5 ? 101 fc/2 12 fs/2 4 ? 110 fc/2 11 fs/2 3 ? 111 fc/2 9 fs/2 ? fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 16 or fs/2 8 fc/2 14 or fs/2 6 fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 9 or fs/2 tbtcr tbten tbtck 3 mpx source clock falling edge detector time base timer control register inttbt interrupt request idle0, sleep0 release request page 60 6. time base timer (tbt) 6.1 time base timer TMP86P820UG note 2: the interrupt frequency (tbtck) must be selected with t he time base timer disabled (tbten="0"). (the interrupt fre- quency must not be changed with the disable from the enable state.) both frequency selection and enabling can be per- formed simultaneously. 6.1.3 function an inttbt ( time base timer interrupt ) is generated on the first falling edge of source clock ( the divider output of the timing generator which is selected by tb tck. ) after time base timer has been enabled. the divider is not cleared by the progra m; therefore, only the first interrupt may be generated ahead of the set interrupt period ( figure 6-2 ). figure 6-2 time base timer interrupt example :set the time base timer frequency to fc/2 16 [hz] and enable an inttbt interrupt. ld (tbtcr) , 00000010b ; tbtck 010 ld (tbtcr) , 00001010b ; tbten 1 di ; imf 0 set (eirl) . 6 table 6-1 time base timer interrupt frequency ( example : fc = 16.0 mhz, fs = 32.768 khz ) tbtck time base timer interrupt frequency [hz] normal1/2, idle1/2 mode normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 000 1.91 1 1 001 7.63 4 4 010 244.14 128 ? 011 976.56 512 ? 100 1953.13 1024 ? 101 3906.25 2048 ? 110 7812.5 4096 ? 111 31250 16384 ? source clock enable tbt interrupt period tbtcr page 61 TMP86P820UG 6.2 divider output ( dvo ) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. divider output is from dvo pin. 6.2.1 configuration figure 6-3 divider output 6.2.2 control the divider output is controlled by the time base timer control register. note: selection of divider output frequency (dvock) must be made whil e divider output is disabled (dvoen="0"). also, in other words, when changing the state of the divider output frequen cy from enabled (dvoen="1") to disable(dvoen="0"), do not change the setting of the divider output frequency. time base timer control register 7654 321 0 tbtcr (0036h) dvoen dvock (dv7ck) (tbten) (tbtck) (initial value: 0000 0000) dvoen divider output enable / disable 0: disable 1: enable r/w dvock divider output ( dvo ) frequency selection: [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 13 fs/2 5 fs/2 5 01 fc/2 12 fs/2 4 fs/2 4 10 fc/2 11 fs/2 3 fs/2 3 11 fc/2 10 fs/2 2 fs/2 2 tbtcr output latch port output latch mpx dvoen tbtcr page 62 6. time base timer (tbt) 6.2 divider output (dvo) TMP86P820UG example :1.95 khz pulse output (fc = 16.0 mhz) ld (tbtcr) , 00000000b ; dvock "00" ld (tbtcr) , 10000000b ; dvoen "1" table 6-2 divider output frequency ( exam ple : fc = 16.0 mhz, fs = 32.768 khz ) dvock divider output frequency [hz] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 00 1.953 k 1.024 k 1.024 k 01 3.906 k 2.048 k 2.048 k 10 7.813 k 4.096 k 4.096 k 11 15.625 k 8.192 k 8.192 k page 63 TMP86P820UG 7. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidly the cpu malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the cpu to a sy stem recovery routine. the watchdog timer signal for detecting malfunctions can be programmed only once as ?reset request? or ?inter- rupt request?. upon the reset release, this signal is initialized to ?reset request?. when the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter- rupt. note: care must be taken in system des ign since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 7.1 watchdog timer configuration figure 7-1 watchdog timer configuration 0034 h overflow wdt output internal reset binary counters wdtout writing clear code writing disable code wdten wdtt 2 0035 h watchdog timer control registers wdtcr1 wdtcr2 intwdt interrupt request interrupt request reset request reset release clock clear 1 2 controller q sr s r q selector fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 19 or fs/2 11 fc/2 17 or fs/2 9 page 64 7. watchdog timer (wdt) 7.2 watchdog timer control TMP86P820UG 7.2 watchdog timer control the watchdog timer is controlled by the watchdog timer control registers (wdtcr1 and wdtcr2). the watch- dog timer is automatically enabled after the reset release. 7.2.1 malfunction detection me thods using the watchdog timer the cpu malfunction is detected, as shown below. 1. set the detection time, select the output, and clear the binary counter. 2. clear the binary counter repeatedly within the specified detection time. if the cpu malfunctions such as en dless loops or the deadlock condition s occur for some reason, the watch- dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. when wdtcr1 page 65 TMP86P820UG note 1: after clearing wdtout to ?0?, the program cannot set it to ?1?. note 2: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don?t care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. if wdtcr1 is read, a don?t care is read. note 4: to activate the stop mode, disable the watchdog timer or clear the counter immediately before entering the stop mode. after clearing the counter, clear the counter again immediately after the stop mode is inactivated. note 5: to clear wdten, set the register in accordance wi th the procedures shown in ?7.2.3 watchdog timer disable?. note 1: the disable code is valid only when wdtcr1 page 66 7. watchdog timer (wdt) 7.2 watchdog timer control TMP86P820UG 7.2.3 watchdog timer disable to disable the watchdog timer, set the register in accordance with the fo llowing procedures . setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. set the interrupt master flag (imf) to ?0?. 2. set wdtcr2 to the clear code (4eh). 3. set wdtcr1 page 67 TMP86P820UG 7.2.5 watchdog timer reset when a binary-counter overflow occurs while wdt cr1 page 68 7. watchdog timer (wdt) 7.3 address trap TMP86P820UG 7.3 address trap the watchdog timer control register 1 and 2 share the a ddresses with the control regi sters to generate address traps. 7.3.1 selection of address tr ap in internal ram (atas) wdtcr1 page 69 TMP86P820UG 7.3.4 address trap reset while wdtcr1 page 70 7. watchdog timer (wdt) 7.3 address trap TMP86P820UG page 71 TMP86P820UG 8. 18-bit timer/counter (tc1) 8.1 configuration figure 8-1 timer/counter1 8.2 control the timer/counter 1 is controlled by timer/counter 1 control registers (tc1cr1/tc1cr2), an 18-bit timer register (treg1a), and an 8-bit inte rnal window gate pulse setting register (treg1b). tc1cr1 treg1b f/f tc1sr cmp tc1cr2 b y a s h c d e f g b a a b y c s treg1a l treg1a m treg1a h window pulse generator edge detector 18- bit up-counter 10 11 00 s y y ecnt pin clear signal ecin pin wgpsck tc1m sgedg inttc1 2 3 22 1 212 wgpsck sgedg sgp tc1c tc1s tc1m tc1ck 2 1 11 pulse width measurement mode frequency measurement mode timer/event count modes fc/2 12 or fs/2 4 fc/2 13 or fs/2 5 fc/2 14 or fs/2 6 fs/2 15 or fc/2 23 fs/2 5 or fc/2 13 fs/2 3 or fc/2 11 fc/2 7 fc/2 3 fs fc page 72 8. 18-bit timer/counter (tc1) 8.2 control TMP86P820UG timer register 76543210 treg1ah (0012h) r/w ?????? treg1ah (initial value: ???? ?? 00) 76543210 treg1am (0011h) r/w treg1am (initial value: 0000 0000) 76543210 treg1al (0010h) r/w treg1al (initial value: 0000 0000) 76543210 treg1b (0013h) ta tb (initial value: 0000 0000) wgpsck normal1/2,idle1/2 modes slow1/2, sleep1/2 modes r/w dv7ck=0 dv7ck=1 ta setting "h" level period of the window gate pulse 00 01 10 (16 - ta) 2 12 /fc (16 - ta) 2 13 /fc (16 - ta) 2 14 /fc (16 - ta) 2 4 /fs (16 - ta) 2 5 /fs (16 - ta) 2 6 /fs (16 - ta) 2 4 /fs (16 - ta) 2 5 /fs (16 - ta) 2 6 /fs tb setting "l" level period of the window gate pulse 00 01 10 (16 - tb) 2 12 /fc (16 - tb) 2 13 /fc (16 - tb) 2 14 /fc (16 - tb) 2 4 /fs (16 - tb) 2 5 /fs (16 - tb) 2 6 /fs (16 - tb) 2 4 /fs (16 - tb) 2 5 /fs (16 - tb) 2 6 /fs page 73 TMP86P820UG note 1: fc; high-frequency clock [hz] fs; low-frequency clock [hz] * ; don?t care note 2: writing to the low-byte of the timer register 1a (tre g1al, treg1am), the compare func tion is inhibited until the high- byte (treg1ah) is written. note 3: set the mode and source clock, and edge (sel ection) when the tc1 stops (tc1cr1 page 74 8. 18-bit timer/counter (tc1) 8.2 control TMP86P820UG note 1: fc; high-frequency clock [hz] fs; low-frequency clock [hz] *; don't care note 2: set the mode, source clock, and edge (selection) when the tc1 stops (tc1cr1 page 75 TMP86P820UG 8.3 function tc1 has four operating modes. the timer mode of the tc 1 is used at warm-up when switching form slow mode to normal2 mode. 8.3.1 timer mode in this mode, counting up is perfor med using the internal clock. the c ontents of tregia are compared with the contents of up-counter. if a match is found, an in ttc1 interrupt is generated, and the counter is cleared. counting up resumes after the counter is cleared. note: when fc is selected for the source clock in slow mode, the lower bits 11 of treg1a is invalid, and a match of the upper bits 7 makes interrupts. figure 8-2 timing chart for timer mode 8.3.2 event counter mode it is a mode to count up at the falling edge of the ecin pin input. when using this mode, set tc1cr1 page 76 8. 18-bit timer/counter (tc1) 8.3 function TMP86P820UG figure 8-3 event count er mode timing chart 8.3.3 pulse width measurement mode in this mode, pulse widths are coun ted on the falling edge of logical and-ed pulse between ecin pin input (window pulse) and the internal clock. when using this mode, set tc1cr1 page 77 TMP86P820UG figure 8-4 pulse width me asurement mode timing chart 8.3.4 frequency measurement mode in this mode, the frequency of ecin pin input pulse is measured. when using this mode, set tc1cr1 page 78 8. 18-bit timer/counter (tc1) 8.3 function TMP86P820UG note 3: because the up counter is counted on the falling e dge of logical and-ed pulse (between ecin pin input and window gate pulse), if window gate pulse becomes falling edge while ecin input is "h" level, the up counter stops plus "1". therefore, if ecin i nput is always "h" level, count value becomes "1". table 8-3 table setting ta and tb (wgpsck = 10, fc = 16 mhz) setting value setting time setting value setting time 0 16.38ms 8 8.19ms 1 15.36ms 9 7.17ms 2 14.34ms a 6.14ms 3 13.31ms b 5.12ms 4 12.29ms c 4.10ms 5 11.26ms d 3.07ms 6 10.24ms e 2.05ms 7 9.22ms f 1.02ms table 8-4 table setting ta and tb (wgpsck = 10, fs = 32.768 khz) setting valuen setting time setting value setting time 0 31.25ms 8 15.63ms 1 29.30ms 9 13.67ms 2 27.34ms a 11.72ms 3 25.39ms b 9.77ms 4 23.44ms c 7.81ms 5 21.48ms d 5.86ms 6 19.53ms e 3.91ms 7 17.58ms f 1.95ms 1 0 2 3 54 1 2 3 56 4 6 0 ecin pin input and-ed pulse (internal signal) inttc1 interrupt window gate pulse up counter tc1cr1 page 79 TMP86P820UG 9. 8-bit timercounter (tc3, tc4) 9.1 configuration figure 9-1 8-bit timercounter 3, 4 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 fc/2 5 fc/2 3 fc/2 fc fc/2 7 fc/2 5 fc/2 3 fc/2 fc pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 11 or fs/2 3 fc/2 11 or fs/2 3 fs fs tc4cr tc3cr ttreg4 pwreg4 ttreg3 pwreg3 tc3 pin tc4 pin tc4s tc3s inttc3 interrupt request inttc4 interrupt request tff4 tff3 pdo 4/pwm 4/ ppg 4 pin pdo 3/pwm 3/ pin tc3ck tc4ck tc3m tc3s tff3 tc4m tc4s tff4 timer f/f4 timer f/f3 page 80 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86P820UG 9.2 timercounter control the timercounter 3 is controlled by the timercounter 3 control register (tc3cr) and two 8-bit timer registers (ttreg3, pwreg3). note 1: do not change the timer register (t treg3) setting while the timer is running. note 2: do not change the timer register (pwreg3) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock[hz] note 2: do not change the tc3m, tc3ck and tff3 settings while the timer is running. note 3: to stop the timer operation (tc3s= 1 0), do not change the tc3m, tc3ck and tff3 settings. to start the timer opera- tion (tc3s= 0 1), tc3m, tc3ck and tff3 can be programmed. note 4: to use the timercounter in the 16-bit mode, set th e operating mode by programming tc4cr page 81 TMP86P820UG note 7: the timer register settings are limited depending on the timer operating mode. for the detailed descriptions, see table 9- 3. note 8: the operating clock fc in the slow or sleep mode can be used only as the high-frequency warm-up mode. page 82 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86P820UG the timercounter 4 is controlled by the timercounter 4 control register (tc4cr) and two 8-bit timer registers (ttreg4 and pwreg4). note 1: do not change the timer register (t treg4) setting while the timer is running. note 2: do not change the timer register (pwreg4) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock [hz] note 2: do not change the tc4m, tc4ck and tff4 settings while the timer is running. note 3: to stop the timer operation (tc4s= 1 0), do not change the tc4m, tc4ck and tff4 settings. to start the timer operation (tc4s= 0 1), tc4m, tc4ck and tff4 can be programmed. note 4: when tc4m= 1** (upper byte in the 16-bit mode), the sour ce clock becomes the tc3 over flow signal regardless of the tc4ck setting. note 5: to use the timercounter in the 16-bit mode, select the operating mode by programming tc4m, where tc3cr page 83 TMP86P820UG note 6: to the timercounter in the 16-bit mode, select the so urce clock by programming tc3cr page 84 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86P820UG note: n = 3 to 4 table 9-3 constraints on register values being compared operating mode register value 8-bit timer/event counter 1 (ttregn) 255 8-bit pdo 1 (ttregn) 255 8-bit pwm 2 (pwregn) 254 16-bit timer/event counter 1 (ttreg4, 3) 65535 warm-up counter 256 (ttreg4, 3) 65535 16-bit pwm 2 (pwreg4, 3) 65534 16-bit ppg 1 (pwreg4, 3) < (ttreg4, 3) 65535 and (pwreg4, 3) + 1 < (ttreg4, 3) page 85 TMP86P820UG 9.3 function the timercounter 3 and 4 have the 8-bit timer, 8-bit ev ent counter, 8-bit programmable divider output (pdo), 8- bit pulse width modulation (pwm) output modes. the time rcounter 3 and 4 (tc3, 4) are cascadable to form a 16- bit timer. the 16-bit timer has the operat ing modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 9.3.1 8-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cl eared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr page 86 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86P820UG figure 9-2 8-bit timer mode timing chart (tc4) 9.3.2 8-bit event counter mode (tc3, 4) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counti ng at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum freque ncy to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 hz in the slow1/2 or sleep1/2 mode. note 1: in the event counter mode, fix tcjcr page 87 TMP86P820UG note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configur ation in the programmable divider output mode, the new value programmed in ttregj is in effect immediately after programming. therefore, if ttregi is changed while the timer is running, an ex pected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr page 88 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86P820UG figure 9-4 8-bit pdo mode timing chart (tc4) 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc4cr page 89 TMP86P820UG 9.3.4 8-bit pulse wi dth modulation (pwm) output mode (tc3, 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up-counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the timer f/fj is switched to the opposite state. the counter continues counting. the logic level output from the timer f/fj is switched to the opposite state again by the up-co unter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr page 90 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86P820UG figure 9-5 8-bit pwm mo de timing chart (tc4) 1 0 nn+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter m p m p n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc4cr page 91 TMP86P820UG 9.3.5 16-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. the timercounter 3 and 4 are cascad- able to form a 16-bit timer. when a match between the up-counter and the timer regi ster (ttreg3, ttreg4) valu e is detected after the timer is started by setting tc4cr page 92 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86P820UG 9.3.6 16-bit event c ounter mode (tc3 and 4) 9.3.7 16-bit pulse width modulatio n (pwm) output mode (tc3 and 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 16 bits of resolution. the timercounter 3 and 4 are cascadable to form the 16-bit pwm signal generator. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again by the counter overflow, and the counter is cleared. the inttc4 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc3 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 to in the slow1/2 or sleep1/2 mode. since the initial value can be set to the timer f/f4 by tc4cr page 93 TMP86P820UG clr (tc4cr).3: stops the timer. clr (tc4cr).7 : sets the pwm 4 pin to the high level. note 3: to enter the stop mode, stop the timer and then enter the stop mode. if the stop mode is entered with- out stopping of the timer when fc, fc/2 or fs is select ed as the source clock, a pulse is output from the pwm 4 pin during the warm-up period time after exiting the stop mode. table 9-7 16-bit pwm output mode source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 fs/2 3 [hz] fs/2 3 [hz] 128 s2 4 4 . 1 4 s 8.39 s 16 s fc/2 7 fc/2 7 ?8 s ? 524.3 ms ? fc/2 5 fc/2 5 ?2 s ? 131.1 ms ? fc/2 3 fc/2 3 ? 500 ns ? 32.8 ms ? fs fs fs 30.5 s3 0 . 5 s2 s 2 s fc/2 fc/2 ? 125 ns ? 8.2 ms ? fc fc ? 62.5 ns ? 4.1 ms ? example :generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 mhz) setting ports ldw (pwreg3), 07d0h : sets the pulse width. ld (tc3cr), 33h : sets the operating clock to fc/2 3 , and 16-bit pwm output mode (lower byte). ld (tc4cr), 056h : sets tff4 to the initial value 0, and 16-bit pwm signal generation mode (upper byte). ld (tc4cr), 05eh : starts the timer. page 94 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86P820UG figure 9-7 16-bit pwm m ode timing chart (tc3 and tc4) 1 0 an an+1 ffff 0 an an+1 ffff 0 1 bm bm+1 ffff 0 bm cp b c 1 1 cp n a an ? ? ? internal source clock 16-bit shift register shift shift shift shift counter match detect match detect one cycle period match detect match detect an bm cp an m p tc4cr page 95 TMP86P820UG 9.3.8 16-bit programmable pulse generate (ppg) ou tput mode (tc3 and 4) this mode is used to generate pulses with up to 16- bits of resolution. the timer counter 3 and 4 are cascad- able to enter the 16-bit ppg mode. the counter counts up using the inte rnal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4 ) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again when a match betw een the up-counter and th e timer register (ttreg3, ttreg4) value is detected, and the counter is cleared. the inttc4 interrupt is generated at this time. since the initial value can be set to the timer f/f4 by tc4cr page 96 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86P820UG figure 9-8 16-bit ppg mode timing chart (tc3 and tc4) 1 0 mn mn+1 qr-1 mn qr-1 1 mn mn+1 mn+1 0 qr 0 qr 1 0 internal source clock counter write of "0" match detect match detect match detect mn mn mn match detect match detect ? n m ? ? r q ? held at the level when the timer stops f/f clear tc4cr page 97 TMP86P820UG 9.3.9 warm-up counter mode in this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. the timer counter 3 and 4 are cascadable to form a 16-bit timercounter. the warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. note 1: in the warm-up counter mode, fi x tcicr page 98 9. 8-bit timercounter (tc3, tc4) 9.1 configuration TMP86P820UG 9.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) in this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. before starting the timer, set sy scr2 page 99 TMP86P820UG 10. synchronous serial interface (sio) the TMP86P820UG has a clocked- synchronous 8-bit serial interface. serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. serial interface is connected to outside peripherl devices via so, si, sck port. 10.1 configuration figure 10-1 serial interface sio control / status register serial clock shift clock shift register 3 2 1 0 7 6 5 4 transmit and receive data buffer (8 bytes in dbr) control circuit cpu serial data output serial data input 8-bit transfer 4-bit transfer serial clock i/o buffer control circuit so si sck siocr2 siocr1 siosr intsio interrupt request page 100 10. synchronous serial interface (sio) 10.2 control TMP86P820UG 10.2 control the serial interface is controlled by sio control registers (s iocr1/siocr2). the serial interface status can be determined by reading sio status register (siosr). the transmit and receive data buffer is controlled by the siocr2 page 101 TMP86P820UG note 1: the lower 4 bits of each buffer are used during 4-bit tr ansfers. zeros (0) are stored to the upper 4bits when receiving. note 2: transmitting starts at the lowest address. received data are also stored starting from the lowest address to the highest address. ( the first buffer address transmitted is 0f90h ). note 3: the value to be loaded to buf is held after transfer is completed. note 4: siocr2 must be set when the serial interface is stopped (siof = 0). note 5: *: don't care note 6: siocr2 is write-only register, whic h cannot access any of in read-modify-wri te instruction such as bit operate, etc. note 1: t f ; frame time, t d ; data transfer time note 2: after sios is cleared to "0", siof is cleared to "0" at the termination of transfer or the setting of sioinh to "1". figure 10-2 fr ame time (t f ) and data transfer time (t d ) 10.3 serial clock 10.3.1 clock source internal clock or external clock for the source clock is selected by siocr1 page 102 10. synchronous serial interface (sio) 10.3 serial clock TMP86P820UG 10.3.1.1 internal clock any of six frequencies can be selected. the serial clock is output to the outside on the sck pin. the sck pin goes high when transfer starts. when data writing (in the transmit mo de) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wa it function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. note: 1 kbit = 1024 bit (fc = 16 mhz, fs = 32.768 khz) figure 10-3 automatic wait fu nction (at 4-bit transmit mode) 10.3.1.2 external clock an external clock connected to the sck pin is used as the serial clock. in this case, output latch of this port should be set to "1". to ensure shifting, a pulse width of at least 4 machine cycles is required. this pulse is needed for the shift operatio n to execute certainly. actually, there is necessary processing time for interrupting, writing, and reading. the minimum pulse is determined by setting the mode and the pro- gram. therfore, maximum transfer frequenc y will be 488.3k bit/sec (at fc=16mhz). figure 10-4 external clock pulse width table 10-1 serial clock rate normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 sck clock baud rate clock baud rate clock baud rate 000 fc/2 13 1.91 kbps fs/2 5 1024 bps fs/2 5 1024 bps 001 fc/2 8 61.04 kbps fc/2 8 61.04 kbps - - 010 fc/2 7 122.07 kbps fc/2 7 122.07 kbps - - 011 fc/2 6 244.14 kbps fc/2 6 244.14 kbps - - 100 fc/2 5 488.28 kbps fc/2 5 488.28 kbps - - 101 fc/2 4 976.56 kbps fc/2 4 976.56 kbps - - 110 - - - - - - 111 external external external external external external a 1 a 2 b 0 b 1 b 2 b 3 c 0 c 1 a 3 a c b a 0 pin (output) pin (output) written transmit data a utomat i ca ll y wait function sck so t sckl t sckh tcyc = 4/fc (in the normal1/2, idle1/2 modes) 4/fs (in the slow1/2, sleep1/2 modes) t sckl , t sckh > 4tcyc sck pin (output) page 103 TMP86P820UG 10.3.2 shift edge the leading edge is used to transmit, a nd the trailing edge is used to receive. 10.3.2.1 leading edge transmitted data are shifted on the leading edge of the serial clock (falling edge of the sck pin input/ output). 10.3.2.2 trailing edge received data are shifted on the trailing edge of the serial clock (rising edge of the sck pin input/out- put). figure 10-5 shift edge 10.4 number of bits to transfer either 4-bit or 8-bit serial transfer can be selected. when 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer register are used. the upper 4 bits are cleared to ?0? when receiving. the data is transferred in sequence star ting at the least significant bit (lsb). 10.5 number of words to transfer up to 8 words consisting of 4 bits of data (4-bit serial tran sfer) or 8 bits (8-bit serial tr ansfer) of data can be trans- ferred continuously. the number of words to be transferred can be selected by siocr2 page 104 10. synchronous serial interface (sio) 10.6 transfer mode TMP86P820UG figure 10-6 number of words to transfer (example: 1word = 4bit) 10.6 transfer mode siocr1 page 105 TMP86P820UG siocr1 page 106 10. synchronous serial interface (sio) 10.6 transfer mode TMP86P820UG figure 10-9 transmiiied data ho ld time at end of transfer 10.6.2 4-bit and 8- bit receive modes after setting the control registers to the receive mode , set siocr1 page 107 TMP86P820UG figure 10-10 receive mode (example: 8b it, 1word transfer, internal clock) 10.6.3 8-bit trans fer / receive mode after setting the sio control register to the 8-bit transmit/recei ve mode, write the data to be transmitted first to the data buffer registers (dbr). after that, enable the transmit/receive by sett ing siocr1 page 108 10. synchronous serial interface (sio) 10.6 transfer mode TMP86P820UG note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by cl earing siocr1 page 109 TMP86P820UG 11. 8-bit ad converter (adc) the TMP86P820UG have a 8-bit successive approximation type ad converter. 11.1 configuration the circuit configuration of the 8-bit ad converter is shown in figure 11-1. it consists of control registers adccr1 and adccr2, converted value registers adcdr1 and adcdr2, a da converter, a sample-and-hold circuit, a comp arator, and a successive comparison circuit. figure 11-1 8-bit ad converter (adc) 3 4 8 8 ainds analog input multiplexer adrs r/2 r/2 r ack irefon ad conversion result register1,2 ad converter control register 1,2 adbf eocf intadc interrupt sain successive approximate circuit adccr2 adcdr1 adcdr2 adccr1 sample hold circuit 0 y to n s en shift clock da converter reference voltage analog comparator control circuit varef ain0 ain7 vss avdd page 110 11. 8-bit ad converter (adc) 11.1 configuration TMP86P820UG 11.2 control the ad converter consists of the following four registers: 1. ad converter control register 1 (adccr1) this register selects the analog channels in which to perform ad conversion and controls the ad con- verter as it starts operating. 2. ad converter control register 2 (adccr2) this register selects the ad conversion time and controls the connect ion of the da converter (ladder resistor network). 3. ad converted value register (adcdr1) this register is used to store the digital value after being converted by the ad converter. 4. ad converted value register (adcdr2) this register monitors the oper ating status of the ad converter. note 1: select analog input when ad converter stops (adcdr2 |