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VND7050AJ12 double channel high - side driver with currentsense analog feedback for automotive applications datasheet - production data features max transient supply voltage v cc 40 v operating voltage range v cc 4 v to 28 v minimum cranking supply volt age (v cc decreasing) v usd_cranking 2.85 v typ. on - state resistance (per ch) r on 50 m current limitation (typ) i limh 30 a standby current (max) i stby 0.5 a ? automotive qualified ? extreme low voltage operation for deep cold cranking applications (compl iant with lv124, revision 2013) ? general ? double channel smart high - side driver with currentsense analog feedback ? very low standby current ? compatible with 3 v and 5 v cmos outputs ? currentsense diagnostic functions ? multiplexed analog feedback of: load curre nt with high precision proportional current mirror ? overload and short to ground (power limitation) indication ? thermal shutdown indication ? off - state open - load detection ? output short to v cc detection ? sense enable/ disable ? protections ? undervoltage shutdown ? o vervoltage clamp ? load current limitation ? self limiting of fast thermal transients ? loss of ground and loss of v cc ? reverse battery with external components ? electrostatic discharge protection applications ? all types of automotive resistive, inductive and capacitive loads ? specially intended for automotive signal lamps (up to p27w or sae1156 or led rear combinations) description the device is a double channel high - side driver manufactured using st proprietary vipower ? technology and housed in powersso - 12 package. the device is designed to drive 12 v automotive grounded loads through a 3 v a nd 5 v cmos compatible interface, providing protection and diagnostics. the device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown. a current sense delive rs high precision proportional load current sense in addition to the detection of overload and short circuit to ground, short to v cc and off - state open - load. a sense enable pin allows off - state diagnosis to be disabled during the module low - power mode as w ell as external sense resistor sharing among similar devices. gapg040515 11 12cf t p o w erss o -12 september 2015 docid027585 re 3 1 43 tis is information on a proct in fll proction. www.st.com
contents VND7050AJ12 contents 1 block diagram and pin description ................................................ 5 2 electric al specification .................................................................... 7 2.1 absolute maximum ratings ................................................................ 7 2.2 thermal data ..................................................................................... 8 2.3 main electrical characteristics ........................................................... 8 2.4 waveforms ...................................................................................... 18 2.5 electrical characteristics curves ...................................................... 19 3 protections ..................................................................................... 23 3.1 power limitation ............................................................................... 23 3.2 thermal shutdown ........................................................................... 23 3.3 current limitation ............................................................................. 23 3.4 negative voltage clamp ................................................................... 23 4 application information ................................................................ 24 4.1 gnd protection network against reverse battery ............................. 24 4.1.1 diode (dgnd) in the ground line ..................................................... 25 4.2 immunity against transient electrical disturbances .......................... 25 4.3 mcu i/os protection ........................................................................ 26 4.4 behaviour dur ing engine start transients ......................................... 26 4.5 currentsense - analog current sense ............................................. 28 4.5.1 principle of currensense signal generation ..................................... 29 4.5.2 short to vcc and off - state open - load detection ........................... 31 5 maximum demagnetization energy (vcc = 16 v) ........................ 33 6 package and pcb thermal data .................................................... 34 6.1 powersso - 12 thermal data ............................................................ 34 7 package information ..................................................................... 37 7.1 powersso - 12 package information ................................................ 37 7.2 powersso - 12 packing information ................................................. 38 7.3 powersso - 12 marking information ................................................. 40 8 order codes ................................................................................... 41 9 revision history ............................................................................ 42 2 / 43 docid027585 rev 3
VND7050AJ12 list of tables list of tables table 1: pin functions ................................................................................................................................. 5 table 2: suggested connections for unused and not connected pins ........................................................ 6 table 3: absolute maximum ratings ........................................................................................................... 7 table 4: thermal data ................................................................................................................................. 8 table 5: electrical characteristics during cranking ..................................................................................... 8 table 6: power section ............................................................................................................................... 9 table 7: switching ....................................................................................................................................... 9 table 8: logic inputs ................................................................................................................................. 10 table 9: protections .................................................................................................................................. 11 table 10: currentsense ............................................................................................................................ 11 table 11: truth table ................................................................................................................................. 17 table 12: currentsense multiplexer addressing ...................................................................................... 17 table 13: iso 7637 - 2 - ele ctrical transient conduction along supply line ................................................. 26 table 14: test parameters, e - 11 start pulses .......................................................................................... 27 table 15: cranking operating m ode ......................................................................................................... 28 table 16: currentsense pin levels in off - state .......................................................................................... 31 table 17: pcb properties ......................................................................................................................... 34 table 18: thermal parameters ................................................................................................................. 36 table 19: powersso - 12 mechanical data ................................................................................................ 38 table 20: reel dimensions ....................................................................................................................... 38 table 21: powersso - 12 carrier tape dimensions .................................................................................... 39 table 22: device summary ....................................................................................................................... 41 table 23: document revision history ........................................................................................................ 42 docid027585 rev 3 3 / 43
list of figures VND7050AJ12 list of figures figure 1: block diagram .............................................................................................................................. 5 figure 2: configuration diagram (top view) ................................................................................................. 6 figure 3: current and voltage conventions ................................................................................................. 7 figure 4: iout/isense versus iout ....................................................................................................... 14 figure 5: current sense accuracy versus iout ....................................................................................... 15 figure 6: switching times and pulse skew ............................................................................................... 15 figure 7: currentsense timings ................................................................................................................ 16 figure 8: tdstkon .................................................................................................................................. 16 figure 9: standby mode activation ........................................................................................................... 18 figure 10: standby state diagram ............................................................................................................. 18 figure 11: off - state output current ......................................................................................................... 19 figure 1 2: standby current ....................................................................................................................... 19 figure 13: ignd(on) vs. tcase ............................................................................................................... 19 figure 14: logic input high level voltage .................................................................................................. 19 figure 15: logic input low level voltage .................................................................................................... 19 figure 16: high level logic input current ................................................................................................... 19 fig ure 17: low level logic input current .................................................................................................... 20 figure 18: logic input hysteresis voltage ................................................................................................. 20 figure 19: undervoltage shutdown ........................................................................................................... 20 figure 20: on - state resistance vs. tcase ................................................................................................. 20 figure 21: on - state resistance vs. vcc ..................................................................................................... 20 figure 22: turn - on voltage slope .............................................................................................................. 20 figure 23: turn - off voltage slope .............................................................................................................. 21 figure 24: won vs tcase .......................................................................................................................... 21 figure 25: woff vs tcase .......................................................................................................................... 21 figure 26: ilimh vs. tcase ....................................................................................................................... 21 figure 27: off - sta te open - load voltage detection threshold ................................................................... 21 figure 28: vsense clamp vs tcase ........................................................................................................... 21 figure 29: vsenseh vs tcase ................................................................................................................... 22 figure 30: application diagram ................................................................................................................. 24 figure 31: simplified internal structure - gnd network protection with schottly diode ............................ 24 figure 32: simplified internal structure - gnd network protection with mosfet .................................... 25 figure 33: cranking profile ....................................................................................................................... 27 figure 34: currentsense and diagnostic ? block diagram ........................................................................ 28 figure 35: currentsense block diagram ................................................................................................... 29 fig ure 36: analogue hsd ? open - load detection in off - state ................................................................... 30 figure 37: open - load / short to vcc condition ......................................................................................... 31 figure 38: maximum t urn off current versus inductance .......................................................................... 33 figure 39: powersso - 12 on two - layers pcb (2s0p to jedec jesd 51 - 5) ............................................ 34 figure 40: powersso - 1 2 on four - layers pcb (2s2p to jedec jesd 51 - 7) ........................................... 34 figure 41: rthj - amb vs pcb copper area in open box free air condition (one channel on) ..................... 35 figure 42: powersso - 12 thermal impedance junction ambient single pulse (one channel on) .............. 35 figure 43: thermal fitting model of a double - channel hsd in powersso - 12.......................................... 36 figure 44: powersso - 12 package dimensions ........................................................................................ 37 figure 45: powersso - 12 reel 13" ............................................................................................................ 38 figure 46: powersso - 12 carrier tape ...................................................................................................... 39 figure 47: powersso - 12 schematic drawing of leader and trailer tape .................................................. 40 figure 48: power sso - 12 marking information ......................................................................................... 40 4 / 43 docid027585 rev 3
VND7050AJ12 block diagram and pin description 1 block diagram and pin description figure 1 : block diagram t able 1: pin functions name function v cc battery connection. output 0,1 power output. gnd ground connection. must be reverse battery protected by an external diode/resistor network. input 0,1 voltage controlled input pins with hysteresis, compatible with 3 v and 5 v cmos outputs. they control output switch state. currentsense multiplexed analog sense output pin; it delivers a current proportional to the load current. sen active high compatible with 3 v and 5 v cmos outputs pin; it enables the currentsens e diagnostic pin. sel active high compatible with 3 v and 5 v cmos outputs pin; it addresses the currentsense multiplexer. docid027585 rev 3 5 / 43
block diagram and pin description VND7050AJ12 figure 2 : configuration diagram (top view) table 2: suggested connections for unused and not connected pins connection/pin currentsense n.c. output input sen, sel floating not allowed x (1) x x x to ground through 1 k resistor x not allowed through 15 k resistor through 15 k resistor notes: (1) x: do not care. 6 / 43 docid027585 rev 3
VND7050AJ12 electrical specification 2 electrical specification figure 3 : current and voltage conventions v fn = v outn - v cc during reverse battery condition. 2.1 absolute maximum ratings stressing the device above the rating listed in table 3: "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operati ng sections of this specification is not implied. exposure to the conditions in table below for extended periods may affect device reliability. table 3: absolute maximum ratings symbol parameter value unit v cc dc supply voltage 38 v -v cc reverse dc suppl y voltage 0.3 v v ccpk maximum transient supply voltage (iso 16750 - 2:2010 test b clamped to 40 v; r l = 4 ) 40 v v ccjs maximum jump start voltage for single pulse short circuit protection 28 v -i gnd dc reverse ground pin current 200 ma i out output 0,1 dc output current internally limited a -i out reverse dc output current 11 i in input 0,1 dc input cu rrent - 1 to 10 ma i sen sen dc input current i sel sel dc input current i sense currentsense pin dc output current (v gnd = v cc and v sense < 0 v) 10 ma currentsense pin dc output current in reverse (v cc < 0v) -20 docid027585 rev 3 7 / 43
electrical specification VND7050AJ12 symbol parameter value unit e max maximum switching energy (singl e pulse) (t demag = 0.4 ms; t jstart = 150 c) 30 mj v esd electrostatic discharge (jedec 22a - 114f) ? input 0,1 ? currentsense ? sen, sel ? output 0,1 ? v cc 4000 2000 4000 4000 4000 v v v v v v esd charge device model (cdm -aec - q100-011) 750 v t j junction operating te mperature - 40 to 150 c t stg storage temperature - 55 to 150 2.2 thermal data table 4: thermal data symbol parameter typ. value unit r thj - board thermal resistance junctio n - board (jedec jesd 51 - 5 / 51 - 8) (1) (2) 6.4 c/w r thj - amb thermal resistance junction - ambient (jedec jesd 51 - 5) (1) (3) 5 9 r thj - amb thermal resistance junction - ambient (jedec jesd 51 - 7) (1) (2) 25 notes: (1) one channel on. (2) device mounted on four - layers 2s2p pcb. (3) device mounted on two - layers 2s0p pcb with 2 cm 2 heatsink copper trace. 2.3 main electrical characteristics 7 v < v cc < 28 v; - 40 c < t j < 150 c, unless otherwise specified. all typical va lues refer to v cc = 13 v; t j = 25c, unless otherwise specified. table 5: electrical characteristics during cranking symbol parameter test conditions min. typ. max. unit v usd_cranking minimum cranking supply voltage (v cc decreasing) 2.85 v r on on - stat e resistance (1) i out = 0.5 a; v cc = 2.85 v; v cc decreasing 500 m t tsd (2) shutdown temperature (v cc decreasing) v cc = 2.85 v 140 c notes: (1) for each channel. (2) parameter guaranteed by design and characterization; not subject to production test. 8 / 43 docid027585 rev 3
VND7050AJ12 electrical specification table 6: power section symbol parameter test conditions min. typ. max. unit v cc operating supply voltage 4 13 28 v v usd undervoltage shutdown 2.85 v usdreset undervoltage shutdown reset 5 v usdhyst undervoltage shutdown hysteresis 0.3 r on on - state resistance (1) i out = 2 a; t j = 25 c 50 m i out = 2 a; t j = 150 c 100 i out = 2 a; v cc = 4 v; t j = 25 c 75 v clamp clamp voltage i s = 20 ma; t j = -40 c 38 v i s = 20 ma; 25c < t j < 150c 41 46 52 i stby supply current in standby at v cc = 13 v (2) v cc = 13 v; v in = v out = v sen = 0 v; v sel = 0 v; t j = 25 c 0.5 a v cc = 13 v; v in = v out = v sen = 0 v; v sel = 0 v; t j = 85 c (3) 0.5 a v cc = 13 v; v in = v out = v sen = 0 v; v sel = 0 v; t j = 125 c 3 a t d_stby standby mode blanking time v cc = 13 v; v in = v out = v sel = 0 v; v sen = 5 v to 0 v 60 300 550 a i s(on) supply current v cc = 13 v; v sen = v sel = 0 v; v in0 = 5 v; v in1 = 5 v; i out0 = 0 a; i out1 = 0 a 5 8 ma i gnd(on) control stage current consum ption in on state. all channels active. v cc = 13 v; v sen = 5 v; v sel = 0 v; v in0 = 5 v; v in1 = 5 v; i out0 = 2 a; i out1 = 2 a 12 ma i l(off) off - state output current at v cc = 13 v (1) v in = v out = 0 v; v cc = 13 v; t j = 25 c 0 0.01 0.5 a v in = v out = 0 v; v cc = 13 v; t j = 125 c 0 3 v f output - v cc diode voltage (1) i out = -2 a; t j = 150 c 0.7 v notes: (1) for each channel. (2) powermos leakage included. (3) parameter specified by d esign; not subject to production test. table 7: switching v cc = 13 v; - 40c < t j < 150c, unless otherwise specified symbol parameter test conditions min. typ. max. unit t d(on) (1) turn - on delay time at t j = 25c r l = 6.5 10 60 120 s t d(off) (1) turn - off delay time at t j = 25c 10 40 100 (dv out /dt) on (1) turn - on voltage slope at t j = 25c r l = 6.5 0.1 0.3 0.7 v/s (dv out /dt) off (1) turn - off voltage slope at t j = 25c 0.1 0.32 0.7 docid027585 rev 3 9 / 43
electrical specification VND7050AJ12 v cc = 13 v; - 40c < t j < 150c, unless otherwise specified symbol parameter test conditions min. typ. max. unit w on switching energy losses at turn - on (t won ) r l = 6.5 ? 0.25 0.33 (2) mj w off switching energy losses at turn - off (t woff ) r l = 6.5 ? 0.23 0. 31 (2) mj t skew (1) differential pulse skew (t phl - t plh ) r l = 6.5 -80 -30 20 s notes: (1) see figure 6: "switching times and pulse skew" (2) paramete r guaranteed by design and characterization; not subject to production test. table 8: logic inputs 7 v < v cc < 28 v; - 40c < t j < 150c symbol parameter test conditions min. typ. max. unit input 0,1 characteristics v il input low level voltage 0.9 v i il low level input current v in = 0.9 v 1 a v ih input high level voltage 2.1 v i ih high level input current v in = 2.1 v 10 a v i(hyst) input hysteresis voltage 0.2 v v icl input clamp voltage i in = 1 ma 5.3 7.2 v i in = -1 ma - 0.7 sel characteristics (7 v < v cc < 18 v) v sell input low level voltage 0.9 v i sell low level input current v in = 0.9 v 1 a v selh input high level voltage 2.1 v i selh high level input current v in = 2.1 v 10 a v sel(hyst) input hysteresis voltage 0.2 v v selcl input clamp voltage i in = 1 ma 5.3 7.2 v i in = -1 ma - 0.7 sen characteristics (7 v < v cc < 18 v) v senl input low level voltage 0.9 v i senl low level input current v in = 0.9 v 1 a v senh input high level voltage 2.1 v i s enh high level input current v in = 2.1 v 10 a v sen(hyst) input hysteresis voltage 0.2 v v sencl input clamp voltage i in = 1 ma 5.3 7.2 v i in = -1 ma - 0.7 10/ 43 docid027585 rev 3
VND7050AJ12 electrical specification table 9: protections 7 v < v cc < 18 v; - 40c < t j < 150c symbol parameter test con ditions min. typ. max. unit i limh dc short circuit current v cc = 13 v 21 30 42 a 4 v < v cc < 18 v (1) 42 i liml short circuit current during thermal cycling v cc = 13 v; t r < t j < t tsd 10 t tsd shutdown temperatu re 150 175 200 c t r reset temperature (1) t rs + 1 t rs + 7 t rs thermal reset of fault diagnostic indication v sen = 5 v 135 t hyst thermal hysteresis (t tsd - t r ) (1) 7 t j_sd dynamic temperature t j = -40 c; v cc = 13 v 60 k v demag turn - off output voltage clamp i out = 2 a; l = 6 mh; t j = -40 c v cc - 38 v i out = 2 a; l = 6 mh; t j = 25 c to +150 c v cc - 41 v cc - 46 v cc - 52 v on output voltage drop limitation i out = 0 .2 a 20 mv notes: (1) parameter guaranteed by design and characterization; not subject to production test. table 10: currentsense 7 v < v cc < 18 v; - 40c < t j < 150c symbol parameter test conditions min. typ. max. unit v sense_cl currentsense clamp voltage v sen = 0 v; i sense = 1 ma -17 -12 v v sen = 0 v; i sense = -1 ma 7 v currentsense characteristics k ol i out /i sense i out = 0.01 a; v sense = 0.5 v; v sen = 5 v 440 dk cal /k cal (1) (2) current sense ratio drift at calibration point i out = 0.01 a to 0.05 a; i cal = 30 ma; v sense = 0.5 v; v sen = 5 v -30 30 % k led i out /i sense i out = 0.05 a; v sense = 0.5 v; v sen = 5 v 530 1450 2200 dk led /k led (1) (2) current sense ratio drift i out = 0.05 a; v sense = 0.5 v; v sen = 5 v -25 25 % k 0 i out /i sense i out = 0.2 a; v sense = 0.5 v; v sen = 5 v 830 1400 1935 dk 0 /k 0 (1) (2) current sense ratio drift i out = 0.2 a; v sense = 0.5 v; v sen = 5 v -20 20 % k 1 i out /i sense i out = 0.4 a; v sense = 4 v; v sen = 5 v 915 1300 1700 docid027585 rev 3 11/ 43
electrical specification VND7050AJ12 7 v < v cc < 18 v; - 40c < t j < 150c symbol parameter test conditions min. typ. max. unit dk 1 /k 1 (1) (2) current sense ratio drift i out = 0.4 a; v sense = 4 v; v sen = 5 v -15 15 % k 2 i out /i sense i out = 1.5 a; v sense = 4 v; v sen = 5 v 980 1230 1470 dk 2 /k 2 (1) (2) current sense ratio drift i out = 1. 5 a; v sense = 4 v; v sen = 5 v -10 10 % k 3 i out /i sense i out = 4.5 a; v sense = 4 v; v sen = 5 v 1095 1215 1335 dk 3 /k 3 (1) (2) current sense ratio drift i out = 4.5 a; v sense = 4 v; v sen = 5 v -5 5 % i sense0 currentsense leakage current currentsense disabled: v sen = 0 v; 0 0.5 a currentsense disabled: -1 v < v sense < 5 v (1) - 0.5 0.5 a currentsense enabled: v sen = 5 v; all channel on; i outx = 0 a; ch x diagnostic selected; ? e.g. ch 0 : v in0 = 5 v; v in1 = 5 v; v sel = 0 v; i out0 = 0 a; i out1 = 2 a 0 2 a currentsense enabled: v sen = 5 v; ch x channel off; ch x diagnostic selected; ? e.g. ch 0 : v in0 = 0 v; v in1 = 5 v; v sel = 0 v; i out1 = 2 a 0 2 a v out_msd (1) output voltage for currentsense shutdown v sen = 5 v; r sense = 2.7 k ? e.g. ch 0 : v in0 = 5 v; v sel = 0 v; i out0 = 2 a 5 v v sense_sat currentsense saturation voltage v cc = 7 v; r sense = 2.7 k; v sen = 5 v; v in 0 = 5 v; v sel = 0 v; i out0 = 4.5 a; t j = 150c 5 v i sense_sat (1) cs saturation current v cc = 7 v; v sense = 4 v; v in0 = 5 v; v sen = 5 v; v sel0 = 0 v; v sel1 = 0 v; t j = 150c 4 ma 12/ 43 docid027585 rev 3
VND7050AJ12 electrical specification 7 v < v cc < 18 v; - 40c < t j < 150c symbol parameter test conditions min. typ. max. unit i out_sat (1) output saturation current v cc = 7 v; v sense = 4 v; v in0 = 5 v; v sen = 5 v; v sel = 0 v; t j = 150c 6 a off - state diagnostic v ol off - state open- load voltage detection threshold v sen = 5 v; ch x off; ch x diagnostic selected ? e.g: ch 0 v in0 = 0 v; v sel = 0 v 2 3 4 v i l(off2) off - state output sink current v in = 0 v; v out = v ol -100 -15 a t dstkon off - state diagnostic delay time from falling edge of input (see figure 8: "tdstkon" ) v sen = 5 v; ch x on to off transitio n ch x diagnostic selected ? e.g: ch 0 v in0 = 5 v to 0 v; v sel = 0 v; i out0 = 0 a; v out = 4 v 100 350 700 s t d_ol_v settling time for valid off - state open load diagnostic indication from rising edge of sen v in0 = 0 v; v in1 = 0 v; v sel = 0 v; v out0 = 4 v; v sen = 0 v to 5 v 60 s t d_vol off - state diagnostic delay time from rising edge of v out v sen = 5 v; ch x off ch x diagnostic selected ? e.g: ch 0 v in0 = 0 v; v sel = 0 v; v out = 0 v to 4 v 5 30 s fault diagnostic feedback (see table 11: "truth table" ) v senseh currentsense output voltage in fault condition v cc = 13 v; r sense = 1 k ? e.g: ch 0 in open load v in0 = 0 v; v sen = 5 v; v sel = 0 v; i out0 = 0 a; v out = 4 v 5 6.6 v i senseh currentsense output current in fault condition v cc = 13 v; v sense = 5 v 7 20 30 ma currentsense timings (current sense mode - see figure 7: "currentsense timings" ) (3) t dsense1h current sense settling time from rising edge of sen v in = 5 v; v sen = 0 v to 5 v; r sense = 1 k; r l = 6.5 60 s t dsense1l current sense disable delay ti me from falling edge of sen v in = 5 v; v sen = 5 v to 0 v; r sense = 1 k; r l = 6.5 5 20 s t dsense2h current sense settling time from rising edge of input v in = 0 v to 5 v; v sen = 5 v; r sense = 1 k; r l = 6.5 100 250 s docid027585 rev 3 13/ 43
electrical specification VND7050AJ12 7 v < v cc < 18 v; - 40c < t j < 150c symbol parameter test conditions min. typ. max. unit t dsense2h current sense sett ling time from rising edge of i out (dynamic response to a step change of i out ) v in = 5 v; v sen = 5 v; r sense = 1 k; i sense = 90 % of i sensemax ; r l = 6.5 100 s t dsense2l current sense turn - off delay time from falling edge of input v in = 5 v to 0 v; v sen = 5 v; r sense = 1 k; r l = 6.5 50 250 s currentsense timings (multiplexer transition times) (3) t d_xtoy currentsense transition delay from ch x to ch y v in0 = 5 v; v in1 = 5 v; v sen = 5 v; v sel = 0 v to 5 v; i out 0 = 0a; i out1 = 3 a; r sense = 1 k 20 s t d_cstovsenseh currentsense transition delay from stable current sense on ch x to v senseh on ch y v in0 = 5 v; v in1 = 0 v; v sen = 5 v; v sel = 0 v to 5 v; i out0 = 3 a; v out1 = 4 v; r sense = 1 k 20 s notes: (1) parameter guaranteed by design and characterization; not subject to production test. (2) all values refer to v cc = 13 v; t j = 25c, unless otherwise specified. (3) transition delay are measured up to +/ - 10% of final conditions. figure 4 : iout/isense versus iout 14/ 43 docid027585 rev 3
VND7050AJ12 electrical specification figure 5 : current sense accuracy versus iout figure 6 : switching times and pulse skew v ou t t v cc twon 80 % vcc 20 % vcc two f f inpu t td ( on ) tplh tph l td ( o f f ) t dv ou t /dt on off dv ou t /dt gapgcft00797 docid027585 re 3 15 43
electrical specification VND7050AJ12 figure 7 : currentsense timings figure 8 : tdstkon g a p g 0912131101 c f t t d s t k o n v i n p u t v o u t c u rr en t s en se v o u t > v o l 16/ 43 docid027585 rev 3
VND7050AJ12 electrical specification table 11: truth table mode conditions in x sen sel out x currentsense comments standby all logic inputs low l l l l hi -z low quiescent current consumption normal nominal load connected; t j < 150c l see (1) l see (1) h h see (1) outputs configured for auto - restart h h see (1) outputs configured for latch off overload overload or short to gnd causing: t j > t tsd or t j > t j_sd l see (1) l see (1) h h see (1) output cycles with temperature hysteresis h l see (1) output latches off under - voltage v cc < v usd (falling) x x x l l hi -z hi -z re - start when v cc > v usd + v usdhyst (rising) off - state diagnostics short to v cc l see (1) h see (1) open - load l h see (1) external pull up negative output voltage inductive loads turn - off l see (1) < 0 v see (1) notes: (1) refer to table 12: "currentsense multiplexer addressing" table 12: currentsense multiplexer addressing sen sel mux channel currentsense output normal mode overload off - state diag. negative output l x hi -z h l channel 0 dia gnostic i sense = 1/k * i out0 v sense = v senseh v sense = v senseh hi -z h h channel 1 diagnostic i sense = 1/k * i out1 v sense = v senseh v sense = v senseh hi -z docid027585 rev 3 17/ 43
electrical specification VND7050AJ12 2.4 waveforms f igure 9 : standby mode activation figure 10 : standby state diagram n o rm a l o p e r a t i o n s t a nd - b y m od e i n x = lo w a n d se n = lo w a n d s e l = lo w i n x = hi g h o r se n = hi g h o r s e l = hi g h g a p g 2911131147 c f t t > t d _ s t b y 18 43 docid027585 re 3
VND7050AJ12 electrical specification 2.5 electrical characteristics curves figure 1 1 : off - state output current figure 12 : standby current figure 13 : ignd(on) vs. tcase figure 14 : logic input high level voltage f igure 15 : logic input low level voltage figure 16 : high level logic input current docid027585 rev 3 19/ 43
electrical specification VND7050AJ12 figure 17 : low level logic input current figure 18 : logic input hy steresis voltage figure 19 : undervoltage shutdown figure 20 : on - state resistance vs. tcase figure 21 : on - state resistance vs. vcc figure 22 : tur n - on voltage slope 20/ 43 docid027585 rev 3
VND7050AJ12 electrical specification figure 23 : turn - off voltage slope figure 24 : won vs tcase figure 25 : woff vs tcase figure 26 : ilimh vs. tcase figure 27 : off - state open - load voltage detection threshold figure 28 : vsense clamp vs tcase docid027585 rev 3 21/ 43
electrical specification VND7050AJ12 figure 29 : vsenseh vs tcase gapg2110131629cft 0 1 2 3 4 5 6 7 8 9 1 0 - 5 0 - 2 5 0 2 5 5 0 7 5 10 0 12 5 15 0 17 5 t [ c ] vse n se h [ v ] 22/ 43 docid027585 rev 3
VND7050AJ12 protections 3 protections 3.1 power limitation the basic working principle of this protection consists of an indirect measurement of the junction temperature swing t j through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output mosfet as soon as t j exceeds the safety level of t j_sd . the output mosfet switches on and cycles with a ther mal hysteresis according to the maximum instantaneous power which can be handled. the protection prevents fast thermal transient effects and, consequently, reduces thermo - mechanical fatigue. 3.2 thermal shutdown in case the junction temperature of the device exceeds the maximum allowed threshold (typically 175c), it automatically switches off and the diagnostic indication is triggered. the device switches on again as soon as its junction temperature drops to t r . 3.3 current limitation the device is equipped with an output current limiter in order to protect the silicon as well as the o ther components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. consequently, in case of short circuit, overload or during load power - up, the output current is clamped to a safety level, i limh , by op erating the output power mosfet in the active region. 3.4 negative voltage clamp in case the device drives inductive load, the output voltage reaches a negative v alue during turn off. a negative voltage clamp structure limits the maximum negative voltage to a certain value, v demag , allowing the inductor energy to be dissipated without damaging the device. docid027585 rev 3 23/ 43
application information VND7050AJ12 4 application information figure 30 : application diagram 4.1 gnd protection network against reverse battery figure 31 : simplified internal structure - gnd network protection with schottly diode 24/ 43 docid027585 rev 3
VND7050AJ12 application information figure 32 : simplified internal structure - gnd network protection with mosfet 4.1.1 diode (d gnd) in the ground line a resistor (typ. r gnd = 4.7 k) should be inserted in parallel to d gnd if the device drives an inductive load. this small signa l diode can be safely shared amongst several different hsds. also in this case, the presence of the ground network produces a shift (?600 mv) in the input threshold and in the status output values if the microprocessor ground is not common to the device gr ound. this shift does not vary if more than one hsd shares the same diode/resistor network. to comply with lv124, e - 11 "severe" start pulse, a schottky diode (see figure 31: "simplified internal structure - gnd network prote ction with schottly diode" ) or n - channel mosfet (see figure 32: "simplified internal structure - gnd network protection with mosfet" ) is recommended in order to ensure a lower ground network shift ( 350 mv). 4.2 immunity agai nst transient electrical disturbances the immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the v cc pin, is tested in accordance with iso7637 - 2:2011 (e) and iso 16750 - 2:2010. the related function performance status classification is shown in table 13: "iso 7637 - 2 - electrical transient condu ction along supply line" . test pulses are applied directly to dut (device under test) both in on and off - state and in accordance to iso 7637 - 2:2011(e), chapter 4. the dut is intended as the present device only, without components and accessed through v cc and gnd terminals. docid027585 rev 3 25/ 43
application information VND7050AJ12 status ii is defined in iso 7637 - 1 function performance status classification (fpsc) as follows: ?the function does not perform as designed during the test but returns automatically to normal operation after the test?. table 13: iso 7637 -2 - electrical transient conduction along supply line test pulse 2011(e) test pulse severity level with status ii functional performance status minimum number of pulses or test time burst cycle / pulse repetition time pulse duration and pulse generator in ternal impedance level u s (1) min max 1 iii -112v 500 pulses 0,5 s 2ms, 10 2a iii +55v 500 pulses 0,2 s 5 s 50s, 2 3a iv -220v 1h 90 ms 100 ms 0.1s, 50 3b iv +150v 1h 90 ms 100 ms 0.1s, 50 4 (2) iv -7v 1 pulse 100ms, 0.01 load dump according to iso 16750 - 2:2010 test b (3) 40v 5 pulse 1 min 400ms, 2 notes: (1) u s is the peak amplitude as defined for each test pulse in iso 7637 - 2:2011(e), chapter 5.6. (2) test pulse from iso 7637 - 2:2004(e). (3) with 40 v external suppressor referred to gr ound ( - 40c < t j < 150c). 4.3 mcu i/os protection if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line both to prevent the microcontroller i/o pins to latch - up and to protect the hsd inputs. the value of these resistors is a compromise between the leakage current of microcontroller and the current required by the hsd i/os (input levels compatibility) with the latch - up limit of microcontroller i/os. equation v ccpeak /i latchup r prot (v ohc - v ih - v gnd ) / i ihmax calculation example: for v ccpeak = - 150 v; i latchup 20 ma; v ohc 4.5 v 7.5 k r prot 140 k. recommended values: r prot = 15 k 4.4 behaviour during engine start transients the battery voltage drops every time an engin e start occurs as well as in start&stop automotive systems. the device is designed to operate during engine start pulses without external components. in particular, the device achieves functional status a, for both e - 11 start pulses, ?normal? and ?severe? as defined in table 14: "test parameters, e - 11 start pulses" . 26/ 43 docid027585 rev 3
VND7050AJ12 application info rmation functional status a is defined as follows: the dut (device under test) must fulfill all functions during and after exposure to the test parameters. table 14: tes t parameters, e - 11 start pulses parameter test pulse ?normal? test pulse ?severe? v b 11,0 v 11,0 v v t 4,5 v (0%, - 4%) 3,2 v +0,2v v s 4,5 v (0%, - 4%) 5,0 v (0%, - 4%) v a 6,5 v (0%, - 4%) 6,0 v (0%, - 4%) v r 2 v 2 v t f 1 ms 1 ms t 4 0 ms 19 ms t 5 0 ms 1 ms t 6 19 ms 329 ms t 7 50 ms 50 ms t 8 10 s 10 s t r 100 ms 100 ms f 2 hz 2 hz break between two cycles 2 s 2 s test cycles 10 10 for more details see standard norm ?lv124 - electric and electronic components in motor vehicles up to 3.5 t?. f igure 33 : cranking profile the extremely low v usd_cranking , minimum cranking supply voltage (v cc decreasing), specification of 2.85 v, much lower than the standard requirement, allows the device docid027585 rev 3 27/ 43
application information VND7050AJ12 operating in all the applications where a ground network protection is required (see section 4.1: "gnd protection network against reverse battery" ). table 15: cranking operating mode operating range voltage range operating mode normal mode 4 v to 28 v 18 v - 28 v all functions are performed as specified. some deviations of the electrical characteristics. 7 v - 18 v all functions are performed as specified. all parameters in range. 4 v - 7 v all functions are performed as specified. some deviations of th e electrical characteristics. cranking mode 2.85 v to 4 v 2.85 v - 4 v device is operating (v cc decreasing). device is protected. no diagnostic. electrical parameters deviations. 4.5 currentsense - analog current sense diagnostic information on device and load status are provided by an analog output pin (currentsense) delivering a current mirror of channel output current figure 34 : currentsense and diagnostic ? block diagram 28/ 43 docid027585 rev 3
VND7050AJ12 application information 4.5.1 principle of currensense signal generation figure 35 : currentse nse block diagram current monitor this output is capable of providing: ? current mirror proportional to the load current in normal operation , delivering current proportional to the load according to known ratio named k ? diagnostics flag in fault conditions delivering fixed voltage v senseh the current delivered by the current sense circuit, i sense , can be easily converted to a voltage v sense by using an external sense resistor, r sense , allowing continuous load monitoring and abnormal condition detection. norm al operation (channel on, no fault, sen active) while device is operating in normal conditions (no fault intervention), v sense calculation can be done using simple equations current provided by currentsense output: i sense = i out /k voltage on r sense : v sense = r sense . i sense = r sense . i out /k where : ? v sense is voltage measurable on r sense resistor docid027585 rev 3 29/ 43
application information VND7050AJ12 ? i sense is current provided from currentsense pin in current output mode ? i out is current flowing through output ? k factor represents the ratio between powermos cells and sensemos cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between i out and i sense . failure flag indication in case of power limitation/overtem perature, the fault is indicated by the currentsense pin which is switched to a ?current limited? voltage source, v senseh . in any case, the current sourced by the currentsense in this condition is limited to i senseh . the typical behavior in case of overloa d or hard short circuit is shown in waveforms section . figure 36 : analogue hsd ? open - load detection in off - state 30/ 43 docid027585 rev 3
VND7050AJ12 application information figure 37 : open - load / short to vcc condition table 16: currentsense pin levels in off - s tate condition output currentsense sen open - load v out > v ol hi -z l v senseh h v out < v ol hi -z l 0 h short to v cc v out > v ol hi -z l v senseh h nominal v out < v ol hi -z l 0 h 4.5.2 short to vcc and off - state open - load detection short to v cc a short circuit between v cc and output is indicated by the relevant current sense pin set to v senseh during th e device off - state. small or no current is delivered by the current sense during the on - state depending on the nature of the short circuit. off - state open - load with external circuitry detection of an open - load in off mode requires an external pull - up resis tor r pu connecting the output to a positive supply voltage v pu . it is preferable v pu to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. docid027585 rev 3 31/ 43
application information VND7050AJ12 r pu must be selected in order to ensure v out > v olmax in accordance with the following equation: equation r pu < v pu - 4 i l(off2)min @ 4v 32 43 docid027585 re 3
VND7050AJ12 maximum demagnetization energy (vcc = 16 v) 5 maximum demagnetization energy (vcc = 16 v) figure 38 : maximum turn off current versus inductance values are generated with r l = 0 . 0 . 1 1 1 0 1 0 0 0 . 1 1 1 0 1 0 0 1 0 0 0 i ( a) l ( m h) maximum turn o f f current versus inductance single pulse r e p e t i t i v e p u l s e t j s t a r t = 10 0 c r e p e t i t i v e p u l s e t j s t a r t = 12 5 c gapg0912131502cf t docid027585 rev 3 33/ 43
package and pcb thermal data VND7050AJ12 6 package and pcb thermal data 6.1 powersso - 12 thermal data figure 39 : powersso - 12 on two - layers pcb (2s0p to jedec jesd 51-5) figure 40 : powersso - 12 on four - layers pcb (2s2p to jedec jesd 51-7) table 17: pcb properties dimension value board finish thickness 1.6 mm +/ - 10% board dimension 77 mm x 86 mm board material fr4 copper thickness (top and bottom layers) 0.070 mm copper thickness (inner layers) 0.035 mm thermal via separation 1.2 mm thermal via diameter 0.3 mm +/ - 0.08 mm copper thickness on via 0.025 mm footprint dimension (top layer) 2.2 mm x 3.9 mm heatsink copper area dimension (bottom layer) footprint, 2 cm 2 or 8 cm 2 34/ 43 docid027585 rev 3
VND7050AJ12 package and pcb thermal data figure 41 : rthj - amb vs pcb copper area in open box free ai r condition (one channel on) figure 42 : powersso - 12 thermal impedance junction ambient single pulse (one channel on) equation: pulse calculation formula z th = r th + z thtp (1 - ) where = t p /t docid027585 rev 3 35/ 43
package and pcb thermal data VND7050AJ12 figure 43 : thermal fitting model of a double - channel hsd in powersso -12 the fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. table 18: thermal parameters area/island (cm 2 ) footprint 2 8 4l r1 = r7 (c/w) 1.8 r2 = r8 (c/w) 3.2 r3 (c/w) 8 8 8 6 r4 (c/w) 14 6 6 4 r5 (c/w) 30 20 10 3 r6 (c/w) 26 20 18 7 c1 = c7 (w.s/c) 0.00035 c2 = c8 (w.s/c) 0.005 c3 (w.s/c) 0.05 c4 (w.s/c) 0.2 0.3 0.3 0.4 c5 (w.s/c) 0.4 1 1 4 c6 (w.s/c) 3 5 7 18 36/ 43 docid027585 rev 3
VND7050AJ12 package information 7 package information in order to meet environmental requirements, st offe rs these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 powersso - 12 package i nformation figure 44 : powersso - 12 package dimensions docid027585 rev 3 37/ 43
package information VND7050AJ12 table 19: powersso - 12 mechanical data symbol millimeters min. ty p. max. a 1.250 1.700 a1 0.000 0.100 a2 1.100 1.600 b 0.230 0.410 c 0.190 0.250 d 4.800 5.000 e 3.800 4.000 e 0.800 h 5.800 6.200 h 0.250 0.500 l 0.400 1.270 k 0 8 x 2.200 2.800 y 2.900 3.500 ddd 0.100 7.2 powersso - 12 packin g information figure 45 : powersso - 12 reel 13" table 20: reel dimensions description value (1) base quantity 2500 bulk quantity 2500 a (max) 330 b (min) 1.5 38/ 43 docid027585 rev 3
VND7050AJ12 package information description value (1) c (+0.5, - 0.2) 13 d (min) 20.2 n 100 w1 (+2 / -0) 12.4 w2 (max) 18.4 notes: (1) all dimensions are in mm. figure 46 : powersso - 12 carrier tape table 21 : powersso - 12 carrier tape dimensions description value (1) a 0 6.50 0.1 b 0 5.25 0.1 k 0 2.10 0.1 k 1 1.80 0.1 f 5.50 0.1 p 1 8.00 0.1 w 12.00 0.3 notes: (1) all dimensions are in mm. 0.30 0.05 1.55 0.05 1.60.1 r 0.5 t ypical k 1 k 0 b 0 p 2 2.0 0.1 p 0 4.0 0.1 p 1 a 0 f w 1.75 0.1 se c tion x - x se c tion y - y ref 4.18 ref 0.6 ref 0.5 x x y y gapg2204151242cft docid027585 re 3 39 43
package information VND7050AJ12 figure 47 : powersso - 12 schematic drawing of leader and trailer tape 7.3 powersso - 12 marking information figure 48 : powersso - 12 mar king information engineering samples: these samples can be clearly identified by a dedicated special symbol in the marking of each unit. these samples are intended to be used for electrical compatibility evaluation only; usage for any other purpose ma y be agreed only upon written authorization by st. st is not liable for any customer usage in production and/or in reliability qualification trials. commercial samples: fully qualified parts from st standard production with no usage restrictions gapg1203151332cft 1 2 3 4 5 6 7 8 m ar k ing a r ea sp ecial fun c tion digit &: en g inee r ing sample : c omme r cial sample p o w erss o -12 t op vi e w (not in scale) 40 43 docid027585 re 3
VND7050AJ12 order codes 8 order co des table 22: device summary package order codes tape and reel powersso -12 VND7050AJ12tr docid027585 rev 3 41/ 43
revision history VND7050AJ12 9 revision history table 23: document revision history date revision changes 09- jun - 2015 1 initial release. 18- jun - 2015 2 table 5: "electrical characteristics during cranking" : ? t tsd : updated value updated table 7: "switching" table 10: "currentsense" : ? k ol , k led , k 0 , k 1 , k 2 : updated values 14- sep - 2015 3 updated table 1: "pin functions" t able 5: "electrical characteristics during cranking" : ? r on : updated test conditions 42/ 43 docid027585 rev 3
VND7050AJ12 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (? st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing ord ers. st products are sold pursuant to st?s terms and conditions of sale in place at the time of order acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for applicati on assist ance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty grante d by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior version s of this document. ? 2015 stmicroelectronics ? all rights reserved docid027585 rev 3 43/ 43

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