View SI53112_8393202.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.1 12/15 copyright ? 2015 by silicon laboratories SI53112 SI53112 db1200zl 12-o utput pci e g en 3 b uffer features applications description the SI53112 is a low-power, 12-output, differential clock buffer that meets all of the performance requirements of the intel db1200zl specification. the device is optimized for distributing reference clocks for intel ? quickpath interconnect (intel qpi), pcie gen 1/gen 2/gen 3/gen 4, sas, sata, and intel scalable me mory interconne ct (intel smi) applications. the vco of the device is optimized to support 100 mhz and 133 mhz operation. each differential output has a dedicated hardware output enable pin for maximum flex ibility and power sa vings. measuring pcie clock jitter is quick and easy wit h the silicon labs pcie clock jitter tool. download it for free at www.silabs.com/pcie-learningcenter . ? twelve 0.7 v low-power, push- pull, hcsl-compatible pcie gen 3 outputs ? individual oe hw pins for each output clock ? 100 mhz /133 mhz pll operation, supports pcie and qpi ? pll bandwidth sw smbus programming overrides the latch value from hw pin ? 9 selectable smbus addresses ? smbus address configurable to allow multiple buffers in a single control network 3.3 v supply voltage operation ? pll or bypass mode ? spread spectrum tolerable ? 1.05 to 3.3 v i/o supply voltage ? 50 ps output-to-output skew ? 50 ps cyc-cyc jitter (pll mode) ? low phase jitter (intel qpi, pcie gen 1/2/3/4 common clock compliant) ? gen 3 srns compliant ? 100 ps input-to-output delay ? extended temperature: ?40 to 85 c ? package: 64-pin qfn ? for higher output devices or variations of this device, contact silicon labs ? server ? storage ? datacenter ? enterprise switches and routers patents pending ordering information: see page 30.
SI53112 2 rev. 1.1 functional block diagram fb_out dif_[11:0] ssc compatible pll control logic scl sda pwrgd / pwrdn sa_1 sa_0 hbw_bypass_lbw 100m_133 clk_in clk_in oe_[11:0] 12
SI53112 rev. 1.1 3 t able of c ontents section page 1. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1. clk_in, clk_in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2. oe and output enables (control registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3. 100m_133m?frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4. sa_0, sa_1?address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5. pwrgd/pwrdn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6. hbw_bypass_lbw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.7. miscellaneous requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.8. buffer power-up state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. test and measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1. input edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2. termination of differential outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1. byte read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2. block read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. power filtering example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1. ferrite bead power filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. pin descriptions: 64-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9. land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SI53112 4 rev. 1.1 1. electrical specifications table 1. dc operating characteristics v dd_a =3.3v5%, v dd =3.3v5% parameter symbol test condition min max unit 3.3 v core supply voltage vdd/vdd_a 3.3 v 5% 3.135 3.465 v 3.3 v i/o supply voltage 1 vdd_io 1.05 v to 3.3 v 5% 0.9975 3.465 v 3.3 v input high voltage v ih vdd 2.0 vdd+0.3 v 3.3 v input low voltage v il vss-0.3 0.8 v input leakage current 2 i il 0 < vin < vdd ?5 +5 a 3.3 v input high voltage 3 v ih_fs vdd 0.7 vdd+0.3 v 3.3 v input low voltage 3 v il_fs vss?0.3 0.35 v 3.3 v input low voltage v il_tri 0 0.8 v 3.3 v input med voltage v im_tri 1.2 1.8 v 3.3 v input high voltage v ih_tri 2.2 vdd v 3.3 v output high voltage 4 v oh i oh =?1ma 2.4 ? v 3.3 v output low voltage 4 v ol i ol =1ma ? 0.4 v input capacitance 5 c in 2.5 4.5 pf output capacitance 5 c out 2.5 4.5 pf pin inductance l pin ?7nh ambient temperature t a no airflow ?40 85 c notes: 1. vdd_io applies to the low-power nmos push-pull hcsl compatible outputs. 2. input leakage current does not include inputs with pull-up or pull-down resistors. inputs with resistors should state current requirements. 3. internal voltage reference is to be used to guarantee v ih _fs and v il _fs thresholds levels over full operating range. 4. signal edge is required to be monotonic when transitioning through this region. 5. ccomp capacitance based on pad metallization and silicon device capacitance. not including pin capacitance. table 2. current consumption t a = ?40 to 85 c; supply voltage v dd =3.3v 5% parameter symbol test c ondition min typ max unit operating current idd vdd 133 mhz, vdd rail ? 18 25 ma idd vdda 133 mhz, vdda + vddr, pll mode ? 17 20 ma idd vddio 133 mhz, cl = full load, vdd io rail ? 85 110 ma power down current idd vddpd power down, vdd rail ? 0.4 1 ma idd vddapd power down, vdda rail ? 2 5 ma idd vddiopd power down, vdd_io rail ? 0.2 0.5 ma
SI53112 rev. 1.1 5 table 3. output skew, pll bandwidth and peaking t a = ?40 to 85 c; supply voltage v dd =3.3v 5% parameter test condition min typ max unit clk_in, dif[x:0] input-to -output delay in pll mode nominal value 1,2,3,4 ?100 27 100 ps clk_in, dif[x:0] input-to-output delay in bypass mode \nominal value 2,4,5 2.5 3.3 4.5 ns clk_in, dif[x:0] input-to-output delay variation in pll mode over voltage and temperature 2,4,5 ?100 39 100 ps clk_in, dif[x:0] input-to-output delay variation in bypass mode over voltage and temperature 2,4,5 ?250 3.7 250 ps dif[11:0] output-to-output sk ew across all 12 outputs (common to bypass and pll mode) 1,2,3,4,5 0 20 50 ps pll jitter peakin g (hbw_bypass_lbw =0) 6 ? 0.4 2.0 db pll jitter peakin g (hbw_bypass_lbw =1) 6 ?0.12.5db pll bandwidth (hbw_bypass_lbw =0) 7 ? 0.7 1.4 mhz pll bandwidth (hbw_bypass_lbw =1) 7 ? 2 4 mhz notes: 1. measured into fixed 2 pf load cap. input-to-output ske w is measured at the first output edge following the corresponding input. 2. measured from differential cross-point to differential cross-point. 3. this parameter is deterministic for a given device. 4. measured with scope averaging on to find mean value. 5. all bypass mode input-to-output specs re fer to the timing between an input edg e and the specific output edge created by it. 6. measured as maximum pass band gain. at frequencies within th e loop bw, highest point of magnification is called pll jitter peaking. 7. measured at 3 db down or half power point.
SI53112 6 rev. 1.1 table 4. phase jitter parameter test condition min typ max unit phase jitter pll mode pcie gen 1, common clock 1,2,3 ?2986ps pcie gen2 low band, common clock f < 1.5 mhz 1,3,4,5 ? 2.0 3.0 ps (rms) pcie gen2 high band, common clock 1.5 mhz < f < nyquist 1,3,4,5 ? 1.9 3.1 ps (rms) pcie gen 3, common clock (pll bw 2?4 mhz, cdr = 10 mhz) 1,3,4,5 ?0.451.0 ps (rms) pcie gen 3 separate refe rence no spread, srns (pll bw of 2?4 or 2?5 mhz, cdr = 10 mhz) 1,3,4,5 ? 0.32 0.71 ps (rms) pcie gen 4, common clock (pll bw of 2?4 or 2?5 mhz, cdr = 10 mhz) 1,4,5,8 ?0.451.0 ps (rms) intel ? qpi & intel smi (4.8 gbps or 6.4 gb/s, 100 or 133 mhz, 12 ui) 1,6,7 ?0.210.5 ps (rms) intel qpi & intel smi (8 gb/s, 100 mhz, 12 ui) 1,6 ?0.130.3 ps (rms) intel qpi & intel smi (9.6 gb/s, 100 mhz, 12 ui) 1,6 ?0.110.2 ps (rms) notes: 1. post processed evaluation through intel supplied matlab* scri pts. defined for a ber of 1e-12. measured values at a smaller sample size have to be extrapolated to this ber target. 2. = 0.54 implies a jitter peaking of 3 db. 3. pcie* gen3 filter characteristics are subject to final ra tification by pcisig. check the pci-sig for the latest specification. 4. measured on 100 mhz pcie output using the template file in the intel-supplied clock jitter tool v1.6.3. 5. measured on 100 mhz output using the template file in the intel-supplied clock jitter tool v1.6.3. 6. measured on 100 mhz, 133 mhz output using the template file in the inte l-supplied clock jitter tool v1.6.3. 7. these jitter numbers are defined for a ber of 1e-12. me asured numbers at a smaller sample size have to be extrapolated to this ber target. 8. gen 4 specifications based on the pci-ex press base specification 4.0 rev. 0.5. 9. download the silicon labs pcie clock jitter tool at www.silabs.com/pcie-learningcenter .
SI53112 rev. 1.1 7 additive phase jitter bypass mode pcie gen 1 1,2,3 ?10?ps pcie gen2 low band f < 1.5 mhz 1,3,4,5 ?1.2? ps (rms) pcie gen2 high band 1.5 mhz < f < nyquist 1,3,4,5 ?1.3? ps (rms) pcie gen3 (pll bw 2?4 mhz, cdr = 10 mhz) 1,3,4,5 ?0.25? ps (rms) pcie gen 4, common clock (pll bw of 2?4 or 2?5 mhz, cdr = 10 mhz) 1,4,5,8 ?0.25? ps (rms) intel qpi & intel? smi (4.8 gbps or 6.4 gb/s, 100 or 133 mhz, 12 ui) 1,6,7 ?0.12? ps (rms) intel qpi & intel? smi (8 gb/s, 100 mhz, 12 ui) 1,6 ?0.1? ps (rms) intel qpi & intel? smi (9.6 gb/s, 100 mhz, 12 ui) 1,6 ?0.09? ps (rms) table 4. phase jitter (continued) notes: 1. post processed evaluation through intel supplied matlab* scri pts. defined for a ber of 1e-12. measured values at a smaller sample size have to be extrapolated to this ber target. 2. = 0.54 implies a jitter peaking of 3 db. 3. pcie* gen3 filter characteristics are subject to final ra tification by pcisig. check the pci-sig for the latest specification. 4. measured on 100 mhz pcie output using the template file in the intel-supplied clock jitter tool v1.6.3. 5. measured on 100 mhz output using the template file in the intel-supplied clock jitter tool v1.6.3. 6. measured on 100 mhz, 133 mhz output using the template file in the inte l-supplied clock jitter tool v1.6.3. 7. these jitter numbers are defined for a ber of 1e-12. me asured numbers at a smaller sample size have to be extrapolated to this ber target. 8. gen 4 specifications based on the pci-ex press base specification 4.0 rev. 0.5. 9. download the silicon labs pcie clock jitter tool at www.silabs.com/pcie-learningcenter .
SI53112 8 rev. 1.1 table 5. dif 0.7 v ac timing characteristics (non-spread spectrum mode) 1 parameter symbol clk 100 m hz, 133 mhz unit notes min typ max clock stabilization time t stab ? 1.5 1.8 ms 2 long term accuracy l acc ?100 ppm 3 , 4 , 5 absolute host clk period (100mhz) t abs 9.94900 10.05100 ns 3 , 4 , 6 absolute host clk period (133mhz) t abs 7.44925 7.55075 ns 3 , 4 , 6 edge rate edge_rate 1.0 4.0 v/ns 3 , 4 , 7 rise time variation ? trise ? 125 ps 3 , 8 , 9 fall time variation ? tfall ? 125 ps 3 , 8 , 9 rise/fall matching t rise_mat / t fall_mat ?20% 3 , 8 , 10 , 11 voltage high (typ 0.7 v) v high 660 850 mv 3 , 8 , 12 voltage low (typ 0.7 v) v low ?150 150 mv 3 , 8 , 13 maximum voltage v max ? 1150 mv 8 absolute crossing point voltages vox abs 250 550 mv 3 , 8 , 14 , 15 , 16 relative crossing point voltages vox rel 3 , 8 , 16 , 17 total variation of vcross over all edges to ta l ? vox ?140 mv 3 , 8 , 18 duty cycle dc 45 55 % 3 , 4 maximum voltage (overshoot) v ovs ?v high + 0.3 v 3 , 8 , 19 maximum voltage (undershoot) v uds ?v low ? 0.3 v 3 , 8 , 20
SI53112 rev. 1.1 9 ringback voltage v rb 0.2 n/a v 3 , 8 notes: 1. unless otherwise noted, all specif ications in this table apply to all processor frequencies. 2. this is the time from the valid clk_in input clocks and the assertion of the pwrgd signal level at 1.8?2.0 v to the time that stable clocks are output fr om the buffer chip (pll locked). 3. test configuration is rs = 33.2 ? , rp = 49.9, 2 pf for 100 ? transmission line; rs = 27 ? , rp = 42.2, 2 pf for 85 ? transmission line. 4. measurement taken from differential waveform. 5. using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 99,750,00 hz, 133,000,000 hz. 6. the average period over any 1 s period of time must be greater than the minimum and less than the maximum specified period. 7. measure taken from differential waveform on a component test board. the edge (slew) rate is measured from ?150 mv to +150 mv on the differential waveform . scope is set to average because the scope sample clock is making most of the dynamic wiggles along the clock edge only valid for rising clock and falling clock . signal must be monotonic through the vol to voh region for trise and tfall. 8. measurement taken from single-ended waveform. 9. measured with oscilloscope, averaging off, using min max statistics. variation is the delta between min and max. 10. measured with oscilloscope, averaging on, the difference between the rising edge rate (average) of clock verses the falling edge rate (average) of clock . 11. rise/fall matching is derived using the follo wing, 2*(trise - tfall) / (trise + tfall). 12. vhigh is defined as the statistical average high value as obtained by using the oscilloscope vhigh math function. 13. vlow is defined as the statistical average low value as obtained by using the oscilloscope vlow math function. 14. measured at crossing point where the instantaneous voltag e value of the rising edge of clk equals the falling edge of clk . 15. this measurement refers to the total va riation from the lowest crossing point to the highest, regardless of which edge is crossing. 16. the crossing point must meet the absolute and rela tive crossing point specifications simultaneously. 17. vcross(rel) min and max are derived using the following, vcross(rel) min = 0.250 + 0.5 (vhavg ? 0.700), vcross(rel) max = 0.550 ? 0.5 (0.700 ? vhavg), (see fi gures 3-4 for further clarification). 18. ? vcross is defined as the total variation of all crossing voltages of rising clock and falling clock . this is the maximum allowed variance in vc ross for any particular system. 19. overshoot is defined as the absolute value of the maximum voltage. 20. undershoot is defined as the absolute value of the minimum voltage. table 5. dif 0.7 v ac timing characteristics (non-spread spectrum mode) 1 (continued) parameter symbol clk 100 m hz, 133 mhz unit notes min typ max
SI53112 10 rev. 1.1 table 6. clock periods differential clock outputs with ssc disabled ssc on center freq, mhz measurement window units 1 clock 1s 0.1s 0.1s 0.1s 1s 1 clock -c-c jitter absper min -ssc short term avg min -ppm long term avg min 0ppm period nominal +ppm long term avg max +ssc short term avg max +c-c jitter absper max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns table 7. clock periods differential clock outputs with ssc enabled ssc on center freq, mhz measurement window units 1 clock 1s 0.1s 0.1s 0.1s 1s 1 clock -c-c jitter absper min -ssc short term avg min -ppm long term avg min 0ppm period nominal +ppm long term avg max +ssc short term avg max +c-c jitter absper max 99.75 9.94900 9.99900 10.02406 10.02506 10.02607 10.05126 10.10126 ns 133.33 7.44925 7.49925 7.51805 7.51880 7.51955 7.53845 7.58845 ns table 8. absolute maximum ratings parameter symbol min max unit 3.3 v core supply voltage 1 vdd/vdd_a ? 4.6 v 3.3 v i/o supply voltage 1 vdd_io ? 4.6 v 3.3 v input high voltage 1,2 vih ? 4.6 v 3.3 v input low voltage 1 vil ? 0.5 ? v storage temperature 1 t s ?65 150 c input esd protection 3 esd 2000 ? v notes: 1. consult manufacturer regarding extended operation in excess of normal dc operating parameters. 2. maximum vih is not to exceed maximum v dd . 3. human body model.
SI53112 rev. 1.1 11 2. functional description 2.1. clk_in, clk_in the differential input clock is expected to be sourced from a clock synthesizer, e.g. ck420bq, ck509b, or ck410b+. 2.2. oe and output enables (control registers) each output can be individually enabled or disabled by smbu s control register bits. additionally, each output of the dif[11:0] has a dedicated oe pin. the oe pins are asynchronous, asserted-low signals. the output enable bits in the smbus registers are active high and are set to enable by default. the disabled state for the db1200zl nmos push-pull output is low/low. please note that the logic le vel for assertion or deassertion is different in software than it is on hardware. th is follows hardware default nomenclature for communication channels (e.g., output is enabled if the oe# pin is pulled low) and still maintains software programming logic (e.g., output is enabled if oe register is true). table 9 is a truth table depicting enabling and disabling of outputs via hardware and software. note that, for the output to be active, the control register bit must be a 1 and the oe pin must be a 0. note: the assertion and deassertion of this signal is absolutely asynchronous. 2.2.1. oe assertion (transition from 1 to 0) all differential outputs that were disabled are to resume normal operation in a glitch-free manner. the latency from the assertion to active outputs is 4 to 12 dif clock periods. 2.2.2. oe de-assertion (transition from 0 to 1) the impact of deasserting oe is that each corresponding output will transition from norm al operation to disabled in a glitch-free manner. a mi nimum of four valid clocks will be provided after the deassertion of oe . the maximum latency from the deassertion to disa bled outputs is 12 dif clock periods. 2.3. 100m_133m ?frequency selection the SI53112 is optimized for lowest phase jitter perf ormance at operating frequencies of 100 and 133 mhz. 100m_133m is a hardware input pin, which programs the appro priate output frequency of the differential outputs. note that the clk_in frequency must be equal to th e clk_out frequency; meaning SI53112 is operated in 1:1 mode only. frequency selection can be enabled by the 100m_133m hardware pin. an external pull-up or pull-down resistor is attached to this pin to select the input/output frequency. the functionality is summarized in table 10. note: all differential outputs transition from 100 to 133 mhz or from 133 to 100 mhz in a glitch free manner. table 9. SI53112 output management inputs oe hardware pins and control register bits outputs pll state pwrgd/ pwrdn clk_in/ clk_in smbus enable bit oe pin dif/dif [11:0] fb_out/ fb_out 0 x x x low/low low/low off 1 running 0 x low/low running on 1 0 running running on 1 1 low/low running on table 10. frequency program table 100m_133m optimized frequency (clk_in = clk_out) 0133.33mhz 1100.00mhz
SI53112 12 rev. 1.1 2.4. sa_0, sa_1? address selection sa_0 and sa_1 are tri-level hardware pins, which program the appropriate address for the SI53112. the two tri- level input pins that can configure the device to nine different addresses. 2.5. pwrgd/pwrdn pwrgd is asserted high and deasserted low. deassertion of pwrgd (pulling the signal low) is equivalent to indicating a power-down condition. pwrgd (assertion) is used by the SI53112 to sample initial configurations, such as frequency select condition and sa selections. after pwrgd has been asserted high for the first time, the pin becomes a pwrdn (power down) pin that can be used to shut off all clocks cleanly and instruct the device to invoke power-saving mode. pwrdn is a completely asynchronous active low input. when entering power-saving mode, pwrdn should be asserted low prior to shutting off the input clock or power to ensure all clocks shut down in a glitch free manner. when pwrdn is asserted low, all cl ocks will be disabled prior to turning off the vco. when pwrdn is deasserted high, all clocks will start and stop without any abnormal beha vior and will meet all ac and dc parameters. note: the assertion and deassertion of pwrdn is absolutely asynchronous. warning: disabling of the clk_in input clock prior to assertion of pwrdn is an undefined mode and not recommended. operation in this mode may result in gl itches, excessive frequency shifting, etc. table 11. smbus address table sa_1 sa_0 smbus address lld8 lmda lhde mlc2 mmc4 mhc6 hlca hmcc hhce table 12. pwrgd/pwrdn functionality pwrgd/ pwrdn dif dif 0 low low 1normal normal
SI53112 rev. 1.1 13 2.5.1. pwrdn assertion when pwrdn is sampled low by two consecutive rising edges of dif , all differential outputs must be held low/ low on the next dif high-to-low transition. figure 1. pwrdn assertion 2.5.2. pwrgd assertion the power-up latency is to be less than 1.8 ms. this is t he time from a valid clk_in input clock and the assertion of the pwrgd signal to the time that stable clocks are outp ut from the device (pll locked). all differential outputs stopped in a low/low condition result ing from power down must be driven high in less than 300 s of pwrdn deassertion to a voltage greater than 200 mv. figure 2. pwrdg assertion (pwrdown?deassertion) pwrdwn dif dif tstable <1.8 ms tdrive_pwrdn# <300 s; > 200 mv dif dif pwrdwn
SI53112 14 rev. 1.1 2.6. hbw_bypass_lbw the hbw_bypass_lbw pin is a tri-level function input pin (refer to table 13 for vil_tri, vim_tri, and vih_tri signal levels). it is used to select between pll high-bandwidth, pll bypass mode, or pll low-bandwidth mode. in pll bypass mode, the input clock is passed directly to the output stage, which may result in up to 50 ps of additive cycle-to-cycle jitter (50 ps + input jitter) on the differenti al outputs. in the case of pll mode, the input clock is passed through a pll to reduce high-frequency jitter. the pll hbw, bypass, and pll lbw modes may be selected by assert ing the hbw_bypass_lbw input pin to the appropriate level described in table 13. the SI53112 has the abilit y to override the latch value of the pll op erating mode from hardwar e strap pin 5 via the use of byte 0 and bits 2 and 1. byte 0 bit 3 must be set to 1 to allow the user to change bits 2 and 1, affecting the pll. bits 7 and 6 will always read ba ck the original latched value. a warm reset of the system will have to be accomplished if the user changes these bits. 2.7. miscellaneous requirements data transfer rate: 100 kbps (standard mode) is the base func tionality required. fast mode (400 kbps) functionality is optional. logic levels: smbus logic levels are based on a percentage of v dd for the controller and other devices on the bus. assume all devices are based on a 3.3 v supply. clock stretching: the clock buffer must not hold/stretch the scl or sda lines low for more than 10 ms. clock stretching is discouraged and should on ly be used as a last resort. stretc hing the clock/data lines for longer than this time puts the device in an error/time-out mode and may not be supported in all platforms. it is assumed that all data transfers can be completed as specifie d without the use of cl ock/data stretching. general call: it is assumed that the clock buffer will no t have to respond to the ?general call.? electrical characteristics: all electrical characteristics must meet the standard mode specifications found in section 3 of the smbus 2.0 specification. pull-up resistors: any internal resistor pull-ups on the sdata and sclk inputs must be stated in the individual data sheet. the use of internal pull-ups on these pins of below 100 k is discouraged. assume that the board designer will use a single external pu ll-up resistor for each line and th at these values are in the 5?6 k ? range. assume one smbus device per dimm (serial presence detect), one smbus controller, one clock buffer, one clock driver plus one/two more smbus devices on th e platform for capacitive loading purposes. input glitch filters: only fast mode smbus devices require input g litch filters to suppress bus noise. the clock buffer is specified as a standard mode device and is not re quired to support this featur e. however, it is considered a good design practice to include the filters. pwrdn : if a clock buffer is placed in pwrdn mode, the sdata and sclk inputs must be tri-stated and the device must retain all programming in formation. idd current due to the smbu s circuitry must be characterized and in the data sheet. table 13. pll bandwidth and readback table hbw_bypass_lbw pin mode byte 0, bit 7 byte 0, bit 6 llbw00 m bypass 0 1 hhbw11
SI53112 rev. 1.1 15 2.8. buffer powe r-up state machine figure 3. buffer power-up state diagram table 14. buffer power-up state machine state description 0 3.3 v buffer power is off. 1 after 3.3 v supply is detected to rise above 1.8?2.0 v, the buffer enters state 1 and initiates a 0.1?0.3 ms delay. 2 buffer waits for a valid cloc k on the clk input and pwrdn de-assertion. 3 once the pll is locked to the clk_in input clock, the buffer enters state 3 and enables outputs for normal operation. notes: 1. the total power-up latency from power-on to all outputs active must be less than 1.8 ms (assuming a valid clock is present on clk_in input). 2. if power is valid and power-down is deasserted but no input clocks are present on the clk_in input, dif clocks must remain disabled. only after valid input clocks are detec ted, valid power, pwrdn deasserted with the pll locked/stable are the dif outputs enabled. power off s0 normal operation s3 powerdown asserted delay 0.1 ms ? 0.3 ms s1 wait for input clock and powerdown deassertion s2 no input clock
SI53112 16 rev. 1.1 3. test and measurement setup 3.1. input edge input edge rate is based on single-ended measurement. this is the minimum input edg e rate at which the SI53112 is guaranteed to meet all performance specifications. 3.1.1. measurement points for differential figure 4. measurement points for rise time and fall time figure 5. single-ended measurement points for v ovs , v uds , v rb table 15. input edge rate frequency min max unit 100 mhz 0.35 n/a v/ns 133 mhz 0.35 n/a v/ns +150 mv -150 mv slew_rise +150 mv -150 mv slew_fall 0.0 v v_swing 0.0 v diff vovs vhigh vrb vlow vrb vuds
SI53112 rev. 1.1 17 figure 6. differential (clock?clock ) measurement points (t period , duty cycle, jitter) 3.2. termination of differential outputs all differential outputs are to be tested into a 100 ? or 85 ? differential impedance transmission line. source terminated clocks have some inherent limitations as to the maximum trace length and frequencies that can be supported. for cpu outputs, a maximum trace length of 10? and a maximum of 200 mhz are assumed. for src clocks, a maximum trace length of 16? and maximum freq uency of 100 mhz is assumed. for frequencies beyond 200 mhz, trace lengths must be restrict ed to avoid signal integrity problems. 3.2.1. termination of differential nmos push-pull type outputs figure 7. 0.7 v configuration test load board termination for nmos push-pull table 16. clock board trace impedance rs rp unit diff clocks?50 ? configuration 100 33+ 5% n/a ? diff clocks?43 ? configuration 85 27+ 5% n/a ? tperiod low duty cycle % high duty cycle % skew measurement point 0.000 v t-line 10" typical t-line 10" typical receiver 2 pf 2 pf source terminated rs rs clock clock # db1200zl
SI53112 18 rev. 1.1 4. control registers 4.1. byte read/write reading or writing a register in an smbus slave device in byte mode always involv es specifying the register number. 4.1.1. byte read the standard byte read is as shown in figure 8. it is an extension of the byte write. the write start condition is repeated; then, the slave device starts sending data, and th e master acknowledges it until the last byte is sent. the master terminates the transfer with a nak, then a stop condition. for byte operation, the 2 x 7th bit of the command byte must be set. for block operations, the 2 x 7th bit must be reset. if the bit is not set, the next byte must be the byte transfer count. figure 8. byte read protocol 4.1.2. byte write figure 9 illustrates a simple, typical byte write. for byte operati on, the 2 x 7th bit of the command byte must be set. for block operations, the 2 x 7th bit must be reset. if the bit is not set, the next byte must be the by te transfer count. the count can be between 1 and 32. it is not allowed to be zero or to exceed 32. figure 9. byte write protocol slave t wr a command slave a rd data byte 0 n p a r command start condition byte read protocol acknowledge repeat start not ack stop condition register # to read 2 x 7 bit = 1 1711 8 117 1 1811 master to slave to slave t wr a command data byte 0 a command start condition byte write protocol acknowledge register # to write 2 x 7 bit = 1 1711 8 1 8 1 1 master to slave to a p stop condition
SI53112 rev. 1.1 19 4.2. block read/write 4.2.1. block read after the slave address is sent with the r/w condition bit set, the command byte is sent with the msb = 0. the slave acknowledges the register index in the command by te. the master sends a repeat start function. after the slave acknowledges this, the slave s ends the number of bytes it wants to transfer (>0 and <33). the master acknowledges each byte except the last and sends a stop function. figure 10. block read protocol 4.2.2. block write after the slave address is sent with the r/w condition bi t not set, the command byte is sent with the msb = 0. the lower seven bits indicate the register at which to start the transfer. if the command byte is 00h, the slave device will be compatible with existing block mode slave devices. the next byte of a write must be the count of bytes that the master will transfer to the slave device. the byte count must be greater than zero and less than 33. following this byte are the data bytes to be transferred to the slave device. the slave device alwa ys acknowledges each byte received. the transfer is terminated after the slav e sends the ack and the mast er sends a stop function. figure 11. block write protocol slave t wr a command code command start condition block read protocol acknowledge repeat start register # to read 2 x 7 bit = 1 1711 8 master to slave to slave a rd a r 11 7 1 1 data byte a data byte 0 a data byte 1 n p 8181811 not acknowledge stop condition slave address t wr a command command bit start condition block write protocol acknowledge register # to write 2 x 7 bit = 0 1711 8 master to slave to a 1 data byte 0 a data byte 1 a p 181811 stop condition byte count = 2 a 8
SI53112 20 rev. 1.1 4.3. control registers note: byte 0, bit_[3:1] are bw pll sw enable for the db1200zl. sett ing bit 3 to 1 allows the user to override the latch value from pin 5 via use of bits 2 and 1. use the values from t he pll operating mode readback table. note that bits 7 and 6 will keep the value originally latched on pin 5. a warm reset of the system will have to be accomplished if the user changes these bits. table 17. byte 0: frequency select, output enable, pll mode control register bit description if bit = 0 if bit = 1 type default output(s) affected 0 100m_133m# frequency select 133 mhz 100 mhz r latched at power up dif[11:0] 1 pll mode 0 see pll operating mode readback table rw 1 2 pll mode 1 rw 1 3 pll software enable hw latch smbus control rw 0 4 reserved 0 5 reserved 0 6 pll mode 0 see pll operating mode readback table r latched at power up 7 pll mode 1 see pll operating mode readback table r latched at power up
SI53112 rev. 1.1 21 table 18. byte 1: output enable control register bit description if bit = 0 if bit = 1 type default output(s) affected 0 output enable dif 0 low/low for SI53112 enabled rw 1 dif[0] 1 output enable dif 1 low/low for SI53112 enabled rw 1 dif[1] 2 output enable dif 2 low/low for SI53112 enabled rw 1 dif[2] 3 output enable dif 3 low/low for SI53112 enabled rw 1 dif[3] 4 output enable dif 4 low/low for SI53112 enabled rw 1 dif[4] 5 output enable dif 5 low/low for SI53112 enabled rw 1 dif[5] 6 output enable dif 6 low/low for SI53112 enabled rw 1 dif[6] 7 output enable dif 7 low/low for SI53112 enabled rw 1 dif[7]
SI53112 22 rev. 1.1 table 19. byte 2: output enable control register bit description if bit = 0 if bit = 1 type default output(s) affected 0 output enable dif 8 low/low for SI53112 enabled rw 1 dif[8] 1 output enable dif 9 low/low for SI53112 enabled rw 1 dif[9] 2 output enable dif 10 low/low for SI53112 enabled rw 1 dif[10] 3 output enable dif 11 low/low for SI53112 enabled rw 1 dif[11] 4 reserved 0 5 reserved 0 6 reserved 0 7 reserved 0 table 20. byte 3: reserved control register bit description if bit = 0 if bit = 1 type default output(s) affected 0 reserved 0 1 reserved 0 2 reserved 0 3 reserved 0 4 reserved 0 5 reserved 0 6 reserved 0 7 reserved 0
SI53112 rev. 1.1 23 table 21. byte 4: reserved control register bit description if bit = 0 if bit = 1 type default output(s) affected 0 reserved 0 1 reserved 0 2 reserved 0 3 reserved 0 4 reserved 0 5 reserved 0 6 reserved 0 7 reserved 0 table 22. byte 5: vendor/revision identification control register bit description if bit = 0 if bit = 1 type default default 0 vendor id bit 0 r vendor specific 0 1 vendor id bit 1 r vendor specific 0 2 vendor id bit 2 r vendor specific 0 3 vendor id bit 3 r vendor specific 1 4 revision code bit 0 r vendor specific 0 5 revision code bit 1 r vendor specific 0 6 revision code bit 2 r vendor specific 0 7 revision code bit 3 r vendor specific 0 table 23. byte 6: device id control register bit description if bit = 0 if bit = 1 type default default 0 device id 0 r 0 1 device id 1 r 0 2 device id 2 r 0 3 device id 3 r 0 4 device id 4 r 0 5 device id 5 r 0 6 device id 6 r 0 7 device id 7 (msb) r 0
SI53112 24 rev. 1.1 table 24. byte 7: byte count register bit description if bit = 0 if bi t = 1 type default output(s) affected 0 bc0 - writing to this register con- figures how many bytes will be read back rw 0 1 bc1 -writing to this register con- figures how many bytes will be read back rw 0 2 bc2 -writing to this register con- figures how many bytes will be read back rw 0 3 bc3 -writing to this register con- figures how many bytes will be read back rw 1 4 bc4 -writing to this register con- figures how many bytes will be read back rw 0 5 reserved 0 6 reserved 0 7 reserved 0
SI53112 rev. 1.1 25 5. power filtering example 5.1. ferrite bead power filtering recommended ferrite bead filtering equivalent to the following: 600 ? impedance at 100 mhz, < 0.1 ? dcr max., > 400 ma current rating. figure 12. schematic example of SI53112 power filtering
SI53112 26 rev. 1.1 6. pin descriptions: 64-pin qfn SI53112 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 vdda gnda nc 100m_133m hbw_bypass_lbw pwrgd / pwrdn gnd vddr clk_in clk_in sa_0 sda scl sa_1 nc nc gnd dif_7 dif_7 oe_7 1 oe_6 1 dif_6 dif_6 gnd vdd dif_5 dif_5 oe_5 1 oe_4 1 dif_4 dif_4 gnd 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dif_11 dif_11 oe_11 1 oe_10 1 dif_10 dif_10 gnd vdd vdd_io dif_9 dif_9 oe_9 1 oe_8 1 dif_8 dif_8 vdd_io 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 17 dif_0 dif_0 oe_0 1 oe_1 1 dif_1 dif_1 gnd vdd vdd_io dif_2 dif_2 dif_3 dif_3 vdd_io notes: 1) internal 100k pull-down oe_2 1 oe_3 1
SI53112 rev. 1.1 27 table 25. SI53112 64-pin qfn descriptions pin # name type description 1vdda 3.3 v 3.3 v power supply for pll. 2 gnda gnd ground for pll. 3nc i/o no connect. 4 100m_133m i,se 3.3 v tolerant inputs for input/output frequency selection. an external pull- up or pull-down resistor is attached to this pin to select the input/output frequency. high = 100 mhz output low = 133 mhz output 5 hbw_bypass_lbw i, se tri-level input for selecting the pll bandwidth or bypass mode. high = high bw mode med = bypass mode low = low bw mode 6 pwrgd/pwrdn i 3.3 v lvttl input to power up or power down the device. 7gnd gnd ground for outputs. 8 vddr vdd 3.3 v power supply for differential input receiver. this vddr should be treated as an analog power rail and filtered appropriately. 9 clk_in i, dif 0.7 v differential input. 10 clk_in i, dif 0.7 v differential input. 11 sa_0 i 3.3 v lvttl input selecting th e address. tri-level input. 12 sda i/o open collector smbus data. 13 scl i/o smbus slave clock input. 14 sa_1 i 3.3 v lvttl input selecting th e address. tri-level input. 15 nc i/o no connect. there are active sign als on pin 15 and 16, do not connect anything to these pins. 16 nc i/o no connect. there are active sign als on pin 15 and 16, do not connect anything to these pins. 17 dif_0 o, dif 0.7 v differential clock outputs. default is 1:1. 18 dif _0 o, dif 0.7 v differential clock outputs. default is 1:1. 19 oe _0 i, se 3.3 v lvttl active low input for enabling differential outputs (default). controls the corresponding output pair. internal pull-down. 20 oe _1 i, se 3.3 v lvttl active low input for enabling differential outputs (default). controls the corresponding output pair. internal pull-down. 21 dif_1 o, dif 0.7 v differential clock outputs. default is 1:1. 22 dif _1 o, dif 0.7 v differential clock outputs. default is 1:1. 23 gnd gnd ground for outputs.
SI53112 28 rev. 1.1 24 vdd 3.3 v 3.3 v power supply for outputs. 25 vdd_io vdd power supply for differential outputs. 26 dif_2 o, dif 0.7 v differential clock outputs. default is 1:1. 27 dif _2 o, dif 0.7 v differential clock outputs. default is 1:1. 28 oe _2 i, se 3.3 v lvttl active low input for enabling differential outputs (default). controls the corresponding output pair. internal pull-down. 29 oe _3 i, se 3.3 v lvttl active low input for enabling differential outputs (default). controls the corresponding output pair. internal pull-down. 30 dif_3 o, dif 0.7 v differential clock outputs. default is 1:1. 31 dif _3 o, dif 0.7 v differential clock outputs. default is 1:1. 32 vdd_io vdd power supply for differential outputs. 33 gnd gnd ground for outputs. 34 dif_4 o, dif 0.7 v differential clock outputs. default is 1:1. 35 dif _4 o, dif 0.7 v differential clock outputs. default is 1:1. 36 oe _4 i, se 3.3 v lvttl active low input for enabling differential outputs (default). controls the corresponding output pair. internal pull-down. 37 oe _5 i, se 3.3 v lvttl active low input for enabling differential outputs (default). controls the corresponding output pair. internal pull-down. 38 dif_5 o, dif 0.7 v differential clock outputs. default is 1:1. 39 dif _5 o, dif 0.7 v differential clock outputs. default is 1:1. 40 vdd 3.3 v 3.3 v power supply for outputs. 41 gnd gnd ground for outputs. 42 dif_6 o, dif 0.7 v differential clock outputs. default is 1:1. 43 dif _6 o, dif 0.7 v differential clock outputs. default is 1:1. 44 oe _6 i, se 3.3 v lvttl active low input for enabling differential outputs (default). controls the corresponding output pair. internal pull-down. 45 oe _7 i, se 3.3 v lvttl active low input for enabling differential outputs (default). controls the corresponding output pair. internal pull-down. 46 dif_7 o, dif 0.7 v differential clock outputs. default is 1:1. 47 dif _7 o, dif 0.7 v differential clock outputs. default is 1:1. 48 gnd gnd ground for outputs. 49 vdd_io vdd power supply for differential outputs. 50 dif_8 o, dif 0.7 v differential clock outputs. default is 1:1. table 25. SI53112 64-pin qfn descriptions pin # name type description
SI53112 rev. 1.1 29 51 dif _8 o, dif 0.7 v differential clock outputs. default is 1:1. 52 oe _8 i, se 3.3 v lvttl active low input for enabling differential outputs (default). controls the corresponding output pair. internal pull-down. 53 oe _9 i, se 3.3 v lvttl active low input for enabling differential outputs (default). controls the corresponding output pair. internal pull-down. 54 dif_9 o, dif 0.7 v differential clock outputs. default is 1:1. 55 dif _9 o, dif 0.7 v differential clock outputs. default is 1:1. 56 vdd_io vdd power supply for differential outputs. 57 vdd 3.3 v 3.3 v power supply for outputs. 58 gnd gnd ground for outputs. 59 dif_10 o, dif 0.7 v differential clock outputs. default is 1:1. 60 dif _10 o, dif 0.7 v differential clock outputs. default is 1:1. 61 oe _10 i, se 3.3 v lvttl active low input for enabling differential outputs (default). controls the corresponding output pair. internal pull-down. 62 oe _11 i, se 3.3 v lvttl active low input for enabling differential outputs (default). controls the corresponding output pair. internal pull-down. 63 dif_11 o, dif 0.7 v differential clock outputs. default is 1:1. 64 dif _11 o, dif 0.7 v differential clock outputs. default is 1:1. table 25. SI53112 64-pin qfn descriptions pin # name type description
SI53112 30 rev. 1.1 7. ordering guide part number package type temperature lead-free SI53112-a00agm 64-pin qfn extended, ?40 to 85 ? c SI53112-a00agmr 64-pin qfn?tape and reel extended, ?40 to 85 ? c
SI53112 rev. 1.1 31 8. package outline figure 13 illustrates the package details for the SI53112. table 26 lists the valu es for the dimensions shown in the illustration. figure 13. 64-pin quad flat no lead (qfn) package table 26. package diagram dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 9.00 bsc. d2 6.00 6.10 6.20 e 0.50 bsc. e 9.00 bsc. e2 6.00 6.10 6.20 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline mo-220 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. ?
SI53112 32 rev. 1.1 9. land pattern figure 14 illustrates the recommended land pattern details for the SI53112 in a 64-pin qfn package. table 27 lists the values for the dimensions shown in the illustration. figure 14. land pattern
SI53112 rev. 1.1 33 table 27. pcb land pattern dimensions dimension mm c1 8.90 c2 8.90 e0.50 x1 0.30 y1 0.85 x2 6.20 y2 6.20 notes: general 1. all dimensions shown are in millimeters (mm). 2. this land pattern design is based on the ipc-7351 guidelines. 3. all dimensions shown are at maximum ma terial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 5. a stainless steel, laser-cut and electro- polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1 for all pads. 8. a 3x3 array of 1.45 mm square openings on a 2.00 mm pitch should be used for the center ground pad. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
SI53112 34 rev. 1.1 d ocument c hange l ist revision 0.7 to revision 1.0 ? updated table 25, ?SI53112 64-pin qfn descriptions,? on page 27. ?? updated pin type for pins 11 and 14. revision 1.0 to revision 1.1 ? updated features on page 1. ? updated description on page 1. ? updated specs in table 4, ?phase jitter,? on page 6.
disclaimer silicon laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the silicon laboratories products. characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "typical" parameters provided can and do vary in different applications. application examples described herein are for illustrative purposes only. silicon laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. silicon laboratories shall have no liability for the consequences of use of the information supplied herein. this document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. the products must not be used within any life support system without the specific written consent of silicon laboratories. a "life support system" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. silicon laboratories products are generally not intended for military applications. silicon laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. trademark information silicon laboratories inc., silicon laboratories, silicon labs, silabs and the silicon labs logo, cmems?, efm, efm32, efr, energy micro, energy micro logo and combinations thereof, "the world?s most energy friendly microcontrollers", ember?, ezlink?, ezmac?, ezradio?, ezradiopro?, dspll?, isomodem ?, precision32?, proslic?, siphy?, usbxpress? and others are trademarks or registered trademarks of silicon laboratories inc. arm, cortex, cortex-m3 and thumb are trademarks or registered trademarks of arm holdings. keil is a registered trademark of arm limited. all other products or brand names mentioned herein are trademarks of their respective holders. http://www.silabs.com silicon laboratories inc. 400 west cesar chavez austin, tx 78701 usa clockbuilder pro one-click access to timing tools, documentation, software, source code libraries & more. available for windows and ios (cbgo only). www.silabs.com/cbpro timing portfolio www.silabs.com/timing sw/hw www.silabs.com/cbpro quality www.silabs.com/quality support and community community.silabs.com

▲Up To Search▲

Price & Availability of SI53112

	To Download SI53112 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .