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nt 256s72v89a0g 256mb : 32 m x 72 unbuffered sdram module preliminar y 0 9 / 200 1 1 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. 32 mx 72 bit one bank unbuffered sdram module based on 32 mx8, 4banks, 8 k refresh, 3.3v synchronous drams with spd features l 168 - pin unbuffered 8 - byte dual in - line memory module l intended for pc133 applications - clock frequency: 133mhz - clock cycle: 7.5ns - clock assess time: 5.4ns l inputs and outputs are lvttl (3.3v) compatible l single 3.3v 0.3v power supply l single pulsed ras interface l sdrams have 4 internal banks l module has 1 physical bank l fully synchronous to positive clock edge l data mask for byte read/ write control l auto refresh (cbr) and self refresh l automatic and controlled precharge commands l programmable operation: - cas latency: 2, 3 - burst type: sequential or interleave - burst length: 1, 2, 4, 8 - operation: burst read and write or multiple burs t read with single write l suspend mode and power down mode l 8192 refresh cycles distributed across 64ms l gold contacts l sdrams in tsop type ii package l serial presence detect with write protect description nt256s72v89a0g is unbuffered 168 - pin synchronous d ram dual in - line memory modules (dimm) which is organized as 32 mx 72 high - speed memory arrays and is configured as one 32 m x 72 physical bank. the dimm use s nine 32 mx8 sdrams in 400mil tsop ii packages. the dimm achieve s high - speed data transfer rates of up to 133mhz by employing a prefetch / pipeline hybrid architecture that supports the jedec 1n rule while allowing very low burst power. all control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs. all inputs are sampled at the positive edge of each externally supplied clock (ck0, ck2). internal operating modes are defined by combinations of ras , cas , we , s0 / s2 , dqmb, and cke0 signals. a command decoder initiates the necessary timings for each operation. a 1 5 - bit address bus accepts address information in a row / column multiplexing arrangement. prior to any access operation, the cas latency, burst type, burst length, and burst operation type must be programmed into the dimm by address inputs a0 - a9 during the mode register set cycle. the dimm uses serial presence detects implemented via a serial eeprom using the two - pin iic protocol. the first 128 bytes of serial pd data are used by the dimm manufacturer. the last 128 bytes are available to the customer. ordering information speed part number organization mhz. cl t rcd t rp leads power 14 3mhz 3 3 3 nt256s72v89a0g - 7k 133mhz 2 2 2 133mhz 3 3 3 nt256s72v89a0g - 75b 100mhz 2 2 2 125mhz 3 3 3 nt256s72v89a0g - 8b 32mx72 100mhz 2 2 2 gold 3.3v * cl = cas latency
nt 256s72v89a0g 256mb : 32 m x 72 unbuffered sdram module preliminar y 0 9 / 200 1 2 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. pin description ck0, ck 2 clock inputs dq0 - dq63 data input/output ck 1 , ck 3 unused (te rminated) clock inputs cb0 - cb7 check bit data input/output cke0 clock enable dqmb0 - dqmb7 data mask ras row address strobe v dd power (3.3v) cas column address strobe v ss ground we write enable nc no connect s0 , s2 chip selects scl serial presence detect clock input a0 - a9, a11 , a12 address inputs sda serial presence detect data input/output a10 / ap address input/autoprecharge sa0 - 2 serial presence det ect address inputs ba0, ba1 sdram bank address inputs wp serial presence detect write protect input pinout pin front pin back pin front pin back pin front pin back 1 v ss 85 v ss 29 dqmb1 113 dqmb5 57 dq18 141 dq50 2 dq0 86 dq32 30 s0 114 nc 58 dq19 142 dq51 3 dq1 87 dq33 31 nc 115 ras 59 v dd 143 v dd 4 dq2 88 dq34 32 v ss 116 v ss 60 dq20 144 dq52 5 dq3 89 dq35 33 a0 117 a1 61 nc 145 nc 6 v dd 90 v dd 34 a2 118 a3 62 nc 146 nc 7 dq4 91 dq36 35 a4 119 a5 63 nc 14 7 nc 8 dq5 92 dq37 36 a6 120 a7 64 v ss 148 v ss 9 dq6 93 dq38 37 a8 121 a9 65 dq21 149 dq53 10 dq7 94 dq39 38 a10/ap 122 ba0 66 dq22 150 dq54 11 dq8 95 dq40 39 ba1 123 a11 67 dq23 151 dq55 12 v ss 96 v ss 40 v dd 124 v dd 68 v ss 152 v ss 13 dq9 97 dq41 41 v dd 125 *ck1 69 dq24 153 dq56 14 dq10 98 dq42 42 ck0 126 a12 70 dq25 154 dq57 15 dq11 99 dq43 43 v ss 127 v ss 71 dq26 155 dq58 16 dq12 100 dq44 44 nc 128 cke0 72 dq27 156 dq59 17 dq13 101 dq45 45 s2 129 nc 73 v dd 157 v dd 18 v dd 102 v dd 46 dqmb2 130 dqmb6 74 dq28 158 dq60 19 dq14 103 dq46 47 dqmb3 131 dqmb7 75 dq29 159 dq61 20 dq15 104 dq47 48 nc 132 nc 76 dq30 160 dq62 21 cb0 105 cb4 49 v dd 133 v dd 77 dq31 161 dq63 22 cb1 106 cb5 50 nc 134 nc 78 v ss 162 v ss 23 v ss 107 v ss 51 n c 135 nc 79 ck2 163 *ck3 24 nc 108 nc 52 cb2 136 cb6 80 nc 164 nc 25 nc 109 nc 53 cb3 137 cb7 81 wp 165 sa0 26 v dd 110 v dd 54 v ss 138 v ss 82 sda 166 sa1 27 we 111 cas 55 dq16 139 dq48 83 scl 167 sa2 28 dqmb0 11 2 dqmb4 56 dq17 140 dq49 84 v dd 168 v dd note: all pin assignments are consistent for all 8 - byte unbuffered versions. check bits (cb0 - cb7) are applicable only to the x72 dimm; *ck1 and ck3 are terminated .
nt 256s72v89a0g 256mb : 32 m x 72 unbuffered sdram module preliminar y 0 9 / 200 1 3 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. sdram dimm block diagram (1 bank, 32 mx8 sdrams) s0 dqmb0 dqmb4 dqm dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d5 dqmb1 dqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d1 dqmb5 dqm dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d6 s2 dqmb2 dqm dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d3 dqmb6 dqm dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d7 dqmb3 dqm dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d4 dqmb7 dqm dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d8 ras cas cke0 we a0-a12 ba0 ba1 ras : sdrams d0-d8 cas : sdrams d0-d8 cke0 : sdrams d0-d8 we : sdrams d0-d8 a0-a11 : sdrams d0-d8 ba0 : sdrams d0-d8 ba1 : sdrams d0-d8 spd a0 a1 a2 scl wp sa0 sa1 sa2 v dd v ss d0 - d8 d0 - d8 sda 0.1uf * all resistor values are 10 ohms except as shown. 47k 0.33uf ck0 ck2 clk : sdrams d0-d2, d5-d6, 3.3pf cap. clk : sdrams d3-d4, d7-d8, 3.3pf cap. dqm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d0 * dqm cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d2 ck1,ck3 10pf
nt 256s72v89a0g 256mb : 32 m x 72 unbuffered sdram module preliminar y 0 9 / 200 1 4 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. input/output functional description symbol type signal polarity function ck0 , ck 2 input pulse positive edge the system clock inputs. all of the sdram inputs are sampled on the rising edge of their associated clock. cke0 i nput level active high activates the sdram ck0 and ck2 signals when high and deactivates them when low. by deactivating the clocks, cke0 low initiates the power down mode, suspend mode, or the self - refresh mode. s0 , s2 input pulse active low enables the associated sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas , we input pulse active low when sampled at the positive rising edge of the clock, ras , cas , we define the operation to be executed by the sdram. ba0, ba1 input level - selects which sdram bank is to be active. a0 - a9 a10/ap a11 , a12 input level - during a bank activate command cycle, a0 - a1 2 defines the row address (ra0 - ra1 2 ) when sampled at the rising clock edge. during a read or write command cycle, a0 - a 9 defi nes the column address (ca0 - ca 9 ) when sampled at the rising clock edge. in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0/ba1 define the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0/ba1 to control which bank(s) to precharge. if ap is high all 4 banks will be precharged regardless of the state of ba0 /ba1. if ap is low, then ba0/ba1 are used to define which bank to pre - charge. dq0 - dq63 , cb0 - cb7 input /output level - data and check bit input/output pins operate in the same manner as on conventional drams. dqmb0 - dqmb7 input pulse active high the d ata input/output mask places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a b yte mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. sa0 ? sa2 input level - address inputs. connected to either v dd or v ss on the system board to configure the serial presence detect eeprom address. s da input /output level - serial data. bi - directional signal used to transfer data into and out of the serial presence detect eeprom. since the sda signal is open drain/open collector at the eeprom, a pull - up resistor is required on the system board. scl i nput pulse - serial clock. used to clock all serial presence detect data into and out of the eeprom. since the scl signal is inactive in the ?high? state, a pull - up resistor is recommended on the system board. wp input level active high hardware write pro tect. when wp is active, writing to the eeprom array is inhibited. on the dimm, this input is connected to the eeprom write protect input and is also tied to ground through a 47k ohm pull - down resistor. v dd , v ss supply power and ground for the module.
nt 256s72v89a0g 256mb : 32 m x 72 unbuffered sdram module preliminar y 09 / 2001 5 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. absolute maximum ratings symbol parameter rating units notes v dd power supply voltage - 0.3 to +4.6 v in input voltage - 0.3 to v dd +0.3 v out output voltage - 0.3 to v dd +0.3 v 1 t a operating temperature (ambient) 0 to +70 c 1 t stg storage te mperature - 55 to +125 c 1 p d power dissipation 9 w 1 i out short circuit output current 50 ma 1 1.1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and func tional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommende d dc operating conditions (t a =0 to 70 c ) rating symbol parameter min. typ. max. units notes v dd power voltage 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 - v dd + 0.3 v 1,2 v il input low voltage - 0.3 - 0.8 v 1,3 v oh out put high voltage 2.4 - - v v ol out put low voltage - - 0.4 v i il input leakage current - 10 - 10 ua 1. all voltages referenced to v ss . 2. v ih (max) = v dd / v dd q + 1.2v for pulse width 5ns 3. v il (min) = v ss / v ssq - 1.2v for pulse width 5ns . capacitance (t a =2 5 c , f =1mhz, v dd =3.3 0.3v) symbol parameter max. unit c i1 input capacitance (a0 - a9, a10/ap, a11, ba0, ba1, ras , cas , we ) 77 c i2 input capacitance (cke0) 58 c i3 input capacitance ( s0 - s2 ) 33 c i4 input capacitance (ck0 - ck3) 40 c i5 input capacitance (dqmb0 - dqmb7) 21 c i6 input capacitance (sa0 - sa2, scl, wp) 9 c io1 input/output capacitance (dq0 - dq63 , cb0 - cb7 ) 10 c io2 input/output capacitance (sda) 11 pf dc output load circuit v oh (dc) = 2.4v,i oh = -2ma v ol (dc) = 0.4v,i ol = -2ma 3.3 v 1200 ohms 870 ohms 50 pf output
nt 256s72v89a0g 256mb : 32 m x 72 unbuffered sdram module preliminar y 0 9 / 200 1 6 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. operating, standby, and refresh currents (t a =0 to 70 c , v dd =3.3 0.3v) speed parameter symbol test condition - 7 k - 75 b - 8 b unit note operating current i cc1 1 bank operation , t rc = t rc (mim), t ck = min active - precharge command cycling without burst operation 1170 1080 1035 ma 1, 2 i cc2p cke0 v il (max), t ck = min, s0 , s2 = v ih (min) 16 16 16 ma precharge standby current in power - down mode i cc2ps cke0 v il (max), t ck = oo , s0 , s2 = v ih (min) 16 16 16 ma i cc2n cke0 3 v ih (min), t ck = min s0 , s2 = v ih (min) 270 270 180 ma 3 precharge standby current in non power - down mode i cc2ns cke0 3 v ih (min), t ck = oo, s0 , s2 = v ih (min) 72 72 72 ma 4 i cc3p cke0 v il (max), t ck = min . s0 , s2 = v ih (min) (power down mode) 54 54 54 ma 5 no operating current ( active state : 4 bank) i cc3n cke0 3 v ih (min), t ck = min s0 , s2 = v ih (min) 540 540 360 ma 3 operating current ( burst mode ) i cc4 t ck =min , read/ write command cycling, multiple banks active, gapless data, bl=4 1080 1080 810 ma 2, 6 auto(cbr) refresh current i cc5 t ck =min , cbr command cycling 1575 1575 1395 ma self refresh current i cc6 cke0 0.2v 27 27 27 ma serial pd device standby current i sb v in = gnd or v dd 30 30 30 m a 7 serial pd device active power supply current i cca scl clock frequency=100 mhz 1 1 1 m a 8 1. these parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t ck and t rc . input signals are changed up to thre e times during t rc (min). 2. the specified values are obtained with the output open. 3. input signals are changed once during three clock cycles. 4. input signals are stable. 5. active standby current will be higher if clock suspend is entered during a bu rst read cycle (add 1ma per dq). 6. input signals are changed once during t ck(min) . 7. v dd =3.3v 8. input pulse levels v dd x 0.1 to v dd x 0.9, input rise and fall times 10ns, input and output timing levels v dd x 0.5, output load 1 ttl gate and cl=100pf.
nt 256s72v89a0g 256mb : 32 m x 72 unbuffered sdram module preliminar y 0 9 / 200 1 7 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac characteristics (t a =0 to 70 c , v dd =3.3 0.3v) 1. an initial pause of 200 us, with dqmb0 - 7 and cke0 held high, is required after power - up. a precharge all banks command must be given followed by a minimum of eight auto (cbr) refresh cycles be fore or after the mode register set operation. 2. the transition time is measured between v ih and v il (or between v ih and v il ). 3. in addition to meeting the transition rate specification, the ck0, ck2, and cke0 signals must transit between v ih and v il (o r between v il and v ih ) in a monotonic manner. 4. ac timing tests have v il =0.8vand v ih = 2.0 v with the timing referenced to the 1.40v crossover point. 5. ac measurements assume t t =1.2 ns. ac output load circuits clock input output t hold t setup t ckl t ckh t t v ih v il 1.4v 1.4v t ac t lz toh 1.4v output zo = 50 ohm 50 pf ac output load circuit
nt 256s72v89a0g 256mb : 32 m x 72 unbuffered sdram module preliminar y 0 9 / 200 1 8 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac timing parameters clock and clock enable parameters - 7 k - 75 b - 8 b symbol parameter min. max. min. max. min. max. unit note tck3 clock cycle time, cas latency = 3 7 1000 7.5 1000 8 1000 ns tck2 clock cycle time , cas latency = 2 7.5 1000 10 1000 1 0 1000 ns tac3(b) clock access time, cas latency = 3 - 5.4 - 5.4 - 6 ns 1 tac2(b) clock access time, cas latency = 2 - 5.4 - 6 - 6 ns 1 tckh clock high pulse width 2.5 - 2.5 - 3 - ns 2 tckl clock low pulse width 2.5 - 2.5 - 3 - ns 2 tces clock enable set - up time 1.5 - 1.5 - 2 - ns tceh clock enable hold time 0.8 - 0.8 - 1 - ns tsb power down mode entry time 0 7.5 0 7.5 0 12 ns tt transition time (rise a nd fall) 0.5 10 0.5 10 0.5 10 ns 1. access time is measured at 1.4v. in ac characteristics section, see notes. 2. t ckh is the pulse width of clk measured from the positive edge to the negative edge referenced to v ih (min). t ckl is the pulse width of clk mea sured from the negative edge to the positive edge referenced to v il (max). common parameters - 7 k - 75 b - 8 b symbol parameter min. max. min. max. min. max. unit note tcs command setup time 1.5 - 1.5 - 2 - ns tch command hold time 0.8 - 0.8 - 1 - ns tas address and bank select set - up time 1.5 - 1.5 - 2 - ns tah address and bank select hold time 0.8 - 0.8 - 1 - ns trcd ras to cas delay 20 - 20 - 20 - ns 1 trc bank cycle time 6 0 - 6 7.5 - 70 - ns 1 tr f c au to refresh to active/auto refresh 60 - 67.5 - 70 - tras active command period 45 100k 45 100k 50 100k ns 1 trp precharge time 20 - 20 - 20 - ns 1 trrd bank to bank delay time 15 - 15 - 20 - ns 1 tccd cas to cas d elay time 1 - 1 - 1 - clk 1.these parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the num ber of clock cycles = specified value of timing / clock period (count fractions as a whole number). mode register set cycle - 7 k - 75 b - 8 b symbol parameter min. max. min. max. min. max. unit note trsc mode register set cycle time 2 - 2 - 2 - clk 1 1.these parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the num ber of clock cycles = specified value of timing / clock period (count fractions as a whole number).
nt 256s72v89a0g 256mb : 32 m x 72 unbuffered sdram module preliminar y 0 9 / 200 1 9 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. read cycle - 7 k - 75 b - 8 b symbol parameter min. max. min. max. min. max. unit note - - - - 2 .5 - ns toh data out hold time 2.7 - 2.7 - 3 - ns tlz data out to low impedance time 0 - 0 - 0 - ns thz3 data out to high impedance time 3 5.4 3 5.4 3 6 ns 1 tdqz dqm data out disable latency 2 - 2 - 2 - clk 1. referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. refresh cycle - 7 k - 75 b - 8 b symbol parameter min. max. min. max. min. max. unit note tref refresh period - 64 - 64 - 64 ms tsrex self refresh exit time 10 - 10 - 10 - ns write cycle - 7 k - 75 b - 8 b symbol parameter min. max. min. max. min. max. unit note tds data in set - up time 1.5 - 1.5 - 2 - ns tdh data in hold time 0.8 - 0.8 - 1 - ns tdpl data input to precharge 15 - 15 - 15 - ns tdal3 data in to active delay cas latency = 3 5 - 5 - 5 - clk tdal2 data in to active delay cas latency = 2 5 - - - - - clk tdqw dqm write mask latency 0 - 0 - 0 - ns
nt 256s72v89a0g 256mb : 32 m x 72 unbuffered sdram module preliminar y 0 9 / 200 1 10 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. serial presence detect -- part 1 of 2 32 mx 72 sdram dimm based on 32 mx8, 4b anks, 8 k refresh, 3.3v sdrams with sp d spd entry value serial pd data entry (hexadecimal) byte description - 7k - 75b - 8b - 7k - 75 - 8b note 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 256 0 8 2 fundamental memory type sdram 0 4 3 number of row addresses on assembly 1 3 0 d 4 number of column addresses on assembly 10 0a 5 number of dimm bank 1 01 6. data width of assembly x 72 4 8 7 data width of assembly (cont?) x 72 00 8 voltage inte rface level of this assembly lvttl 0 1 9 sdram device cycle time at cl= 3 7ns 7.5ns 8ns 70 75 80 10 sdram device access time from clock at cl= 3 5.4ns 5.4 ns 6 ns 54 54 60 11 dimm configuration type ecc 02 12 refresh rate/type sr/1x( 7.8 us) 82 13 prima ry sdram width x8 08 14 error checking sdram device width x8 08 15 sdram device attributes: min c l k delay, random col access 1 clock 01 16 sdram device attributes: burst length supported 1, 2,4,8 0 f 17 sdram device attributes: number of device bank s 4 04 18 sdram device attributes: cas latencies supported 2/3 2/ 3 2/ 3 0 6 0 6 0 6 19 sdram device attributes: cs latency 0 01 20 sdram device attributes: we latency 0 0 1 21 sdram device attributes unbuffered 00 22 sdram device attributes: general w r - 1/rd burst, precharge all, auto - precharge, v dd +/ - 1 0% 0e 23 minimum clock cycle at cl=2 7.5ns 10ns 10ns 75 a0 a0 24 maximum data access time from clock at cl=2 5.4 ns 6 ns 6 ns 54 60 60 25 minimum clock cycle time at cl=1 n/a 00 26 maximum data acc ess time from clock at cl=1 n/a 00 27 minimum row precharge time( t r p ) 15ns 20ns 20ns 0f 14 14 28 minimum row active to row active delay ( t r rd ) 15ns 15ns 20ns 0f 0f 14 29 minimum ras to cas delay ( t r cd ) 15ns 20ns 20ns 0f 14 14 30 minimum ras pulse w idth ( t ras ) 45ns 45ns 50ns 2d 2d 32 31 module bank density 256 mb 4 0 32 address and command setup time before clock 1.5 ns 1.5 ns 2 ns 15 15 20 33 address and command hold time after clock 0. 8 ns 0. 8 ns 1 ns 08 08 10 34 data input setup time before clock 1.5 ns 1.5 ns 2 ns 15 15 20 35 data input hold time after clock 0. 8 ns 0. 8 ns 1 ns 08 08 10 36 - 61 reserved undefined 00 62 spd revision 1.2a 1.2a 1.2a 12 12 12 63 checksum for byte 0 - 62 checksum data 1e 64 ab
nt 256s72v89a0g 256mb : 32 m x 72 unbuffered sdram module preliminar y 0 9 / 200 1 11 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. serial presence detect -- part 2 of 2 3 2 mx72 sdram dimm based on 32 mx8, 4banks, 8k refresh, 3.3 v sdrams with sp d spd entry value serial pd data entry (hexadecimal) byte description - 7k - 75b - 8b - 7k - 75 b - 8b note 64 - 71 manufacturer?s jeded id code nanya 7f7f7f0b 00000000 3 72 module manufa cturing location n/a 00 73 - 90 module part number n/a n/a n/a 00 00 00 91 - 92 module revision code n/a 00 93 - 94 module manufacturing data year/week code yy/ww 1,2 95 - 98 module serial number serial number 00 99 - 125 reserved undefined 00 126 modules supports this clock frequency 100mhz 64 127 attributes for clock frequency defined in byte 126 ck0, ck2,cl3, cl2 concurrent ap af 128 - 255 open for customer use undefined 00 1. yy= binary coded decimal year code, 0 - 99(decimal) , 00 - 63(hex) 2. ww= binary cod ed decimal year code, 01 - 52(decimal) , 01 - 34(hex) 3. nanya 11decimal (bank four) 0000 1011 binary 0b hex.
nt 256s72v89a0g 256mb : 32 m x 72 unbuffered sdram module preliminar y 0 9 / 200 1 12 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. package dimensions note : all dimensions are typical unless otherwise stated. 133.35 127.33 1.660 2.625 detail b 0.079 detail b 1.375 0.157 0.700 front view side pin 1 0.118 0.050 6.35 6.35 0.079 detail a detail a detail c 2.489 0.050 detail c 0.039 0.008 2.59 unit : millimeters back view inches 5.013 5.250 3.0 66.67 42.17 0.250 0.250 4.00 17.78 34.925 0.106 max. 1.27 3.124 0.123 2.006 2.006 3.124 0.123 0.203 1.0 1.27 0.098

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