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? semiconductor components industries, llc, 2008 december, 2008 ? rev. 1 1 publication order number: NCN6804/d NCN6804 dual smart card interface ic with spi programming interface the NCN6804 is a dual interface ic with serial control. it is dedicated for smart card/secure access module (sam) reader/writer applications. it allows the management of two external iso/emv cards (class a, b or c). an spi bus is used to control and configure the dual interface. the cards are controlled in a multiplexed mode. two NCN6804 devices (4 smart card interfaces) can share one single control bus thanks to a dedicated hardware address pin (s1). an accurate protection system guarantees timely and controlled shutdown in the case of external error conditions. this device is an enhanced version of the ncn6004a, more compact, more flexible and fully compatible with the ncn6001, its single interface counterpart version. it is fully compatible with iso 7816 ? 3, emv and gie ? cb standards. features ? dual smart card / sam interface with spi programming bus ? fully compatible with iso 7816 ? 3, emv and gie ? cb standards ? one protected bidirectional buffered i/o line per card port ? wide power supply voltage range: 2.7v < v ddpa/b & v dd < 5.5v ? programmable/independent crd_vcc supply for each smart card ? multiplexed mode of operating ? handles 1.8 v, 3.0 v and 5.0 v smart cards ? programmable rise & fall card clock slopes (slow & fast modes) ? support up to 40 mhz clock with internal programmable clock (division ratio 1/1, 1/2, 1/4) managed independently for each card ? built ? in programmable crd_clk stop function handles low state ? esd protection on card pins (8 kv, human body model) ? activation / deactivation built ? in sequencer ? internal i/o pull ? up resistor with resistor disconnection option (en_rpu) ? 4?wire series bus interface ? spi ? qfn32 (5x5 mm 2 ) package ? this is a pb ? free device typical application ? point of sales (pos) and transaction terminals ? atm (automatic teller machine) / banking terminal interfaces ? set top box decoder and pay tv pin connections http://onsemi.com qfn32 case 488am marking diagram a = assembly location l = wafer lot y = year w = work week g = pb ? free package device package shipping ? ordering information NCN6804mnr2g qfn32 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. 32 1 ncn 6804 alywg 1 exposed pad 32 gndd crd_deta crd_c4a crd_c8a crd_i/oa crd_rsta crd_clka crd_vcca s1 33 crd_detb crd_c4b crd_c8b crd_i/ob crd_rstb crd_clkb crd_vccb int cs gndpa l1a vddpa vddpb l1b gndpb l2b l2a vdd en_rpu mosi miso clk_spi clk_in i/o 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 31 30 29 28 27 26 25 9 10111213141516 1
NCN6804 http://onsemi.com 2 figure 1. typical interface application microcontroller 22 h smart card a smart card b gndd gndpa gndpb vdd 10 f 10 f 0.1 f gnd crd_deta crd_c4a crd_c8a crd_i/oa crd_rsta crd_clka crd_vcca s1 crd_detb crd_c4b crd_c8b crd_i/ob crd_rstb crd_clkb crd_vccb int cs l1a vddpa vddpb l1b l2b l2a vdd en_rpu mosi miso clk_spi clk_in i/o NCN6804 22 h 10 f gnd gnd gnd gnd vdd vbat spi bus data port det det det det vcc rst clk c4 gnd vpp i/o c8 vcc rst clk c4 gnd vpp i/o c8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
NCN6804 http://onsemi.com 3 i/o mux logic control interrupt block card #a detection clock dc ? dc converter card #a vdd clk div clk div exposed pad figure 2. NCN6804 block diagram vdd int cs miso mosi clk_spi clk_in i/o en_rpu gndd s1 vddpa l1a l2a crd_vcca gndpa crd_i/oa crd_rsta crd_clka crd_c8a crd_c4a crd_deta crd_detb crd_c4b crd_c8b crd_clkb crd_rstb crd_i/ob gndpb crd_vccb l2b l1b vddpb 1 12 11 9 8 10 5 6 7 4 3 2 23 22 21 18 19 20 15 17 16 14 13 32 24 27 29 30 28 26 25 31 33 vdd vdd vdd 18 k 18 k 50 k mux card #b detection dc ? dc converter card #a dc ? dc converter card #b dc ? dc converter card #b address decoding register dual 8 ? bit shift iso7816 sequencer card #a iso7816 sequencer card #b 18 k gnd int#a det#a det#b int#b det#a det#b int#a
NCN6804 http://onsemi.com 4 pin function and description pin name type description 1 s1 i address pin (chip identification pin) ? allows having in parallel up to 2 NCN6804 devices (4 inter- faces) managed by 1 chip select pin only (cs ) ? multiple interface application case. when one dual interface only is used this pin can be connected to ground. 2, 23 crd_deta, crd_detb i the signal coming from the external card connector is used to detect the presence of the card. a built ? in pull ? up low current source biases this pin high, making it active low, assuming one side of the external switch is connected to ground. a built ? in digital filter protects the system against voltage spikes present on this pin. the polarity of the signal is programmable by the mosi message; refer to table 2. on the other hand, the meaning of the feedback message contained in the miso register bit b4, depends upon the spi mode of operation as defined here below: spi normal mode : the miso bit b4 is high when a card is inserted, whatever be the polarity of the card detect switch. spi special mode : the miso bit b4 copies the logic state of the card detect switch as depicted here below, whatever be the polarity of the switch used to handle the detection: crd_det = low => miso/b4 = low crd_det = high => miso/b4 = high in both cases, the chip must be programmed to control the right logic state (table 2). since the bias current supplied by the chip is very low, typically 5.0 a, care must be observed to avoid low imped- ance or cross coupling when this pin is in the open state. 3, 22 crd_c4a, crd_c4b o auxiliary mixed analog/digital line to handle synchronous card connected when used to the card pin c4. an accelerator circuit makes sure the output positive going rise time is fully within the iso/emv specifications. 4, 21 crd_c8a, crd_c8b o auxiliary mixed analog/digital line to handle synchronous card connected when used to the card pin c8. an accelerator circuit makes sure the output positive going rise time is fully within the iso/emv specifications. 5, 20 crd_ioa, crd_iob i/o this pin handles the connection to the serial i/o pin of the card connector. a bi ? directional level translator adapts the serial i/o signal between the card and the c. an internal active pull down device forces this pin to ground during either the crd_vcc start up sequence, or when crd_vcc = 0v. the output current is internally limited to 15ma. when operating in a synchronous mode i/o is transmitted through the spi bus (mosi bit b2) to crd_i/o. in that case i/o is disconnec- ted and no longer used. 6, 19 crd_rsta, crd_rstb o this pin is connected to the reset pin of the card connector. a level translator adapts the reset signal from the c (through the spi bus) to the external card. the output current is internally limited to 15ma. the crd_rst is validated when cs = low, and is hard wired to ground by and intern- al active pull down circuit when the card is deactivated. 7, 18 crd_clka, crd_clkb o clock pin connected to the card pin c3. an internal active pull down device forces this pin to ground during the crd_vcc start up sequence, or when crd_vcc = 0v. the rise and fall slopes, either fast or slow, of this signal can be programmed by the spi bus. refer to table 2. 8, 17 crd_vcca, crd_vccb power power supply to the external card (card pin c1). an external capacitor c out = 10 f minimum is re- quired. in the event of a crd_vcc under ? voltage issue, the NCN6804 detects the situation and feedback the information in the status bit (miso bit b0). the device does not take any further ac- tion; particularly the dc/dc converter is neither stopped nor re ? programmed by the NCN6804. it is up to the external c to handle the situation. however, when crd_vcc is overloaded, the NCN6804 shuts off the dc/dc converter, runs a power down iso7816 sequence and reports the fault in the status register (miso register bit b0). 9 l2a power the high side of the external inductor a. 10 gndpa power dc/dc converter a power ground pin. 11 l1a power the low side of the external inductor a. 12 vddpa power dc/dc converter a power supply input (c bypass_min = 4.7 f). 13 vddpb power dc/dc converter b power supply input (c bypass_min = 4.7 f). 14 l1b power the low side of the external inductor b. 15 gndpb power dc/dc converter b power ground pin. 16 l2b power the high side of the external inductor b. 24 int o this pin is activated low when a card has been inserted and detected by the crd_deta or crd_detb pins in either of the external ports. similarly an interrupt is generated when the crd_vcca or b output is overloaded, or when the card has been extracted whatever be the trans- action status (running or stand by). the int signal is reset to high according to table 7. on the other hand, the pin is forced to logic high when the power supply voltage vddpa or b drops below 2 v.
NCN6804 http://onsemi.com 5 pin function and description pin description type name 25 i/o i/o this pin is connected to an external micro ? controller ( c) interface. a bi ? directional level translator adapts the serial i/o signal between the smart card and the c. the level translator is enabled when cs = low, the sub address has been selected and the system operates in the asynchronous mode. when a synchronous card is in use this pin is disconnected and the data and transaction take place through the mosi and the miso registers. the internal pull up resistor connected on the c side is activated and visible by the selected chip only. 26 clk_in i this pin (high impedance) can be connected to either the c master clock or to a crystal oscillator clock to drive the external smart cards. the signal is fed to the internal clock selector circuit and translated to the crd_clka or crd_clkb pins at either the same frequency, or divided by 2, 4 or 8, depending upon the programming mode. refer to table 2. synchronous case: clock managed through the spi bus ? clk_in is disconnected. note: the chip guarantees the emv 50% duty cycle when the clock divider ratio is 1/2, 1/4, or 1/8, even when the clk_in signal is out of the 45% to 55% range specified by iso and emv specifications. 27 cs i this pin synchronizes and enables the spi communication. all the NCN6804 functions, both pro- gramming and card transaction, are disabled when cs = high. 28 clk_spi clock signal to synchronize the spi data transfer. this clock is fully independent from the clk_in signal and does not play any role with the data transaction (i/o ? crd_i/o). 29 miso o master in slave out: spi data output from the NCN6804. this status byte carries the state of the interface, the serial transfer being achieved according to the programmed mode (table 2), using the same clk_spi signal and during the same mosi time frame. an external 4.7 k pull down resistor might be necessary to avoid misunderstanding of the pin 29 voltage during the high z state. 30 mosi i master out slave in: spi data input from the c. this byte contains the address of the selected chip among the two possible (bit b6), together with the programming code for a given interface. see table 2. 31 en_rpu i this pin is used to activate the i/o internal pull ? up resistor such as: en_rpu = low => i/o pull ? up resistor disconnected en_rpu = high => i/o pull ? up resistor connected when two or more NCN6804 chips share the same i/o bus, one chip only shall have the internal pull ? up resistor enabled to avoid any overload of the i/o line. moreover, when asynchronous and synchronous cards are handled by the interfaces, the activated i/o pull ? up resistor must preferably be the one associated with the asynchronous circuit . on the other hand, since no internal pull ? up bias resistor is built in the chip, pin 31 must be connected to the right voltage level to make sure the logic function is satisfied. 32 vdd power this pin is connected to the system controller power supply (c bypass_min = 100 nf). when v dd is below 2.5 v the crd_vcca or b is disabled. the NCN6804 goes into a shutdown mode. 33 gndd power digital/analog ground. this pin is the exposed pad and is the ground for the digital/analog circuit section. it needs to be connected to the pcb ground. attributes characteristics values esd protection human body model, smart card pins (card interface pins (card a and b)) (note 1) human body model, crd_deta/b pins (2, 23) (note 1) human body model, all other pins (note 1) 8 kv 4 kv 2 kv moisture sensitivity (note 2) qfn ? 32 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in meets or exceeds jedec spec eia/jesd78 ic latchup test 1. human body model (hbm), r = 1500 , c = 100 pf. 2. for additional information, see application note and8003/d.
NCN6804 http://onsemi.com 6 maximum ratings (note 3) rating symbol value unit dc/dc converter power supply voltage (v ddpa/b ) v sup (note 4) ? 0.5 v sup 6 v power supply from microcontroller side (v dd ) v dd ? 0.5 v dd 6 v external card power supply (card a and b) crd_vcc ? 0.5 crd_vcc 6 v digital input pins v in i in ? 0.5 v in (v dd + 0.5) but < 6.0 5 v ma digital output pins (i/o, miso, int ) v out i out ? 0.5 vo ut (v dd + 0.5) but < 6.0 10 v ma smart card output pins v out ? 0.5 v out (crd_vcc + 0.5) but< 6.0 v smart card output pins excepted crd_clk i out 15 (internally limited) ma crd_clk pin i out 70 (internally limited) ma inductor current i lmax 500 (internally limited) ma qfn ? 32 5x5 mm 2 package power dissipation @ t a = +85 c thermal resistance junction ? to ? air p d r ja 1650 40 mw c/w operating ambient temperature range t a ? 40 to +85 c operating junction temperature range t j ? 40 to +125 c maximum junction temperature t jmax +125 c storage temperature range t stg ? 65 to + 150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. maximum electrical ratings are defined as those values beyond which damage to the device may occur at t a = +25 c. 4. v sup = v ddpa/b = v ddpa and v ddpb
NCN6804 http://onsemi.com 7 power supply section ( ? 40 c to +85 c, unless otherwise noted) pin symbol rating min typ max unit 12, 13 v sup power supply (v ddpa/b ) (note 5) 2.7 5.5 v 12, 13 i sup dc operating current ? all card pins unloaded, clk_in=low v sup = 2.7 v, crd_vcca or b = 5 v v sup = 5.5 v, crd_vcca or b = 5 v 0.5 0.5 ma 12, 13 i supst standby supply current, no card inserted int =clk_in=clk_spi=cs = i/o = mosi = en_rpu = h v sup = 5.5 v 50 a 32 v dd operating voltage (note 5) 2.7 5.5 v 32 i vdd operating current ? clk_in = clk_spi = mosi = high, cs = i/o =low 150 a 32 i vdd_sd shutdown current ? cs = high 60 a 32 uvlov dd under voltage lockout 1.8 2.5 v 8, 17 crd_vcc output card supply voltage @ 2.7 v< vcc < 5.5 v crd_vcca/b = 1.8 v @ i load = 35 ma crd_vcca/b = 3.0 v @ i load = 60 ma crd_vcca/b = 5.0 v @ i load = 65 ma 1.66 2.76 4.65 1.80 3.00 5.00 1.94 3.24 5.35 v 8, 17 i crd_vcc maximum continuous output current @ crd_vcc = 1.8 v @ crd_vcc = 3.0 v @ crd_vcc = 5.0 v 35 60 65 ma 8, 17 i crd_vcc_ov output over ? current limit : v sup = 2.7 v, crd_vcca/b = 1.8 v, 3.0 v, 5.0 v v sup = 5.5 v, crd_vcca/b = 1.8 v, 3.0 v, 5.0 v 200 260 ma 8, 17 dv crd_vcc output card supply voltage ripple @ v sup = 3.6v, l = 22 h, c out = 10 f (ceramic x7r), i crd_vcc = iso maximum current (note 6) crd_vcca/b = 5.0 v crd_vcca/b = 3.0 v crd_vcca/b = 1.8 v 60 45 40 mv 8, 17 crd_vcc ton output card turn on time v sup = 2.7 v, crd_vcca/b = 5.0 v l out = 22 h, c out = 10 f ceramic 500 s 8, 17 crd_vcc toff output card turn off time vcca/p = 2.7 v, crd_vcca/b = 5.0 v l out = 22 h, c out = 10 f ceramic, crd_vcc off < 0.4 v 100 250 s note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. v dd and v sup have separated pads for noise and emi immunity improvement ? by similarity with the ncn6001 v dd and v sup have to be equal and connected to the same power supply (v dd = v sup = v ddpa/b ) 6. ceramic x7r, smd type capacitors are mandatory to achieve the crd_vcc ripple specifications. the ceramic capacitor has to be chosen according to its esr (very low esr) and dc bias features. the capacitance value can strongly vary with the dc voltage applied (see figure 22).
NCN6804 http://onsemi.com 8 digital input/output section clk_in, i/o, clk_spi, mosi, miso, cs , int , en_rpu ( ? 40 c to +85 c) pin symbol rating min typ max unit 26 f clk_in input asynchronous clock duty cycle = 50% @ v dd = 3.0 v @ v dd = 5.0 v 30 40 mhz 26 f tr f tf input clock rise time input clock fall time 2 2 ns 28 f clk_spi input spi clock 15 mhz 28 tr spi , tf spi input clk_spi rise/falltime 12 ns 30 tr mosi , tf mosi input mosi rise/falltime 12 ns 29 tr miso , tf miso output miso rise/falltime @ c s = 30 pf 12 ns 27 tr str , tf str input cs rise/falltime 12 ns 25 t rio t fio i/o data transfer switching time, both directions (i/o & crd_ioa/b) @ cs = 30 pf i/o rise time (see note 7) i/o fall time 0.8 0.8 s 24 r int int pull up resistor 20 45 80 k 25,26,2 7,28,30 v ih positive going input high level voltage threshold (clk_in, mosi, clk_spi, cs , en_rpu) 0.70 * v dd v dd v 25,26,2 7,28,30 v il negative going input low level voltage (clk_in, mosi, clk_spi, cs , en rpu) 0 0.3 *v dd v 24, 29 v oh output high voltage int , miso @ i oh = ? 10 a (source) v dd ? 1.0 v 24, 29 v ol output low voltage int , miso @ i ol = 200 a (sink) 0.40 v 28 td clk_spi delay between 2 consecutive clk_spi burst sequence 33 ns 25 r pu_i/o i/0 pullup resistor 12 18 24 k note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions are not implied. device specificatio n limit values are applied individually under normal operating conditions and not valid simultaneously. 7. since a 18 k (typical) pullup resistor is provided by the NCN6804, the external mpu can use an open drain connection. on the other hand nmos smart cards can be used straightforward.
NCN6804 http://onsemi.com 9 smart card interface section ( ? 40 c to +85 c temperature range unless otherwise noted) note: digital inputs undershoot 0.30v to ground, digital inputs overshoot < v dd + 0.30v pin symbol rating min typ max unit 6,19 v oh v ol t r t f crd_rsta/b @ crd_vcca/b = 1.8 v, 3.0 v, 5.0 v output reset v oh @ i rst = ? 200 a output reset v ol @ i rst = 200 a crd_rsta/b @ crd_vcca/b = 1.8 v, 3.0 v, 5.0 v output reset risetime @ c out = 30 pf output reset falltime @c out = 30 pf crd_vcc ? 0.5 crd_vcc 0.40 100 100 v v ns ns 3, 4 21, 22 v oh v ol t r t f crd_c4a/b, crd_c8a/b @ crd_vcca/b = 1.8 v, 3.0 v, 5.0 v output v oh @ i rst = ? 200 a output v ol @ i rst = 200 a output rise time @ c out = 30 pf output fall time @c out = 30 pf crd_vcc ? 0.5 crd_vcc 0.4 100 100 v v ns ns 7, 18 f crdclk v oh v ol f crddc t ress t fcs t rills t ulsa crd_clka/b as a function of crd_vcca/b crd_vcca/b = 1.8 v, 3.0 v or 5.0v output frequency output v oh @ icrd_clk = ? 200 a output v ol @ icrd_clk = 200 a crd_clka/b output duty cycle crd_vcca/b = 1.8 v, 3.0 v or 5.0 v rise & fall time @ crd_vcca/b = 1.8 v, 3.0 v or 5.0 v clock programmed as fst_slp output crd_clka/b risetime @ c out = 30 pf output crd_clka/b falltime @ c out = 30 pf rise & fall time @ crd_vcca/b = 1.80v to 5.0v clock programmed as slo_slp output crd_clka/b risetime @ c out = 30 pf output crd_clka/b falltime @ c out = 30 pf crd_vcc ? 0.5 45 20 crd_vcc 0.4 55 4 4 16 16 mhz v v % ns ns ns ns 5,20 v ih v il v oh v ol t r t f crd_ioa/b input voltage high level @ crd_vcca/b = 1.8 v, 3 v and 5 v crd_ioa/b input voltage low level @ crd_vcca/b = 1.8 v, 3 v and 5 v output v oh @ icrd_i/o = ? 20 a, v ih = vdd @ crd_vcca/b = 1.8 v, 3 v and 5 v output v ol @ icrd_i/o = 500 a, v il = 0 v @ crd_vcca/b = 1.8 v, 3 v and 5 v crd_ioa/b rise time, @ c out = 30 pf crd_ioa/b fall time, @ c out = 30 pf crd_vcc*0.6 ? 0.30 crd_vcc ? 0.5 0 crd_vcc+0.3 0.80 crd_vcc 0.40 0.8 0.8 v v v v s s 5, 20 r crdpu crd_ioa/b pull up resistor 12 18 24 k 2, 23 t crdin t crdoff card detection digital filter delay: card insertion card extraction 25 25 50 50 150 150 s s 2, 23 v ihdet card insertion or extraction positive going input high voltage 0.70 * vcc vcc v 2, 23 v ildet card insertion or extraction negative going input low voltage 0 0.30 * vcc v 3, 4, 5, 6, 19, 20, 21, 22 icrd output peak max current under card static operation mode @ crd_vcc = 1.8v, 3.0v, 5.0v crd_i/oa/b, crd_rsta/b, crd_c4a/b, crd_c8a/b 15 ma 7, 18 icrd_clk output peak max current under card static operation mode @ crd_vcc = 1.8 v, 3.0 v, 5.0 v crd_clka/b 70 ma note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
NCN6804 http://onsemi.com 10 programming write register wrt_reg (is low only) similar to the ncn6001, the NCN6804?s wrt_reg register handles 3 command bits [b5:b7] and 5 data bits [b0:b4] as depicted in tables 1 and 2. these bits are concatenated into 1 byte [msb0,lsb0] in order to accelerate the programming sequence. the register can be updated when cs is low only. the wrt_rgt has been defined to be compatible with the ncn6001 write register. table 1. wrt_reg bit definitions b0 b1 if (b7 + b6 + b5 ) = 000 or (b7 + b6 + b5 ) = 010 then case 00 crd_vcca = 0 v case 01 crd_vcca = 1.8 v case 10 crd_vcca = 3.0 v case 11 crd_vcca = 5.0 v else if (b7 + b6 + b5 ) = 001 or (b7 + b6 + b5 ) = 011 then case 00 crd_vccb = 0 v case 01 crd_vccb = 1.8 v case 10 crd_vccb = 3.0 v case 11 crd_vccb = 5.0 v else if (b7 + b6 + b5) =110 or (b7 + b6 + b5) = 111 then b1 drives crd_c4a or b (respectively) b0 drives crd_c8a or b (respectively) else if (b7 + b6 + b5) =101 then case 00 crd_det = no case 01 crd_det = nc case 10 spi_mode = special case 11 spi_mode = normal else if (b7 + b6 + b5) =100 then na (not applicable) end if 8. when operating in asynchronous mode, b6 is compared with the external voltage level present pin s1 (pin 1). 9. the crd_rst pin reflects the content of the mosi wrt_reg [b4] during the chip programming sequence. since the bit shall be lo w to address the chip?s internal register, care must be observed as this signal will be immediately transferred to the crd_rst pi n.
NCN6804 http://onsemi.com 11 table 1. wrt_reg bit definitions b2 b3 if (b7 + b6 + b5 ) = 000 or (b7 + b6 + b5 ) = 010 then case 00 crd_clka = low case 01 crd_clka = clk_in case 10 crd_clka = clk_in / 2 case 11 crd_clka = clk_in / 4 else if (b7 + b6 + b5 ) = 001 or (b7 + b6 + b5 ) = 011 then case 00 crd_clkb = low case 01 crd_clkb = clk_in case 10 crd_clkb = clk_in / 2 case 11 crd_clkb = clk_in / 4 else if (b7 + b6 + b5) =110 or (b7 + b6 + b5) = 111 then b3 drives crd_clka or b (respectively) b2 drives crd_ioa or b (respectively) else if (b7 + b6 + b5) =101 then case 00 crd_clka & b = slo_slp case 01 crd_clka & b = fst_slp case 10 na case 11 na else if (b7 + b6 + b5) =100 then na (not applicable) end if b4 if (b7 + b6 + b5) <> 101 and (b7 + b6 + b5) <> 100 then b4 drives crd_rsta or b pin b5 b6 b7 000 select NCN6804 device # 1 asynchronous card a (note 8) 001 select NCN6804 device # 1 asynchronous card b (note 8) 010 select NCN6804 device # 2 asynchronous card a (note 8) 011 select NCN6804 device # 2 asynchronous card b (note 8) 100 na 101 set card detection switch polarity, set spi_mode normal or special , set crd_clka & b slopes fast or slow 110 select external synchronous card a 111 select external synchronous card b 8. when operating in asynchronous mode, b6 is compared with the external voltage level present pin s1 (pin 1). 9. the crd_rst pin reflects the content of the mosi wrt_reg [b4] during the chip programming sequence. since the bit shall be lo w to address the chip?s internal register, care must be observed as this signal will be immediately transferred to the crd_rst pi n.
NCN6804 http://onsemi.com 12 table 2. wrt_reg bit definitions and functions adress parameters msb0 lsb0 mosi bits[ b3 : b2] mosi bits [b1 : b0 ] mosi bits [b3 : b0 ] b7 b6 b5 b4 b3 b2 b1 b0 crd_clk crd_vcc 0 s1 a/b crd_rst 0 0 0 0 low 0 0 s1 a/b crd_rst 0 1 0 1 1/1 1.8v 0 s1 a/b crd_rst 1 0 1 0 1/2 3.0v 0 s1 a/b crd_rst 1 1 1 1 1/4 5.0v 1 1 a/b crd_rst crd_clk crd_i/o crd_c4 crd_c8 synchronous 1 0 1 x x 0 0 0 no 1 0 1 x x 0 0 1 nc 1 0 1 x x 0 1 0 special 1 0 1 x x 0 1 1 normal 1 0 1 x x 1 0 0 slo_slp 1 0 1 x x 1 0 1 fst_slp 10. card a: b5 = 0, card b: b5 = 1, device # 1: b6 = 0 ? pin s1 connected to gnd, device # 2: b6 = 1 ? pin s1 connected to v dd 11. address 101 and bits [b0:b4] not documented in the table are not applicable with no effect on the device programming and con figuration. the sign x in the table means that either 1 or 0 can be used. read register read_reg the read_reg register (1 byte) contains the data read from the card interface. the selected chip register is transferred to the miso pin during the mosi sequence (cs = low). table 3 gives a definition of the bits. depending upon the programmed spi_mode, the content of read_reg is transferred on the miso line either on the positive going (spi_mode = special) or upon the negative going slope (spi_mode = normal) of the clk_spi signal. the external microcontroller shall discard the three high bits since they carry no valid data. table 3. mosi and miso bits identifications and functions mosi b7 b6 b5 b4 b3 b2 b1 b0 operating mode . 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 crd_rst crd_rst crd_rst crd_rst crd_rst crd_rst crd_clk crd_clk crd_clk crd_clk crd_clk crd_clk crd_clk crd_clk crd_clk crd_clk crd_i/o crd_i/o crd_vcc crd_vcc crd_vcc crd_vcc crd_c4 crd_c4 crd_vcc crd_vcc crd_vcc crd_vcc crd_c8 crd_c8 async. card a, program chip async. card b, program chip async. card a, program chip async. card b, program chip sync. card a, sets card bits sync. card b, sets card bits miso z z z card detect crd_i/o crd_c4 crd_c8 pwr monitor read back data when a command is sent to a for example by selecting the address %000 the corresponding miso byte has the state of the interface a (card detecta, b4; i/oa, b3; c4a, b2; c8a, b1; crd_vcca ok, b0) ? that is the state loaded while sending the previous mosi command a or b. when a command is sent to b for example by selecting the address %001 the corresponding miso byte has the state of the interface b (card detectb, b4; i/ob, b3; c4b, b2; c8b, b1; crd_vccb ok, b0) ? that is the state loaded while sending the previous mosi command a or b. card a or card b selection ? multiplexed mode the bit b5 in the mosi sequence enables the selection of the NCN6804?s interface a or b (see table 2) to the exception of the addresses {100} decoded with no effect on the device and {101} used to program device general configuration. then: when b5 = low the interface a is selected and the transaction or communication takes place through this interface according to table 2. the programming applies to card a only. when b5 = high the interface b is selected and the transaction or communication takes place through this interface according to table 1. the programming applies to card b only. crd_vcca and crd_clka can be maintained applied to card a when the device is switched from a to b. this mode of operating is of course the same when the device is switched from b to a: crd_vccb and crd_clkb can be maintained applied to card b. the device configuration is programmed using the address {101} similarly to the ncn6001. in that case, the programming is applied simultaneously to card a and card b.
NCN6804 http://onsemi.com 13 asynchronous mode in this mode, the s1 pin is used to define the physical address (by comparison with the bit b6 (mosi)) of the interfaces when a bank of up to 2 NCN6804 (total of 4 interfaces) shares the same digital bus. synchronous mode in this mode, the clk_in clock input and the i/o input/output are not used. the clock and the data are provided and transferred through the spi bus using mosi and miso as shown table 2. when this operating mode is used and if two NCN6804 devices want to be implemented, it is no longer possible to share the same cs signal. consequently in this particular case and when the devices operate in a multiple interface mode a dedicated cs signal must be provided to each NCN6804 device. since bits [b4 ? b0] of the mosi register contain the smart card data, programming the crd_vcc output voltage shall be done by sending a previous mosi message according to table 2 using the address [b7, b6, b5] = [0, s1, a/b]. for example if a synchronous card is used, prior to make a transaction with it, it will be powered ? up for example at 5 v by sending the command %0000001 1 (address s1 = 0 and card a selected). the crd_rsta/b pin reflects the content of the mosi wrt_reg [b4] during the chip programming sequence. since this bit shall be low to address the internal register of the chip, care must be observed as this signal will be immediately transferred tot he crd_rsta/b pin. startup default conditions at startup, when power supply is turned on, the internal por (power on reset) circuit sets the chip in the default conditions as defined below (table 4). table 4. startup default conditions crd_deta/b normally open crd_vcca/b off crd_clka/b tr & tf = slow crd_clka/b low protocol special mode i/o pull ? up resistor connected int high card detection the card is detected by the external switch connected to pin 23 for card b and pin 2 for card a. the internal circuit provides a positive bias of this pin and the polarity of the insertion/extraction is programmable by the mosi protocol as depicted table 2. the bias current is 1 a typical and cares must be observed to avoid leakage to ground from this pin to maintain the logic function. in particular, using a low impedance probe (< 1 m ) might lead to uncontrolled operation during the debug. depending upon the programmed condition, the card can be detected either by a normally open (default condition) or a normally close switch (see table 2). on the other hand, the meaning of the feedback message contained in the miso register bit b4 depends upon the spi mode of operation as defined here below: spi normal mode: the miso bit b4 is high when a card is inserted, whatever be the polarity of the card detect switch. spi special mode: the miso bit b4 copies the logic state of the card detect switch as depicted here below, whatever be the polarity of the switch used to handle the detection: crd_deta/b = low ? miso / b4 = low crd_deta/b = high ? miso / b4 = high crd_vcc operation the dual NCN6804 interface has 2 built ? in dc/dc converters. each of them can be programmed to provide one of the three possible values, 1.8 v, 3.0 v or 5.0 v, assuming the input voltage vddpa or b is within the 2.7 v to 5.5 v range. card a and card b can be independently powered ? up or down. consequently if necessary for example the device can be switched from card a to card b while the card a power voltage is maintained (this is of course true from a to b or from b to a). crd_vcca & b are voltage regulated and protected against overload by a current overload detection system. the dc/dc converter operates as a buck/boost converter. the power conversion mode is automatically switched to handle one of these two modes of operation depending upon the voltage difference between the crd_vcca or b and vddpa or b respectively. the crd_vcca or b output current range is given table 5; these values comply with the smart card iso7816 standard and related. table 5. crd_vcca or b output voltage definition crd_vcca or b current range per card cumulated cur- rent range (card a and card b) 1.8 v 0 to 35+ ma 0 to 70 + ma 3.0 v 0 to 60+ ma 0 to 120 + ma 5.0 v 0 to 65+ ma 0 to 130 + ma whatever is the crd_vcca or b output voltage, a built ? in comparator makes sure the voltage is within the iso7816 ? 3/emv specifications. if the voltage is no longer within the minimum/maximum values, the dc/dc is switched off, the powerdown sequence takes place and an interrupt is presented at the int pin 24. powerup sequence the powerup sequence makes sure all the card related signals are low during the crd_vcca/b positive going slope. these lines are validated when crd_vcca/b is above the minimum voltage specified by the emv standard depending upon the programmed crd_vcc a or b value (see crd_vcc power supply section on page no tag).
NCN6804 http://onsemi.com 14 figure 3. startup crd_vcc sequence cs crd_vcc crd_io crd_clk crd_c4 crd_c8 crd_rst atr figure 4. measured typical startup crd_vcc sequence at powerup, the crd_vcca/b turn ? on time depends upon the current capability of the dc/dc converter associated with the external inductor l and the reservoir capacitor connected across crd_vcca or b and ground. during this sequence, the average input current is 300 ma typical (see figure 4), assuming the system is fully loaded during the start up. even if enabled by the built ? in sequencer the activation sequence is under the control and responsibility of the application software. on the other hand, at turn off, the crd_vcca/b fall time depends upon the external reservoir capacitor and the peak current absorbed by the internal nmos transistor built across crd_vcca/b and ground. these behaviors are depicted figure 5. since these parameters have finite values, depending upon the external constraints, the designer must take care of these limits if the t on or t off provided by the datasheet does not meet his requirements. figure 5. crd_vcc typical turn ? on and turn ? off times
NCN6804 http://onsemi.com 15 figure 6. figure 7: start up sequence with atr. powerdown sequence the NCN6804 provides an automatic power down sequence, according to the iso7816 ? 3 specifications. when a power down sequence is enabled the communication session terminates immediately. the sequence is launched under a micro ? controller decision, when the card is extracted, or when the crd_vcca/b voltage is overloaded as described by the iso/cei 7816 ? 3 sequence depicted here after (see figure 8): crd_ rst is forced to low crd_clk is forced to low, unless it is already in this state crd_c4 & crd_c8 are forced to low then crd_io is forced to low finally the crd_vcc supply is powered down figure 7. typical power down sequence (typical delay between each signal is 500 ns) crd_rst crd_vcc crd_i/o crd_c4 crd_clk since the internal digital filter is activated for any card insertion or extraction, the physical power ? down sequence will be activated 50 s (typical) after the card has been extracted. of course, such a delay does not exist when the micro ? controller intentionally launches the power down. data i/o level shifter the level shifter accommodates the voltage difference that might exist between the micro ? controller and the smart card. a pulsed accelerator circuit provides the fast positive going transient according to the iso7816 ? 3 specifications. the basic i/o level shifter is depicted figure 8.
NCN6804 http://onsemi.com 16 logic and level shift q4 q3 q2 r2 18 k q5 gnd crd_vcc 13 crd_io 20 crd_vcc card enable por seq 1 200 ns 200 ns q1 r1 18 k en_rpu 6 i/o 1 v cc 9 v cc pmos u1 vcc q5 gnd sync mosi/b3 mosi/b2 from mosi decoding figure 8. basic i/o internal circuit the transaction is valid when the chip select pin is low, the i/o signal being open drain or totem pole on either sides. since the device can operate either in a single or a multiple card system provisions have been made to avoid crd_ioa or b current overload. depending upon the selected mode of operation (async. or sync), the card i/o line is respectively connected to either i/o pin 25, or to the mosi register byte bit 2. on the other hand, the logic level present at the card i/o is feedback to the micro ? controller via the miso register bit 3. the logic levels present at pin 31 (en_rpu) controls the connection of the internal pullup as depicted table 6. table 6. i/o pullup resistor table en_rpu i/o pullup resistor device operation low open, 18 k disconnected applicable in the multidevice mode case high internal 18 k pullup active single device mode note: 18 k typical value figure 9. typical i/o rise & fall time (crd_ioa or b/ c out > 30 pf and open ? drain) interrupt when the system is powered up, the int pin is set to high upon power on reset (por) signal. the interrupt pin 24 is forced low when a card is inserted or extracted in either of the external ports, or when a fault is developed across the crd_vcc output voltage a or b. this signal is neither combined with cs signal, nor with the chip address. the int signal is clear to high upon one of the conditions table 7.
NCN6804 http://onsemi.com 17 table 7. interrupt reset logic table interrupt source (int set to low) cs interrupt clearance (int reset to high) crd_vcca/b / {b1, b0} pro- gramming chip address card insertion l {0,1}, {1,0} or {11} {b7:b5} = 0xx card extraction l {0,0} {b7:b5} = 0xx over load l {0,0} {b7:b5} = 0xx in order to know the source of the interrupt (card a or card b), the software has to poll the miso register by sending a mosi a command (address {b7, b6, b5} = {0, x, 0}) followed by a mosi b command (address {b7, b6, b5} = {0, x, 1}) (or conversely). the corresponding miso content provides the previous state of the interface a or b that is the information related to the cause of the interrupt. for each case the miso status obtained will be compared with the miso state prior to the interrupt. when 2 NCN6804 devices share the same digital spi bus, it is up to the software to poll the devices using again the miso register to identify the reason of the interrupt. figure 10. basic interrupt function cs int crd_det mosi_b0 mosi_b1 crd_vcc > 0 v over load crd_vcc t0 t2 t10 t3 t4 t9 t6 t8 t5 t1 t11 t12 t7 {b1,b0} = {0,1}, {1,0} or {1,1} {b1,b0} = {0,0} crd_vcc > 0 v table 8. interrupt function operation t0 a card has been inserted into the reader and detected by the crd_det signal. the ncn6001 pulls down the interrupt line. t1 the c sets the cs signal to low, the chip is now active, assuming the right address has been placed by the mosi register. t2 the c acknowledges the interrupt and resets the int to high by the mosi [b1 : b0 ] logic state: crd_vcc is programmed higher than zero volt. t3 the card has been extracted from the reader, crd_det goes low and an interrupt is set (int = l). on the other hand, the pwr_down sequence is activated by the ncn6001. t4 the interrupt pin is clear by the zero volt programmed to the interface. t5 same as t0 t6 the c start the dc/dc converter, the interrupt is cleared (same as t2) t7 an overload has been detected by the chip : the crd_vcc voltage is zero, the int goes low. t8 the card is extracted from the reader, crd_det goes low and an interrupt is set (int = l). t9 the card is re ? inserted before the interrupt is acknowledged by the c: the int pin stays low. t10 the c acknowledges the interrupt and reset the int to high by the mosi [b1 : b0 ] logic state: crd_vcc is programmed higher than zero volt. t11 the chip select signal goes high, all the related ncn6001 interface(s) are deactivated and no further programming or transaction can take place.
NCN6804 http://onsemi.com 18 spi port the product communicates to the external micro controller by means of a serial link using a synchronous port interface protocol, the clk_spi being low or high during the idle state. the NCN6804 is not intended to operate as a master controller , but executes commands coming from the mpu. the clk_spi, cs and mosi signals are under the microcontroller?s responsibility. the miso signal is generated by the NCN6804, using the clk_spi and cs lines to synchronize the bits carried out by the data byte. the basic timings are given in figure 11 and 12. the system runs with two inter nal registers associated with mosi and miso data: wrt_reg is a write only register dedicated to the mosi data. read_reg is a read only register dedicated to the miso data. figure 11. basic spi timings and protocol mpu asserts chip select NCN6804 reads bit mpu reads bit rst_counter mosi spi_clk cs miso tclr mpu enables clock mpu sends bit ncn6001 sends bit from read_reg when the cs line is high, no data can be written or read on the spi port. the two data lines become active when cs = low, the internal shift register is cleared and the communication is synchronized by the negative going edge of the cs signal. the data presents on the mosi line are considered valid on the negative going edge of the clk_spi clock and is transferred to the shift register on the next positive edge of the same clk_spi clock. to accommodate the simultaneous miso transmit, an internal logic identifies the chip address on the fly (reading and decoding the three first bits) and validate the right data present on the line. consequently, the data format is msb first to read the first three signal as bits b5, b6 and b7. the chip address is decoded from this logic value and validates the chip according to the s1 pin conditions: see figure 12. figure 12. chip address decoding protocol and miso sequence mpu asserts chip set miso line = high impedance address decode mosi spi_clk cs miso mpu enables clock b7 b6 b5 b4 b3 b2 b1 b0 lsb command and control chip address the chip address is decoded on the third clock pulse. the miso signal is activated and data transferred msb when the bit transfer is completed, the content of the internal shift register is latched on the positive going edge of the cs signal and the NCN6804 related functions are updated accordingly.
NCN6804 http://onsemi.com 19 figure 13. basic multi command spi bytes select chip from synchronous bank chip ny chip nx tdclk special mode: miso is synchronized with the spi_clk positive going slope normal mode: miso is synchronized with the spi_clk negative going slope miso line = high impedance miso line = high impedance b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 spi_clk cs mosi set_rst set_clk set_vcc address decode chip address command and control msb msb lsb lsb miso special mode miso normal mode mpu enables clock since the 2 dual circuits present in the asynchronous bank have an individual physical address, the system can control 2 of these chips by sending the data content within the same cs frame as depicted in figure 13. the bits are decoded on the fly and the related sub blocks are updated accordingly. according to the spi general specification, no code or ac tivity will be transferred to any chip when the cs is high. when 2 spi dual bytes are sequentially transferred on the mosi line, the clk_spi sequence must be separated by at least one half positive period of this clock (see td clk parameter). the oscillograms given figures 14 and 15 illustrate the spi communication protocol. figure 14. programming sequence special mode standard mode figure 15. miso read out sequences
NCN6804 http://onsemi.com 20 dc/dc operation the power conversion is based on a full bridge structure able to handle either step up or step down power supply (see figure 16). the opera tion is fully automatic and, beside the output voltage programming, does not need any further adjustment. figure 16. basic dc/dc converter g_q4 g_q2 g_q7 g_hiz g_q3 g_q1 cmd_stop cmd_5.0v cmd_3.0v cmd_1.8v gnd gnd gnd 22 h l1 gnd pwr_gnd 10 f c2 q2 q7 q4 q6 q5 q3 q1 10 f mixed logic/analog block v cc crd_vcc c1 in order to achieve the 250 s maximum time to discharge crd_vcca or b to 400 mv called by the emv specifications, an active pull down nmos is provided to discharge the external crd_vcca/b reservoir capacitor. this timing is guaranteed for a 10 f maximum load reservoir capacitor value (see figure 4). the system operates with a two cycle concept (all comments are referenced to figures 16 and 17): 1. cycle 1 q1 and q4 are switched on and the inductor l1 is charged by the energy supplied by the external battery. during this phase, the pair q2/q3 and the pair q5/q6 are switched off. the current flowing the two mosfet q1 and q4 is internally monitored and will be switched off when the i peak value (depending upon the programmed output voltage value) is reached. at this point, cycle 1 is completed and cycle 2 takes place. the on time is a function of the battery voltage and the value of the inductor network (l and zr) connected across pins 10/11. a 4 _ s timeout structure ensures the system does run in a continuous cycle 1 loop. 2. cycle 2 q2 and q3 are switched on and the energy stored into the inductor l1 is dumped into the external load through q2. during this phase, the pair q1/q4 and the pair q5/q6 are switched off. the current flow period is constant (900 ns typical) and cycle 1 repeats after this time if the crd_vcc voltage is below the specified value. when the output voltage reaches the specified value (1.8 v, 3.0 v or 5.0 v), q2 and q3 are switched off immediately to avoid over voltage on the output load. in the meantime, the two extra nmos q5 and q6 are switched on to fully discharge any current stored into the inductor, avoiding ringing and voltage spikes over the system. figure 17 illustrates the theoretical waveforms present in the dc/dc converter.
NCN6804 http://onsemi.com 21 crd_vcc charged figure 17. theoretical dc/dc operating waveforms i peak crd_vcc il q5/q6 q2/q3 q1/q4 v ripple crd_vcc voltage regulated t off t on charge crd_vcc next crd_vcc charge (time is not to scale) when the crd_vcc is programmed to zero volt, or when the card is extracted from the socket, the active pull down q7 rapidly discharges the output reservoir capacitor, making sure the output voltage is below 0.4 v when the card slides across the iso contacts. based on the experiments carried out during the NCN6804 characterization, the best comprise, at time of printing this document, is to use two 4.7 f/10 v/ ceramic/x7r capacitors in parallel to achieve the crd_vcc filtering. the esr will not extend 50 m over the temperature range and the combination of standard parts provides an acceptable ?20% to +20% tolerance, together with a low cost. obviously, the capacitor must be smd type to achieve the extremely low esr and esl necessary for this application. figure 18 illustrates the crd_vcc ripple observed in the NCN6804 demoboard depending upon the type of capacitor used to filter the output voltage. figure 18. typical crd_vcc ripple voltage (5 v, 3 v and 1.8 v) ? cms capacitor c out = 10 f, 1210, x7r, 16 v during the operation, the inductor is subject to high peak current as depicted figure 19 and the magnetic core must sustain this level of current without damage. in particular, the ferrite material shall not be saturated to avoid uncontrolled current spike during the charge up cycle. moreover, since the dc/dc efficiency depends upon the losses developed into the active and passive components, selecting a low esr inductor is preferred to reduce these losses to a minimum. figure 19. typical inductor current according to the iso7816 ? 3 and emv specifications, it is recommended the interface limits the crd_vcc output current to 200 ma maximum, under short circuit conditions. the NCN6804 supports such a parameter, the limit being depending upon the input and output voltages as depicted figure 20.
NCN6804 http://onsemi.com 22 figure 20. output current limit: output voltage crd_vcc (1.8 v, 3.0 v, 5.0 v) crd_vcc (v) 6 5 4 3 2 1 0 0 50 100 150 200 icrd_vcc (ma) 3.0 v 5.0 v 1.8 v on the other hand, the circuit is designed to make sure no over current exist over the full temperature range. as a matter of fact, the output current limit is reduced when the temperature increases. dc ? to ? dc converter external passif component selection to be functional the NCN6804?s dc ? to ? dc converters need external passive components carefully selected. the performance and specification compliance of the NCN6804 are guaranteed by the dc/dc converter input capacitor, by the inductor and the reservoir capacitor characteristics. the input capacitor enables the decoupling and filtering of the input power supply voltage (v bat ) and its value has to be high enough to guarantee a good operating stability of the converter. a cms very low esr capacitor shall be preferably used with a minimum value of 4.7 f recommended, 10 f will be preferred ? this will strongly depend on how the capacitance value varies with the dc voltage applied across the capacitor terminals (see figure 21). the inductor shall be sized to handle the 500 ma peak current (min. i sat ) flowing during the dc/dc operation and will have to offer a low parasitic series resistor in order to maintain a good efficiency (ex: coilcraft, 1008ps ? 223klc). the reservoir output capacitor shall be also ceramic surface mount capacitor with very low esr (lower than 50 m ) and good temperature characteristics (x7r type). 10 f is the recommended capacitance value under 5 v, 3 v and 1.8 v to get the better operating performance with a low crd_vcc ripple level. the cms capacitor shall be selected accordingly that is with a capacitance value of 10 f covering the range 1.8 v ? 5 v (see figure 21). this value constitutes a good compromise for a good crd_vcc ripple and crd_vcc turn ? on and turn ? off times. figure 21. variation of the capacitance value of different cms capacitors with the dc voltage applied across its terminals capacitance (pf) dc bias voltage (v) 10 f, x7r, 1210, 16 v 10 f, x5r, 1206, 16 v 10 f, x7r, 0805, 10 v 10 f, y5v, 0805, 16 v 1.2e+7 1e+7 8e+6 6e+6 4e+6 2e+6 0 1.25 2.5 3.75 5 6.25 smart card clock divider the main purpose of the built in clock generator is three folds: 1. adapts the voltage level shifter to cope with the different voltages that might exist between the mpu and the smart card 2. provides a frequency division to adapt the smart card operating frequency from the external clock source. 3. controls the clock state according to the smart card specification. in addition, the NCN6804 adjusts the signal coming from the c to get the duty cycle window as defined by the iso7816 ? 3 specification. the byte content of the spi port b2 and b3 fulfills the programming functions when cs is low as depicted figures 22 and 23. the clock input stage (clock_in) can handle a 40 mhz frequency maximum signal, the divider being capable to provide a 1:4 ratio. of course, the ratio must be defined by the engineer to cope with the smart card considered in a given application and, in any case, the output clock [crd_clka/b] shall be limited to 20 mhz maximum. in order to minimize the di/dt and dv/dv developed in the crd_clka/b line, the output stage includes a special function to adapt the slope of the clock signal for different applications. this function is programmed by the mosi register (see t able 2) whatever be the clock division.
NCN6804 http://onsemi.com 23 crd_clk clock_in clock : 2 clock : 4 b2 b3 clock is updated upo n these bits progra m internal clock programming is activated by the b2 + b3 logic state clock = 1:1 rati o clock : 1 figure 22. typical clock divider synchronization clock: 4 rising edg e clock divider in order to avoid any duty cycle out of the smart card iso7816 ? 3 specification, the divider is synchronized by the last flip flop, thus yielding a constant 50% duty cycle, whatever be the divider ratio (see figure 22). consequently, the output crd_clka/b frequency division can be delayed by four clock_in pulses and the micro controller software must take this delay into account prior to launch a new data transaction. on the other hand, the output signal duty cycle cannot be guaranteed 50% if the division ratio is 1 and if the input duty cycle signal is not within the 46% ? 56% range. the input signals clk_in and mosi/b3 are automatically routed to the level shifter and control block according to the mode of operation. figure 23. basic clock divider and level shifter b1 b0 b3 b2 clk_in vcc crd_clk crd_vcc level shifter and control programming crd_clk slope note: bits [b0...b3] come from spi data programming crd_clk division sync async sync u1 digital_mux out sel a b the input clock can be divided by 1/1, ? , or ? ,, depending upon the specific application, prior to be applied to the smart card driver. on the other hand, the positive and negative going slopes of the output clock (crd_clka/b) can be programmed to optimize the operation of the chip: see table 2. the slope of the output clock can be programmed on the fly, independently of either the crd_vcca/b voltage or the operating frequency, but cares must be observed as the crd_rsta/b will reflect the logic state present at mosi / b4 register. table 9. output clock rise and fall time selection b0 b1 crd_clk division ratio crd_clk slo_slp crd_clk fst_slp 0 0 ? output clock = low output clock = low 0 1 1 10 ns (typ.) 2 ns (typ.) 1 0 1/2 10 ns (typ.) 2 ns (typ.) 1 1 1/4 10 ns (typ.) 2 ns (typ.)
NCN6804 http://onsemi.com 24 input schmitt triggers all the logic input pins have built in schmitt trigger circuits to protect the NCN6804 against uncontrolled operation. the typical dynamic characteristics of the related pins are depicted figure 24. figure 24. typical schmitt trigger characteristic output input v bat on off 0.3 vbat 0.7 vbat vba t security features in order to protect both the interface and the external smart card, the NCN6804 provides security features to prevent irreversible failures as described here after. pin current limitation : in the case of a short circuit to ground, the current forced by the device is limited to 15 ma for any pins, except crd_clk a/b pin which is limited to 70 ma. no feedback is provided to the external mpu. dc/dc operation : the internal circuit continuously senses the crd_vcca/b voltage; in the case of either over or undervoltage situation it updates the read_reg register accordingly and forces the int pin to low. this register can be readout by the mpu. battery voltage : both the over and undervoltage are detected by the NCN6804, the read_reg register being updated accordingly. the external mpu can read the register through the miso pin to take whatever is appropriate to cope with the situation. esd protection the NCN6804 dual smart card interface features an hbm esd voltage protection (jedec standard) in excess of 8 kv for all the crd pins (crd_ioa/b, crd_clka/b, crd_rsta/b, crd_v cca/b and gnd). crd_deta/b have a protection of 4 kv hbm. all the other pins (microcontroller side) sustain at least 2 kv. these values are guaranteed for the device in its full integrity without considering the external capacitors added to the circuit for a proper operating. consequently in the operating conditions it is able to sustain much more than 8 kv on its crd pins making it perfectly protected against electrostatic discharge well over the hbm esd voltages required by the iso7816 standard. printed circuit board layout careful layout routing will be applied to achieve a good and efficient operating of the device in its application environment and to fully exploit its performance. the bypass capacitors have to be connected as close as possible to the device pins (crd_vcca/b, vdd or vddpa/b) in order to reduce as much as possible parasitic behaviors (ripple and noise). it is recommended to use ceramic capacitors (very low esr). the exposed pad of the qfn ? 32 package will be connected to the ground. a relatively large ground plane is recommended. figure 25 shows a example of pcb device implementation and component routing. figure 25. example of pcb device implementation v dd decoupling capacitor 100 nf la 22 h vddpa/b decoupling capacitor 10 f lb 22 h crd_vcca reservoir capacitor 10 f, 1210, x7r, 16 v
NCN6804 http://onsemi.com 25 package dimensions qfn32, 5x5, 0.5p mn suffix case 488am ? 01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actu al performance may vary over time. all operat- ing parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc do es not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for s urgical implant into the body, or other applications inten- ded to support or sustain life, or for any other application in which the failure of the scillc product could create a situatio n where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any c laim of personal injury or death associ- ated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or man ufacture of the part. scillc is an equal opportunity/af- firmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. NCN6804/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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