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this is information on a product in full production. february 2014 docid023765 rev 4 1/37 m24m01-a125 automotive 1-mbit serial i2c bus eeprom with 1 mhz clock datasheet - production data features ? compatible with all i 2 c bus modes ?1 mhz ?400 khz ?100 khz ? memory array ? 1 mbit (128 kbytes) of eeprom ? page size: 256 bytes ? additional write lockable page (identification page) ? extended temperature and voltage ranges ? -40 c to 125 c; 2.5 v to 5.5 v ? schmitt trigger inputs for noise filtering. ? short write cycle time ? byte write within 4 ms ? page write within 4 ms ? write cycle endurance ? 4 million write cycles at 25 c ? 1.2 million write cycles at 85 c ? 600 k write cycles at 125 c ? data retention ? 50 years at 125 c ? 100 years at 25 c ? esd protection (human body model) ? 4000 v ? packages ? rohs compliant and halogen-free (ecopack ? 2) tssop8 (dw) so8 (mn) 169 mil width 150 mil width www.st.com
contents m24m01-a125 2/37 docid023765 rev 4 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 chip enable (e2, e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 write control (wc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 v ss (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.4 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.5 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.3 write identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.4 lock identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.5 minimizing write delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 18 4.2 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.1 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.2 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.4 read identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.5 read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.6 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
docid023765 rev 4 3/37 m24m01-a125 contents 3 5 application design recommendati ons . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.3 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 cycling with error correction code (ecc) . . . . . . . . . . . . . . . . . . . . . . . . 24 6 delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
list of tables m24m01-a125 4/37 docid023765 rev 4 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. address significant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. device identification code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7. operating conditions (voltage range w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 10. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11. 400 khz ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12. 1 mhz ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13. tssop8 ? 8-lead thin shrink small outline, pa ckage mechanical data. . . . . . . . . . . . . . . . 33 table 14. so8n ? 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 34 table 15. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 16. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
docid023765 rev 4 5/37 m24m01-a125 list of figures 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. write mode sequences with wc = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. write mode sequences with wc = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 figure 8. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 10. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 11. maximum r bus value versus bus parasitic capacitance c bus ) for an i 2 c bus at maximum frequency f c = 1mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 12. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 13. tssop8 ? 8-lead thin shrink small outline, pa ckage outline . . . . . . . . . . . . . . . . . . . . . . . 33 figure 14. so8n ? 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 34
description m24m01-a125 6/37 docid023765 rev 4 1 description the m24m01-a125 is a 1-mbit serial eeprom automotive grade device operating up to 125 c. the m24m01-a125 is compliant with the ve ry high level of reliability defined by the automotive standard aec-q100 grade 1. the device is accessed by a simple serial i 2 c compatible interfac e running up to 1 mhz. the memory array is based on advanced true eeprom technology (elect rically erasable programmable memory). the m24m01-a125 is a byte-alterable memory (128 k 8 bits) organized as 512 pages of 256 bytes in which the data integrity is significantly improved with an embedded error correction code logic. the m24m01-a125 offers an additional identification page (256 bytes) in which the st device identification can be read. this page can also be used to st ore sensitive application parameters which can be later permanently locked in read-only mode. figure 1. logic diagram -36 7# #ontrollogic (ighvoltage generator )/shiftregister !ddressregister andcounter $ata register page 8decoder 9decoder )dentificationpage % % 3#, 3$!
docid023765 rev 4 7/37 m24m01-a125 description 36 figure 2. 8-pin package connections 1. du: don't use (if connected, must be connected to vss) 2. see section 9: package mechanical data for package dimensions, and how to identify pin 1. table 1. signal names signal name function direction e2, e1 chip enable input sda serial data i/o scl serial clock input wc write control input v cc supply voltage - v ss ground - -36 3$! 6 33 3#, 7# % $5 6 ## % --
signal description m24m01-a125 8/37 docid023765 rev 4 2 signal description 2.1 serial clock (scl) the signal applied on this input is used to stro be the data available on sda(in) and to output the data on sda(out). 2.2 serial data (sda) sda is an input/output used to transfer data in or out of the device. sda(out) is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull up resistor must be connected between sda and v cc ( figure 10 indicates how to calculate the value of the pull-up resistor). 2.3 chip enable (e2, e1) (e2,e1) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2) of the 7-bit device select code (see table 2 ). these inputs must be tied to v cc or v ss , as shown in figure 3 . when not connected (left floating), these inputs are read as low (0). figure 3. device select code 2.4 write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write operations are disa bled to the entire memory array when write control ( wc ) is driven high. write operations are enabled when write control ( wc ) is either driven low or left floating. when write control ( wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. !i 6 ## -xxx 6 33 % i 6 ## -xxx 6 33 % i
docid023765 rev 4 9/37 m24m01-a125 signal description 36 2.5 v ss (ground) v ss is the reference for the v cc supply voltage. 2.6 supply voltage (v cc ) v cc is the supply voltage pin.
device operation m24m01-a125 10/37 docid023765 rev 4 3 device operation the device supports the i 2 c protocol (see figure 4 ). the i 2 c bus is controlled by the bus master and the device is always a slave in all communications. the device (bus master or a slave) that sends data on to the bus is defined as a transmitter; the device (bus master or a slave) is defined as a receiver when reading the data. figure 4. i 2 c bus protocol 3#, 3$! 3#, 3$! 3$! 34!24 #ondition 3$! )nput 3$! #hange !)" 34/0 #ondition -3" !#+ 34!24 #ondition 3#, -3" !#+ 34/0 #ondition
docid023765 rev 4 11/37 m24m01-a125 device operation 36 3.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must prece de any data transfer instruction. the device continuously monitors (except during a writ e cycle) serial data (sda) and serial clock (scl) for a start condition. 3.2 stop condition stop is identified by a rising edge of serial da ta (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a stop condition at the end of a write instruction triggers the internal write cycle. 3.3 data input during data input, the device samples serial da ta (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low. 3.4 acknowledge bit (ack) the acknowledge bit is used to indicate a succ essful byte transfer. the bus transmitter, whether it be bus master or slave device, releas es serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits.
device operation m24m01-a125 12/37 docid023765 rev 4 3.5 device addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. follo wing this, the bus master sends the device select code, as shown in table 2 . the device select code consists of a 4-bit device type identifier and a 2-bit chip enable address (e2, e1). a device select code handling any value other than 1010b (to select the memory) or 1011b (to select the identificati on page) is not acknowledged by the memory device. up to four memory devices can be connected on a single i 2 c bus. each one is given a unique 2-bit code on the chip enable (e2, e1) inputs. when the device select code is received, the memory device only responds if the chip enable address is the same as the value decoded on the e2, e1 inputs. the 8 th bit is the read/ write bit (r w ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding memory device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the memory device does not match the device select code, it deselects itself from th e bus, and goes into standby mode. once the memory device has acknowledged the device select code ( table 2 ), the memory device waits for the master to send two addr ess bytes (most significa nt address byte sent first, followed by the least significant address byte ( table 3 ). the memory device responds to each address byte with an acknowledge bit. note: a: significant address bit. x: bit is don?t care. table 2. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address (2) 2. e2 and e1 bits are compared with the value read on input pins e2,e1. address bit rw when accessing the memory b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 e2 e1 a16 rw when accessing the identification page 1 0 1 1 e2 e1 x (3) 3. x = don?t care. rw
docid023765 rev 4 13/37 m24m01-a125 device operation 36 table 3. address significant bits memory (1) (2) (device type identifier = 1010b) identification page (device type identifier = 1011b) random address read write read identification page write identification page lock identification page read lock status device select bit 1 b16 a16 a16 x x x x upper address byte b15 a15 a15 x x x x b14 a14 a14 x x x x b13 a13 a13 x x x x b12 a12 a12 x x x x b11a11a11xxxx b1 0 a1 0 a1 0 x010 b9 a9 a9 x x x x b8 a8 a8 x x x x lower address byte b7 a7 a7 a7 a7 x x b6 a6 a6 a6 a6 x x b5 a5 a5 a5 a5 x x b4 a4 a4 a4 a4 x x b3 a3 a3 a3 a3 x x b2 a2 a2 a2 a2 x x b1 a1 a1 a1 a1 x x b0 a 0 a 0 a 0 a 0 xx 1. a: significant address bit. 2. x: bit is don?t care.
device operation m24m01-a125 14/37 docid023765 rev 4 3.6 identification page the m24m01-a125 offers an id entification page (256 bytes) in addition to the 1 mb memory. the identification page contains two fields: ? device identification code: the first three bytes are programmed by stmicroelectronics with the device identification code, as shown in table 4 . ? application parameters: the bytes after the de vice identification code are available for application specific data. note: if the end application does not need to read the device identification code, this field can be overwritten and used to store application-spec ific data. once the app lication-specific data are written in the identification page, the whol e identification page should be permanently locked in read-only mode. the instructions read, write and lock identification page are detailed in section 4: instructions . table 4. device identification code address in identification page content value 00h st manufacturer code 20h 01h i 2 c family code e0h 02h memory density code 11h (1024 kbit)
docid023765 rev 4 15/37 m24m01-a125 instructions 36 4 instructions 4.1 write operations for a write operation, the bus master sends a start condition followed by a device select code with the r/w bit reset to 0. the device acknowledges this, as shown in figure 5 , and waits for the master to send two address byte s (most significant address byte sent first, followed by the least significant address byte ( table 3 ). the device responds to each address byte with an acknowledge bit, and then waits for the data byte. the 128 kbytes (1 mb) are addressed with 17 ad dress bits, the 16 lower address bits being defined by the two address bytes and the most significant address bit (a16) being included in the device select code (see table 2 ). when the bus master generates a stop condit ion immediately after a data byte ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle t w is then triggered. a stop condition at any ot her time slot does not trigger the internal write cycle. during the internal write cycle, serial data (s da) is disabled internally, and the device does not respond to any requests. after the successful completion of an internal write cycle (t w ), the device internal address counter is automatically increment ed to point to the next byte after the last modified byte. if the write control input (wc) is driven high, the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in figure 6 .
instructions m24m01-a125 16/37 docid023765 rev 4 4.1.1 byte write after the device select code and the address byte s, the bus master send s one data byte. if the addressed location is write-protected, by write control ( wc ) being driven high, the device replies with noack, and the location is not modified (see figure 6 ). if, instead, the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 5 . figure 5. write mode sequences with wc = 0 (data write enabled) 3top 3tart "yte7rite $evsel "yteaddr "yteaddr $atain 7# 3tart 0age7rite $evsel "yteaddr "yteaddr $atain 7# $atain !)d 0age7ritecontgd 7#contgd 3top $atain. !#+ 27 !#+ !#+ !#+ !#+ !#+ !#+ !#+ 27 !#+ !#+
docid023765 rev 4 17/37 m24m01-a125 instructions 36 4.1.2 page write the page write mode allows up to n (a) bytes to be written in a si ngle write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, a16/ a8, are the same. if more bytes ar e sent than will fit up to the end of the page, a condition known as ?roll-over? occurs. in case of roll-over, the first bytes of the page are overwritten. the bus master sends from 1 to n (a) bytes of data, each of which is acknowledged by the device if write control ( wc ) is low. if write control ( wc ) is high, the contents of the addressed memory location are not modified, and each data byte received by the device is not acknowledged, as shown in figure 6 . after each byte is transfe rred, the internal byte address counter is incremented. the transfer is terminated by the bus master generating a stop condition. figure 6. write mode sequences with wc = 1 (data write inhibited) a. n is the number of bytes in a page. 3top 3tart "yte7rite $evsel "yteaddr "yteaddr $atain 7# 3tart 0age7rite $evsel "yteaddr "yteaddr $atain 7# $atain !)d 0age7ritecontgd 7#contgd 3top $atain. !#+ !#+ !#+ ./!#+ 27 !#+ !#+ !#+ ./!#+ 27 ./!#+ ./!#+
instructions m24m01-a125 18/37 docid023765 rev 4 4.1.3 write identification page the identification page (256 bytes) is an additional page which can be written and (later) permanently locked in read-only mode. it is writ ten by issuing the write identification page instruction. this instruction us es the same protocol and format as page write (into memory array), except for the following differences: ? device type identifier = 1011b ? most significant address bits a16/a8 are don't care, except for address bit a10 which must be ?0?. least significant address bits a7/a0 define the byte location inside the identification page. if the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (noack). 4.1.4 lock identification page the lock identification page instruction (lock id) permanently locks the identification page in read-only mode. the lock id instruction is si milar to byte write (into memory array) with the following specific conditions: ? device type identifier = 1011b ? address bit a10 must be ?1?; all other address bits are don't care ? the data byte must be equal to the binary value xxxx xx1x, where x is don't care 4.1.5 minimizing write delays by polling on ack the maximum write time (t w ) is shown in ac characteristics tables in section 8: dc and ac parameters , but the typical time is shorter. to ma ke use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 7 , is: ? initial condition: a write cycle is in progress. ? step 1: the bus master issues a start condi tion followed by a device select code (the first byte of the new instruction). ? step 2: if the device is bu sy with the internal write cycl e, no ack will be returned and the bus master goes back to step 1. if t he device has terminated the internal write cycle, it responds with an ack, indicating th at the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1).
docid023765 rev 4 19/37 m24m01-a125 instructions 36 figure 7. write cycle polling flowchart using ack :ulwhf\foh lqsurjuhvv $ , g !)e 1h[w 2shudwlrqlv dgguhvvlqjwkh phpru\ 6wduwfrqglwlrq 'hylfhvhohfw zlwk5: $&. uhwxuqhg <(6 12 <(6 12 5h6wduw 6wrs 'dwdiruwkh :ulwhfshudwlrq $eviceselect with27 6hqg$gguhvv dqg5hfhlyh$&. )luvwe\whrilqvwuxfwlrq zlwk5: douhdg\ ghfrghge\wkhghylfh <(6 12 6wduw&rqglwlrq &rqwlqxhwkh :ulwhrshudwlrq &rqwlqxhwkh 5dqgrp5hdgrshudwlrq
instructions m24m01-a125 20/37 docid023765 rev 4 4.2 read operations read operations are performed independently of the state of the write control ( wc ) signal. after the successful completion of a read oper ation, the device internal address counter is incremented by one, to point to the next byte address. figure 8. read mode sequences 4.2.1 random address read the random address read is a sequence co mposed of a truncated write sequence (to define a new address pointer value, see table 3 ) followed by a current read. the random address read sequence is therefore the sum of [start + device select code with rw=0 + two address bytes] (with out stop condition, as shown in figure 8 )] and [start condition + device select code with rw=1]. the memory device acknowledges the sequence and then outputs the contents of the addressed byte. to terminate the data transfer, the bus master does not acknowledge the last data byte and then issues a stop condition. 3tart $evsel
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$ataout 3top !#+ 27 ./!#+ !#+ 27 !#+ !#+ !#+ 27 !#+ !#+ !#+ ./!#+ 27 ./!#+ !#+ !#+ !#+ 27 !#+ !#+ 27 !#+ ./!#+
docid023765 rev 4 21/37 m24m01-a125 instructions 36 4.2.2 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the r/ w bit set to 1. the device acknowledges this, and outputs the byte pointed by the internal addre ss counter. the counter is then incremented. the bus master terminates the transfer with a stop condition , as shown in figure 8 , without acknowledging the byte. note that the address counter value is defined by instructions accessing either the memory or the identification page. when accessing the identification page, the address counter value is loaded with the identification page byte location, when accessing the memory, it is safer to always use the random address re ad instruction (this instruction loads the address counter with the byte location to read in the memory) instead of the current address read instruction. 4.2.3 sequential read a sequential read can be used after a current address read or a random address read. after a read instruction, the device can continue to output the next byte(s) in sequence if the bus master sends additional clock pulses and if the bus master does acknowledge each transmitted data byte. to te rminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 8 . the sequential read is controlled with the device internal address counter which is automatically incremented after each byte ou tput. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 4.2.4 read identification page the identification page can be read by issuing a read identification page instruction. this instruction uses the same protocol and form at as the random address read (from memory array) with device type identifier defined as 10 11b. the most significant address bits a16/a8 are don't care and the least significant address bits a7/a0 define the byte location inside the identification page. the number of bytes to re ad in the id page must not exceed the page boundary. 4.2.5 read the lock status the locked/unlocked status of the identifica tion page can be checked by transmitting a specific truncated command [identification page write instruction + one data byte] to the device. the device returns an acknowledge bit afte r the data byte if the identification page is unlocked, otherwise a noack bit if the identification page is locked. right after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that: ? start: the truncated command is not execut ed because the start condition resets the device internal logic, ? stop: the device is then set back into standby mode by the stop condition.
instructions m24m01-a125 22/37 docid023765 rev 4 4.2.6 acknowledge in read mode for all read instructions, the device waits, af ter each byte sent out, for an acknowledgment during the 9th bit time. if the bus master does not send the acknowledge (the master drives sda high during the 9th bit time), the device terminates the data transfer and enters its standby mode.
docid023765 rev 4 23/37 m24m01-a125 application design recommendations 36 5 application design recommendations 5.1 supply voltage 5.1.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see table 7 ). this voltage must remain stable and valid unt il the end of the transmission of the instruction and, for a write instructio n, until the completion of the internal write cycle (t w ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. 5.1.2 power-up conditions when the power supply is turned on, the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage defined in table 7 . in order to prevent inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not re spond to any instruction until v cc reaches the internal threshold voltage (this threshold is defined in the dc characteristic table 10 as v res ). when v cc passes over the por threshold, the device is reset and in the following state: ? in the standby power mode ? deselected as soon as the v cc voltage has reached a stable value within the [v cc (min), v cc (max)] range (defined in table 7 ), the device is ready for operation. 5.1.3 power-down during power-down (continuous decrease in the v cc supply voltage below the minimum v cc operating voltage defined in table 7 ), the device must be in standby power mode (that is after a stop condition or after the completion of the write cycle t w if an internal write cycle is in progress).
application design recommendations m24m01-a125 24/37 docid023765 rev 4 5.2 cycling with error correction code (ecc) the error correction code (ecc) is an internal logic function which is transparent for the i 2 c communication protocol. the ecc logic is implemented on each group of four eeprom bytes (b) . inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ecc detects this bit and replaces it with the correct value. the read reliability is therefore much improved. even if the ecc function is performed on group s of four bytes, a single byte can be written/cycled independently. in this case, th e ecc function also writes/cycles the three other bytes located in the same group (b) . as a consequence, the maximum cycling budget is defined at group level and the cycling can be di stributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in table 6 . example 1: maximum cycling limit reached with 1 million cycles per byte each byte of a group can be equally cycled 1 million times (at 25 c) so that the group cycling budget is 4 million cycles. example 2: maximum cycling limit reached with unequal byte cycling inside a group, byte0 can be cycled 2 million times, by te1 can be cycled 1 million times, byte2 and byte3 can be cycled 500,000 times, so that the group cycling budget is 4 million cycles. b. a group of four bytes is located at addresses [4 *n, 4*n+1, 4*n+2, 4*n+3], where n is an integer.
docid023765 rev 4 25/37 m24m01-a125 delivery state 36 6 delivery state the device is delivered as follows: ? the memory array is set to all 1s (each byte = ffh). ? identification page: the first three bytes def ine the device identification code (value defined in table 4 ). the content of the following bytes is don?t care. 7 maximum rating stressing the device outside the ratings listed in table 5 may cause permanent damage to the device. these are stress ratings only, and o peration of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 5. absolute maximum ratings symbol parameter min. max. unit ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec standard j-std-020d (for small body, sn-pb or pb-free assembly), the st ecopack? 7191395 specification, and the european direct ive on restrictions of hazardous substances (rohs directive 2011/65/euof july 2011). c v io input or output range ?0.50 6.5 v i ol dc output current (sda = 0) - 5 ma v cc supply voltage ?0.50 6.5 v v esd electrostatic pulse (human body model) (2) 2. positive and negative pulses applied on pin pairs, ac cording to aec-q100-002 (compliant with jedec std jesd22-a114, c1=100 pf, r1=1500 , r2=500 ). - 4000 v
dc and ac parameters m24m01-a125 26/37 docid023765 rev 4 8 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. table 6. cycling performance by groups of four bytes symbol parameter test condition min. max. unit ncycle write cycle endurance (1) ta 25 c, 2.5 v < v cc < 5.5 v - 4,000,000 write cycle (2) ta = 85 c, 2.5 v < v cc < 5.5 v - 1,200,000 ta = 125 c, 2.5 v < v cc < 5.5 v - 600,000 1. the write cycle endurance is defined for groups of four data by tes located at addresses [4*n, 4*n+1, 4*n+2, 4*n+3] where n is an integer, or for the status register byte (refer also to section 5.2: cycling with error correction code (ecc) ). the write cycle endurance is defined by characterization and qualification. 2. a write cycle is executed when either a page write, a byte write, a write identification p age or a lock identification page instruction is decoded. when using those write instructions, refer also to section 5.2: cycling with error correction code (ecc) . table 7. operating conditions (voltage range w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature ?40 125 c table 8. ac measurement conditions symbol parameter min. max. unit c bus load capacitance 100 pf - scl input rise/fall time, sda input fall time - 50 ns - input levels 0.2 v cc to 0.8 v cc v - input and output timing reference levels 0.3 v cc to 0.7 v cc v
docid023765 rev 4 27/37 m24m01-a125 dc and ac parameters 36 figure 9. ac measurement i/o waveform table 9. input parameters symbol parameter (1) 1. characterized only, not tested in production. test condition min. max. unit c in input capacitance (sda) - - 8 pf c in input capacitance (other pins) - - 6 pf z l input impedance (e2, e1, wc ) (2) 2. e2, e1 input impedance when the memory is selected (after a start condition). v in < 0.3 v cc 30 - k z h v in > 0.7 v cc 500 - k -36 6 ## 6 ## 6 ## 6 ## )nputandoutput 4imingreferencelevels )nputvoltagelevels
dc and ac parameters m24m01-a125 28/37 docid023765 rev 4 table 10. dc characteristics symbol parameter test conditions (in addition to those in table 7 and table 8 ) min. max. unit i li input leakage current (scl, sda, e2, e1) v in = v ss or v cc, device in standby mode - 2a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc - 2a i cc supply current (read) f c = 400 khz, v cc = 5.5 v - 2 ma f c = 400 khz, v cc = 2.5 v - 2 ma f c = 1 mhz, v cc = 5.5 v - 2 ma f c = 1 mhz, v cc = 2.5 v - 2 ma i cc0 supply current (write) during t w -2ma i cc1 standby supply current device not selected (1) , t = 85 c v in = v ss or v cc , v cc = 2.5 v -2a device not selected (1) , t = 85 c, v in = v ss or v cc , v cc = 5.5 v -3a device not selected (1) , t = 125 c, v in = v ss or v cc , v cc = 2.5 v -15a device not selected (1) , t = 125 c, v in = v ss or v cc , v cc = 5.5 v -20a v il input low voltage (scl, sda, wc ) - ?0.45 0.3 v cc v v ih input high voltage (scl, sda) - 0.7 v cc 6.5 v input high voltage (wc , e2, e1) - 0.7 v cc v cc +0.6 v v ol output low voltage i ol = 2.1 ma, v cc = 2.5 v or i ol = 3 ma, v cc = 5.5 v -0.4v v res (2) internal reset threshold voltage - 0.5 1.5 v 1. the device is not selected after power-up, after a read instru ction (after the stop condition), or after the completion of th e internal write cycle t w (t w is triggered by the correct dec oding of a write instruction). 2. characterized only, not 100% tested.
docid023765 rev 4 29/37 m24m01-a125 dc and ac parameters 36 table 11. 400 khz ac characteristics symbol alt. parameter (1) 1. test conditions (in addition to those in table 7 and table 8 ). min. max. unit f c f scl clock frequency - 400 khz t chcl t high clock pulse width high 600 - ns t clch t low clock pulse width low 1300 - ns t ql1ql2 (2) 2. characterized value, not tested in production. t f sda (out) fall time (3) 3. with c l = 10 pf. 20 120 ns t xh1xh2 t r input signal rise time (4) 4. there is no min. or max. values for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal rise and fa ll times be more than 20 ns and less than 300 ns when f c < 400 khz. (4) ns t xl1xl2 t f input signal fall time (4) (4) ns t dxcx t su:dat data in set up time 100 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (5) 5. to avoid spurious start and stop conditions, a mini mum delay is placed between scl=1 and the falling or rising edge of sda. t dh data out hold time 100 - ns t clqv (6) 6. t clqv is the time (from the falling edge of scl) r equired by the sda bus line to reach either 0.3v cc or 0.7v cc , assuming that r bus c bus time constant is within the values specified in figure 10. t aa clock low to next data valid (access time) - 900 ns t chdl t su:sta start condition setup time 600 - ns t dlcl t hd:sta start condition hold time 600 - ns t chdh t su:sto stop condition set up time 600 - ns t dhdl t buf time between stop condition and next start condition 1300 - ns t wldl (7)(2) 7. wc =0 set up time condition to enable the execution of a write command. t su:wc wc set up time (before the start condition) 0 - s t dhwh (8)(2) 8. wc =0 hold time condition to enable the execution of a write command. t hd:wc wc hold time (after the stop condition) 1 - s t w t wr write time - 4 ms t ns (2) - pulse width ignored (input filter on scl and sda) - single glitch -80ns
dc and ac parameters m24m01-a125 30/37 docid023765 rev 4 table 12. 1 mhz ac characteristics symbol alt. parameter (1) 1. test conditions (in addition to those in table 7 and table 8 ). min. max. unit f c f scl clock frequency 0 1 mhz t chcl t high clock pulse width high 260 - ns t clch t low clock pulse width low 400 - ns t xh1xh2 t r input signal rise time (2) 2. there is no min. or max. values for the input signal rise and fall times. however, it is recommended by the i2c specification that the input signal rise and fa ll times be more than 20 ns and less than 120 ns when f c < 1 mhz. (2) ns t xl1xl2 t f input signal fall time (2) (2) ns t ql1ql2 (3) 3. characterized only, not tested in production. t f sda (out) fall time - 120 ns t dxcx t su:dat data in setup time 50 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (4) 4. to avoid spurious start and stop conditions, a mini mum delay is placed between scl=1 and the falling or rising edge of sda. t dh data out hold time 100 - ns t clqv (5) 5. t clqv is the time (from the falling edge of scl) requi red by the sda bus line to reach either 0.3 v cc or 0.7 v cc , assuming that the rbus cbus time cons tant is within the values specified in figure 11 . t aa clock low to next data valid (access time) - 450 ns t chdl t su:sta start condition setup time 250 - ns t dlcl t hd:sta start condition hold time 250 - ns t chdh t su:sto stop condition setup time 250 - ns t dhdl t buf time between stop condition and next start condition 500 - ns t wldl (6) (3) 6. wc =0 set up time condition to enable the execution of a write command. t su:wc wc set up time (before the start condition) 0 - s t dhwh (7) (3) 7. wc =0 hold time condition to enable the execution of a write command. t hd:wc wc hold time (after the stop condition) 1 - s t w t wr write time - 4 ms t ns (3) - pulse width ignored (input filter on scl and sda) -80ns
docid023765 rev 4 31/37 m24m01-a125 dc and ac parameters 36 figure 10. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz figure 11. maximum r bus value versus bus parasitic capacitance c bus ) for an i 2 c bus at maximum frequency f c = 1mhz aib "uslinecapacitorp& "uslinepull upresistor k )#bus master -xxx 2 bus 6 ## # bus 3#, 3$! 2 bus # bus ns (ere2 bus # bus ns k ? p& 4he2x#timeconstant mustbebelowthens timeconstantlinerepresented ontheleft bus bus "uslinecapacitorp& "uslinepull upresistork -36 )#bus master -xxx 2 bus 6 ## # bus 3#, 3$! (ere 2 bus # bus ns 2 bu s # bu s ns 4he2 bus # bus timeconstant mustbebelowthens timeconstantlinerepresented ontheleft
dc and ac parameters m24m01-a125 32/37 docid023765 rev 4 figure 12. ac waveforms ^> ^k? ^> ^/v ?o] ?>ys ?>yy ?,, ^?}? }v]?]}v ?,> ^??? }v]?]}v t?]??o ?t /??] ?o] ?y>y>? ^/v ?,> ^??? }v]?]}v ?y, ?>y ^ /v?? ^ zvp ?,, ?,> ^?}? }v]?]}v ^??? }v]?]}v ?y,y,? ^> ?,> ?>> ?>, ?y,y,? ?y>y>? ?y>y>? t ?t>> ?,t, ?,>
docid023765 rev 4 33/37 m24m01-a125 package mechanical data 36 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 13. tssop8 ? 8-lead thin shrink small outline, package outline 1. drawing is not to scale. table 13. tssop8 ? 8-lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to four decimal digits. typ. min. max. typ. min. max. a - - 1.200 - - 0.0472 a1 - 0.050 0.150 - 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b - 0.190 0.300 - 0.0075 0.0118 c - 0.090 0.200 - 0.0035 0.0079 cp - 0.100 - - 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 - - 0.0256 - - e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 - - 0.0394 - - - 0 8 - 0 8
package mechanical data m24m01-a125 34/37 docid023765 rev 4 figure 14. so8n ? 8 lead plastic small ou tline, 150 mils body width, package outline 1. drawing is not to scale. table 14. so8n ? 8 lead plastic small outline, 150 mils body width, package data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a - - 1.750 - - 0.0689 a1 - 0.100 0.250 - 0.0039 0.0098 a2 - 1.250 - - 0.0492 - b - 0.280 0.480 - 0.0110 0.0189 c - 0.170 0.230 - 0.0067 0.0091 ccc - - 0.100 - - 0.0039 d 4.900 4.800 5.000 0.1929 0.1890 0.1969 e 6.000 5.800 6.200 0.2362 0.2283 0.2441 e1 3.900 3.800 4.000 0.1535 0.1496 0.1575 e 1.270 - - 0.0500 - - h - 0.250 0.500 - 0.0098 0.0197 k - 0 8 - 0 8 l - 0.400 1.270 - 0.0157 0.0500 l1 1.040 - - 0.0409 - - 62$ ( fff e h $ ' f ( k[? $ n pp / / $ *$8*(3/$1(
docid023765 rev 4 35/37 m24m01-a125 part numbering 36 10 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of the devices, please contact your nearest st sales office. table 15. ordering information scheme example: m24m01-d w mn 3 t p /k device type m24 = i 2 c serial access eeprom device function m01-d = 1 mbit (128 k x 8 bits) plus identification page operating voltage w = v cc = 2.5 v to 5.5 v package mn = so8 (150 mil width) (1) 1. rohs-compliant and halogen-free (ecopack2 ? ) dw = tssop8 (169 mil width) (1) device grade 3 = -40 to 125 c. device tested with high reliability certified flow (2) 2. the high reliability certified flow (hrcf) is des cribed in quality note qnee9801. please ask your nearest st sales office for a copy. option blank = standard packing t = tape and reel packing plating technology p = ecopack ? (rohs compliant) process /k = manufacturing technology code
revision history m24m01-a125 36/37 docid023765 rev 4 11 revision history table 16. document revision history date revision changes 24-jan-2013 1 initial release. 27-may-2013 2 document reformatted. document status changed from ?target specification? to ?preliminary data?. updated: ? section 3.6: identification page ? note (1) under table 5: absolute maximum ratings ?i cc ,v il and v ol values in table 10: dc characteristics ? package information in table 15: ordering information scheme removed information related to ufdfpn8 (mlp8) package. 19-aug-2013 3 document status changed from ?preliminary data? to ?production data?. updated ?v ol ? row in table 10: dc characteristics . 04-feb-2014 4 changed data retention from "40 ye ars at 55 c" to "50 years at 125 c" in features .
docid023765 rev 4 37/37 m24m01-a125 37 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications . products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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