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tm ?2007 fairchild semiconductor corporation 1 www.fairchildsemi.com FDMF8704 rev. g FDMF8704 high efficiency / high frequency fet plus driver multi-chip module november 2007 FDMF8704 high efficiency / high frequency fe t plus driver multi-chip module benefits ? fully optimized system efficienc y. higher efficiency levels are achievable compared wi th conventional discrete components. ? space savings of up to 50% pcb versus discrete solutions. ? higher frequency of operation. ? simpler system design and board layout. reduced time in component selection and optimization. features ? 7v to 20v input voltage range ? output current to 32a ? 1mhz switching frequency capable ? internal adaptive gate drive ? low side fet with integrated schottky diode ? peak efficiency >90% ? output disable for lost phase shutdown ? low profile smd package ? rohs compliant general description the FDMF8704 is a fully optimized integrated driver plus mosfet power stage solution for high current synchronous buck dc-dc applications. the device integrates a driver ic and two power mosfets into a space saving, mlp 8x8, 56-pin package. fairchild semiconductor?s integrated approach optimizes the complete switching power stage with regards to driver to fet dynamic performance, system inductance and overall solution on resistance. package parasitics and problematical layouts associat ed with conventional discrete solutions are greatly reduced. this integrated approach results in significant board space saving, therefore maximizing footprint power density. this solution is based on the intel? drmos specification. applications ? desktop and server vr11.x v-core and non v-core buck converters. ? cpu/gpu power train in game consoles and high end desktop systems. ? high-current dc-dc point of load (pol) converters. ? networking and telecom microprocessor voltage regulators. ? small form factor voltage regulator modules. powertrain application circuit ordering information part current rating max [a] input voltage typical [v] frequency max [khz] device marking FDMF8704 32 12-19 1000 FDMF8704 disb pwm cgnd pgnd vin vcin vswh disb pwm input c vcin 5v c boot c out output 7 - 20v c vin boot hsen figure 1. powertrain application circuit
2 www.fairchildsemi.com FDMF8704 rev. g FDMF8704 high efficiency / high frequency fet plus driver multi-chip module pin configuration pin description pin name function 1, 6, 51, a cgnd ic ground. ground return for driver ic. 2 hsen high side fet enable. must be connected to boot pin. 3, 7, 52-54 nc no connect 4 vcin ic supply. +5v chip bias power. bypass with a 1f ceramic capacitor. 5boot bootstrap supply input. provides voltage s upply to high-side mosfet driver. connect bootstrap capacitor. 21, 40-50, c vswh switch node input. sw provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection. 8, 9, 11-20, b vin power input. output stage supply voltage. 10 test pad 1 for manufacturing test only. hdrv pin. this pin must be floated. must not be connected to any pin. 22-38 pgnd power ground. output stage ground. source pin of low side mosfet(s). 39 test pad 2 for manufacturing test only. ldrv pin. this pin must be floated. must not be connected to any pin. 55 disb output disable. when low, this pin dis able fet switching (hdrv and ldrv are held low). 56 pwm pwm signal input. this pin accepts a l ogic-level pwm signal from the controller. figure 2. mlp 8x8 56l bottom view pwm cgnd disb nc nc nc cgnd vswh vswh vswh vswh vswh vswh vswh vswh hsen nc vcin boot cgnd nc vin vin test pad 1 vin vin vin vin vin vin vin vin vin vin vswh pgnd pgnd pgnd pgnd pgnd pgnd pgnd vswh vswh vswh test pad 2 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd 15 114 43 28 42 29 56 a (cgnd) b (vin) c (vswh)
3 www.fairchildsemi.com FDMF8704 rev. g FDMF8704 high efficiency / high frequency fet plus driver multi-chip module absolute maximum rating stresses exceeding the absolute maximum ra tings may damage the device. the device ma y not function or be operable above the recommended operating conditions and stressing the parts to thes e levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect dev ice reliability. the absolute maximum ratings are stress rati ngs only. note 1: package power dissipation based on 4 layers , 2 square inch, 2 oz. copper pad. r jpcb is the steady state junction to pcb thermal resistance with pcb temperature referenced at vswh pin. recommended operating range the recommended operating conditions tabl e defines the conditions for actual dev ice operation. recommended operating condi- tions are specified to ensure optimal performance to the data sheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. electrical characteristics v in = 12v, v cin = 5v, t a = 25c unless otherwise noted . note 2: t pdl(ldrv/hrdv) refers to high-to-low transition, t pdh(ldrv/hdrv) refers to low-to-high transition. parameter min. max. units v cin , pwm, disb to pgnd -0.3 6 v v in to pgnd -0.3 24 v boot to vswh -0.3 6 v vswh to pgnd -1.0 24 v boot to pgnd -0.3 30 v i o(av) v in = 12v, v o = 1.3v, f sw = 1mhz, t pcb = 100c 32 a i o(pk) v in = 12v, t pulse = 10s 65 a r jpcb junction to pcb thermal resistance (note 1) 5 c/w p d t pcb = 100c (note 1) 10 w operating and storage junction temperature range -55 150 c parameter min. typ. max. units v cin control circuit supply voltage 4.5 5 5.5 v v in output stage supply voltage 7 12 20 v v out output voltage 0.8 1.3 3.2 v parameter symbol conditions min. typ. max. units operating voltage range v cin 4.5 5 5.5 v control circuit supply current i cc f sw = 0hz, v disb = 0v 1 3 ma f sw = 1mhz, v disb = 5v 50 pwm input high voltage v ih(pwm) 2.4 v pwm input low voltage v il(pwm) 0.8 v pwm input current i il(pwm) -2 2 a disb input high voltage v ihdisb) 2.4 v disb input low voltage v il(disb) 0.8 v disb input current i il(disb) -2 2 a propagation delay t pdl(disb-ldrv) (2) v in = 12v, v out = 1.3v, f sw = 1mhz, i o = 30a 8ns t pdh(disb-ldrv) (2) 6ns t pdl(ldrv) (2) 9ns t pdl(hdrv) (2) 22 ns t pdh(ldrv) (2) 12 ns t pdh(hdrv) (2) 20 ns
4 www.fairchildsemi.com FDMF8704 rev. g FDMF8704 high efficiency / high frequency fet plus driver multi-chip module functional block diagram figure 3. functional block diagram pwm disb cgnd pgnd vswh vin boot vcin vcin hdrv ldrv hsen q1 q2 functional description the FDMF8704 is a driver pl us fet module optimized for synchronous buck converte r topology. a single pwm input signal is all that is required to properly drive the high-side and the low-side mosfets. each part is capable of driving speeds up to 1mhz. low-side driver the low-side driver (ldrv) is designed to drive a ground referenced low r ds(on) n-channel mosfet. the bias for ldrv is internally connected between vcin and cgnd. when the driver is enabled, the driver's output is 180 out of phase with the pwm input. when the driver is disabled (disb = 0v), ldrv is held low. high-side driver the high-side driver (hdrv) is designed to drive a floating n-channel mosfet. the bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of the external diode and external bootstrap capacitor (c boot ). during start-up, vswh is held at pgnd, allowing c boot to charge to vcin through the internal diode. when the pwm input goes high, hdrv will begin to char ge the high-side mosfet's gate (q1). during this transition, charge is removed from c boot and delivered to q1's gate. as q1 turns on, vswh rises to v in , forcing the boot pin to v in +v c(boot) , which provides sufficient vgs enhancement for q1. to complete the switching cycle, q1 is turned off by pulling hdrv to vswh. c boot is then recharged to vcin when vswh falls to pgnd. hdrv output is in phase with the pwm input. when the driver is disabled, the high-side gate is held low. adaptive gate drive circuit the driver ic embodies an advanced design that ensures minimum mosfet dead-time while eliminating potential shoot- through (cross-conduction) currents. it senses the state of the mosfets and adjusts the gate drive, adaptively, to ensure they do not conduct simultaneously. refer to figure 4 and 5 for the relevant timing waveforms. to prevent overlap during the low- to-high switching transition (q2 off to q1 on), the adaptive circuitry monitors the voltage at the ldrv pin. when the pwm signal goes high, q2 will begin to turn off after some propagation delay (t pdl(ldrv) ). once the ldrv pin is discharged below ~1.2v, q1 begins to turn on after adaptive delay t pdh(hdrv) . to preclude overlap during the high-to-low transition (q1 off to q2 on), the adaptive circuitry monitors the voltage at the sw pin. when the pwm signal goes low, q1 will begin to turn off after some propagation delay (t pdl(hdrv) ). once the vswh pin falls below ~2.2v, q2 begins to turn on after adaptive delay t pdh(ldrv) . additionally, v gs of q1 is monitored. when v gs(q1) is discharged below ~1.2v, a secondary adaptive delay is initiated, which results in q2 being driven on after t pdh(ldrv) , regardless of sw state. this function is implemented to ensure c boot is recharged each switching cycle, particularly for cases where the power converter is sinking current and sw voltage does not fall below the 2.2v adaptive threshold. secondary delay t pdh(hdrv) is longer than t pdh(ldrv) .
5 www.fairchildsemi.com FDMF8704 rev. g FDMF8704 high efficiency / high frequency fet plus driver multi-chip module timing diagram disb v il(disb) v ih(disb) t pdl(disb) t pdh(disb) ldrv / hdrv v ih(pwm) pwm t pdl(ldrv) ldrv figure 4. output disable timing t pdh(hdrv) 1.2v hdrv-sw t pdl(hdrv) sw 2.2v t pdh(ldrv) v il(pwm) figure 5. adaptive gate drive timing
6 www.fairchildsemi.com FDMF8704 rev. g FDMF8704 high efficiency / high frequency fet plus driver multi-chip module typical characteristics v in = 12v, v cin = 5v, t a = 25c unless otherwise noted. 0 5 10 15 20 25 30 35 0 25 50 75 100 125 15 0 pcb temperature, o c i load , a v in = 12v v out = 1.3v f sw = 1mhz l = 0.33uh 0 2 4 6 8 10 0 5 10 15 20 25 3 0 i load , a p loss , w v in = 12v v out = 1.3v l = 0.33uh f sw = 1mhz f sw = 500khz 0.70 0.80 0.90 1.00 1.10 300 400 500 600 700 800 900 1000 1100 120 0 f sw , khz p loss (normalized) v in = 12v v out = 1.3v i out = 30a l = 0.33uh 0.95 1.00 1.05 1.10 1.15 6 8 10 12 14 1 6 input voltage, v p loss (normalized) v out = 1.3v i out = 30a l = 0.33uh f sw = 1mhz 0.95 1.00 1.05 1.10 1.15 4.5 5.0 5.5 6.0 driver supply voltage, v p loss (normalized) v in = 12v v out = 1.3v i out = 30a l = 0.33uh f sw = 1mhz 0.8 1.0 1.2 1.4 1.6 0.8 1.2 1.6 2.0 2.4 2.8 3.2 output voltage, v p loss (normalized) v in = 12v i out = 30a l = 0.33uh f sw = 1mhz figure 8. power loss vs. switching frequency figure 9. power loss vs. input voltage figure 10. power loss vs. driver supply voltage figure 11. power loss vs. output voltage figure 6. safe operating area figure 7. module power loss vs. output current
7 www.fairchildsemi.com FDMF8704 rev. g FDMF8704 high efficiency / high frequency fet plus driver multi-chip module typical characteristics v in = 12v, v cin = 5v, t a = 25c unless otherwise noted. 0.98 1.00 1.02 1.04 1.06 0.0 0.2 0.4 0.6 0.8 1.0 output inductance, uh p loss (normalized) v in = 12v v out = 1.3v i out = 30a f sw = 1mhz 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -50 -25 0 25 50 75 100 125 temperature, o c driver suppy current , ma v cin = 5v disb = 5v pwm = 5v pwm = 0v 0 10 20 30 40 50 0 200 400 600 800 100 0 f sw , khz driver suppy current , ma v cin = 5v 1.75 1.77 1.79 1.81 1.83 -50 -25 0 25 50 75 100 125 temperature, o c pwm threshold voltage, v v cin = 5 v v ih v il 1.65 1.70 1.75 1.80 1.85 1.90 -50 -25 0 25 50 75 100 125 temperature, o c disb threshold voltage, v v cin = 5 v v ih v il figure 14. driver supply current vs. frequency figure 15. pwm threshold voltage vs. temperature figure 16. disb threshold voltage vs. temperature figure 12. power loss vs. output inductance figure 13. driver supply current vs. temperature
8 www.fairchildsemi.com FDMF8704 rev. g FDMF8704 high efficiency / high frequency fet plus driver multi-chip module application information supply capacitor selection for the supply input (v cin ) of the FDMF8704, a local ceramic bypass capacitor is recommended to reduce the noise and to supply the peak current. use at least a 1f, x7r or x5r capacitor. keep this capacitor close to the FDMF8704 v cin and cgnd pins. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c boot ) and the external schottky diode, as shown in figure 18. a bootstrap capacitance of 100nf, x7r or x5r capacitor is adequate. the peak surge current rating of the boot diode should be checked in-circuit, since th is is dependent on the equivalent impedance of the entire bootstrap circuit, including the pcb traces. boot diode must be sized big enough to carry the forward charge current. refer to figure 14 for boot diode average forward current. the bootstrap diode must have low v f and low reverse current leakage. breakdown voltage of the bootstrap diode must be greater than the boot to vswh voltage. v cin 5v signal v in 12v pwm3 vcc pwm1 pwm2 gnd pwm controller en pwm4 gnd power gnd vout pwm disb vin vcin vswh boot FDMF8704 pwm disb vin vcin FDMF8704 pwm disb vin vcin FDMF8704 pwm disb cgnd pgnd vin vcin FDMF8704 cgnd pgnd cgnd pgnd pwm typical application hsen vswh boot hsen vswh boot hsen vswh boot hsen figure 17. typical application cgnd pgnd
9 www.fairchildsemi.com FDMF8704 rev. g FDMF8704 high efficiency / high frequency fet plus driver multi-chip module module power loss measurement and calculation refer to figure 18 for module power loss testing method. power loss calculation are as follows: (a) p in = (v in x i in ) + (v cin x i cin ) (w) (b) p out = v o x i out (w) (c) p loss = p in - p out (w) pcb layout guideline figure 19. shows a proper layout example of FDMF8704 and critical parts. all of high current flow path, such as v in , vswh, v out and gnd copper, should be short and wide for better and stable current flow, heat radiation and system performance. following is a guideline which the pcb designer should consider: 1. input bypass capacitors should be close to v in and gnd pin of FDMF8704 to help reduce input current ripple component induced by switching operation. 2. it is critical that the vswh copper has minimum area for lower switching noise emission. vswh copper trace should also be wide enough for high current flow. other signal routing path, such as pwm in and boot signal, should be considered with care to avoid noise pickup from vswh copper area. 3. output inductor location should be as close as possible to the FDMF8704 for lower power loss due to copper trace. 4. snubber for suppressing ringing and spiking of vswh voltage should be placed near the FDMF8704. the resistor and capacitor need to be of proper size for power dissipation. 5. place boot diode, ceramic bypass capacitor and boot capacitor as close to v cin and boot pin of FDMF8704 in order to supply stable power. routing width and length should also be considered 6. use multiple vias on each copper area to interconnect each top, inner and bottom layer to help smooth current flow and heat conduction. vias should be relati vely large and of reasonable inductance. disb pwm cgnd pgnd vin vcin vswh disb pwm input c vcin v cin c boot c out v out v in c vin boot i in a i out a v v o i cin a figure 18. power loss measurement block diagram figure 19. typical pcb layout example (top view) hsen l
10 www.fairchildsemi.com FDMF8704 rev. g FDMF8704 high efficiency / high frequency fet plus driver multi-chip module dimensional outline and pad layout bayan lepas fiz 11900, penang, malaysia (datum a)
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