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features low operating curremt consumption (typical 4 ma) high input sensetivity, high input frequencies ( 50 mhz) synchronous programming of the counters (n-, n/a, r-counters) switchable modulus trigger edge large dividing ratios for small channel spacing a counter 0 to 127 n counter 3 to 16,380 r counter 3 to 65,535 serial control: 3-wire bus: data, clock (<10 mhz), enable switchable polarity and programmable phase detector current 2 programmable outputs digital phase detector output signals (e.g. for external charge pump) drfin, dvfi outputs (e.g. for prescalar standby) external current setting for pd output lock detect outpuut with gated anti-backlash pulse (quasi digital lock detect) esd protection in accordance with mil- stds d ata sheet pll-frequency synthesizer linear dimensions, inc. 445 east ohio street, chicago, il 60611 p 312.3211810 f 312.321.1830 LND-TRN902 LND-TRN902pll-frequency synthesizer block diagram clk en rfi vfi data analog control logic 7 bit a counter lock detect phase detector charge pump drfi dvfi vdd vss avdd avss mod po2 ld po1 pd serial control logic modulus control 14 bit n counter 16 bit r counter
linear dimensions, inc. 445 east ohio street, chicago, il 60611 p 312.3211810 f 312.321.1830 pll-frequency synthesizer proposed data sheet pin definitions and functions pin no. s y mbol function 1 rfi reference fre q uenc y high sensitivity preamplifier input for the r-counter. the input can be ac-coupled for small input signals or dc-coupled for large input signals. 2 vss ground for the digital logic 3 en 3-wire interface: enable enable line of the serial interface with internal pull-up resistor. when en = h, the input signals clk and data are internally disabled. when en = l, the received data is transferred to the latches on the positive edge of the en-signal. 4 data 3-wire interface: data serial data input with internal pull-up resistor. the last two bits before the en-signal define the destination address. 5 clk 3-line interface : clock clock line with internal pull-up resistor. the serial data is read into the internal shift register on the positive edge (see p ulse diagram for serial data control) 6 vdd positive supply voltage for the digital logic 7 mod modulus control for external dual modulus prescaler. the modulus output is low at the beginning of the cycle. when the a-counter has reached its set value, mod switches to high. when the n-counter has reached its set value, mod switches to low and the cycle starts again. when the prescaler has the counter factor p or p+1 (p for mod = h, p+1 for mod =l), the overall scaling factor is np + a. the value of the a-counter must be smaller than that of the n-counter. the trigger edge of the modulus signal to the input signal can be selected (see programming tables and mod a, b) according to the needs of the prescaler. in single modulus operation and for standby operation in dual modulus operation, the output is low. 8 vfi vco-fre q uenc y high sensitivity preamplifier input for the n-counter. the input can be ac-coupled for small input signals or dc-coupled for large input signals. 9 avss ground for the analog logic ( note: the p ins vdd and avdd and also p ins vss and avss must have the same su pp l y volta g e. ) 10 pd phase detector tristate charge pump output. the level of the charge pump output current can be programmed using the digital interface. frequency dvfi < drfi p-channel current source active frequency dvfi > drfi n-channel current source active frequency dvfi = drfi and pll locked pd-output is tristate standby mode pd-output is tristate the polarity of the output signals of the phase detector can be programmed. 11 avdd positive supply voltage for the analog logic ( note: the p ins vdd and avdd and also p ins vss and avss must have the same su pp l y volta g e. ) 12 po1 pro g rammable out p ut for the signals drfin, phiv, phivn and probit. (drfin, dvfin, phivn are the inverted signals of drfi, dvfi, phiv.) 13 po2 pro g rammable i/o-pin for the output signals dvfi, phir and the input signal iref - - - - the signals phir and phiv are the digital output signals of the phase and frequency detector for use with external active current sources. the signals drfin and dvfin are the scaled down signals of the reference frequency and vco-frequency. the programmed bit probit is assigned to the po1 output in the internal charge pump mode. the standby mode does not affect this function. in the internal charge pump mode the input signal iref determines the value of the pd-output current. 14 ld lock detector ( o p en drain ) unipolar output of the phase detector in the form of a pulse-width modulated signal. the ld-pulse width corresponds to the phase difference. in the locked state the ld-signal is at h-level. in standby mode the output is resistive.
linear dimensions, inc. 445 east ohio street, chicago, il 60611 p 312.3211810 f 312.321.1830 pll-frequency synthesizer proposed data sheet theory of operation the th7010 is a pll frequency synthesizer intended for use in a frequency generation loop with a dual modulus prescaler and a vco. the vco frequency is divided by the external dual modulus prescaler. this divided signal is fed to the internal a and n counters. the reference frequency is fed to an internal r counter to define the channel spacing. both frequencies are compared in the phase detector which drives the charge pump. a lock detect is provided to monitor the lock state of the loop. all blocks are program- med by a 3 wire interface. the division ratio can be calculated as follows : fvco = ( n x p + a) / r x fref fvco : output frequency of the external vco fref : reference oscillator fr equency n : divide ratio of the n counter 3 n 16380 a : divide ratio of the a counter 0 a 127 r : divide ratio of the r counter 3 r 65535 p : divide ratio of the external dual modulus prescaler programming the programming of the device must start with the loading of the status register. the n, a and r counters can be loaded synchro- nously or asynchronously. if synchronous loading is selected, all counters are loaded when they reach the value zero. as a result, the phase difference between the divided vfi and rfi signals remains the same. for synchronous loading the following order of programming must be followed : 1. programming of synchronous loading using the status register 2. programming of the r counter 3. programming of the n/a counter. the rising edge of en enables the synchronous loading of all counters at their zero value. the phase detector and charge pump the phase detector is a digital edge sensitive comparator with up and down outputs. both outputs can be monitored at the outputs po1 and po2. the phase detector drives a charge pump which is a switch with a tristate state. the output current can be programmed in 8 steps between 0.125 ma and 2 ma with a reference current of 100 a. if vfi < rfi, the charge pump delivers a positive current to the external loop filter. if vfi > rfi, the charge pump sinks a negative current from the external loop filter. the charge pump output can be inverted by software. anti-backlash pulses are generated to extend the very short phase difference between vfi and rfi. standby the th7010 can be programmed through a 3 wire interface. four different words can be sent over this interface to program the internal registers. all four words have a 2 bit address part and a variable data part. when en = l the data is transferred. it is loaded into the internal registers at the rising edge of en. the last two bits which are transferred form the address bits. when en = h, the input signals clk and data are internally disabled. the status register contains all status informa- tion. the reduced status register is a reduced version of the status register. the n and a counter register and the r counter register contain the applicable counter values. the th7010 has two standby modes. in standby mode 1, the whole device is powered down with the exception of the serial interface. in standby mode 2, the serial interface and the input amplifiers are active. all other parts are powered down.
linear dimensions, inc. 445 east ohio street, chicago, il 60611 p 312.3211810 f 312.321.1830 pll-frequency synthesizer proposed data sheet anti backlash pulse width b8 b7 min. t yp . max. unit 0 0 1.6 2 2.4 ns 0 1 3.2 4 4.8 ns 1 0 4.8 6 7.2 ns 1 1 8 10 12 ns the above values are valid for vdd = 4.5 ... 5.5 v 0 0 1.2 2 2.4 ns 0 1 2.4 4 5.6 ns 1 0 3.6 6 7.2 ns 1 1 8 10 12 ns the above values are valid for vdd = 2.7 ... 3.3 v the best system performance is reached with the shortest abl pulse n & a counter re g ister dual mode 0 1 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 a1 a2 a3 a4 a5 a6 a7 single mode 0 1 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 note: n14 is the msb of the n counter value; a7 is the msb of the a counter value. a7 is the first bit which is transferred to the th7010. out p ut pd phase detector (p in 10 ) b14 b13 b12 min. t yp . max. unit 0 0 0 0.140 0.175 0.210 ma 0 0 1 0.200 0.250 0.300 ma 0 1 0 0.280 0.350 0.420 ma 0 1 1 0.400 0.500 0.600 ma 1 0 0 0.560 0.700 0.840 ma 1 0 1 0.800 1.000 1.200 ma 1 1 0 1.120 1.400 1.680 ma 1 1 1 1.600 2.000 2.400 ma stand by 0.1 50 na note: these values are valid under the following conditions vdd = 4.5 ... 5.5 v, vcp = 2.5 v, iref = 100 a. r counter re g ister 1 1 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r134 r14 r15 r16 note: r16 is the msb of the r counter value. r16 is the first bit which is transferred to the th7010. internal registers reduced status re g ister 0 0 b14 b13 b12 b11 b11 is the first bit which is transferred to the th7010.
linear dimensions, inc. 445 east ohio street, chicago, il 60611 p 312.3211810 f 312.321.1830 pll-frequency synthesizer proposed data sheet b1 counter loadin g 0 asynchronous counter load 1 synchronous counter load b3 b2 po1 po2 modes 0 0 drfin drvin test mode 0 1 phiv phirn external charge pump mode 1 0 phivn phirn external charge pump mode 1 1 probit iref internal charge pump mode b4 pd p olarit y 0 ne g ative 1 positive note: positive means increasin g vco frequenc y with increasin g volta g e. b6 stand b y 2 0 device in power down, input amplifiers active 1 device active b11 out p ut bit probit on po1 0 0 1 1 b10 b9 in p ut am p lifier modes 0 0 single mode 0 1 1 0 dual mode, fi trigger edge lh 1 1 dual mode, fi trigger edge hl b5 stand b y 1 0 device in power down 1 device active internal registers status re g ister 0 0 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b1 is the first bit which is transferred to the th7010.
linear dimensions, inc. 445 east ohio street, chicago, il 60611 p 312.3211810 f 312.321.1830 pll-frequency synthesizer proposed data sheet note: [4] vdd = 4.5 ... 5.5 v note: [5] vdd = 2.7 ... 3.3 v operating characteristics absolute maximum ratin g s s y m parameter condition min. t yp . max. unit vdd power supply voltage - 0.3 7 v vin input voltage - 0.3 vcc + 3 v iin input current - 10 10 ma tst storage temperature range - 40 125 c recommended operating conditions current consumption current consum p tion s y m parameter condition min. t yp . max. unit is current consumption vfi = 90 mhz, vri = 10 mhz, ipd = 0.25 ma 3.7 ma is current consumption standby 10 a characteristics recommended o p eratin g conditions s y m parameter condition min. t yp . max. unit vdd power supply voltage 2.7 5.5 v top operating temperature range - 40 85 c tj junction temperature - 10 150 c in p uts vfi vco fre q uenc y in p ut ( p in 8 ) , rfi reference fre q uenc y in p ut ( p in 1 ) s y m parameter condition min. t yp . max. unit vfi input vco frequency dual mode vdd = 4.5 ...5.5 v vdd = 2.7 v 4 4 66 [1] 30 [1] mhz mhz single mode vdd = 4.5 ...5.5 v vdd = 2.7 v 4 4 100 [2] 100 [2] mhz mhz rfi input reference frequency vdd = 4.5 v vdd = 2.7 v 4 4 60 [3] 30 [3] mhz mhz vfi input vco frequency vdd = 2.7 ... 3.3 v 1 70 mhz rfi input reference frequency vdd = 2.7 ... 3.3 v 1 70 mhz vin input voltage f = 4 ... 70 mhz [4] 100 mvrms vin input voltage f = 4 ... 50 mhz [5] 100 mvrms sr slew rate vdd = 2.7 v ... 5.5 v 4 v/s ci input capacitance 3 pf note: [1] @ 180 mv note: [2] @ 200 mv note: [3] @ 100 mv
linear dimensions, inc. 445 east ohio street, chicago, il 60611 p 312.3211810 f 312.321.1830 pll-frequency synthesizer proposed data sheet characteristics (continued) out p ut pd phase detector ( p in 10 ) b14 b13 b12 min. t yp . max. unit 0 0 0 0.10 0.175 0.23 ma 0 0 1 0.14 0.250 0.33 ma 0 1 0 0.19 0.350 0.47 ma 0 1 1 0.27 0.500 0.66 ma 1 0 0 0.41 0.700 0.92 ma 1 0 1 0.57 1.000 1.32 ma 1 1 0 0.79 1.400 1.83 ma 1 1 1 1.13 2.000 2.6 ma standby 0.1 50 na note: these values are valid under the following conditions vdd = 4.5 ... 5.5 v, vcp = vdd/2, iref = 100 a. out p ut po1 pro g rammable out p ut ( p in 12 ) s y m parameter condition min. t yp . max. unit voh voltage output high ioh = 2 ma [1] vdd - 0.8 v vol voltage output low ioh = 2 ma [1] 0.4 v voh voltage output high ioh = 1.2 ma [2] vdd - 0.8 v vol voltage output low ioh = 1.2 ma [2] 0.4 v tr rise time cl = 10 pf [1] 2.6 7.2 ns tf fall time cl = 10 pf [1] 3 4 ns tr rise time cl = 10 pf [2] 2.8 14.4 ns tf fall time cl = 10 pf [2] 4.5 6 ns note [1]: vdd = 4.5 ... 5.5 v note [2]: vdd = 2.7 ... 3.3 v
linear dimensions, inc. 445 east ohio street, chicago, il 60611 p 312.3211810 f 312.321.1830 pll-frequency synthesizer proposed data sheet characteristics (continued) in p ut - out p ut po2 pro g rammable in p ut - out p ut (p in 12 ) s y m parameter condition min. t yp . max. unit input voh voltage output high ioh = 2 ma [1] vdd - 0.8 v vol voltage output low ioh = 2 ma [1] 0.4 v voh voltage output high ioh = 1.2 ma [2] vdd - 0.8 v vol voltage output low ioh = 1.2 ma [2] 0.4 v tr rise time cl = 10 pf [1] 2.6 7.2 ns tf fall time cl = 10 pf [1] 3 4 ns tr rise time cl = 10 pf [2] 2.8 14.4 ns tf fall time cl = 10 pf [2] 4.5 6 ns output vref reference voltage iref = 100 a 0.8 1.2 1.3 v note [1]: vdd = 4.5 ... 5.5 v note [2]: vdd = 2.7 ... 3.3 v ou p ut ld lock detect (p in 14 ) s y m parameter condition min. t yp . max. unit vol voltage output low iol = 0.5 ma [1] 0.4 v vol voltage output low iol = 0.5 ma [2] 0.4 v tf fall time cl = 10 pf [1] 3.6 6 ns tf fall time cl = 10 pf [2] 4.5 10 ns note [1]: vdd = 4.5 ... 5.5 v note [2]: vdd = 2.7 ... 3.3 v
linear dimensions, inc. 445 east ohio street, chicago, il 60611 p 312.3211810 f 312.321.1830 pll-frequency synthesizer proposed data sheet characteristics (continued) out p ut mod modulus control out p ut ( p in 7 ) s y m parameter condition min. t yp . max. unit voh voltage output high ioh = - 0.5 ma [1] vdd - 0.4 v vol voltage output low ioh = - 0.5 ma [1] 0.4 v voh voltage output high ioh = - 0.3 ma [2] vdd - 0.4 v vol voltage output low ioh = - 0.3 ma [2] 0.4 v tr rise time cl = 10 pf [1] 2.6 18 ns tf fall time cl = 10 pf [1] 3 10 ns tr rise time cl = 10 pf [2] 2.8 30 ns tf fall time cl = 10 pf [2] 4.5 19 ns tphl propagation delay time h - l transition mod to vci cl = 5 pf [1] 10 12 ns tplh propagation delay time l - h transition mod to vci cl = 5 pf [1] 10 12 ns tphl propagation delay time h - l transition mod to vci cl = 5 pf [2] 19 22 ns tplh propagation delay time l - h transition mod to vci cl = 5 pf [2] 17 21 ns note [1]: vdd = 4.5 .. 5.5 v note [2]: vdd = 2.7 .. 3.3 v
linear dimensions, inc. 445 east ohio street, chicago, il 60611 p 312.3211810 f 312.321.1830 pll-frequency synthesizer proposed data sheet characteristics (continued) in p uts en (p in 3 ) , data (p in 4 ) , clk (p in 5 ) s y m parameter min. t yp . max. unit vil voltage input low 1.5 v vil voltage input low 1.5 v vih voltage input high 3.5 v vih voltage input high 3.5 v fclk clock frequency 10 mhz tr rise time clk 1 s tf fall time clk 1 s tclw clk pulse width (high) 60 ns tds data setup time 20 ns tcles clk-enable setup time 20 ns tecls enable-clk setup time 20 ns tenw en pulse width (high) 60 ns propagation delay time enable - port1 1 s not : these values are valid under the following conditions: vdd = 2.7 .. .5.5 v standb y pin overview po1 po2 ld pd mod phiv phivn standb y 1 low high high high resistance tristate low standb y 2 low high high high resistance tristate low
linear dimensions, inc. 445 east ohio street, chicago, il 60611 p 312.3211810 f 312.321.1830 pll-frequency synthesizer proposed data sheet phase detected output waveforms pinout
linear dimensions, inc. 445 east ohio street, chicago, il 60611 p 312.3211810 f 312.321.1830 pll-frequency synthesizer proposed data sheet package d h e a a1 l e b 123 package type d e h a a 1 e b l a package code sop nb 14 min max 8,56 8,89 3,81 4,09 5,79 6,40 1,35 2,01 0,08 0,30 1,27 0,33 0,51 0,30 1,27 10 dc14 quality data is available on request. contact: quality data thesys gesellschaft fr mikroelektronik mbh quality assurance haarbergstr. 67, 99097 erfurt, germany tel.: +49-361-4276155, fax: +49-361-4276060 important notice this data sheet contains preliminary information on new products. the specifications are subject to change without notice. verify with your local thesys sales office that you have the latest data sheet before finalizing a design. ordering information the th7010 pll synthesizer is available in a standard 14-pin sop package and for the operating range -40 c...+85 c (industrial). the order number is th7010i (i=industrial)

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