View AN1264_8349633.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/11 author: g. grasso may 2000 AN1264 application note serial communication rs232 with st52x420 introduction this application note presents a standard rs232 serial communication between st52x420 and a pc or another microcontroller. the assembler code provided at the end of the document could be easily ar- ranged to meet user specifications. the software was optimized in order to allow the user to embed these rx and tx subroutines in his main program. alternatively the software can be written by using the fuzzystudio tm 4.0 in a graphical envi- ronment instead of assembler instructions. rs232 protocol this asynchronous technique is the most used implementation of a communication channel between a pc and a low cost external device. the reason is due to the low numbers of copper wires and to the high emi immunity also for long distance connections. the complete standardized rs232 protocol uses some synchronisation/handshaking pins (dta, dtr,...etc) that allow a more powerful communication but, in this case, the electrical connection requires a 25-pin connector. among several ways to implement a serial communication by using the rs232 standard, a very utilized simplification is the half-duplex communication on 3 wires. half-duplex specification means that a commu- nication is possible in both directions but not simultaneously. the baud rate can vary among different val- ues but it should be the same for tx and rx. in this case, the electrical connection needs at least 3 wires that can be arranged into a 9 pins connector (standard db9 connector of a personal computer). from an electrical point of view, the pc serial port transmits a '1' as -3 to -25 volts and a '0' as +3 to +25 volts. therefore the serial port can have a maximum swing of 50v compared to the parallel port which has a maximum swing of 5v. due to this, cable losses and the inducted noise are not so problematic as for parallel cables. on the other hand, these electrical levels impose the use of level translators when a pc is interfaced to a digital device as a cmos/ttl microcontroller. common level translators are the max232, st232, etc which include a charge pump generating +10v and -10v from a single 5v supply. these i.c. also include two receivers and two transmitters in the same package.
AN1264 - application note 2/11 figure 1. st232 application circuit of course, if the serial communication links two microcontrollers or, in general, two digital cmos/ttl de- vices it is not necessary to use a level translator. from a logic point of view, the rs232 protocol consists in a sequence of bits that are arranged in a tem- poral frame as shown in figure 2. figure 2. rs232 data frame since a clock signal is not sent with the data, each frame is synchronized using its start bit, and an internal clock on each side of the serial link. a frame is always composed with two control bits ( 2 temporal slots) and 8 data bits (8 temporal slots) and optionally with other bits (parity, ninth bit). the time duration of each slot depends from the baud-rate cho- sen. for instance, 9600 baud (9600 bit/sec) means a time duration of 100 s for each bit. this must be taken into account when the internal clock of the transmitter/reiceiver is initialized. a transmission starts with a start bit which is 0. then, each bit is sent down the line, one at a time. the lsb (least significant bit) is sent first. a stop bit 1 is then appended to the signal to end the transmission. start bit stop bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 8-bit word length logic '1' logic '0' 0 volt level 5 volt level
3/11 AN1264 - application note software description the assembler code here described is intended as a subprogram that can be added to the user main pro- gram in order to perform also the rs232 serial communication. the assembler code is shared into two different call subroutines that are invoked from the main. the utilized resources in st52x420 are only 3 pins and an internal timer. the timer can be reconfigured on-fly after each transmission/reception in order to employ it for other purposes. since the start-bit has to be detected from the st52x420 (receiver) when the pc is transmitting, it is sug- gested to use the external interrupt pin of the st52x420 to recognize immediately the start of communi- cation. the hardware configuration is shown in figure 3. figure 3. hardware connections after the voltage translation, the signal coming from the pc can be read directly on the pin pa1 of st52x420. a second input pin (ext_int) is used to detect the falling edge of the start bit of the data frame. in this case, an inverter is used because the pin ext_int of st52x420 is sensitive only to the rising edges of a signal. if the ext_int pin is used for other purposes, the falling edge of the start-bit can be detected in polling mode directly on pa1. likewise, the transmission from st52x420 to pc is carried out on the pa0 pin. now, let us analyze the assembler code referred in the appendix. the code begins with the allocation of the interrupt vectors (0, 1, 2, ..) at predefined labels. the interrupt service routines are written at the end of the document, but these can be located anywhere. after these 5 lines the cpu and peripherals are ini- tialized. to understand these configurations please refer to the registers description in the st52x420 data- sheet. each configuration register is written with a ldcr instruction. this instruction will cause the load of a conf_reg from a ram register. following in the analysis, the main block is shown. the function of the main block is to produce a reply of the data received towards the transmitter. infact, the main sequentially invokes two subroutines for the reception and transmission of the same data. before to analyze the subroutines it is useful to observe the timer2 configuration. st52x420 provides three different autoreload timers with a 16-bit prescaler for each one. these timers can be configured as independent pwm generators or general purposes timers. in the current application, timer2 is used to count a fixed time period in order to clock each bit duration. st52x420 ext_int pa1 pa0 st232 0 5v 0 5v (-12v) (+12v) from pc to p c start bit
AN1264 - application note 4/11 figure 4. timer schematic blocks with a baud-rate of 9600 the timer has to count a duration of 100 s for each bit (double for 4800 baud, .. etc). to achieve this, a division ratio of 16 has been chosen for the prescaler. the ldrc 0 4 , ldcr 11 0 instructions will write the binary 0000 0100 into the conf_reg11. (see table 9.7 in the st52x420 data- sheet). by using a clock frequency for the device of 20 mhz (t=50ns) the output period of the timer 2 prescaler will be: tpsc = 50 ns x 16 = 0.8 s therefore a pulse wave with 0.8s period will feed the 8-bit counter witch will count between 0.8 s up to 204 s (1 255). in the subroutine, the timer2 counter register (output register 7 ) will be loaded with 40 and 128 in order to count for 32 s and 102 s for the reason that will be clarified later. a second configuration register (conf_reg10) for the timer 2 is the control register. by writing in this reg- ister the user can handle the start/stop, reset and interrupts signals of timer2. the instructions ldrc 0 64, ldcr 10 0 will set the peripheral in stop and reset mode and will enable the interrupt on the falling edge of the timerout (see table 9.6 of datasheet). reception task in the procedure implemented, the start bit of the coming data is detected by using the external interrupt. for this purpose, a flag (ram 3) is issued in the ext_int service routine. the rx subroutine checks if the flag is issued and starts with the sampling of the data on pa1. since the first coming bit (100 s) is the start bit, this does not need to be sampled. timer 2 is then set in order to count for 50 s. this means that the timer 2 will provide an interrupt at the center of the start bit. figure 5. sampling points the first data sampling will be performed after 100 s from the center of the start bit. this will read the logic level of the bit0 in its center. the same for the other bits until bit7. each time, the sampled bit is shift- ed to left in the data byte. of course the sampled data byte contains as msb the first bit sampled bit0, therefore the received byte has to be mirrored. 16 bit prescaler 8 bit counter output reg 7 interrupt on 120 m s count = 128 0.8 m s div:4 20mhz 50ns start bit stop bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 t 0 us 50 100 m s 100 m s
5/11 AN1264 - application note transmission task transmission is carried out on pin pa0. to set/reset this pin the user has to write the correct value on the port_a output register by using a ldpr instruction. the subroutine task starts by lowering the pa0 line for 100 s; after that, each bit of the byte (to be transmitted) is isolated and sent to pa0 for 100 s. the stop bit is sent to pa0 as last bit for the same time duration, therefore the line is released at the high level. conclusion this application note is intended to guide the user in the st52x420 assembler code. the rx/tx algorithm could be enhanced and modified in order to meet the users requirements. a second way to organize the algorithm is the use of the graphical environment fuzzystudio? 4.0 which allows a fast program development, debugging, simulation also for novice designers. references [1] st52x420 - datasheet, stmicroelectronics, 2000 [2] fuzzystudio tm 4.0 - user manual, stmicroelectronics, 2000 [3] st232 datasheet, stmicroelectronics, 1999
AN1264 - application note 6/11 appendix: st52x420 assembler code ;********************************************************************* ; ; purpose: rs232 with st52x420 ; ; author: fuzzy logic application group ; ;********************************************************************* ;******************************************************************* ;* transmission rs232 frame=9600baud(100us /bit) data=8bit, ;* 1 bit stop, 1 bit start ;* transmit on pa0 (pin 25) and receive on pa1 (pin24) ;* receive the start bit on "ext_int" (pin 5) ;**************************************************************** irq 0 ad_int irq 1 tim0 irq 2 tim1 irq 3 tim2 irq 4 ext_int ;******** peripheral and chip configurations ******** ldrc 0 17 ; load ram0("tmp") with "0001 0001" ldcr 0 0 ; move on reg_conf0 the ram0 content ; interrupt mask "nu(msb)|nu|nu|tim2|tim1|tim0|ad|ext_int" ; all masked unless ext_int e tim2 ldrc 0 27 ; priority configuration 0001 1011 ldcr 1 0 ; from the top: tim2, tim1, tim0, adc(lowest) ldrc 0 00001111b ldcr 2 0 ; watchdog configuration ; 9375*50ns*500= 234ms count wdtslp ; watchdog disabled ldrc 0 0 ldcr 3 0 ; adc configuration ; default settings ldrc 0 254 ldcr 4 0 ; port a configuration "1111 1110" ; only pa0 is output ldrc 0 0
7/11 AN1264 - application note ldcr 5 0 ; pwm-timer 0 configuration ; default settings ldrc 0 0 ldcr 6 0 ; pwm-timer 0 configuration ; default settings ldrc 0 0 ldcr 7 0 ; pwm-timer 0 configuration ; default settings ldrc 0 0 ldcr 8 0 ; pwm-timer 1 configuration ; default settings ldrc 0 0 ldcr 9 0 ; pwm-timer 1 configuration ; default settings ldrc 0 64 ldcr 10 0 ; pwm-timer 2 "tim/pwm(msb)|int|pe/ne/both/nu|nu|start/ stop|nu|timrst" ; tim2 is: reset,stop,int on falling of timout,no pwm ldrc 0 4 ldcr 11 0 ; pwm-timer 2 configuration "psc=0000 0100" ; outpsc=0,8us (timerout "pulse type") ldrc 0 0 ldcr 12 0 ; port a mode configuration ; configured as i/o , not as timers_out ldrc 0 0 ldcr 13 0 ; port b direction configuration ; all pins output ldrc 0 0 ldcr 14 0 ; port b mode configuration ; all pins digital ldrc 0 255 ldcr 15 0 ; port c direction configuration ; all pins input ldrc 0 255 ldcr 16 0 ; port c mode configuration ; pins as portc in input, not timerout(pc0 e' l'int) ldrc 0 255 ; ram0=1111 1111 ldpr 0 0 ; set all pins pa ;********* variables definition *********** ; ram0("tmp") temporary var ; ram1("datotx") data to transmit ; ram2("count") count sent digit ; ram3("flag") ; ram4("datorx") data received
AN1264 - application note 8/11 ; ram5("buffa") porta buffer ;********* main *********** start: ldrc 4 0 ; clear "datorx" ldrc 3 0 ; reset "flag" call rx mirror 4 ; mirror "datorx" i^ entry became lsb ldrc 2 8 ; init "count"=8 ldrc 0 0 ldrr 1 4 ; "datorx"="datotx" call tx ldrc 0 17 ; load "tmp" with "0001 0001" ldcr 0 0 ; enable ext_int jp start ;********* end main *********** ;======== reception call =============== rx: wt: ldrc 0 255 sub 0 3 ; sub ram0 with "flag". z is set if "flag"=255 jpnz wt ; infinite loop on transmitter start_bit ldrc 0 16 ; load "tmp" with "0001 0000" ldcr 0 0 ; disable ext_int ldrc 0 40 ; tim2_counter=56 (56 x 0.8us=45us) ldpr 7 0 ; 49us==> samples in the middle of next bit ldrc 0 69 ldcr 10 0 ; tim2 starts (with int) waiti ; skip start_bit int ldrc 0 64 ldcr 10 0 ; tim2 stop counting ldrc 0 128 ; tim2_counter=120 (120 x 0.8us=96 us) ldpr 7 0 ; i^ sample at 150us, ii^ sample at 250us ..etc ldrc 0 69 ldcr 10 0 ; tim2 start counting
9/11 AN1264 - application note ldrc 2 7 ; "count"=7 next: waiti ldri 5 9 ; read pa; move port_a contents in "buffa" ldrc 0 2 ; "tmp"=0000 0010=mask to isolate pa1 and 0 5 ; and between "tmp" and "buffa" asr 0 ; lsb"tmp"=last bit received add 4 0 ; adds "datorx" with last bit received asl 4 ; shift "datorx" left dec 2 ; decrement "count" jpnz next waiti ldri 5 9 ; read pa; move port_a contents in "buffa" ldrc 0 2 ; "tmp"=0000 0010=mask to isolate pa1 and 0 5 ; and between "tmp" and "buffa" asr 0 ; lsb"tmp"=last bit received add 4 0 ; adds "datorx" with last bit received waiti ldrc 0 64 ldcr 10 0 ; tim2 stop counting ret ;========= end call ========== ;========== transmission call ======== tx: ldpr 0 0 ; reset pin pa: start bit ldrc 0 125 ldpr 7 0 ; tim2_counter=128 (130 x 0.8us=104 us) ldrc 0 69 ldcr 10 0 ; tim2 start counting loop: waiti ; wait 100us for timer2_int ldrc 0 1 ; ram0=0000 0001 is the mask to isolate lsb and 0 1 ; and between "tmp" and lsb"datotx" ldpr 0 0 ; pa0=lsb of "datotx" asr 1 ; shift "datotx" for next int dec 2 ; decrement "count" jpnz loop
AN1264 - application note 10/11 waiti ldrc 0 1 ; stop bit (hi) ldpr 0 0 ; set pa0 waiti ldrc 0 64 ldcr 10 0 ; tim2 stop counting ret ;========= end call ========== ;**** ints subroutines ********* ext_int: ldrc 3 255 ;"flag"=255 reti ad_int: reti tim0: reti tim1: reti tim2: reti
11/11 AN1264 - application note information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved fuzzystudio tm is a registered trademark of stmicroelectronics stmicroelectronics group of companies http://www.st.com australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco- singapore - spain - sweden - switzerland - united kingdom - u.s.a.

▲Up To Search▲

Price & Availability of AN1264

	To Download AN1264 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .