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1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wme128k8-xxx january 2004 rev. 5 white electronic designs corp. reserves the right to change products or speci? cations without notice. january 2004 rev. 5 features read access times of 120, 140, 150, 200, 250, 300ns jedec approved packages ? 32 pin, hermetic ceramic, 0.600" dip (package 300) ? 32 lead, hermetic ceramic, 0.400" soj (package 101) commercial, industrial and military temperature ranges mil-std-883 compliant devices available write endurance 10,000 cycles data retention at 25c, 10 years low power cmos operation figure 1 C pin con? guration 32 dip 32 csoj top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v cc we# nc a14 a13 a8 a9 a11 oe# a10 cs# i/o7 i/o6 i/o5 i/o4 i/o3 128kx8 cmos monolithic eeprom, smd 5962-96796 pin description a0-16 address inputs i/o0-7 data input/output cs# chip selects oe# output enable we# write enable v cc +5.0v power v ss ground automatic page write operation ? internal address and data latches for 128 bytes ? internal control timer page write cycle time 10ms max. data polling for end of write detection hardware and software data protection ttl compatible inputs and outputs this product is subject to change without notice.
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wme128k8-xxx january 2004 rev. 5 white electronic designs corp. reserves the right to change products or speci? cations without notice. figure 2 C ac test circuit dc characteristics v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol conditions min max unit input leakage current i li v cc = 5.5, v in = gnd to v cc 10 a output leakage current i lo cs# = v ih , oe# = v ih , v out = gnd to v cc 10 a operating supply current i cc cs# = v il , oe# = v ih , f = 5mhz, v cc = 5.5 80 ma standby current i sb cs# = v ih , oe# = v ih , f = 5mhz, v cc = 5.5 0.625 ma output low voltage v ol i ol = 2.1ma, v cc = 4.5v 0.45 v output high voltage v oh i oh = -400a, v cc = 4.5v 2.4 v note: dc test conditions: v ih = v cc -0.3v, v il = 0.3v truth table cs# oe# we# mode data i/o h x x standby high z l l h read data out l h l write data in x h x out disable high z/data out x x h write x l x inhibit capacitance t a = +25c parameter symbol conditions max unit input capacitance c in v in = 0 v, f = 1mhz 20 pf output capacitance c out v i/o = 0 v, f = 1mhz 20 pf this parameter is guaranteed by design but not tested. absolute maximum ratings parameter symbol unit operating temperature t a -55 to +125 c storage temperature t stg -65 to +150 c signal voltage relative to gnd v g -0.6 to + 6.25 v voltage on oe# and a9 -0.6 to +13.5 v note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci? cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol min max unit supply voltage v cc 4.5 5.5 v input high voltage v ih 2.0 v cc + 0.3 v input low voltage v il -0.5 +0.8 v operating temp. (mil.) t a -55 +125 c operating temp. (ind.) t a -40 +85 c ac test conditions parameter typ unit input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z0 = 75 ? . v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. current source i oh i ol current source v z ~ 1.5v bipolar supply ~ d.u.t c eff = 50 pf
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wme128k8-xxx january 2004 rev. 5 white electronic designs corp. reserves the right to change products or speci? cations without notice. read figure 3 shows read cycle waveforms. a read cycle begins with selection address, chip select and output enable. chip select is accomplished by placing the cs# line low. output enable is done by placing the oe# line low. the memory places the selected data byte on i/o0 through i/o7 after the access time. the output of the memory is placed in a high impedance state shortly after either the oe# line or cs# line is returned to a high level. figure 3 C read waveforms t address cs# oe# output oh t df t acc t rc t oe t acs output valid address valid high z note: oe# may be delayed up to t acs - t oe after the falling edge of cs# without impact on t oe or by t acc - t oe after an address change without impact on t acc . ac read characteristics (see figure 3) v cc = 5.0v, v ss = 0v, -55c t a +125c read cycle parameter symbol -120 -140 -150 -200 -250 -300 unit min max min max min max min max min max min max read cycle time t rc 120 140 150 200 250 300 ns address access time t acc 120 140 150 200 250 300 ns chip select access time t acs 120 140 150 200 250 300 ns output hold from address change, oe# or cs# t oh 000000ns output enable to output valid t oe 050055055055085085ns chip select or oe# to high z output t df 60 70 70 70 70 70 ns
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wme128k8-xxx january 2004 rev. 5 white electronic designs corp. reserves the right to change products or speci? cations without notice. write cycle timing figures 4 and 5 show the write cycle timing relationships. a write cycle begins with address application, write enable and chip select. chip select is accomplished by placing the cs# line low. write enable consists of setting the we# line low. the write cycle begins when the last of either cs# or we# goes low. the we# line transition from high to low also initiates an internal 150sec delay timer to permit page mode operation. each subsequent we# transition from high to low that occurs before the completion of the 150sec time out will restart the timer from zero. the operation of the timer is the same as a retriggerable one-shot. write write operations are initiated when both cs# and we# are low and oe# is high. the eeprom devices support both a cs# and we# controlled write cycle. the address is latched by the falling edge of either cs# or we#, whichever occurs last. the data is latched internally by the rising edge of either cs# or we#, whichever occurs ? rst. a byte write operation will automatically continue to completion. ac write characteristics v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol 128kx8 unit min max write cycle time, typ = 6ms t wc 10 ms address set-up time t as 10 ns write pulse width (we# or cs#) t wp 100 ns chip select set-up time t cs 0ns address hold time t ah 100 ns data hold time t dh 10 ns chip select hold time t ch 0ns data set-up time t ds 50 ns output enable set-up time t oes 0ns output enable hold time t oeh 0ns write pulse width high t wph 50 ns
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wme128k8-xxx january 2004 rev. 5 white electronic designs corp. reserves the right to change products or speci? cations without notice. t address cs# we # data in dh t wph t wp t csh t oeh t ah t oes t as t cs oe# t wc t ds t address we # cs # data in dh t wph t wp t csh t oeh t ah t oes t as t cs oe# t ds t wc figure 4 C write waveforms we# controlled figure 5 C write waveforms cs# controlled
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wme128k8-xxx january 2004 rev. 5 white electronic designs corp. reserves the right to change products or speci? cations without notice. data polling the wme128k8-xxx offers a data polling feature which allows a faster method of writing to the device. figure 6 shows the timing diagram for this function. during a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on i/o7. once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the write cycle. figure 6 C data polling waveforms data polling characteristics v cc = 5.0v, v ss = 0v, -55c t a +125c parameter symbol min max unit data hold time tdh 10 ns oe# hold time toeh 10 ns oe# to output valid toe 55 ns write recovery time twr 0 ns we# t oeh t dh t oe t wr high z cs# oe# i/o 7 address toggle but characteristics (1) symbol parameter min max units tdh data hold time 10 ns toeh oe hold time 10 ns toe oe to output delay ns toehp oe high pulse 150 ns twr write recovery time 0 ns toggle bit: in addition to data# polling another method for determining the end of a write cycle is provided . during the write operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the write has completed, i/o6 will stop toggling and valid data will be read. reading the toggle bit may begin at any time during the write cycle. note: 1. toggling either oe# or cs# or both oe# and cs# will operate toggle bit. 2. beginning and ending state of i/o6 will vary 3. any address location may be used but the address should not vary. t wr high z t dh t oe t oeh we# cs# oe# i/o6 (2)
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wme128k8-xxx january 2004 rev. 5 white electronic designs corp. reserves the right to change products or speci? cations without notice. page write operation the wme128k8-xxx has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively loads during the internal programming period. successive bytes may be loaded in the same manner after the ? rst data byte has been loaded. an internal timer begins a time out operation at each write cycle. if another write cycle is completed within 150s or less, a new time out period begins. each write cycle restarts the delay period. the write cycles can be continued as long as the interval is less than the time out period. the usual procedure is to increment the least signi? cant address lines from a0 through a6 at each write cycle. in this manner a page of up to 128 bytes can be loaded in to the eeprom in a burst mode before beginning the relatively long interval programming cycle. after the 150s time out is completed, the eeprom begins an internal write cycle. during this cycle the entire page of bytes will be written at the same time. the internal programming cycle is the same regardless of the number of bytes accessed. figure 7 C page mode write waveforms page write characteristics v cc = 5.0v, v ss = 0v, -55c t a +125c page mode write characteristics symbol unit parameter min max write cycle time, typ = 6ms t wc 10 ms address set-up time t as 10 ns address hold time (1) t ah 100 ns data set-up time t ds 50 ns data hold time t dh 10 ns write pulse width t wp 100 ns byte load cycle time t blc 150 s write pulse width high t wph 50 ns 1. page address must remain valid for duration of write cycle. oe# byte 0 byte 1 byte 2 byte 3 valid data valid address t wc t blc t wph t wp address data cs# we# byte 127 t ds t dh t as t ah
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wme128k8-xxx january 2004 rev. 5 white electronic designs corp. reserves the right to change products or speci? cations without notice. figure 8 C software data protection enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a 16 - a 0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data to be loaded. writes enabled (2) enter data protect state load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data xx to any address (4) load last byte to last address
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wme128k8-xxx january 2004 rev. 5 white electronic designs corp. reserves the right to change products or speci? cations without notice. load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 20 to address 5555 load data xx to any address (4) load last byte to last address notes: 1. data format: i/o7 - i/o0 (hex); address format: a16 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded. figure 9 C software block data protection disable algorithm (1) exit data protect state (3) software data protection a software write protection feature may be enabled or disabled by the user. when shipped by white microelectronics, the wme128k8-xxx has the feature disabled. write access to the device is unrestricted. to enable software write protection, the user writes three access code bytes to three special internal locations. once write protection has been enabled, each write to the eeprom must use the same three byte write sequence to permit writing. after setting software data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc . the write protection feature can be disabled by a six byte write sequence of speci? c data to speci? c locations. power transitions will not reset the software write protection. the software write protection guards against inadvertent writes during power transitions or unauthorized modi? cation using a prom programmer. hardware data protection these features protect against inadvertent writes to the wme128k8-xxx. these are included to improve reliability during normal operation: a) v cc power on delay as v cc climbs past 3.8v typical the device will wait 5msec typical before allowing write cycles. b) v cc sense while below 3.8v typical write cycles are inhibited. c) write inhibiting holding oe# low and either cs# or we# high inhibits write cycles. d) noise ? lter pulses of <15ns (typ) on we# or cs# will not initiate a write cycle.
10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wme128k8-xxx january 2004 rev. 5 white electronic designs corp. reserves the right to change products or speci? cations without notice. all linear dimensions are millimeters and parenthetically in inches package 101: 32 lead, ceramic soj 1.27 (0.050) typ 21.1 (0.830) 0.25 (0.010) pin 1 identifier 19.1 (0.750) typ 11.3 (0.446) 0.2 (0.009) 3.96 (0.156) max 0.2 (0.008) 0.05 (0.002) 9.55 (0.376) 0.25 (0.010) 1.27 (0.050) 0.25 (0.010) 0.89 (0.035) radius typ package 300: 32 pin, ceramic dip, single cavity side brazed 42.4 (1.670) 0.4 (0.016) pin 1 identifier 0.84 (0.033) 0.4 (0.014) 4.34 (0.171) 0.79 (0.031) 15.04 (0.592) 0.3 (0.012) all linear dimensions are millimeters and parenthetically in inches
11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wme128k8-xxx january 2004 rev. 5 white electronic designs corp. reserves the right to change products or speci? cations without notice. ordering information device type speed package smd no. 128k x 8 eeprom monolithic 300ns 32 pin dip (c) 5962-96796 01hyx 128k x 8 eeprom monolithic 250ns 32 pin dip (c) 5962-96796 02hyx 128k x 8 eeprom monolithic 200ns 32 pin dip (c) 5962-96796 03hyx 128k x 8 eeprom monolithic 150ns 32 pin dip (c) 5962-96796 04hyx 128k x 8 eeprom monolithic 140ns 32 pin dip (c) 5962-96796 05hyx 128k x 8 eeprom monolithic 120ns 32 pin dip (c) 5962-96796 06hyx 128k x 8 eeprom monolithic 300ns 32 lead soj (de) 5962-96796 01hxx 128k x 8 eeprom monolithic 250ns 32 lead soj (de) 5962-96796 02hxx 128k x 8 eeprom monolithic 200ns 32 lead soj (de) 5962-96796 03hxx 128k x 8 eeprom monolithic 150ns 32 lead soj (de) 5962-96796 04hxx 128k x 8 eeprom monolithic 140ns 32 lead soj (de) 5962-96796 05hxx 128k x 8 eeprom monolithic 120ns 32 lead soj (de) 5962-96796 06hxx lead finish: blank = gold plated leads a = solder dip leads device grade: q = mil-std-883 compliant m = military screened -55c to +125c i = industrial -40c to +85c c = commercial 0c to +70c package type: c = 32 pin ceramic dip (package 300) de = 32 lead csoj (package 101) access time (ns) organization 128k x 8 eeprom monolithic white electronic designs corp. w m e 128k8 - xxx x x x

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