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cyrf6986 wirelessusb? lpstar 2.4 ghz radio soc cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-66073 rev. *d revised january 6, 2014 wirelessusb? lpstar 2.4 ghz radio soc features 2.4 ghz direct sequence spread spectrum (dsss) radio trans- ceiver operates in the unlicensed worldw ide industrial, scientific, and medical (ism) band (2.400 ghz to 2.483 ghz) on air compatible with second generation radio wirelessusb? lp and proc lp pin-to-pin compatible with wirelessusb lp except the pin30 and pin37 low power operating current: 21 ma (transmit at ?5 dbm) sleep current less than 1 ? a operating voltage: 2.7 v to 3.6 v fast startup and fast channel changes supports coin-cell operated applications reliable and robust receive sensitivity typical ?90 dbm autorate? ? dynamic data rate reception ? enables data reception for any of the supported bit rates automatically. ? dsss (250 kbps), gfsk (1 mbps) operating temperature: 0 c to 70 c closed-loop frequency synthesis for minimal frequency drift simple development auto transaction sequencer (ats): enables mcu to sleep longer framing, length, crc16, and auto ack separate 16-byte transmit and receive fifos receive signal strength indication (rssi) serial peripheral interface (spi) control while in sleep mode 4 mhz spi microcontroller interface bom savings low external component count battery voltage monitoring circuitry small footprint 40-pi n qfn (6 mm 6 mm) applications wireless keyboards and mice presentation tools wireless gamepads remote controls to y s fitness applications support see www.cypress.com for development tools, reference designs, and application notes. logic block diagram rf bias data interface and sequencer dsss baseband & framer spi frequency synthesizer gfsk demodulator gfsk modulator irq ss sck miso mosi rf p rf n rssi v dd v bat rst v cc power management gnd
cyrf6986 document number: 001-66073 rev. *d page 2 of 23 contents functional description ..................................................... 3 pinouts .............................................................................. 3 pin definitions .................................................................. 3 functional overview ........................................................ 4 data transmission modes ........................................... 4 link layer modes ........................................................ 4 packet buffers ............................................................. 5 auto transaction sequencer (ats) ............................ 5 functional block overview .............................................. 5 2.4 ghz radio ............................................................. 5 frequency synthesizer ................................................ 6 baseband and framer ................................................. 6 packet buffers and radio configuration registers ............................................ 6 spi interface ................................................................ 6 interrupts ..................................................................... 8 clocks ............ .............. .............. .............. ........... ......... 8 power management ............... .............. .............. ......... 8 low noise amplifier and received signal strength indication ................................... 8 application example ........................................................ 9 registers ......................................................................... 11 absolute maximum ratings .......................................... 12 operating conditions ..................................................... 12 dc characteristics ......................................................... 12 ac characteristics ......................................................... 13 spi interface .............................................................. 13 rf characteristics .......................................................... 14 typical operating characteristics ................................ 16 ac test loads and waveforms for digital pins .......... 18 ordering information ...................................................... 19 ordering code definitions ..... .................................... 19 package diagram ............................................................ 20 acronyms ........................................................................ 21 document conventions ................................................. 21 units of measure ....................................................... 21 document history page ................................................. 22 sales, solutions, and legal information ...................... 23 worldwide sales and design s upport ......... .............. 23 products .................................................................... 23 psoc? solutions ...................................................... 23 cypress developer community ................................. 23 technical support ................. .................................... 23
cyrf6986 document number: 001-66073 rev. *d page 3 of 23 functional description the cyrf6986 wirelessusb lpstar radio is a second generation me mber of the cypress wirelessusb radio system-on-chip (soc) family. the cyrf6986 ic adds a range of enhanced features, incl uding reduced supply current in all operating modes, reduced cry stal start up, synthesizer settling, and link turnaround times. pinouts figure 1. 40-pin qfn pinout rf bias nc nc v bat2 v cc v bat1 xtal v cc nc nc v cc nc nc v bat0 gnd nc nc v io v dd rst rf n nc nc v cc nc nc resv nc gnd rf p nc ss sck irq / gpio mosi / sdat miso / gpio xout / gpio nc nc nc * e-pad bottom side 21 22 23 24 25 26 27 28 29 30 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 40 39 38 37 36 35 34 33 32 31 1 cyrf6986 wirelessusb lpstar 40-pin qfn pin definitions pin number name type default description 1 xtal i i 12 mhz crystal. 2, 4, 5, 9, 14, 15, 17, 18, 20, 21, 22, 23, 31, 32, 36, 39 nc nc connect to gnd. 3, 7, 16, 40 v cc pwr v cc = 2.7 v to 3.6 v. 6, 8, 38 v bat(0-2) pwr v bat = 2.7 v to 3.6 v. main supply. 10 rf bias o o rf io 1.8 v reference voltage. 11 rf p i/o i differential rf signal to and from antenna. 12 gnd gnd ground. 13 rf n io i differential rf signal to and from antenna. 19 resv i must be connected to gnd. 24 ss i i spi enable, active low assert ion. enables and frames transfers. 25 sck i i spi clock. 26 irq i/o o interrupt output (configurable active high or low), or gpio. 27 mosi i/o i spi data input pin (master out slave in), or sdat.
cyrf6986 document number: 001-66073 rev. *d page 4 of 23 functional overview the cyrf6986 ic provides a complete wirelessusb spi to antenna wireless modems. the soc is designed to implement wireless device links operating in the worldwide 2.4 ghz ism frequency band. it is intended for systems compliant with worldwide regulations covered by etsi en 301 489-1 v1.41, etsi en 300 328-1 v1.3.1 (europe), fcc cfr 47 part 15 (usa and industry canada), and telec arib_t66_march, 2003 (japan). the soc contains a 2.4 ghz, 1 mbps gfsk radio transceiver, packet data buffering, packet fr amer, dsss baseband controller, received signal strength indication (rssi), and spi interface for data transfer and device configuration. the radio supports 98 discrete 1 mhz channels (regulations may limit the use of some of these channels in certain jurisdictions). the baseband performs dsss spre ading/despreading, start of packet (sop), end of packet (eop) detection, and crc16 generation and checking. the baseband may also be configured to automatically transmit acknowledge (ack) handshake packets whenever a valid packet is received. when in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates. this enables the implementation of mixed-rate systems in which different devices use different data rates. this also enables the implementation of dynamic data rate systems that use high data rates at shorter distances or in a low-moderate interference enviro nment or both. it changes to lower data rates at longer distances or in high interference environments or both. data transmission modes the soc supports two different data transmission modes: in gfsk mode, data is transmitted at 1 mbps, without any dsss. in dsss mode eight bits (8dr, 32-chip) are encoded in each derived code symbol transmitted, resulting in effective 250 kbps data rate. 32-chip pseudo noise (pn) codes are supported. the two data transmission modes apply to the dat a after the sop. in particular the length, data, and crc16 are all sent in the same mode. in general, dsss reduce packet error rate in any given environment. link layer modes the cyrf6986 ic device supports the following data packet framing features: sop packets begin with a two-symbol sop marker. if framing is disabled then an sop event is inferred whenever two successive correlations are detected. th e sop_code_adr code used for the sop is different from that us ed for the ?body? of the packet, and if desired may be a different length. sop must be configured to be the same length on both sides of the link. length length field is the first eight bits after the sop symbol, and is transmitted at the payload data rate. an eop condition is inferred after reception of the number of by tes defined in the length field, plus two bytes for the crc16. crc16 the device may be configured to append a 16 bit crc16 to each packet. the crc16 uses the usb crc polynomial with the added programmability of the seed. if enabled, the receiver verifies the calculated crc16 for the payload data against the received value in the crc16 field. the seed value for the crc16 calculation is configurable, and the crc16 transmitted may be calculated using either the loaded seed value or a zero seed; the received data crc16 is checked against both the configured and zero crc16 seeds. crc16 detects the following errors: any one bit in error. any two bits in error (irrespective of how far apart, which column, and so on). 28 miso i/o z spi data output pin (master in sl ave out), or gpio (in spi 3-pin mode). tri-states when spi 3pin = 0 and ss is deasserted. 29 xout i/o o buffered 0.75, 1.5, 3, 6, or 12 mhz clock or gpio. tri-states in sleep mode (conf igure as gpio drive low). 30 nc nc must be floating. 33 v io pwr i/o interface voltage, 2.7?3.6 v. 34 rst i i device reset. internal 10 k ? pull down resistor. active high, connect through a 0.47 ? f capacitor to v bat. must have rst = 1 event the first time power is applied to the radio. otherwise the stat e of the radio control registers is unknown. 35 v dd pwr decoupling pin for 1.8 v logic regulator, connect through a 0.47 ? f capacitor to gnd. 37 gnd gnd must be connected to ground. e-pad gnd gnd must be soldered to ground. pin definitions (continued) pin number name type default description
cyrf6986 document number: 001-66073 rev. *d page 5 of 23 any odd number of bits in error (irrespective of the location). an error burst as wide as the checksum itself. figure 2 shows an example packet with sop, crc16, and lengths fields enabled, and figure 3 shows a standard ack packet. figure 2. example packet format figure 3. exampl e ack packet format packet buffers all data transmission and reception use the 16 byte packet buffers - one for transmission and one for reception. the transmit buffer allows loading a complete packet of up to 16 bytes of payload data in one burst spi transaction. this is then transmitted with no further mcu intervention. similarly, the receive buffer allows receiving an entire packet of payload data up to 16 bytes with no firmware intervention required until the packet reception is complete. the cyrf6986 ic supports packets up to 255 bytes. however, the actual maximum packet length depends on the accuracy of the clock on each end of the link and the data mode. interrupts are provided to allow an mcu to use the transmit and receive buffers as fifos. when transmitting a packet longer than 16 bytes, the mcu can load 16 bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. similarly, when receiving packets longer than 16 bytes, the mcu must fetch received data from the fifo periodically during packet reception to prevent it from overflowing. auto transaction sequencer (ats) the cyrf6986 ic provides automated support for transmission and reception of acknowledged data packets. when transmitting in transaction mode, the device automatically: starts the crystal and synthesizer enters transmit mode transmits the packet in the transmit buffer transitions to receive mode and waits for an ack packet transitions to the transaction end state when an ack packet is received or a timeout period expires similarly, when receiving in transaction mode, the device automatically: waits in receive mode for a valid packet to be received transitions to transmit mode, transmits an ack packet transitions to the transaction end state (receive mode to await the next packet, and so on.) the contents of the packet buffers are not affected by the transmission or reception of ack packets. in each case, the entire packet transaction takes place without any need for mcu firmware action (as long as packets of 16 bytes or less are used). to transmit data, the mcu must load the data packet to be transmitted, se t the length, and set the tx go bit. similarly, when receiving packets in transaction mode, firmware must retrieve the full y received packet in response to an interrupt request indicating reception of a packet. data rates the cyrf6986 ic supports the following data rates by combining the pn code lengths and data transmission modes described in the previous sections: 1000 kbps (gfsk) 250 kbps (32 chip 8dr) functional block overview 2.4 ghz radio the radio transceiver is a dual conversion low if architecture optimized for power, range, and robustness. the radio employs channel-matched filters to achieve high performance in the presence of interference. an integrated power amplifier (pa) provides up to 0 dbm transmit power, with an output power preamble sop1 sop2 <== p a y l o a d ==> crc 16 length preamble n*16us 1st framing symbol* 2nd framing symbol* packet length 1 byte period *note: 32 us preamble sop1 sop2 crc 16 preamble n*16us 1st framing symbol* 2nd framing symbol* c r c field from received packet. 2 byte periods *note: 32 us
cyrf6986 document number: 001-66073 rev. *d page 6 of 23 control range of 35 db in six steps. the supply current of the device is reduced as the rf output power is reduced. frequency synthesizer before transmission or reception may begin, the frequency synthesizer must settle. the settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100 ? s. the ?fast channels? (less than 100 ? s settling time) are every third channel, starting at 0 up to and including 72 (for example, 0, 3, 6, 9 ?. 69, 72). baseband and framer the baseband and framer bloc ks provide the dsss encoding and decoding, sop generatio n and reception, crc16 generation and checking, and eop detection and length field. packet buffers and radio configuration registers packet data and configuration registers are accessed through the spi interface. all confi guration registers are directly addressed through the address field in the spi packet. configuration register s allow configuration of dsss pn codes, data rate, operating mode, inte rrupt masks, inte rrupt status, and so on. spi interface the cyrf6986 ic has an spi interface supporting communication between an application mcu and one or more slave devices (including the cyrf6986). the spi interface supports single-byte and multi-byte serial transfers using either 4-pin or 3-pin interfacing. th e spi communications interface consists of slave select (ss ), serial clock (sck), master out-slave in (mosi), master in-s lave out (miso), or serial data (sdat). spi communication may be described as the following: ? command direction (bit 7) = ?1? enables spi write transaction. a ?0? enables spi read transactions. ? command increment (bit 6) = ?1? enables spi auto address increment. when set, the address field automatically increments at the end of each data byte in a burst access. otherwise the same address is accessed. ? six bits of address ? eight bits of data the device receives sck from an application mcu on the sck pin. data from the application mcu is shifted in on the mosi pin. data to the application mcu is sh ifted out on the miso pin. the active low slave select (ss ) pin must be asserted to initiate an spi transfer. the application mcu can initia te spi data transfers using a multi-byte transaction. the first byte is the command/address byte, and the following bytes are the data bytes shown in table 2 through figure 6 on page 7 . the spi communications interface has a burst mechanism, where the first byte can be followed by as many data bytes as required. a burst transaction is terminated by deasserting the slave select (ss = 1). the spi communications interface single read and burst read sequences are shown in figure 4 on page 7 and figure 5 on page 7 , respectively. the spi communications interfac e single write and burst write sequences are shown in figure 6 on page 7 and figure 7 on page 7 , respectively. this interface may be optionally operated in a 3-pin mode with the miso and mosi functions combined in a single bidirectional data pin (sdat). when using 3-pin mode, user firmware must ensure that the mosi pin on the mcu is in a high impedance state except when mosi is actively transmitting data. the device registers may be writte n to or read from one byte at a time, or several sequential regi ster locations may be written or read in a single spi transaction using incrementing burst mode. in addition to single byte configuration registers, the device includes register files. regist er files are fifos written to and read from using nonincrementi ng burst spi transactions. the irq pin function may be optionally multiplexed onto the mosi pin. when this option is enabled, the irq function is not available while the ss pin is low. when using this configuration, user firmware must ensure that the mosi pin on the mcu is in a high impedance state whenever the ss pin is high. the spi interface is not dependent on the internal 12 mhz clock. registers may therefore be read fr om or written to when the device is in sleep mode, and the 12 mhz oscillator disabled. the spi interface and the irq and rst pins have a separate voltage reference pin (v io ). this enables the device to interface directly to mcus operating at voltages below the cyrf6986 ic supply voltage. table 1. internal pa output power step table pa setting typical output power (dbm) 60 5?5 4?13 3?18 2?24 1?30 0?35 table 2. spi transaction format parameter byte 1 byte 1+n bit # 7 6 [5:0] [7:0] bit name dir inc address data
cyrf6986 document number: 001-66073 rev. *d page 7 of 23 figure 4. spi single read sequence figure 5. spi incrementing burst read sequence figure 6. spi single write sequence figure 7. spi incrementing burst write sequence dir 0 inca5a4a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 sck mosi ss miso cmd addr data to mcu dir 0 inca5a4a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 data to mcu 1 cmd addr data to mcu 1+n sck mosi ss miso dir 1 inca5a4a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 sck mosi ss miso cmd addr data from mcu dir 1 inca5a4a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 sck mosi ss miso cmd addr data from mcu 1 d7 d6 d5 d4 d3 d2 d1 d0 data from mcu 1+n
cyrf6986 document number: 001-66073 rev. *d page 8 of 23 interrupts the device provides an interrupt (irq) output, which is configurable to indicate the occurrence of various different events. the irq pin may be programmed to be either active high or active low, and be eith er a cmos or open drain output. the available interrupts are described in the section registers on page 11 . the cyrf6986 ic features three sets of interrupts: transmit, receive, and system interrupts. these interrupt s all share a single pin (irq), but can be i ndependently enabled or disabled. the contents of the enable registers are preserved when switching between transmit and receive modes. if more than one interrupt is enabled at any time, it is necessary to read the relevant status register to determine which event caused the irq pin to assert. even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status register. it is therefore possible to use the devices without the irq pin, by polling the status registers to wait for an event, rather than using the irq pin. clocks a 12 mhz crystal (30 ppm or better) is directly connected between xtal and gnd without the need for external capacitors. a digital clock out function is provided, with selectable output frequencies of 0. 75, 1.5, 3, 6, or 12 mhz. this output may be used to clock an external microcontroller (mcu) or asic. this output is enabled by default, but may be disabled. the requirements to directly connect the crystal to the xtal pin and gnd are: nominal frequency: 12 mhz operating mode: fundamental mode resonance mode: parallel resonant frequency stability: 30 ppm series resistance: < 60 ohms load capacitance: 10 pf drive level: 100 w power management the operating voltage of the devi ce is 2.7 v to 3.6 v dc, which is applied to the v bat pin. the device can be shut down to a fully static sleep mode by writing to the frc end = 1 and end state = 000 bits in the xact_cfg_adr register over the spi interface. the device enters sleep mode within 35 s after the last sck positive edge at t he end of this spi transaction. alternatively, the device ma y be configured to automatically enter sleep mode after completing the packet transmission or reception. when in sleep mode, t he on-chip oscillator is stopped, but the spi interface remains functional. the device wakes from sleep mode automatically when the device is commanded to enter transmit or receive mode. when resuming from sleep mode, there is a short delay while the oscillator restarts. the device can be configured to assert the irq pin when the oscillator has stabilized. low noise amplifier and received signal strength indication the gain of the receiver can be controlled directly by clearing the agc en bit and writing to the low noise amplifier (lna) bit of the rx_cfg_adr register. clearing the lna bit reduces the receiver gain approximately 20 db, allowing accurate reception of very strong received signals (for example, when operating a receiver very close to the trans mitter). approximately 30 db of receiver attenuation can be added by setting the attenuation (att) bit. this limits data reception to devices at very short ranges. disabling agc and enabling lna is recommended, unless receiving from a device using external pa.when the device is in receive mode the rssi_adr register returns the relative signal strength of the on-channel signal power. when receiving, the device autom atically measures and stores the relative strength of the signal being received as a five bit value. an rssi reading is taken automatically when the sop is detected. in addition, a new rssi reading is taken every time the previous reading is read from the rssi_adr register, allowing the background rf energy level on any given channel to be easily measured when rssi is read while no signal is being received. a new reading can occur as fast as once every 12 s. received.
cyrf6986 document number: 001-66073 rev. *d page 9 of 23 application example sw1 vbus nss sck miso mosi irq sw1 nled1 nled2 rst nled1 nled2 irq rst mosi sck nss miso dp dm 5v vcc_3.3v vcc_3.3v 5v vcc_3.3v vcc_3.3v vcc_3.3v vcc_3.3v vbat vbat "bind" power supply "connect/activity" note1:e-pad must be soldered to ground note2:pin30 must be floating. 0805 c13 4.7 ufd 0805 c13 4.7 ufd 1 2 ant1 wiggle 32 ant1 wiggle 32 1 2 tv1 tv-20r tv1 tv-20r 0402 r1 zero 0402 r1 zero 0402 c10 0.047 ufd 0402 c10 0.047 ufd 1 2 0603 c12 1500pfd 0603 c12 1500pfd 1 2 0402 c5 0.47 ufd 0402 c5 0.47 ufd 1 2 0402 c3 2.0 pfd 0402 c3 2.0 pfd ind0603 l1 22 nh ind0603 l1 22 nh 1 2 0402 c8 0.047 ufd 0402 c8 0.047 ufd 1 2 j1 usb a ra plug smd j1 usb a ra plug smd vbus 1 dm 2 dp 3 gnd 4 s1 5 s2 6 u2 cy7c64315 u2 cy7c64315 dm 7 dp 6 xres 11 p1[1]/mosi/issp_sclk 4 p1[5]/miso 3 p1[7]/spi_ss 2 p2[3] 1 p2[5] 16 p0[1] 15 vss 5 vcc 8 p0[4] 12 p1[4] 10 p1[0]/spi_sclk/issp_sda 9 p0[7] 13 p0[3] 14 ind0402 l2 1.8 nh ind0402 l2 1.8 nh 1 2 0402 r5 22 ohm 0402 r5 22 ohm d1 led green red d1 led green red gr 1 rd 2 kg 3 kr 4 y1 12 mhz crystal y1 12 mhz crystal 1 2 0402 c6 0.047 ufd 0402 c6 0.047 ufd 1 2 s1 sw ra push s1 sw ra push 1a 1b 2a 2b 0402 c9 0.047 ufd 0402 c9 0.047 ufd 1 2 0402 c4 1.5 pfd 0402 c4 1.5 pfd 1 2 0402 r2 620 ohm 0402 r2 620 ohm 1 2 0402 c15 0.47ufd 0402 c15 0.47ufd u1 cyrf6986 u1 cyrf6986 nc15 36 nc2 4 vbat2 8 resv 19 vcc3 16 nc9 20 nc1 2 sck 25 mosi 27 irq 26 xout 29 rst 34 miso 28 vcc1 3 vcc2 7 nc3 5 rfn 13 vbat1 6 gnd 37 xtal 1 ss 24 nc16 39 vcc4 40 e-pad 41 vdd 35 nc4 9 nc5 14 rfbias 10 rfp 11 gnd1 12 nc6 15 nc7 17 nc8 18 nc10 21 nc17 30 nc11 22 vio 33 nc12 23 nc13 31 nc14 32 vbat0 38 0402 c11 0.047 ufd 0402 c11 0.047 ufd 1 2 0402 c7 0.047 ufd 0402 c7 0.047 ufd 1 2 0805 c16 10 ufd 0805 c16 10 ufd 0402 r6 22 ohm 0402 r6 22 ohm 0402 c1 15 pfd 0402 c1 15 pfd 0805 c14 2.2 ufd 0805 c14 2.2 ufd
cyrf6986 document number: 001-66073 rev. *d page 10 of 23 table 3. recommended bom item qty cy part number reference description manufacturer mfr part number 1 1 na ant1 2.5 ghz h-stub wiggle antenna for 32 mil pcb na na 2 1 730-10012 c1 cap 15 pf 50 v ceramic npo 0402 panasonic ecj-0ec1h150j 3 1 730-11955 c3 cap 2.0 pf 50 v ceramic npo 0402 kemet c0402c209c5gactu 4 1 730-11398 c4 cap 1.5 pf 50 v ceramic npo 0402 smd panasonic ecj-0ec1h1r5c 5 1 730-13322 c5, c15 cap 0.47 uf 6.3 v ceramic x5r 0402 murata grm155r60j474ke19d 6 6 730-13404 c6,c7,c8,c 9,c10,c11 cap 0.047 uf 16 v ceramic x5r 0402 avx 0402yd473kat2a 7 1 730-11953 c12 cap 1500 pf 50 v ceramic x7r 0402 kemet c0402c152k5ractu 8 1 730-13040 c13 cap ceramic 4.7 uf 6.3 v xr5 0805 kemet c0805c475k9pactu 9 1 730-12003 c14 cap cer 2.2 uf 10 v 10% x7r 0805 murata electronics north america grm21br71a225ka01l 10 1 na c16 cap ceramic 10 uf 6.3 v xr5 0805 na na 11 1 800-13333 d1 led green/red bico lor 1210 smd liteon ltst-c155kgjrkt 12 1 420-13046 j1 conn usb plug t ype a pcb smt acon uar72-4n5j10 13 1 800-13401 l1 inductor 22nh 2% fixed 0603 smd panasonic - ecg elj-re22ngf2 14 1 800-11651 l2 inductor 1.8nh +-.3nh fixed 0402 smd panasonic - ecg elj-rf1n8df 15 1 610-10343 r1 res zero ohm 1/16w 0402 smd panasonic - ecg erj-2ge0r00x 16 1 610-13472 r2 res chip 620 ohm 1/16w 5% 0402 smd panasonic - ecg erj-2gej621x 17 1 200-13471 s1 switch lt 3.5 mm x 2.9mm 160gf smd panasonic - ecg evq-p7j01k 18 1 cyrf6986- 40lfc u1 ic, lpstar 2.4 ghz radio soc qfn-40 cypress semiconductor cyrf6986 19 1 cy7c64315 u2 ic en core v full-speed usb controller cypress semiconductor cy7c64315 20 1 800-13259 y1 crystal 12.00 mhz hc49 smd ecera gf-1200008 21 1 xxx-xxxx-x pcb printed circuit board cypress semiconductor xxx-xxxx-x
cyrf6986 document number: 001-66073 rev. *d page 11 of 23 registers all registers are read and writable, except where noted. registers may be written to or read from individually or in sequential groups. [1, 2] table 4. register map summary address mnemonic b7 b6 b5 b4 b3 b2 b1 b0 default [1] access [1] 0x00 channel_adr not used channel -1001000 -bbbbbbb 0x01 tx_length_adr tx length 00000000 bbbbbbbb 0x02 tx_ctrl_adr tx go tx clr txb15 irqen txb8 irqen txb0 irqen txberr irqen txc irqen txe irqen 00000011 bbbbbbbb 0x03 tx_cfg_adr not used not used data code length rsvd data mode pa setting --000101 --bbbbbb 0x04 tx_irq_status_adr os irq rsvd txb15 irq txb8 irq txb0 irq txberr irq txc irq txe irq -------- rrrrrrrr 0x05 rx_ctrl_adr rx go rsvd rxb16 irqen rxb8 irqen rxb1 irqen rxberr irqen rxc irqen rxe irqen 00000111 bbbbbbbb 0x06 rx_cfg_adr agc en lna att hilo fast turn en not used rxow en vld en 10010-10 bbbbb-bb 0x07 rx_irq_status_adr rxow irq sopdet irq rxb16 irq rxb8 irq rxb1 irq rxberr irq rxc irq rxe irq -------- brrrrrrr 0x08 rx_status_adr rx ack pkt err eop err crc0 bad crc rx code rx data mode -------- rrrrrrrr 0x09 rx_count_adr rx count 00000000 rrrrrrrr 0x0a rx_length_adr rx length 00000000 rrrrrrrr 0x0b pwr_ctrl_adr the firmware should set ? 00010000? to this register while initiating 10100000 bbbbbbbb 0x0c xtal_ctrl_adr xout fn xsirq en not used not used freq 000--100 bbb--bbb 0x0d io_cfg_adr irq od irq pol miso od xout od rsvd rsvd spi 3pin irq gpio 00000000 bbbbbbbb 0x0e gpio_ctrl_adr xout op miso op rsvd irq op xout ip miso ip rsvd irq ip 0000---- bbbbrrrr 0x0f xact_cfg_adr ack en not used frc end end state ack to 1-000000 b-bbbbbb 0x10 framing_cfg_adr sop en sop len len en sop th 10100101 bbbbbbbb 0x11 data32_thold_adr not used not used not used not used th32 ----0100 ----bbbb 0x12 data64_thold_adr not used not used not used th64 ---01010 ---bbbbb 0x13 rssi_adr sop not used lna rssi 0-100000 r-rrrrrr 0x14 eop_ctrl_adr [3] hen hint eop 10100100 bbbbbbbb 0x15 crc_seed_lsb_adr crc seed lsb 00000000 bbbbbbbb 0x16 crc_seed_msb_adr crc seed msb 00000000 bbbbbbbb 0x17 tx_crc_lsb_adr crc lsb -------- rrrrrrrr 0x18 tx_crc_msb_adr crc msb -------- rrrrrrrr 0x19 rx_crc_lsb_adr crc lsb 11111111 rrrrrrrr 0x1a rx_crc_msb_adr crc msb 11111111 rrrrrrrr 0x1b tx_offset_lsb_adr strim lsb 00000000 bbbbbbbb 0x1c tx_offset_msb_adr not used not used not used not used strim msb ----0000 ----bbbb 0x1d mode_override_adr rsvd rsvd frc sen frc awake not used not used rst 00000--0 wwwww--w 0x1e rx_override_adr ack rx rxtx dly man rxack frc rxdr dis crc0 dis rxcrc ace not used 0000000- bbbbbbb- 0x1f tx_override_adr ack tx frc pre rsvd man txack ovrd ack dis txcrc rsvd tx inv 00000000 bbbbbbbb 0x26 xtal_cfg_adr rsvd rsvd rsvd rsvd start dly rsvd rsvd rsvd 00000000 wwwwwwww 0x27 clk_override_adr rsvd rsvd rsvd rsvd rsvd rsvd rxf rsvd 00000000 wwwwwwww 0x28 clk_en_adr rsvd rsvd rsvd rsvd rsvd rsvd rxf rsvd 00000000 wwwwwwww 0x29 rx_abort_adr rsvd rsvd abort en rsvd rsvd rsvd rsvd rsvd 00000000 wwwwwwww 0x32 auto_cal_time_adr auto_cal_time 00000011 wwwwwwww 0x35 auto_cal_offset_adr auto_cal_offset 00000000 wwwwwwww 0x39 analog_ctrl_adr rsvd rsvd rsvd rsvd rsvd rsvd rx inv all slow 00000000 wwwwwwww register files 0x20 tx_buffer_adr tx buffer file -------- wwwwwwww 0x21 rx_buffer_adr rx buffer file -------- rrrrrrrr 0x22 sop_code_adr sop code file note 4 bbbbbbbb 0x23 data_code_adr data code file note 5 bbbbbbbb 0x24 preamble_adr preamble file note 6 bbbbbbbb 0x25 mfg_id_adr mfg id file na rrrrrrrr notes 1. b = read/write; r = read only; w = write only; ?-? = not used, default value is undefined. 2. registers must be configured or accessed only when the radio is in idle or sleep mode. the gpios, and rssi registers can be a ccessed in active tx and rx mode. 3. eop_ctrl_adr[6:4] must never have the value of ?000? , that is, eop hint symbol count must never be ?0? 4. sop_code_adr default = 0x17ff9e213690c782. 5. data_code_adr default = 0x02f9939702fa5ce3012bf1db0132be6f. 6. preamble_adr default = 0x333302.
cyrf6986 document number: 001-66073 rev. *d page 12 of 23 absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ..... ............... ............... ?55 c to +125 c supply voltage on any power supply pin relative to v ss ..............................................?0.3 v to +3.9 v dc voltage to logic inputs [8] ................. ?0.3 v to v io +0.3 v dc voltage applied to outputs in high-z state ...................................... ?0.3 v to v io +0.3 v static discharge voltage (digital) [9] ......................... >2000 v static discharge voltage (rf) [9] ................................ 1100 v latch-up current .....................................+200 ma, ?200 ma operating conditions v cc ................................................................. 2.7 v to 3.6 v v io ...................................................................2.7 v to 3.6 v v bat .................................................................2.7 v to 3.6 v t a (ambient temperature under bias) .......... 0 c to +70 c ground voltage ................................................................ 0 v f osc (crystal frequency) .......................... 12 mhz 30 ppm dc characteristics (t = 25 ? c, v bat = 2.7 v, f osc = 12.000000 mhz) parameter description conditions min typ max unit v bat battery voltage 0?70 ? c 2.7 ? 3.6 v v io [10] v io voltage 2.7 ? 3.6 v v cc v cc voltage 0?70 ? c 2.7 ? 3.6 v v oh1 output high voltage condition 1 at i oh = ?100.0 a v io ? 0.2 v io ?v v oh2 output high voltage condition 2 at i oh = ?2.0 ma v io ? 0.4 v io ?v v ol output low voltage at i ol = 2.0 ma ? 0 0.45 v v ih input high voltage 0.7 v io v io v v il input low voltage 0 0.3 v io v i il input leakage current 0 < v in < v io ?1 0.26 +1 a c in pin input capacitance except xtal, rf n , rf p , rf bias ? 3.5 10 pf i cc (gfsk) [11] average tx i cc , 1 mbps, slow channel pa = 5, 2 way, 4 bytes/10 ms ? 0.87 ? ma i cc (32-8dr) [11] average tx i cc , 250 kbps, fast channel pa = 5, 2 way, 4 bytes/10 ms ? 1.2 ? ma i sb [12] sleep mode i cc ? 0.8 10 a idle i cc radio off, xtal active xout disabled ? 1.0 ? ma i synth i cc during synth start ? 8.4 ? ma tx i cc i cc during transmit pa = 5 (?5 dbm) ? 20.8 ? ma tx i cc i cc during transmit pa = 6 (0 dbm) ? 26.2 ? ma rx i cc i cc during receive lna off, att on ? 18.4 ? ma rx i cc i cc during receive lna on, att off ? 21.2 ? ma notes 8. it is permissible to connect voltages above v io to inputs through a series resistor limiting input current to 1 ma. ac timing not guaranteed. 9. human body model (hbm). 10. in sleep mode, the io interface voltage reference is v bat . 11. includes current drawn while starting crystal, starting synthesizer, transmitting packet (including sop and crc16), changing to receive mode, and receiving ack handshake. device is in sleep e xcept during this transaction. 12. isb is not guaranteed if any io pin is connected to voltages higher than v io .
cyrf6986 document number: 001-66073 rev. *d page 13 of 23 figure 8. spi timing ac characteristics spi interface parameter [13, 14] description min typ max unit t sck_cyc spi clock period 238.1 ? ? ns t sck_hi spi clock high time 100 ? ? ns t sck_lo spi clock low time 100 ? ? ns t dat_su spi input data setup time 25 ? ? ns t dat_hld spi input data hold time 10 ? ? ns t dat_val spi output data valid time 0 ? 50 ns t dat_val_tri spi output data tri-state (mosi from slave select deassert) ? ? 20 ns t ss_su spi slave select setup time befo re first positive edge of sck [15] 10 ? ? ns t ss_hld spi slave select hold time after last negative edge of sck 10 ? ? ns t ss_pw spi slave select mi nimum pulse width 20 ? ? ns t sck_su spi slave select setup time 10 ? ? ns t sck_hld spi sck hold time 10 ? ? ns t reset minimum rst pin pulse width 10 ? ? ns sck nss mosi input mi so mosi output t sck_hi t sck_lo t ss_su t sck_su t sck_cyc t ss_hld t sck_hld t dat_su t dat_hld t dat_val t dat_val_tri notes 13. ac values are not guaranteed if voltage on any pin exceeding v io . 14. c load = 30 pf 15. sck must start low at the time ss goes low, otherwise the success of spi transactions are not guaranteed.
cyrf6986 document number: 001-66073 rev. *d page 14 of 23 rf characteristics table 5. radio parameters parameter description conditions min typ max unit rf frequency range note 19 2.400 ? 2.497 ghz receiver (t = 25 c, v cc = v bat = 3.0 v, f osc = 12.000000 mhz, ber < 1e-3) sensitivity 250 kbps 32-8dr ber 1e-3 ? ?90 ? dbm sensitivity gfsk ber 1e-3, all slow = 1 ? ?84 ? dbm lna gain ? 22.8 ? db att gain ??31.7? db maximum received signal lna on ?15 ?6 ? dbm rssi value for pwr in ?60 dbm lna on ? 21 ? count rssi slope ? 1.9 ? db/count interference performance (cer 1e-3) co-channel interference rejection carrier-to-interf erence (c/i) c = ?60 dbm ? 9 ? db adjacent (1 mhz) channel selectivity c/i 1 mhz c = ?60 dbm ? 3 ? db adjacent (2 mhz) channel selectivity c/i 2 mhz c = ?60 dbm ? ?30 ? db adjacent (> 3 mhz) channel selectivity c/i > 3 mhz c = ?67 dbm ? ?38 ? db out-of-band blocking 30 mhz?12.75 mhz [20] c = ?67 dbm ? ?30 ? dbm inter modulation c = ?64 dbm, ? f = 5,10 mhz ? ?36 ? dbm receive spurious emission 800 mhz 100 khz resbw ? ?79 ? dbm 1.6 ghz 100 khz resbw ? ?71 ? dbm 3.2 ghz 100 khz resbw ? ?65 ? dbm transmitter (t = 25 c, v cc = 3.0 v) maximum rf transmit power pa = 6 ?2 0 +2 dbm maximum rf transmit power pa = 5 ?7 ?5 ?3 dbm maximum rf transmit power pa = 0 ? ?35 dbm rf power control range ? 35 db rf power range control step size six steps, monotonic ? 5.6 db frequency deviation min pn code pattern 10101010 ? 270 khz frequency deviation max pn code pattern 1111 0000 ? 323 khz error vector magnitude (fsk error) >0 dbm ? 10 ? %rms occupied bandwidth ?6 dbc, 100 khz resbw 500 876 ? khz notes 19. subject to regulation. 20. exceptions f/3 & 5c/3.
cyrf6986 document number: 001-66073 rev. *d page 15 of 23 transmit spurious emission (pa = 6) in-band spurious second channel power (2 mhz) ? ?38 ? dbm in-band spurious third channel power (> 3 mhz) ? ?44 ? dbm non-harmonically related spurs (800 mhz) ? ?38 ? dbm non-harmonically related spurs (1.6 ghz) ? ?34 ? dbm non-harmonically related spurs (3.2 ghz) ? ?47 ? dbm harmonic spurs (second harmonic) ? ?43 ? dbm harmonic spurs (third harmonic) ? ?48 ? dbm fourth and greater harmonics ? ?59 ? dbm power management (crystal pn# ecera gf-1200008) crystal start to 10 ppm ? 0.7 1.3 ms crystal start to irq xsirq en = 1 ? 0.6 ? ms synth settle slow channels ? ? 270 s synth settle medium channels ? ? 180 s synth settle fast channels ? ? 100 s link turnaround time gfsk ? ? 30 s link turnaround time 250 kbps ? ? 62 s max packet length <60 ppm cr ystal-to-crystal ? ? 40 bytes table 5. radio parameters (continued) parameter description conditions min typ max unit
cyrf6986 document number: 001-66073 rev. *d page 16 of 23 typical operating characteristics figure 9. typical operating characteristics [21] 0 8 16 24 32 -120 -100 -80 -60 -40 -20 rssi count input power (dbm) typical rssi count vs. input power -15 -13 -11 -9 -7 -5 -3 -1 1 2.7 2.9 3.1 3.3 3.5 output power (dbm) vcc transmit power vs. vcc -15 -13 -11 -9 -7 -5 -3 -1 1 0204060 output power (dbm) temp (deg c) transmit power vs. temperature (vcc = 2.7 v) -15 -13 -11 -9 -7 -5 -3 -1 1 0 20406080 output power (dbm) channel transmit power vs. channel 12 13 14 15 16 17 18 19 0204060 rssi count temp (deg c) average rssi vs. temperature (rx signal = -70 dbm) 10 11 12 13 14 15 16 17 18 19 20 2.7 2.9 3.1 3.3 3.5 rssi count vcc average rssi vs. vcc (rx signal = -70 dbm) 0 2 4 6 8 10 12 14 16 18 0 20406080 rssi count channel rssi vs. channel (rx signal = -70 dbm) -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 2.7 2.9 3.1 3.3 3.5 rx sensitivity (dbm) vcc rx sensitivity vs. vcc (1 mbps cer) -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 0204060 rx sensitivity (dbm) temp (deg c) rx sensitivity vs. temperature (1 mbps cer) -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -150 -50 50 150 rx sensitivity (dbm) crystal offset (ppm) receiver sensitivity vs. frequency offset -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 0 20406080 rx sensitivity (dbm) channel receiver sensitivity vs. channel (3.0 v, room temp) -60 -50 -40 -30 -20 -10 0 10 20 -10 -5 0 5 10 c/i (db) channel offset (mhz) carrier to interferer (narrow band, lp modulation) pa6 pa5 pa4 pa6 pa5 pa4 pa6 pa5 pa4 gfsk att on 8dr32 gfsk 8dr32 lna off lna on gfsk gfsk 8dr32 8dr32 note 21. with lna on, att off, above -2dbm erroneous rssi values may be read. cross-checking rssi with lna off/on is recommended for accurate readings.
cyrf6986 document number: 001-66073 rev. *d page 17 of 23 typical operating characteristics (continued) 17 17.5 18 18.5 19 19.5 20 20.5 21 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 operating current (ma) temperature (c) icc rx (lna off) 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 24.5 25 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 operating current (ma) temperature (c) icc rx (lna on) 7.8 7.9 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9 9.1 9.2 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 operating current (ma) temperature (c) icc rx synth 7.8 7.9 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9 9.1 9.2 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 operating current (ma) temperature (c) icc tx synth 14 14.5 15 15.5 16 16.5 17 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 operating current (ma) temperature (c) icc tx at pa0 14 14.5 15 15.5 16 16.5 17 17.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 operating current (ma) temperature (c) icc tx at pa1 15 15.5 16 16.5 17 17.5 18 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 operating current (ma) temperature (c) icc tx at pa2 15.5 16 16.5 17 17.5 18 18.5 19 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 operating current (ma) temperature (c) icc tx at pa3 16.5 17 17.5 18 18.5 19 19.5 20 20.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 operating current (ma) temperature (c) icc tx at pa4 19.5 20 20.5 21 21.5 22 22.5 23 23.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 operating current (ma) temperature (c) icc tx at pa5 24.5 25 25.5 26 26.5 27 27.5 28 28.5 29 29.5 30 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 operating current (ma) temperature (c) icc tx at pa6 3.3 v 3.0 v 2.7 v 3.3 v 3.0 v 2.7 v 3.3 v 3.0 v 2.7 v 3.3 v 3.0 v 2.7 v 3.3 v 3.0 v 2.7 v 3.3 v 3.0 v 2.7 v 3.3 v 3.0 v 2.7 v 3.3 v 3.0 v 2.7 v 3.3 v 3.0 v 2.7 v 3.3 v 3.0 v 2.7 v 3.3 v 3.0 v 2.7 v
cyrf6986 document number: 001-66073 rev. *d page 18 of 23 ac test loads and wavef orms for digital pins figure 10. ac test loads and waveforms for digital pins 90% 10% v cc gnd 90% 10% all input pulses output 30 pf including jig and scope output r th equivalent to: v th thvenin equivalent rise time: 1 v/ns fall time: 1 v/ns output 5 pf including jig and scope max typical parameter unit r1 1071 ? r2 937 ? r th 500 ? v th 1.4 v v cc 3.00 v v cc output r1 r2 ac test loads dc test load 0.00001 0.0001 0.001 0.01 0.1 1 10 -100 -90 -80 -70 %ber input power (dbm) ber vs. data threshold (32-8dr) (sop threshold = 5, c38 slow) 0 through 6 0.00001 0.0001 0.001 0.01 0.1 1 10 100 -100 -50 0 %ber input power (dbm) gfsk vs. ber (sop threshold = 5, c38 slow) gfsk
cyrf6986 document number: 001-66073 rev. *d page 19 of 23 ordering information ordering code definitions table 6. key feature and package information part number radio package name package type operating range CYRF6986-40LTXC transceiver 001-44328 40-pin qfn (sawn type) commercial temperature range: c = commercial pb-free package type: lt = 40-pin qfn (sawn type) no of pins in package / kgd level: 40 = 40 pins part number marketing code: rf = wireless (radio frequency) product line company id: cy = cypress cy 6986 - 40 rf c lt x
cyrf6986 document number: 001-66073 rev. *d page 20 of 23 package diagram the recommended dimension of the pcb pad size for the e-pad underneath the qfn is 3.5 mm 3.5 mm (width length). figure 11. 40-pin qfn (6 6 0.90 mm) 3.5 3.5 e-pad (sawn) package outline, 001-44328 001-44328 *f
cyrf6986 document number: 001-66073 rev. *d page 21 of 23 acronyms document conventions units of measure table 7. acronyms used in this document acronym description ack acknowledge (packet received, no errors) ber bit error rate bom bill of materials cmos complementary metal oxide semiconductor crc cyclic redundancy check fec forward error correction fer frame error rate gfsk gaussian frequency-shift keying hbm human body model ism industrial, scientific, and medical irq interrupt request mcu microcontroller unit nrz non return to zero pll phase locked loop qfn quad flat no-leads rssi received signal strength indication rf radio frequency rx receive tx transmit table 8. units of measure symbol unit of measure c degree celsius db decibel dbc decibel relative to carrier dbm decibel-milliwatt hz hertz kb 1024 bytes kbit 1024 bits khz kilohertz k ? kilohm mhz megahertz m ? megaohm ? a microampere ? s microsecond ? v microvolt ? vrms microvolts root-mean-square ? w microwatt ma milliampere ms millisecond mv millivolt na nanoampere ns nanosecond nv nanovolt ? ohm pp peak-to-peak ppm parts per million ps picosecond sps samples per second v volt
cyrf6986 document number: 001-66073 rev. *d page 22 of 23 document history page description title: cyrf6986, wirel essusb? lpstar 2.4 ghz radio soc document number: 001-66073 revision ecn orig. of change submission date description of change ** 3139241 kkcn 01/14/2011 new data sheet. *a 3170692 kkcn 02/11/2011 updated in new template. *b 3196461 kkcn 03/15/2011 updated the text with lpstar. *c 3333406 kpmd 08/01/2011 changed stat us from preliminary to final. *d 4237039 lip 01/06/2014 updated package diagram : spec 001-44328 ? changed revision from *d to *f. updated in new template. completing sunset review.
document number: 001-66073 rev. *d revised january 6, 2014 page 23 of 23 wirelessusb? is a trademark of cypress semiconductor corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. cyrf6986 ? cypress semiconductor corporation, 2011-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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