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this is information on a product in full production. october 2013 docid17359 rev 4 1/44 vnd5e004a-e vnd5e004asp30-e double 4m high-side driver with analog current sense for automotive applications datasheet - production data features ? general ? very low standby current ? 3.0 v cmos compatible inputs ? optimized electromagnetic emissions ? very low electromagnetic susceptibility ? compliant with european directive 2002/95/ec ? very low current sense leakage ? diagnostic functions ? proportional load current sense ? high current sense precision for wide currents range ? diagnostic enable pin ? off-state open-load detection ? output short to v cc detection ? overload and short to ground (power limitation) indication ? thermal shutdown indication ? protection ? undervoltage shutdown ? overvoltage clamp ? load current limitation ? self limiting of fast thermal transients ? protection against loss of ground and loss of v cc ? overtemperature shutdown with auto restart (thermal shutdown) ? inrush current active management by power limitation ? reverse battery protection with self switch on of the power mosfet ? electrostatic discharge protection applications ? all types of resistive, inductive and capacitive loads ? suitable for power management applications description the vnd5e004a-e and vnd5e004asp30-e are double channel high-side drivers manufactured using st proprietary vipower ? m0-5 technology and housed in pqfn-12x12 power lead-less and multipowerso-30 packages. the devices are designed to drive 12 v automotive grounded loads, and to provide protection and diagnostics. they also implement a 3 v and 5 v cmos-compatible interface for use with any microcontroller. the devices integrate advanced protective functions such as load current limitation, inrush and overload active management by power limitation, overtemperature shut-off with auto- restart and overvoltage active clamp. a dedicated analog current sense pin is associated with every output channel providing enhanced diagnostic functions including fast detection of overload and short-circuit to ground through power limitation indication, overtemperature indication, short- circuit to v cc diagnosis and on-state and off-state open-load detection. the current sensing and diagnostic feedback of the whole device can be disabled by pulling the de pin low to share the external sense resistor with similar devices. max transient supply voltage v cc 41 v operating voltage range v cc 4.5 to 28 v max on-state resistance (per ch.) r on 4 m current limitation (typ) i limh 90 a off-state supply current i s 2 a (1) 1. typical value with all loads connected multipowerso-30 pqfn - 12x12 power lead-less www.st.com
contents vnd5e004a-e, vnd5e004asp30-e 2/44 docid17359 rev 4 contents 1 block diagram and pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 mcu i/os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.1 short to vcc and off-state open-load detection . . . . . . . . . . . . . . . . . . 26 3.4 maximum demagnetization energy (vcc = 13.5v) . . . . . . . . . . . . . . . . . 27 4 package and pc board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1 multipowerso-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 pqfn - 12x12 power lead-less thermal data . . . . . . . . . . . . . . . . . . . . . . 31 5 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2 multipowerso-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 pqfn - 12x12 power lead-less mechanical data . . . . . . . . . . . . . . . . . . . 36 5.4 multipowerso-30 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.5 pqfn - 12x12 power lead-less packing information . . . . . . . . . . . . . . . . 39 6 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
docid17359 rev 4 3/44 vnd5e004a-e, vnd5e004asp30-e list of tables 3 list of tables table 1. pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. switching (vcc = 13 v; tj = 25 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7. logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 9. current sense (8 v < v cc < 18 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 10. open-load detection (8 v < v cc < 18 v; v de = 5 v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 11. truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 14. electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 15. thermal parameters for multipowerso-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 16. thermal parameters for pqfn - 12x12 power lead-less . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 17. multipowerso-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 18. pqfn - 12x12 power lead-less mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 19. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 20. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
list of figures vnd5e004a-e, vnd5e004asp30-e 4/44 docid17359 rev 4 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. configuration diagram (not in scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. delay response time between rising edge of output current and rising edge of current sense (cs enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. i out /i sense vs i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10. maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. overload or short to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 13. intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14. off-state open-load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 15. short to v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 16. t j evolution in overload or short to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17. off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 18. high level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 19. input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 20. input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 21. input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 22. input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 23. on-state resistance vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 24. on-state resistance vs v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 25. undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 26. turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 27. i limh vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 28. turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 29. de high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 30. de clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 31. de low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 32. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 33. current sense and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 34. maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 35. multipowerso-30 pc board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 36. rthj-amb vs pcb copper area in open box free air condition (one channel on) . . . . . . . . 28 figure 37. multipowerso-30 thermal impedance junction ambient single pulse (one channel on) . . 29 figure 38. thermal fitting model of a double channel hsd in multipowerso-30 . . . . . . . . . . . . . . . . 29 figure 39. 12x12 power lead-less package pc board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 40. rthj-amb vs pcb copper area in open box free air condition (one channel on) . . . . . . . . 31 figure 41. pqfn - 12x12 power lead-less package thermal impedance junction ambient single pulse (one channel on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 42. thermal fitting model of a double channel hsd in pqfn - 12x12 power lead-less . . . . . 32 figure 43. multipowerso-30 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 44. pqfn - 12x12 power lead-less outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 figure 45. multipowerso-30 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 46. multipowerso-30 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
docid17359 rev 4 5/44 vnd5e004a-e, vnd5e004asp30-e list of figures 5 figure 47. pqfn - 12x12 power lead-less tray shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 48. pqfn - 12x12 power lead-less tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . 41
block diagram and pin configurations vnd5e004a-e, vnd5e004asp30-e 6/44 docid17359 rev 4 1 block diagram and pin configurations figure 1. block diagram table 1. pin functions name function v cc battery connection out1,2 power output gnd ground connection in1,2 voltage controlled input pin with hysteresis, cmos compatible, controls output switch state cs1,2 analog current sense pin; delivers a current proportional to the load current de active high diagnostic enable pin &rqwuro 'ldjqrvwlf 9 && &+ &rqwuro 'ldjqrvwlf /2*,& '5,9(5 9 21 /lplw dw lrq &x u u hq w /lplw dw lrq 3rzhu &o dp s 2))6 wdwh 2shqordg 2yhu whps 8qghuyrow djh 9 6(1 6( + &xuuhqw 6hqv h &+ 29( 5/2$ ' 3527(&7 ,21 $&7,9(32:(5/,0,7$7,21 ,1 ,1 &6 &6 '( *1' 287 287 6l j q d o &o dp s 5h y h u vh %dwwhu\ 3u r w hfw l r q ("1($'5
docid17359 rev 4 7/44 vnd5e004a-e, vnd5e004asp30-e block diagram and pin configurations 43 figure 2. configuration diagram (not in scale) table 2. suggested connections for unused and not connected pins connection / pin current sense nc (1) 1. not connected output input de for test only floating not allowed x x x x x to ground through 1k resistor x not allowed through 10k resistor through 10k resistor not allowed 12 11 10 9 8 7 6 5 4 3 2 1 13 1 nc 2 nc 3 nc 4 gnd 5 de 6 cs 1 7 cs 2 8 in 1 9 in 2 10 nc 11 nc 12 nc 13 for test only 14 v cc 15 out 2 16 out 1 v cc out 1 v cc out 2 out 1 out 2 out 1 out 1 out 1 out 1 nc out 2 out 2 out 2 out 2 1 15 16 30 multipowerso-30 v cc gnd v cc in 1 nc nc for test only nc nc de cs 1 cs 2 in 2 nc for test only v cc heat slug1 (top view) pqfn -12x12 power (bottom view) lead-less 14 15 16
electrical specifications vnd5e004a-e, vnd5e004asp30-e 8/44 docid17359 rev 4 2 electrical specifications figure 3. current and voltage conventions 2.1 absolute maximum ratings applying stress which exceeds above the ratings listed in table 3: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to the conditions in this section for extended periods may affect device reliability. v cc output1,2 current sense1,2 de input1,2 gnd i de i in1,2 v de v in1,2 v sense1,2 v out1,2 v cc i s i out1,2 i sense1,2 i gnd v cc output1,2 current sense1,2 de input1,2 gnd i de i in1,2 v de v in1,2 v sense1,2 v out1,2 v cc i s i out1,2 i sense1,2 i gnd table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 28 v v ccpk transient supply voltage (t < 400 ms , r load > 0.5 ) 41 v -v cc reverse dc supply voltage 16 v i out dc output current internally limited a -i out reverse dc output current 70 a i in dc input current -1 to 10 ma i de dc diagnostic enable input current -1 to 10 ma v csense current sense maximum voltage (v cc > 0 v) v cc - 41 +v cc v v e max maximum switching energy (single pulse) (l = 0.3 mh; r l = 0 ; v bat = 13.5 v; t jstart = 150 c; i out = i liml (typ.)) 600 mj v esd electrostatic discharge (human body model: r = 1.5 k ; c = 100 pf) 2000 v v esd charge device model (cdm-aec-q100-011) 750 v
docid17359 rev 4 9/44 vnd5e004a-e, vnd5e004asp30-e electrical specifications 43 2.2 thermal data 2.3 electrical characteristics values specified in this section are for 8 v < v cc < 24 v, -40 c < t j < 150 c , unless otherwise stated. t j junction operating temperature -40 to 150 c t stg storage temperature -55 to 150 c table 3. absolute maximum ratings (continued) symbol parameter value unit table 4. thermal data symbol parameter maximum value unit multipowerso-30 12x12 pllp r thj-case thermal resistance junction-case (with one channel on) 0.35 0.35 c/w r thj-amb thermal resistance junction-ambient 58 (1) 1. pcb fr4 area 58 mm x 58 mm, pcb thickness 2 mm, cu thickness 35 m, minimum pad layout 39 (2) 2. pcb fr4 area 78 mm x 78 mm, pcb thickness 2 mm, cu thickness 35 m, minimum pad layout c/w table 5. power section symbol parameter test conditions min. typ. max. unit v cc operating supply voltage 4.5 13 28 v v usd undervoltage shutdown 3.5 4.5 v v usdhyst undervoltage shutdown hysteresis 0.5 v r on on-state resistance (1) i out = 15 a; t j = 25 c 3 m i out = 15 a; t j = 150 c 6 m i out = 15 a; v cc = 5 v; t j = 25 c 6 m r on rev r dson in reverse battery condition v cc = -13 v; i out = -15 a; t j = 25 c 3m v clamp v cc clamp voltage i cc = 20 ma; i out1,2 = 0 a 41 46 52 v i s supply current standby v de = 0 v; v cc = 13 v; t j = 25 c; v in = 0; v out = v sense = 0 v 25a off-state; v cc = 13 v; v de = 5 v; t j = 25 c; v in = v out = v sense = 0 v 10 15 a on-state; v cc = 13 v; v de = 5 v; v in = 5 v; i out = 0 a 3.5 6 ma
electrical specifications vnd5e004a-e, vnd5e004asp30-e 10/44 docid17359 rev 4 i l(off) off-state output current (1) v in = 0 v or v de = 0 v; v out = 0 v; v cc = 13 v; t j = 25 c 00.013 a v in = 0 v or v de = 0 v; v out = 0 v; v cc = 13 v; t j = 125 c 05a 1. for each channel table 6. switching (v cc = 13 v; t j = 25 c) symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time r l = 0.87 (see table 6 )? 25 ? s t d(off) turn-off delay time r l = 0.87 (see table 6 )? 35 ? s (dv out /dt) on turn-on voltage slope r l = 0.87 ? see figure 26 ?v / s (dv out /dt) off turn-off voltage slope r l = 0.87 ? see figure 28 ?v / s w on switching energy losses during t won r l = 0.87 (see table 6 )? 5.4 ?mj w off switching energy losses during t woff r l = 0.87 (see table 6 )? 2.3 ?mj table 7. logic inputs symbol parameter test conditions min. typ. max. unit v il1,2 input low level voltage 0.9 v i il1,2 low level input current v in = 0.9 v 1 a v ih1,2 input high level voltage 2.1 v i ih1,2 high level input current v in = 2.1 v 10 a v i(hyst)1,2 input hysteresis voltage 0.25 v v icl1,2 input clamp voltage i in = 1 ma 5.5 7 v i in = -1 ma -0.7 v v del de low level voltage 0.9 v i del de low level current v in = 0.9 v 1 a v deh de high level voltage 2.1 v i deh de high level current v in = 2.1 v 10 a v de(hyst) de hysteresis voltage 0.25 v v decl de clamp voltage i de = 1 ma 5.5 7 v i de = -1 ma -0.7 v table 5. power section (continued) symbol parameter test conditions min. typ. max. unit
docid17359 rev 4 11/44 vnd5e004a-e, vnd5e004asp30-e electrical specifications 43 table 8. protections and diagnostics (1) 1. to ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. if the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. symbol parameter test conditions min. typ. max. unit i limh short circuit current v cc = 13 v 65 90 130 a 5 v < v cc < 24 v 130 a i liml short circuit current during thermal cycling v cc = 13 v; t r < t j < t tsd 40 a t tsd shutdown temperature 150 175 200 c t r reset temperature t rs +1 t rs +5 c t rs thermal reset of status 135 c t hyst thermal hysteresis (t tsd -t r ) 7c v demag turn-off output voltage clamp i out = 2 a; v in = 0; l = 6 mh v cc -28 v cc -32 v cc -35 v v on output voltage drop limitation i out = 1 a; t j = -40 c to 150 c (see figure 8 ) 25 mv table 9. current sense (8 v < v cc < 18 v) symbol parameter test conditions min. typ. max. unit k 0 i out /i sense i out = 5 a; v sense = 4 v; v de = 5 v; t j = -40 c...150 c t j = 25 c...150 c 11420 12130 17580 17580 23740 23030 ? k 1 i out /i sense i out = 10 a; v sense = 4 v; v de = 5 v; t j = -40 c...150 c t j = 25 c...150 c 11830 12680 16910 16910 21990 21140 ? dk 1 /k 1 (1) current sense ratio drift i out =10 a; v sense = 4 v; v de = 5 v; t j = -40 c to 150 c -14 14 % k 2 i out /i sense i out = 15 a; v sense = 4 v; v de = 5 v; t j = -40 c...150 c t j = 25 c...150 c 11760 13040 16110 16110 20460 19180 ? dk 2 /k 2 (1) current sense ratio drift i out = 15 a; v sense = 4 v; v de = 5 v; t j = -40 c to 150 c -10 10 % k 3 i out /i sense i out = 30 a; v sense = 4 v; v de = 5 v; t j = -40 c...150 c t j = 25 c...150 c 13040 13810 15520 15520 18000 17230 ? dk 3 /k 3 (1) current sense ratio drift i out = 30 a; v sense = 4 v; v de = 5 v; t j = -40 c to 150 c -5 5 %
electrical specifications vnd5e004a-e, vnd5e004asp30-e 12/44 docid17359 rev 4 i sense0 analog sense leakage current i out = 0 a; v sense = 0 v; v de = 0 v; v in = 0 v; t j = -40 c...150 c 01a i out = 0 a; v sense = 0 v; v de = 5 v; v in = 5 v; t j = -40 c...150 c 02a i out = 15 a; v sense = 0 v; v de = 0 v; v in = 5 v; 01a i ol open-load on- state current detection threshold v in = 5 v; 8 v < v cc < 18 v i sense = 5 a 10 150 ma v sense max analog sense output voltage i out = 45 a; v csd = 0 v; r sense = 3.9 k 5v v senseh analog sense output voltage in fault condition (2) v cc =13 v; r sense = 3.9 k 8v i senseh analog sense output current in fault condition (2) v cc =13 v; v sense = 5 v 9 ma t dsense1h delay response time from rising edge of de pin v sense < 4 v, 5 a < i out < 30 a; i sense = 90 % of i sense max (see figure 4 ) 50 100 s t dsense1l delay response time from falling edge of de pin v sense < 4 v, 5 a < i out < 30 a; i sense = 10 % of i sense max (see figure 4 ) 520s t dsense2h delay response time from rising edge of input pin v sense < 4 v, 5 a < i out < 30 a; i sense = 90 % of i sense max v de = 5 v (see figure 4 ) 200 600 s t dsense2l delay response time from falling edge of input pin v sense < 4 v, 5 a < i out < 30 a; i sense = 10 % of i sense max v de = 5 v (see figure 4 ) 100 250 s 1. parameter guaranteed by design; it is not tested. 2. fault condition includes: power limitation, overtemperature and open-load off-state detection. table 10. open-load detection (8 v < v cc < 18 v; v de = 5 v) symbol parameter test conditions min. typ. max. unit v ol open-load off-state voltage detection threshold v in = 0 v, v de = 5 v; see figure 5 2?4v t dstkon output short circuit to v cc detection delay at turn off v de = 5 v; see figure 5 180 ? 1200 s i l(off2)r off-state output current at v out = 4 v v in = 0 v; v sense = 0 v; v de = 5 v; v out rising from 0 v to 4 v -120 ? 90 a table 9. current sense (8 v < v cc < 18 v) (continued) symbol parameter test conditions min. typ. max. unit
docid17359 rev 4 13/44 vnd5e004a-e, vnd5e004asp30-e electrical specifications 43 figure 4. current sense delay characteristics figure 5. open-load off-state delay timing i l(off2)f off-state output current at v out = 2 v v in = 0 v; v sense = v senseh ; v de = 5 v; v out falling from v cc to 2 v -50 ? 90 a td_vol delay response from output rising edge to v sense rising edge in open-load v out = 4 v; v in = 0 v; v de = 5 v; v sense = 90 % of v senseh ?20s td_voh delay response from output falling edge to v sense falling edge in open-load v out = 2 v; v in = 0v; v de = 5 v; v sense = 10 % of v senseh ?20s table 10. open-load detection (8 v < v cc < 18 v; v de = 5 v) (continued) symbol parameter test conditions min. typ. max. unit sense current input load current de t dsense2h t dsense2l t dsense1l t dsense1h v in v cs t dstkon output stuck at v cc v out > v ol v senseh
electrical specifications vnd5e004a-e, vnd5e004asp30-e 14/44 docid17359 rev 4 figure 6. switching characteristics figure 7. delay response time between rising edge of output current and rising edge of current sense (cs enabled) v out dv out /dt (on) t r 80% 10% t f dv out /dt (off) t d(off) t d(on) input t t 90% t won t woff v in i out i sense i outmax i sensemax 90% i sensemax 90% i outmax t dsense2h t t t
docid17359 rev 4 15/44 vnd5e004a-e, vnd5e004asp30-e electrical specifications 43 figure 8. output voltage drop limitation figure 9. i out /i sense vs i out v on i out v cc -v out t j = 150 c t j =25c t j =-40c v on /r on(t) legend: a : max, t j = -40 c to 150 c b : max, t j = 25 c to 150 c c : typical, t j = -40 c to 150 c d : min, t j = 25 c to 150 c e : min, t j = -40 c to 150 c , 287 $ , 287 , 6(16( $ % & ' ( *$3*&)7
electrical specifications vnd5e004a-e, vnd5e004asp30-e 16/44 docid17359 rev 4 figure 10. maximum current sense ratio drift vs load current 1. parameter guaranteed by design; it is not tested. table 11. truth table conditions enable input output sense (v de =5v) (1) 1. if the v de is low, the sense output is at a high impedance; its potential depends on leakage currents and external circuit. normal operation h h l h l h 0 nominal overtemperature h h l h l l 0 v senseh undervoltage h h l h l l 0 0 overload h h h h x (no power limitation) cycling (power limitation) nominal v senseh short circuit to gnd (power limitation) h h l h l l 0 v senseh open-load off-state (with external pull up) hl h v senseh short circuit to v cc (external pull up disconnected) h h l h h h v senseh < nominal negative output voltage clamp hl l 0 , 287 $ g.. *$3*&)7
docid17359 rev 4 17/44 vnd5e004a-e, vnd5e004asp30-e electrical specifications 43 table 12. electrical transient requirements (part 1/3) iso 7637-2: 2004(e) test pulse test levels (1) 1. the above test levels must be considered referred to v cc = 13.5v except for pulse 5b. number of pulses or test times burst cycle/pulse repetition time delays and impedance iii iv 1 -75 v -100 v 5000 pulses 0.5 s 5 s 2 ms, 10 2a +37 v +50 v 5000 pulses 0.2 s 5 s 50 s, 2 3a -100 v -150 v 1h 90 ms 100 ms 0.1 s, 50 3b +75 v +100 v 1h 90 ms 100 ms 0.1 s, 50 4 -6 v -7 v 1 pulse 100 ms, 0.01 5b (2) 2. valid in case of external load dump clamp: 40v maximum referred to ground. the protection strategy allows powermos to be cyclically switched on duri ng load dump, so distributing the load dump energy along the time and to transfer a part of it to the load. +65 v +87 v 1 pulse 400 ms, 2 table 13. electrical transient requirements (part 2/3) iso 7637-2: 2004(e) test pulse test level results (1) 1. the above test levels must be considered referred to v cc = 13.5v except for pulse 5b iii iv 1c c 2a c c 3a c c 3b c c 4c c 5b (2) (3) 2. valid in case of external load dump clamp: 40v ma ximum referred to ground. the protection strategy allows powermos to be cyclically switched on during load dump, so distributing the load dump energy along the time and to transfer a part of it to the load. 3. suppressed load dump (pulse 5b) is withstood with a minimum load connected as specified in table 3 . cc table 14. electrical transient requirements (part 3/3) class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
electrical specifications vnd5e004a-e, vnd5e004asp30-e 18/44 docid17359 rev 4 2.4 waveforms figure 11. normal operation figure 12. overload or short to gnd i out v sense v de input nominal load nominal load i out v sense v de input nominal load nominal load power limitation i limh > i liml > i out v sense v de input thermal cycling power limitation i limh > i liml > i out v sense v de input thermal cycling
docid17359 rev 4 19/44 vnd5e004a-e, vnd5e004asp30-e electrical specifications 43 figure 13. intermittent overload figure 14. off-state open-load with external circuitry i out v sense v de input i limh > nominal load i liml > overload v senseh > i out v sense v de input i limh > nominal load i liml > overload v senseh > input v ol i out v sense v de v out v out > v ol t dstk (on) v senseh > input v ol i out v sense v de v out v out > v ol t dstk (on) v senseh >
electrical specifications vnd5e004a-e, vnd5e004asp30-e 20/44 docid17359 rev 4 figure 15. short to v cc figure 16. t j evolution in overload or short to gnd t dstk (on) v out > v ol resistive short to v cc hard short to v cc i out v de v out v ol t dstk (on) input t dstk (on) v out > v ol resistive short to v cc hard short to v cc i out v de v out v ol t dstk (on) input t tsd t r i limh > < i liml t j_start t hyst power limitation self-limitation of fast thermal transients input i out t j t tsd t r i limh > < i liml t j_start t hyst power limitation self-limitation of fast thermal transients input i out t j
docid17359 rev 4 21/44 vnd5e004a-e, vnd5e004asp30-e electrical specifications 43 2.5 electrical characteristics curves figure 17. off-state output current figure 18. high level input current figure 19. input clamp voltage figure 20. input low level voltage figure 21. input high level voltage figure 22. input hysteresis voltage 7 f >?&@ ,orii >q $ @ *$3*&)7 7f> ?&@ ,lk>x$@ *$3*&)7 7jo7 7f> ?&@ 9lfo>9@ *$3*&)7 *jon" 7f>?&@ 9lo>9@ *$3*&)7 7f> ?&@ 9lk>9@ *$3*&)7 7f> ?&@ 9lk\vw>9@ *$3*&)7
electrical specifications vnd5e004a-e, vnd5e004asp30-e 22/44 docid17359 rev 4 figure 23. on-state resistance vs t case figure 24. on-state resistance vs v cc figure 25. undervoltage shutdown figure 26. turn-on voltage slope figure 27. i limh vs t case figure 28. turn-off voltage slope 7f> ?&@ 5rq>p2kp@ ,rxw $ 9ff 9 *$3*&)7 9ff>9@ 5rq>p2kp@ *$3*&)7 5d?$ 5d?$ 5d?$ 5d?$ 7f> ?&@ 9xvg>9@ *$3*&)7 7f> ?&@ g9rxwgw2q>9pv@ 9ff 9 5o *$3*&)7 7f>?&@ ,olpk>$@ *$3*&)7 7dd7 7f> ?&@ g9rxwgw2ii>9pv@ 9ff 9 5o *$3*&)7
docid17359 rev 4 23/44 vnd5e004a-e, vnd5e004asp30-e electrical specifications 43 figure 29. de high level voltage figure 30. de clamp voltage figure 31. de low level voltage 7f> ?&@ 9ghk>9@ *$3*&)7 7f> ?&@ 9ghfo>9@ *$3*&)7 *jon" 7f> ?&@ 9gho>9@ *$3*&)7
application information vnd5e004a-e, vnd5e004asp30-e 24/44 docid17359 rev 4 3 application information figure 32. application schematic 3.1 mcu i/os protection when negative transients are present on the v cc line, the control pins are pulled negative to approximately -1.5v. st suggests the insertion of resistors (r prot ) in the lines to prevent the microcontroller i/o pins from latching up. the values of these resistors provide a compromise between the leakage current of the microcontroller, the current required by the hsd i/os (input levels compatibility) and the latch-up limit of the microcontroller i/os. -v ccpeak /i latchup r prot (v ohc -v ih ) / i ihmax calculation example: for v ccpeak = - 1.5v and i latchup 20ma; v ohc 4.5v 75 r prot 240k . recommended values: r prot =10k , c ext = 10nf 3.2 load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the v ccpk maximum rating. the same applies if the device is subject to transients on the v cc line that are greater than the ones shown in the iso 7637-2: 2004(e) table. 9 && *1' 287387 ' og 0 &8 9 '( ,1387 5 surw 5 surw &855(176(16( 5 surw 5 6(16( & h[w ("1($'5
docid17359 rev 4 25/44 vnd5e004a-e, vnd5e004asp30-e application information 43 3.3 current sense and diagnostic the current sense pin performs a double function (see figure 33: current sense and diagnostics ): ? current mirror of the load current in normal operation, delivering a current proportional to the load current according to a known ratio k x . the current i sense can be easily converted to a voltage v sense by means of an external resistor r sense . linearity between i out and v sense is ensured up to 5v minimum (see parameter v sense in table 9: current sense (8 v < vcc < 18 v) ). the current sense accuracy depends on the output current (refer to current sense electrical characteristics table 9: current sense (8 v < vcc < 18 v) ). ? diagnostic flag in fault conditions , delivering a fixed voltage v senseh up to a maximum current i senseh in case of the following fault conditions (refer to table 11: truth table ): ? power limitation activation ? overtemperature ? short to v cc in off-state ? open-load in off-state with additional external components. a logic level low on the de pin simultaneously sets all the current sense pins of the device in a high impedance state, thus disabling the current monitoring and diagnostic detection. this feature allows multiplexing of the microcontroller analog inputs by sharing the sense resistance and adc line among different devices. figure 33. current sense and diagnostics 0dlq026q 9 287q , /riiu 5 6(16( 5 3527 7rx&$'& 5 3' 5 38 9 38 3zub/lp 9 6 ( 1 6 ( 38b&0' 2yhuwhpshudwxuh 2/2)) 9 2/ &855(17 6(16(q , 287 . ; , 6(16(+ 9 %$7 , /riii 9 6(16(+ /rdg ,1387q 9 && *1' '( ("1($'5
application information vnd5e004a-e, vnd5e004asp30-e 26/44 docid17359 rev 4 3.3.1 short to v cc and off-state open-load detection short to v cc a short circuit between v cc and output is indicated by the relevant current sense pin set to v senseh during the device off-state. little or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. off-state open-load with external circuitry detection of an open-load in off mode requires an external pull-up resistor (r pu ) connecting the output to a positive supply voltage (v pu ). it is preferable that v pu be switched off during the module standby mode to avoid an increase in the overall standby current consumption in normal conditions, that is, when the load is connected. an external pull down resistor (r pd ) connected between output and gnd is mandatory to avoid misdetection in case of floating outputs in off-state (see figure 33: current sense and diagnostics ). r pd must be selected in order to ensure v out < v olmin unless pulled up by the external circuitry: r pd 22 k is recommended. for proper open-load detection in off-state, the external pull-up resistor must be selected according to the following formula: for the values of v olmin ,v olmax , i l(off2)r and i l(off2)f see table 10: open-load detection (8 v < vcc < 18 v; vde = 5 v) . v out pull-up_off r pd i l(off2)f ? v olmin < 2v == v out pull-up_on r pd v pu ? r pu ? r pd i l(off2)r ?? r pu r pd + ------------------------------------------------------------------------------------- v olmax 4v ===
docid17359 rev 4 27/44 vnd5e004a-e, vnd5e004asp30-e application information 43 3.4 maximum demagnetization energy (v cc = 13.5v) figure 34. maximum turn-off current versus inductance 1. values are generated with r l = 0 . in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves a and b. c: t jstart = 125 c repetitive pulse a: t jstart = 150 c single pulse b: t jstart = 100 c repetitive pulse ,$ /p+ ("1($'5 " # $ 'hpdjqhwl]dwlrq 'hpdjqhwl]dwlrq 'hpdjqhwl]dwlrq w 9 ,1 , / *$3*&)7
package and pc board thermal data vnd5e004a-e, vnd5e004asp30-e 28/44 docid17359 rev 4 4 package and pc board thermal data 4.1 multipowerso-30 thermal data figure 35. multipowerso-30 pc board 1. layout condition of r th and z th measurements (pcb: double layer, thermal vias, fr4 area = 58 mm x 58 mm, pcb thickness = 2 mm, cu thickness = 70 m (front and back side), copper areas: from minimum pad lay-out to 16 cm 2 ). figure 36. r thj-amb vs pcb copper area in open box free air condition (one channel on) 35 40 45 50 55 60 012345 rthj_amb(c/w) pcb cu heatsink area (cm^2)
docid17359 rev 4 29/44 vnd5e004a-e, vnd5e004asp30-e package and pc board thermal data 43 figure 37. multipowerso-30 thermal impedance junction ambient single pulse (one channel on) figure 38. thermal fitting model of a dou ble channel hsd in multipowerso-30 1. the fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protection functions (power limi tation or thermal cycling during t hermal shutdown) are not triggered. equation 1: pulse calculation formula 7 l p h v = 7 + ? & : ) r r w s u l q w f p *$3*&)7 z th r th z thtp 1 ? () + ? = where t p t ? =
package and pc board thermal data vnd5e004a-e, vnd5e004asp30-e 30/44 docid17359 rev 4 table 15. thermal parameters for multipowerso-30 area/island (cm 2 ) footprint 4 r1 (c/w) 0.05 r2 (c/w) 0.3 r3 (c/w) 0.5 r4 (c/w) 1.3 r5 (c/w) 14 r6 (c/w) 44.7 23.7 r7 (c/w) 0.05 r8 (c/w) 0.3 c1 (w.s/c) 0.005 c2 (w.s/c) 0.008 c3 (w.s/c) 0.01 c4 (w.s/c) 0.3 c5 (w.s/c) 0.6 c6 (w.s/c) 5 11 c7 (w.s/c) 0.005 c8 (w.s/c) 0.008
docid17359 rev 4 31/44 vnd5e004a-e, vnd5e004asp30-e package and pc board thermal data 43 4.2 pqfn - 12x12 power lead-less thermal data figure 39. 12x12 power lead-less package pc board 1. layout condition of r th and z th measurements (pcb: double layer, thermal vias, fr4 area = 77 mm x 86 mm, pcb thickness = 1.6 mm, cu thickness = 70 m (front and back side), copper areas: minimum pad lay-out). figure 40. r thj-amb vs pcb copper area in open box free air condition (one channel on) 20 25 30 35 40 45 50 0 5 10 15 20 pcb cu heatsink area (cm^ 2)
package and pc board thermal data vnd5e004a-e, vnd5e004asp30-e 32/44 docid17359 rev 4 figure 41. pqfn - 12x12 power lead-less package thermal impedance junction ambient single pulse (one channel on) figure 42. thermal fitting model of a double channel hsd in pqfn - 12x12 power lead-less 1. the fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protection functions (power limi tation or thermal cycling during t hermal shutdown) are not triggered. equation 2: pulse calculation formula w l p h v ? & : ) r rw r w s u l q w f p f p f p *$3*&)7 z th r th z thtp 1 ? () + ? = where t p t ? =
docid17359 rev 4 33/44 vnd5e004a-e, vnd5e004asp30-e package and pc board thermal data 43 table 16. thermal parameters for pqfn - 12x12 power lead-less area/island (cm 2 )footprint 4 8 16 r1 (c/w) 0.35 r2 (c/w) 0.15 r3 (c/w) 4.2 r4 (c/w) 9.6 9.4 9.2 9 r5 (c/w) 15.1 10.5 8.5 5.5 r6 (c/w) 16.7 12 9 6 r7 (c/w) 0.35 r8 (c/w) 0.15 c1 (w.s/c) 0.018 c2 (w.s/c) 0.015 c3 (w.s/c) 0.2 c4 (w.s/c) 1.9 2.2 2.32 2.45 c5 (w.s/c) 2.45 7.3 13.7 20 c6 (w.s/c) 11.85 22 25 30 c7 (w.s/c) 0.018 c8 (w.s/c) 0.015
package and packing information vnd5e004a-e, vnd5e004asp30-e 34/44 docid17359 rev 4 5 package and packing information 5.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 5.2 multipowerso-30 mechanical data figure 43. multipowerso-30 outline table 17. multipowerso-30 mechanical data symbol millimeters min. typ. max. a 2.35 a2 1.85 2.25 a3 0 0.1 b0.42 0.58 c0.23 0.32
docid17359 rev 4 35/44 vnd5e004a-e, vnd5e004asp30-e package and packing information 43 d 17.1 17.2 17.3 e 18.85 19.15 e1 15.9 16 16.1 ?e? 1 f6 14.3 f7 5.45 f8 0.73 l 0.8 1.15 n10 deg s 0 deg 7 deg table 17. multipowerso-30 mechanical data (continued) symbol millimeters min. typ. max.
package and packing information vnd5e004a-e, vnd5e004asp30-e 36/44 docid17359 rev 4 5.3 pqfn - 12x12 power lead-less mechanical data figure 44. pqfn - 12x12 power lead-less outline
docid17359 rev 4 37/44 vnd5e004a-e, vnd5e004asp30-e package and packing information 43 table 18. pqfn - 12x12 power lead-less mechanical data symbol millimeters min. typ. max. a2 2.2 a1 0 0.05 b0.35 0.47 c0.50 d 11.90 12.10 dh1 4.65 4.95 dh2 10.45 10.65 dh3 4.80 5 dh4 4.80 5 e 11.90 12.10 eh1 2.15 2.45 eh2 5.15 5.45 eh3 1.70 2 e1 0.90 e2 3.45 e3 1.10 f0.50 f1 0.60 l0.75 0.95 l1 1.65 1.90 l2 0.76 0.78 m11.10 11.30 n11.10 11.30 v0.1 w0.05 y0.05 y1 0.1
package and packing information vnd5e004a-e, vnd5e004asp30-e 38/44 docid17359 rev 4 5.4 multipowerso-30 packing information the devices can be packed in tube or tape and reel shipments (see table 19: device summary ). figure 45. multipowerso-30 tube shipment (no suffix) a b c tube dimension dimension mm base q.ty 29 bulk q.ty 435 tube length ( 0.5) 532 a 3.82 b 23.6 c ( 0.13) 0.8
docid17359 rev 4 39/44 vnd5e004a-e, vnd5e004asp30-e package and packing information 43 figure 46. multipowerso-30 tape and reel shipment (suffix ?tr?) 5.5 pqfn - 12x12 power lead-less packing information the devices can be packed in tray or tape and reel shipments (see table 19: device summary ). reel dimension dimension mm base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 d (min) 20.2 g (+ 2 / -0) 32 n (min) 100 t (max) 38.4 to p cover tape start no components no components components 500 mm min 500 mm min empty components pockets user direction of feed tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 description dimension mm tape width w 32 tape hole spacing p0 ( 0.1) 4 component spacing p 24 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 2 hole position f ( 0.1) 14.2 compartment depth k (max) 2.2 hole spacing p1 ( 0.1) 2 end
package and packing information vnd5e004a-e, vnd5e004asp30-e 40/44 docid17359 rev 4 figure 47. pqfn - 12x12 power lead-less tray shipment (no suffix) tray information parameter base q.ty 189 bulk q.ty 945
docid17359 rev 4 41/44 vnd5e004a-e, vnd5e004asp30-e package and packing information 43 figure 48. pqfn - 12x12 power lead-less tape and reel shipment (suffix ?tr?) tape dimensions dimension mm a0 0.1 12.30 b0 0.1 12.30 k0 0.1 2.15 f 0.1 11.50 e 0.1 1.75 w 0.3 24 p2 0.1 2 p0 0.1 4 p1 0.1 16 t 0.05 0.30 d1.50 d1 (min) 1.50 reel dimensions dimension mm base q.ty 1500 bulk q.ty 1500 a (max) 330 b (min) 1.5 c ( 0.2) 13 d (min) 20.2 g (+ 2 / -0) 32 n (min) 100 t (max) 38.4
order codes vnd5e004a-e, vnd5e004asp30-e 42/44 docid17359 rev 4 6 order codes table 19. device summary package order codes tube tape and reel tray pqfn-12x12 power lead-less ? vnd5e004atr-e vnd5e004a-e multipowerso-30 VND5E004A30-E vnd5e004a30tr-e ?
docid17359 rev 4 43/44 vnd5e004a-e, vnd5e004asp30-e revision history 43 7 revision history table 20. document revision history date revision changes 20-jul-2010 1 initial release. 07-nov-2012 2 updated figure 1: block diagram and figure 10: maximum current sense ratio drift vs load current 19-sep-2013 3 updated disclaimer. 25-oct-2013 4 updated footnote 2 into the table 12: electrical transient requirements (part 1/3) and table 13: electrical transient requirements (part 2/3) .
vnd5e004a-e, vnd5e004asp30-e 44/44 docid17359 rev 4 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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