? semiconductor components industries, llc, 2015 march, 2015 ? rev. 0 1 publication order number: b300am/d belasigna 300 with aftermaster hd audio processor for aftermaster hd introduction belasigna ? 300 am is a dsp?based audio processor which is able to execute the aftermaster hd algorithm within a system that also includes a host processor and/or external 12s? based mono or stereo a/d converters and d/a converters. aftermaster hd is an algorithm which processes audio signals in real?time to provide a significant increase in loudness, clarity, depth, and fullness. belasigna 300 am is specifically designed for use in applications requiring a solution to overcome the limitations of small or downward?facing speakers, includi ng flat?screen televisions or headphones. this datasheet describes only the specific information required to integrate belasigna 300 am into an audio system. for a more general description of the programmable belasigna 300 device from on semiconductor, please refer to the belasigna 300 datasheet. key features ? ultra?low?power: typically 4?8 ma when executing aftermaster hd ? miniature form factor: available in a miniature 3.63 mm x 2.68 mm x 0.92 mm (including solder balls) wlcsp package. ? full range of configurable interfaces: including a fast i 2 c?based interface for download and general configuration of the aftermaster hd algorithm, a highly configurable pcm interface to stream data into and out of the device, a high?speed uart, an spi port and 5 gpios ? these devices are pb?free, halogen free/bfr free and are rohs compliant www. onsemi.com marking diagram wlcsp?35 w suffix case 567ag belasigna300 35?02?g xxxxyzz belasigna300 = device code 35 = number of balls 02 = revision of die g = pb?free xxxx = date code y = assembly plant identifier = (may be two characters) zz = traceability code device package ordering information B300W35A109A1G wlcsp (pb?free) shipping ? 2500 / tape & reel ?for information on tape and reel specifications, in - cluding part orientation and tape sizes, please refe r to our tape and reel packaging specification s brochure, brd8011/d.
belasigna 300 with aftermaster hd www. onsemi.com 2 figures and data table 1. absolute maximum ratings parameter min max unit voltage at any input pin ?0.3 2.0 v operating supply voltage (note 1) 0.9 2.0 v operating temperature range (note 2) ?40 85 c storage temperature range ?55 85 c caution: class 2 esd sensitivity, jesd22?a114?b (2000 v) stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. functional operation only guaranteed below 0 c for digital core (vddc) and system voltages above 1.0 v. 2. parameters may exceed listed tolerances when out of the temperature range 0 to 50 c. electrical performance specifications the tests were performed at 20 c with a clean 1.8 v supply voltage. belasigna 300 am was running in high voltage mode (vddc = 1.8 v unless otherwise noted). the system clock (sys_clk) was generated externally at 38 mhz. parameters marked as screened are tested on each chip. other parameters are qualified but not tested on every part. table 2. electrical specifications description symbol conditions min typ max units screened overall supply voltage v bat 1.8 2.0 v current consumption i bat aftermaster hd @ fs= 48 khz ? 8 ? ma fs = 44.1 khz ? 7 ? ma fs =16 khz ? 3 ? ma fs = 8 khz ? 2 ? ma vreg (1 f external capacitor) measurement at vddc = 1.0 v, low voltage mode regulated voltage output v reg 0.95 1.00 1.05 v regulator psrr v reg_psrr 1 khz 50 55 ? db load current i load ? ? 2 ma load regulation load reg ? 6.1 6.5 mv/ma line regulation line reg ? 2 5 mv/v vdbl (1 f external capacitor) measurement at vddc = 1.0 v, low voltage mode regulated doubled voltage output vdbl 1.9 2.0 2.1 v regulator psrr vdbl psrr 1 khz 35 41 ? db load current i load ? ? 2.5 ma load regulation load reg ? 7 10 mv/ma line regulation line reg ? 10 20 mv/v vddc (1 f external capacitor) measurement at vddc = 1.0 v, low voltage mode digital supply voltage output vddc configured by a control register 0.79 0.95 1.25 v vddc output level adjustment vddc step 27 29 31 mv regulator psrr vddc psrr 1 khz 25 25.5 26 db load current i load ? ? 3.5 ma load regulation load reg ? 3 12 mv/ma line regulation line reg ? 3 8 mv/v
belasigna 300 with aftermaster hd www. onsemi.com 3 table 2. electrical specifications (continued) description screened units max typ min conditions symbol power?on?reset (por) por startup voltage vddc startup 0.775 0.803 0.837 v por shutdown voltage vddc shutdown 0.755 0.784 0.821 v por hysteresis por hysteresis 13.8 19.1 22.0 mv por duration t por 11.0 11.6 12.3 ms digital pads voltage level for high input v ih vbat * 0.8 ? ? v voltage level for low input v il ? ? vbat * 0.2 v voltage level for high output v oh 2 ma source current vddo * 0.8 ? ? v voltage level for low output v ol 2 ma sink current ? ? vddo * 0.2 v input capacitance for digital pads c in ? 4 ? pf pull?up resistance for digital input pads r up_in 220 270 320 k pull?down resistance for digital input pads r down_in 220 270 320 k sample rate tolerance fs sample rate of 16 khz or 32 khz ?1 0 +1 % rise and fall time tr, tf digital output pad esd human body model (hbm) 2 kv machine model (mm) 200 v latch?up v < gndc, v > vbat 200 ma digital interfaces i2c baud rate system clock < 1.6 mhz ? ? 100 kbps system clock > 1.6 mhz ? ? 400 kbps general?purpose uart baud rate system clock 5.12 mhz ? 1 ? mbps product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
belasigna 300 with aftermaster hd www. onsemi.com 4 environmental characteristics all belasigna 300 am packages are pb?free, rohs?compliant and green. belasigna 300 am parts are qualified against standards outlined in the following sections. all belasigna 300 am package options are green (rohs?compliant). contact on semiconductor for supporting documentation. wlcsp package option the solder ball composition for the wlcsp package is sac266. table 3. wlcsp package?level qualification packaging level moisture sensitivity level jedec level 1 thermal cycling test (tct) ?55 c to 150 c for 500 cycles highly accelerated stress test (hast) 85 c / 85% rh for 1000 hours high temperature stress test (htst) 150 c for 1000 hours table 4. wlcsp board?level qualification board level temperature ?40 c to 125 c for 2500 cycles with no failures mechanical information and circuit design guidelines belasigna 300 am is available in a 2.68 x 3.63 mm ultra?miniature wafer?level chip scale package (wlcsp) figure 1. belasigna 300 with aftermaster layout schematic belasigna 300 dsp pcm_fr pcm_sero pcm_seri pcm_clk vreg ai0 ai1 ai2 agnd gndc gndrcvr cap1 cap0 ai4 vbatrcvr ext_clk reserved scl sda spi_seri spi_sero spi_cs vddc vbat spi_clk 1.8v to programming interface to host controller or adc/dac to host controller as needed 1uf 10uf 1uf 100nf 1.8v eeprom ~38mhz clock source vdbl 10uf gpio4 gpio3 gpio2 gpio1 gpio0
belasigna 300 with aftermaster hd www. onsemi.com 5 wlcsp pin out a total of 35 active pins are present on the belasigna 300 am wlcsp package. they are organized in a staggered array. a description of these pins is given in table 5. table 5. wlcsp pad descriptions pad index belasigna 300 am pad name description i/o a/d a1 gndrcvr ground for output driver n/a a a5 vbatrcvr power supply for output stage / nc for aftermaster i a b2 rcvr_hp+ extra output driver pad for high power mode / nc for aftermaster* o a c3 rcvr+ output from output driver / nc for aftermaster* o a a3 rcvr? output from output driver / nc for aftermaster* o a b4 rcvr_hp? extra output driver pad for high power mode / nc for aftermaster* o a b6 cap0 charge pump capacitor pin 0 n/a a c5 cap1 charge pump capacitor pin 1 n/a a a7 vdbl doubled voltage o a b8 vbat power supply i a b10 vreg regulated supply voltage / nc for aftermaster* o a a9 agnd analog ground n/a a a11 ai4 audio signal input 4 / nc for aftermaster* i a b12 ai2/lout2 audio signal input 2/output signal from preamp 2 / gnd for aftermaster* i/o a a13 ai1/lout1 audio signal input 1/output signal from preamp 1 / gnd for aftermaster* i/o a b14 ai0/lout0 audio signal input 0/output signal from preamp 0 / gnd for aftermaster* i/o a d14 gpio[4]/lsad[4] general?purpose i/o 4/low speed ad input 4 i/o a/d e13 gpio[3]/lsad[3] general?purpose i/o 3/low speed ad input 3 i/o a/d c13 gpio[2]/lsad[2] general?purpose i/o 2/low speed ad input 2 i/o a/d d12 gpio[1]/lsad[1]/uar t?rx general?purpose i/o 1/low speed ad input 1/and uart rx i/o a/d e11 gpio[0]/uar t?tx general?purpose i/o 0/uart tx i/o a/d c9 gndc digital ground n/a a c11 sda (i2c) i2c data i/o d d10 scl (i2c) i2c clock i/o d e9 ext_clk external clock input/internal clock output i/o d d8 vddc core logic power o a e7 spi_clk serial peripheral interface clock o d c7 spi_seri serial peripheral interface input i d d6 spi_cs serial peripheral interface chip select o d e5 spi_sero serial peripheral interface output o d d4 pcm_fr pcm interface frame i/o d e3 pcm_seri pcm interface input i d d2 pcm_sero pcm interface output o d c1 pcm_clk pcm interface clock i/o d e1 reserved reserved / gnd for aftermaster *nc = not connected.
belasigna 300 with aftermaster hd www. onsemi.com 6 wlcsp assembly / design notes for pcb manufacture with belasigna 300 am wlcsp, on semiconductor recommends solder?on?pad (sop) surface finish. with sop, the solder mask opening should be non?solder mask?defined (nsmd) and copper pad geometry will be dictated by the pcb vendor?s design requirements. alternative surface finishes are enig and osp; volume of screened solder paste (#5) should be less than 0.0008 mm 3 . if no pre?screening of solder paste is used, then following conditions must be met: 1. the solder mask opening should be >0.3 mm in diameter, 2. the copper pad will have 0.25 mm diameter, and 3. soldermask thickness should be less than 1 mil thick above the copper surface. on semiconductor can provide belasigna 300 am wlcsp land pattern cad files to assist your pcb design upon request. wlcsp weight belasigna 300 am wlcsp (b300w35a109xxg) has an average weight of 0.095 grams. digital interfaces general?purpose input output (gpio) ports belasigna 300 am has five gpio ports that can connect to external digital inputs such as push buttons, or digital outputs such as the control or trigger of an external companion chip (gpio[0..4]). the direction of these ports (input or output) is configurable and each pin has an internal pull?up resistor when configured as a gpio. a read from an unconnected pin will give a value of logic 1. four of the five gpio pins are multiplexed with an lsad (see the low?speed a.d converters section) and as such the functionality of the pin can be either a gpio or an lsad depending on the configuration. note that gpio0 cannot be used as an lsad. inter?ic communication (i 2 c) interfaces the i 2 c interface is an industry?standard interface that can be used for high?speed transmission of data between belasigna 300 am and an external device. the interface operates at speeds up to 400 kbit/sec for system clocks (ext_clk) higher than 1.6 mhz. in product development mode, the i 2 c interface is used for application debugging purposes, communicating with the belasigna 300 am development tools. the interface can be configured to operate in either master mode or slave mode. serial peripheral interface (spi) port an spi port is available on belasigna 300 am for applications such as communication with a non?volatile memory (eeprom). the i/o levels on this port are defined by the vbat. the spi port operates in master mode only, which supports communications with slave spi devices. the spi port on belasigna 300 am only supports master mode, so it will only communicate with spi slave devices. when connecting to an spi slave device other than a boot eeprom, the spi_cs pin should be left unconnected and the slave device cs line should be driven from a gpio to avoid belasigna 300 am boot malfunction. when connecting to an spi eeprom for boot, the designer can choose to connect the spi_cs pin to the eeprom or use a gpio (high at boot) for a design with several daisy-chained spi devices. pcm interface belasigna 300 am includes a highly configurable pulse code modulation (pcm) interface that can be used to stream audio signal data into and out of the device. the i/o levels on this port are defined by the voltage on the vbat pin.
belasigna 300 with aftermaster hd www. onsemi.com 7 assembly information carrier details 2.6 x 3.8 mm wlcsp on semiconductor offers tape and reel packing for belasigna 300 am wlcsp. the packing consists of a pocketed carrier tape, a cover tape, and a molded anti?static polystyrene reel. the carrier and cover tape create an esd safe environment, protecting the components from physical and electrostatic damage during shipping and handling. figure 2. package orientation on tape for wlcsp package option pin 1 quantity per reel: 2500 units pin 1 orientation: upper left, bumps down tape brand / width: advantek / 12 mm pocket pitch: 8 mm p/n: bcb043 cover tape: 3m 2666 psa 9.3 mm a = 13 inches b = 12 mm c = 4 inches d = 13 mm reel brand / width: advantek lokreel ? / 13 in figure 3. wlcsp carrier tape drawing 10 sprockets hole pitch cumulative tolerance 0.1. camber in compliance with eia 763. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
belasigna 300 with aftermaster hd www. onsemi.com 8 sample shipping label figure 4. sample shipping label re?flow information the re?flow profile depends on the equipment that is used for the re?flow and the assembly that is being re?flowed. information from jedec standard 22?a113d and j?std?020d.01 can be used as a guideline. electrostatic discharge (esd) sensitive device caution: esd sensitive device. permanent damage may occur on devices subjected to high?energy electrostatic discharges. proper esd precautions in handling, packaging and testing are recommended to avoid performance degradation or loss of functionality. device is 2 kv hbm esd qualified. miscellaneous ordering information to order belasigna 300 with am, please contact your account manager and ask for part number B300W35A109A1G. chip identification chip identification information can be retrieved by using the communications accelerator adaptor (caa) tool along with the protocol software provided by on semiconductor (see caa instruction manual). for belasigna 300 am, the key identifier components and values are as follows for the different package options: package option chip family chip version chip revision wlcsp 0x03 0x02 0x0100 support software a set of tools is available at http://onsemi.com for downloading the proprietary aftermaster hd algorithm to belasigna 300 am. an aftermaster hd image is supplied by on semiconductor, but must be downloaded to belasigna 300 am upon boot. training to facilitate development on the belasigna 300 am platform, training is available upon request. contact your account manager for more information. company or product inquiries for more information about on semiconductor products or services visit our web site at http://onsemi.com .
belasigna 300 with aftermaster hd www. onsemi.com 9 package dimensions wlcsp35, 3.63x2.68 case 567ag issue b seating plane 0.10 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max 0.84 millimeters a1 d 3.63 bsc e b 0.24 0.29 ed 0.25 bsc 1.00 d e a b pin a1 reference ed a 0.05 b c 0.03 c 0.05 c 35x b 4 5 6 c b a 0.10 c a a1 a2 c 0.17 0.23 2.68 bsc ee 0.433 bsc 0.25 35x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.250 0.10 c 2x top view side view bottom view note 3 ee a2 0.72 ref recommended a1 package outline 1 2 3 7 8 9 pitch c 0.125 bsc e d 10 11 12 13 14 c 0.433 pitch 0.125 p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 b300am/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. belasigna is a registered trademark of semiconductor components industries, llc.
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