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this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev. 0.2 / may. 2004 1 preliminary HY5V72D(l/s)m(p) series 4banks x4m x 32bits synchronous dram document title 4bank x 4m x 32bits synchronous dram revision history revision no. history draft date remark 0.1 initial draft nov. 2003 preliminary 0.2 renew the part number HY5V72D(l/s)f(p) series --> HY5V72D(l/s)m(p) series may 2004 preliminary
this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev. 0.2 / may. 2004 2 preliminary HY5V72D(l/s)m(p) series 4banks x4m x 32bits synchronous dram description the HY5V72D(l/s)m series is a 536,870, 912 cmos synchronous dram, ideally suit ed for the mobile applications which require low power consumption. HY5V72D(l/ s)m is organized as 4banks of 4,194,304 x32. HY5V72D(l/s)m is offering fully synchronous operation referenc ed to a positive edge of the clock. all inputs and out- puts are synchronized with th e rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. all input and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read latency of 2 and 3), the number of consecutive read or write cycles initiated by a single control command (burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). a burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burs t read or write command on any cycle. (this pipelined design is not restricted by a `2n` rule.) features standard sdram protocol ordering information part number clock frequency cas latency organization interface HY5V72D(l/s)m(p)-p 100mhz 2 4banks x 4mb x 32 lvttl HY5V72D(l/s)m(p)-h 133mhz 3 4banks x 4mb x 32 lvttl ? single 3.30.3v power supply ? all device balls are compatible with lvttl interface ? packages : 90ball, 0.8mm pitch fbga (lead, lead free) HY5V72D(l/s)m-h (lead) HY5V72D(l/s)m-p (lead) HY5V72D(l/s)mp-h (lead free) HY5V72D(l/s)mp-p (lead free) ? tras lock out function is supported ? data mask function by udqm or ldqm ? internal four banks operation ? auto refresh and self refresh ? 8192 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst
rev. 0.2 / may. 2004 3 preliminary HY5V72D(l/s)m(p) series 4banks x 4m x 32bits synchronous dram ball description dq26 dq28 vssq vssq vddq vss a4 a7 clk dqm1 vddq vssq vssq dq11 dq13 dq24 vddq dq27 dq29 dq31 dqm3 a5 a8 cke nc dqs dq10 dq12 vddq dq15 vss vssq dq25 dq30 nc a3 a6 a12 a9 nc vss dq9 dq14 vssq vss vdd vddq dq22 dq17 nc a2 a10 nc ba0 /cas vdd dq6 dq1 vddq vdd dq23 vssq dq20 dq18 dq16 dqm2 a0 ba1 /cs /we dq7 dq5 dq3 vssq dq0 dq21 dq19 vddq vddq vssq vdd a1 nc,a11 /ras dqm0 vssq vddq vddq dq4 dq2 1 1 2 2 3 3 7 7 8 8 9 9 4 4 5 5 6 6 a a b b c c d d e e f f g g h h j j k k l l m m n n p p r r top view dq26 dq28 vssq vssq vddq vss a4 a7 clk dqm1 vddq vssq vssq dq11 dq13 dq24 vddq dq27 dq29 dq31 dqm3 a5 a8 cke nc dqs dq10 dq12 vddq dq15 vss vssq dq25 dq30 nc a3 a6 a12 a9 nc vss dq9 dq14 vssq vss vdd vddq dq22 dq17 nc a2 a10 nc ba0 /cas vdd dq6 dq1 vddq vdd dq23 vssq dq20 dq18 dq16 dqm2 a0 ba1 /cs /we dq7 dq5 dq3 vssq dq0 dq21 dq19 vddq vddq vssq vdd a1 nc,a11 /ras dqm0 vssq vddq vddq dq4 dq2 1 1 2 2 3 3 7 7 8 8 9 9 4 4 5 5 6 6 a a b b c c d d e e f f g g h h j j k k l l m m n n p p r r top view
rev. 0.2 / may. 2004 4 preliminary HY5V72D(l/s)m(p) series 4banks x 4m x 32bits synchronous dram ball description pin pin name description clk clock the system clock input. all other in puts are registered to the sdram on the rising edge of clk. cke clock enable controls internal clock signal and wh en deactivated, the sdram will be one of the states among power down, suspend or self refresh cs chip select enables or disables al l inputs except clk, cke and dqm ba0, ba1 bank address selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a12 address row address : ra0 ~ ra12, column address : ca0 ~ ca8 auto-precharge flag : a10 ras , cas , we row address strobe, column address strobe, write enable ras , cas and we define the operation refer function truth table for details dqm0~3 data input/output mask controls output buffers in read mo de and masks input data in write mode dq0 ~ dq31 data input/output multip lexed data input / output pin vdd/vss power supply/ground power supply fo r internal circuits and input buffers vddq/vssq data output power/ ground power supply for output buffers nc no connection no connection
rev. 0.2 / may. 2004 5 preliminary HY5V72D(l/s)m(p) series 4banks x 4m x 32bits synchronous dram functional block diagram 4mbit x 4banks x 32 i/o low power synchronous dram internal row counter column pre decoder column add counter self refresh logic & timer sense amp & i/o gate i/o buffer & logic address register burst counter mode register state machine address buffers bank select column active row active cas latency clk cke cs ras cas we u/ldqm a0 a1 ba1 ba0 a12 row pre decoder refresh dq0 dq15 x decoder x decoder x decoder x decoder y decoder 4mx32 bank 0 4mx32 bank 1 4mx32 bank 2 4mx32 bank 3 memory cell array data out control pipe line control
rev. 0.2 / may. 2004 6 preliminary HY5V72D(l/s)m(p) series 4banks x 4m x 32bits synchronous dram basic functional description mode register note: 1. it must be used `ba1=0 /ba0=0' to set the mode resistor ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000 op code 00 cas latency bt burst length op code a9 write mode 0burst read and burst write 1 burst read and single write burst type a3 burst type 0 sequential 1 interleave burst length a2 a1 a0 burst length a3 = 0 a3=1 00 0 1 1 00 1 2 2 01 0 44 01 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved cas latency a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved
rev. 0.2 / may. 2004 7 preliminary HY5V72D(l/s)m(p) series 4banks x 4m x 32bits synchronous dram absolute maximum rating dc operating condition (t a = 0 to 70 o c ) note : 1. all voltages are referenced to v ss = 0v 2. v ih (max) is acceptable 5.6v ac puls e width with <=3ns of duration. 3. v il (min) is acceptable -2.0v ac pulse width with <=3ns of duration ac operating test condition (t a = 0 to 70 o c , v dd =3.3 0.3v, v ss =0v) note : parameter symbol rating unit ambient temperature t a 0 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd -1.0 ~ 4.6 v voltage on v ddq relative to v ss v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation pd 1 w soldering temperature . time t solder 260 . 10 o c . sec parameter symbol min typ max unit note power supply voltage v dd, v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.3 v ddq+ 0.3 v 1, 2 input low voltage v il -0.3 - 0.8 v 1, 3 parameter symbol value unit note ac input high/low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage v trip 1.4 v input rise/fall time t r / t f 1ns output timing measurement reference level voltage v outref 1.4 v output load capacitance for access time measurement cl 50 pf 1 vtt=1.4v rt=250 ?
rev. 0.2 / may. 2004 8 preliminary HY5V72D(l/s)m(p) series 4banks x 4m x 32bits synchronous dram capacitance (t a = 25 o c, f=1mhz ) dc characterristics i (t a = 0 to 70 o c, v dd =3.3 0.3v) note : 1. v in = 0 to 3.6v, all other balls are not tested under v in =0v 2. d out is disabled, v out =0 to 3.6 parameter pin symbol -h/p unit min max input capacitance clk ci1 tbd tbd pf a0~a11, ba0, ba1, cke, cs , ras , cas , we , udqm, ldqm ci2 tbd tbd pf data input/output capacitance dq0 ~ dq15 ci/o tbd tbd pf parameter symbol min max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -2ma output low voltage v ol -0.4v i ol = +2ma
rev. 0.2 / may. 2004 9 preliminary HY5V72D(l/s)m(p) series 4banks x 4m x 32bits synchronous dram dc characteristics ii (t a = 0 to 70 o c ) note : 1. i dd1 and i dd4 depend on output loading and cycle rates. spec ified values are measured with the output open 2. min. of trc (refresh ras cycle time) is shown at ac characteristics ii parameter symbol test condition speed unit note h p operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 240 220 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = 15ns 4 ma i dd2ps cke v il (max), t ck = 2ma precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 30 ma i dd2ns cke v ih (min), t ck = input signals are stable. 30 active standby current in power down mode i dd3p cke v il (max), t ck = 15ns 10 ma i dd3ps cke v il (max), t ck = 10 active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 60 ma i dd3ns cke v ih (min), t ck = input signals are stable. 40 burst mode operating cur- rent i dd4 t ck t ck (min), i ol =0ma all banks active cl=3 260 220 ma 1 cl=2 280 240 auto refresh current i dd5 t rc t rc (min), all banks active 440 400 ma 2 self refresh current i dd6 cke 0.2v nornal 6 ma low power 3 sl power 1.8 ma
rev. 0.2 / may. 2004 10 preliminary HY5V72D(l/s)m(p) series 4banks x 4m x 32bits synchronous dram ac characteristics i (ac operating conditions unless otherwise noted) note : 1. assume t r / t f (input rise and fall time) is 1ns. if t r & t f > 1ns, then [(t r +t f )/2-1]ns should be added to the parameter. 2. access time to be measured with input signal s of 1v/ns edge rate, from 0.8v to 0.2v. if t r > 1ns, then (t r /2-0.5)ns should be added to the parameter. parameter symbol h p unit note min max min max system clockcycle time cas latency=3 t ck3 7.5 1000 10 1000 ns cas latency=2 t ck2 10 10 ns clock high pulse width t chw 2.5 - 3.0 - ns 1 clock low pulse width t clw 2.5 - 3.0 - ns 1 access time from clock cas latency=3 t ac3 -5.4- 6 ns 2 cas latency=2 t ac2 -6-6 ns data-out hold time t oh 2.5 - 2.5 - ns data-input setup time t ds 2-2- ns 1 data-input hold time t dh 0.8 - 1 - ns 1 address setup time t as 1.5 - 2 - ns 1 address hold time t ah 0.8 - 1 - ns 1 cke setup time t cks 1.5 - 2 - ns 1 cke hold time t ckh 0.8 - 1 - ns 1 command setup time t cs 1.5 - 2 - ns 1 command hold time t ch 0.8 - 1 - ns 1 clk to data output in low-z time t olz 1-1- ns clk to data output in high-z time cas latency=3 t ohz3 2.0 5.4 2.0 6 ns cas latency=2 t ohz2 2.0 6 2.0 6 ns
rev. 0.2 / may. 2004 11 preliminary HY5V72D(l/s)m(p) series 4banks x 4m x 32bits synchronous dram ac characteristics ii (ac operating conditions unless otherwise noted) note : 1. a new command can be given t rc after self refresh exit. parameter symbol h p unit note min max min max ras cycle time operation t rc 65 - 70 - ns ras cycle time auto refresh t rrc 65 - 70 - ns ras to cas delay t rcd 20 - 20 - ns ras active time t ras 45 100k 50 100k ns ras precharge time t rp 20 - 20 - ns ras to ras bank active delay t rrd 15 - 20 - ns cas to cas delay t ccd 1-1-clk write command to data-in delay t wtl 0 - 0 - clk data-in to precharge command t dpl 2-2-clk data-in to active command t dal t dpl + t rp dqm to data-out hi-z t dqz 2-2-clk dqm to data-in mask t dqm 0-0-clk mrs to new command t mrd 2-2-clk precharge to data output high-z cas latency=3 t proz3 3-3-clk cas latency=2 t proz2 2-2-clk power down exit time t dpe 1-1-clk self refresh exit time t sre 1-1-clk1 refresh time t ref -64-64ms
rev. 0.2 / may. 2004 12 preliminary HY5V72D(l/s)m(p) series 4banks x 4m x 32bits synchronous dram command truth table command cken-1 cken cs ras cas we dqm addr a10/ap ba note mode register set h x l l l l x op code no operation h x hx xx xx lhhh bank active h x l l h h x ra v read hxlhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single-write h x l l l l x a9 ball high (other balls op code) mrs mode self refresh 1 entry h l l l l h x x exit l h hx xx x lhhh precharge power down entry h l hx xx x x lhhh exit l h hx xx x lhhh clock suspend entry h l hx xx x x lvvv exit l h x x
rev. 0.2 / may. 2004 13 preliminary HY5V72D(l/s)m(p) series 4banks x 4m x 32bits synchronous dram package information 90ball fbga with 0.8mm of pin pitch 6.40 0.80 (typ) 13.00+/-0.1 pin#1 id 0.80 (typ) 6.50+/-0.5 11.00 3.20+/-0.5 5.50+/-0.5 5.60+/-0.5 11.20 (ball-side view) 1.40 max 0.96+/-0.05 seating plane 6.40 0.80 (typ) 13.00+/-0.1 pin#1 id 0.80 (typ) 6.50+/-0.5 11.00 3.20+/-0.5 5.50+/-0.5 5.60+/-0.5 11.20 (ball-side view) 1.40 max 0.96+/-0.05 seating plane

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