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this is information on a product in full production. october 2014 docid026965 rev 1 1/26 aled6001 automotive-grade pwm-dimmable si ngle channel led driver with integrated boost controller datasheet - production data features ? switching controller section ? 5.5 v to 36 v input voltage range ? very low shutdown current: i shdn < 10 a ? internal +5 v ldo for gate driver supply ? internal +3.3 v ldo for device supply ? fixed frequency peak current mode control ? adjustable (100 khz to 1 mhz) switching frequency ? external synchronization for multi-device applications ? high performance external mosfet driver ? cycle-by-cycle external mosfet ocp ? fixed internal soft-start ? programmable output ovp ? boost, buck-boost and sepic topologies supported ? thermal shutdown with autorestart ? output short-circuit detection ? led control section ? up to 60 v output voltage ? constant current control loop ? high-side output current sensing circuitry ? 30 to 300 mv differential sensing voltage ? 4% output current reference accuracy ? output overcurrent protection ? sensing resistor failure protection ? pwm dimming with auxiliary series switch ? analog dimming applications ? automotive exterior lighting ? daytime running lights ? high and low beam lights ? fog lights ? position lights / blinkers description the aled6001 is an automotive-grade (aecq100 compliant) led driver that combines a boost controller and high-side current sensing circuitry optimized for driving one string of high- brightness leds. the device is compatible with multiple topologies su ch as boost, sepic and floating load buck-boost. pwm dimming of the led brightness is achieved by means of an external mosfet in series with the led string and directly driven by a dedicated pin. the pin that manages the led current setting, usually connected to an external resistor, can also be used as analog control if a microcontroller is located in the led module. the high-side current sensing, in combination with a p-channel mosfet, provides effective protection in case the positive terminal of the led string is shorted to ground. the high precision current sensing circuitry allows an led current regulation reference within 4% accuracy over the entire temperature range and production spread. a fault output (open-drain) informs the host system of faulty conditions: device overtemperature, output overvoltage (disconnected led string) and led overcurrent. table 1. device summary htssop-16 order code package packaging aled6001 htssop-16 (exposed pad) tube ALED6001TR tape and reel www.st.com
contents aled6001 2/26 docid026965 rev 1 contents 1 typical application circui t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 recommended operating c onditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.1 device supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2 boost controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2.1 turn on and power-down sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2.2 boost controller operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2.3 boost converter stability and slope compensation . . . . . . . . . . . . . . . . . 14 7.2.4 switching frequency osc illator and external synchron ization . . . . . . . . . 16 7.3 led current regulation and brightness control . . . . . . . . . . . . . . . . . . . . . 17 7.4 device protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.4.1 linear regulators undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.4.2 power switch overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.4.3 output overvoltage and ovfb pin disconnection . . . . . . . . . . . . . . . . . 20 7.4.4 output rail disconnection detection or output short-circuit to ground . . . 21 7.4.5 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
docid026965 rev 1 3/26 aled6001 typical application circuit 26 1 typical application circuit figure 1. basic application ci rcuit schematic (boost topology) $/(' 9'5 9,1 *$7( &616 3*1' 9)%3 9)%1 3:02 29)% /'2 &203 ;)$8/7 $',0 6*1' 3:0, )6: 9 ,1 & ,1 & 287 5 9)% 5 *$7( 4 6: 4 ',0 5 616 5 )6: 5 &203 & /'2 & 9'5 & &203 9 29)% 9 29)% 9 287 5 6/23( 5 29)%+ 5 29)%/ 9 /'2 9 /'2 9 /'2 / %2267 ' ): $09
pin function aled6001 4/26 docid026965 rev 1 2 pin function figure 2. pin connection (through top view) $09 3:0, )6 : ;)$8 /7 /'2 6*1' &203 $',0 29 )% 9)%3 9)%1 9,1 9'5 *$7( 3*1' &616 3:02
docid026965 rev 1 5/26 aled6001 pin function 26 table 2. pin description no. pin 1 pwmi device enable and pwm dimming control input. 2fsw switching frequency setting. a resistor between this pin and sgnd sets the desired switching frequency. this pin is also used as synchronization input. if tied high (e.g.: connected to ldo3 pin) a 600 khz switching frequency is set. 3xfault fault indicator, open-drain output. this pin is tied low by the device in case of faulty condition. see section 7.4 on page 20 for details. 4ldo3 3.3 v linear regulator output and device supply. connect a 1 ? f (typ.) bypass mlcc between this pin and sgnd as close as possible to the chip. 5sgnd signal ground. return for analog circuitry. all setting components must refer to this grounding pin. 6comp boost controller loop compensation. a simple rc series must be connected between this pin and sgnd for pr oper loop compensation. see section 7.2.3 on page 14 for details. 7adim analog dimming control input. the current at the output is linear ly controlled by the voltage applied to this pin (0.3 v to 1.2 v). when the device is set to operate in standalone mode, a partition of the ldo3 voltage must be applied to this pin through a resistor divider. 8ovfb output overvoltage protection feedback input. connect to the central tap of a resistor divider at the output. 9 csns boost controller power switch current sens ing input. connect to the source of the external power mosfet for proper switch overcurrent protection. 10 pwmo pwm dimming control output. this pin pr ovides a pwm output signal (in phase with the one applied to the pwmi pin) for direct control of a dimming n-channel mosfet. 11 pgnd power ground. return for the vdr linear regulator and the power switch gate drivers. also used as reference for the power mosfet current sensing circuitry. connect to ground as close as possible to the quiet terminal of the power switch sensing resistor. 12 gate power switch gate driver output. conn ect to the gate of the power mosfet through a small value resistor. 13 vdr 5 v linear regulator output and gate driver supply. connect a 1 ? f (typ.) bypass mlcc between this pin and pgnd as close as possible to the chip. 14 vin supply voltage input. connect this pin to the supply power rail. a 1 ? f (typ.) bypass mlcc must be connected between this pin and pgnd as close as possible to the chip. 15 vfbn output current differential sensing input, negative terminal. connect to the hot terminal (load side) of the high-side sensing resistor. 16 vfbp output current differential sensing inpu t, positive terminal. connect to the quiet terminal (output capacitor side) of the high-side sensing resistor. -tpad thermal pad. connect to a suitable ground plane area in order to ensure proper heat dissipation. electrically connected to pgnd and sgnd.
block diagram aled6001 6/26 docid026965 rev 1 3 block diagram figure 3. simplified block diagram /'2 )6: 3:0, ;)$8/7 &203 3*1' &616 9,1 6\qf ghwhfwru 26& 89/2 ghwhfwru 9/'2 5dps jhqhudwru &xuuhqw vhqvlqj 6riwvwduw %rrvw frqyhuwhu frqwuroorjlf b *$7( b $',0 9 293 29)% 9)%3 9)%1 9'5 9/'2 &rqwuroorjlf 3:02 6*1' b j p 2xwsxw fxuuhqw vhwwlqj 3:0ghwhfwru 3rz hugrzq zdwfkgrj wlphu )dxow pdqdjhphqw (1 (1 9'5 3*1' (1 7khupdo surwhfwlrq p9p9 6orsh frpshqvdwlrq )hhgedfnrxwsxw glvfrqqhfwlrqdqg ryhuordgghwhfwlrq $0
docid026965 rev 1 7/26 aled6001 absolute maximum ratings 26 4 absolute maximum ratings table 3. absolute maximum ratings (1) 1. stresses beyond those listed in table 3 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any ot her condition above those indicated in table 5 is not implied. exposure to absolute maximum rated conditions for extended per iods may affect device reliability. parameter pin min. max. unit maximum pin voltage vin to sgnd 40 v vfbp and vfbn to sgnd 65 vdr to sgnd -0.3 6 ldo3 to sgnd -0.3 3.6 comp, csns and ovfb to sgnd -0.3 3.6 pgnd to sgnd -0.3 0.3 xfault, fsw, adim and gate to sgnd -0.3 6 pwmi and pwmo to sgnd -0.3 6 hbm esd susceptibility jedec js001 all pins -2000 2000 vin, vfbp, vfbn and adim esd susceptibility vin, vfbp, vfbn, adim to sgnd -4000 4000 cdm esd resistivity to sgnd ansi/esd stm5.3.1 corner pins -750 750 non-corner pins -500 500 table 4. thermal characteristics symbol parameter conditions min. typ. max. unit t j,op operating junction temperature -40 150 c t stg storage temperature range -50 150 t shdn thermal shutdown threshold 150 160 175 thermal shutdown hysteresis 20 xfault release hysteresis 40 r th,ja (1) junction to ambient thermal resistance 1s0p 55 c/w 2s2p 45 r th,jc junction to case thermal resistance 37 1. the device mounted on a standard jesd51-5 test board.
recommended operating conditions aled6001 8/26 docid026965 rev 1 5 recommended operating conditions table 5. recommended operating conditions symbol parameter conditions min. max. unit dc characteristics v vin supply input voltage range 5.5 36 v v vdr vdr pin input voltage range vdr and vin shorted together 4.7 5.5 v vfbx feedback input common mode voltage range 4.4 60 v fb feedback input differential mode voltage range vfbp to vfbn 30 300 mv ac characteristics f sw switching frequency 100 1000 khz f pwmi dimming frequency 0.1 20 t pwmi,en minimum pwmi pulse duration for device enable (turn on) pwmi input, f sw = 800 khz 100 s t pwmi,dim minimum dimming on-time pwmi input, f sw = 1 mhz 6 s
docid026965 rev 1 9/26 aled6001 electrical characteristics 26 6 electrical characteristics v in = 12 v, v vfbp = 12 v, v vfbn = 12 v and t j =- 40 c to 125 c if not otherwise specified. table 6. electrical characteristics symbol parameter conditions min. typ. max. unit supply section v vin supply voltage range 5.5 36 v pwmi turn on threshold 1.34 1.65 pwmi turn off threshold 0.7 0.85 1.1 pwmi pull-down resistor pmwi at 3.3 v 350 570 810 k ? t shdn pwmi low to shutdown mode delay 10 15 22 ms t start start-up time c ldo3 = c vdr = 470 nf 100 180 s v ldo3 3.3 v ldo output voltage 6 v ? v in ? 36 v, i ldo3 = 0.5 ma, pwmi high 3.17 3.3 3.4 v 3.3 v ldo line regulation i ldo3 = 20 ma, pwmi high 6 v ? v in ? 36 v 520 mv 3.3 v ldo load regulation v in = 6 v, pwmi high 0.5 ma ? i ldo3 ? 20 ma 90 100 v ldo3,on ldo3 undervoltage lockout upper threshold 2.2 2.8 3.0 v v ldo3,off ldo3 undervoltage lockout lower threshold 2.5 2.7 2.9 ldo3 undervoltage lockout hysteresis 50 200 400 mv 3.3 v ldo current limit vldo3 = 3.0 v 25 38 46 ma v vdr 5 v ldo output voltage 6 v ? v in ? 36 v i vdr = 0.5 ma, pwmi high 4.75 5.0 5.2 v 5 v ldo line regulation i vdr = 40 ma, pwmi high 6 v ? v in ? 36 v 10 40 mv 5 v ldo load regulation v in = 6 v, pwmi high 0.5 ma ? i vdr ? 40 ma 120 200 5 v ldo dropout voltage i vdr = 25 ma, v vin = 4.8 v 150 300 v vdr,on vdr undervoltage lockout upper threshold 4.3 4.6 4.75 v v vdr,off vdr undervoltage lockout lower threshold 4.1 4.4 4.6 vdr undervoltage lockout hysteresis 100 150 340 mv 5 v ldo current limit v vdr = 4.5 v 50 75 100 ma
electrical characteristics aled6001 10/26 docid026965 rev 1 power consumption i vin,shdn shutdown current v in = 16 v, pwmi low, -40 c ?? t j ?? 25 c 1410 ? a v in = 16 v, pwmi low, 25 c ?? t j ?? 125 c 1925 i vin,q quiescent current v in = 16 v, pwmi to ldo3, -40 c ?? t j ?? 125 c switching off-time 11.7 ma i vin,on operating current v in = 16 v, pwmi high, f sw = 200 khz, c l = 3.3 nf 57 boost controller t on,min minimum switching on-time pulse skipping mode 140 180 ns k fsw switching frequency constant r fsw = 250 k ? 45 50 55 mhz ? k ? f sw adjustable switching frequency r fsw = 500 k ? 90 100 110 khz r fsw = 250 k ? 180 200 220 r fsw = 50 k ? 870 1000 1070 fixed switching frequency fsw pin high (ldo3) 490 600 710 synchronization signal frequency capture range t clk,h = 250 ns, v clk,l = 0.8 v, v clk,h = 3.0 v 100 1000 fsw synchronization input high level f clk = 100 khz to 1 mhz, t clk,h = 250 ns 2.8 v fsw synchronization input low level 0.5 synchronization input high level pulse width f clk = 100 khz to 1 mhz, v clk,l = 0.5 v, v clk,h = 2.8 v 250 ns r gate power switch gate driver output resistance pull-up 3 6 ? pull-down 1 3 t r,gate power switch gate driver rise time (20 to 80%) v vdr = 5 v, c l = 3.3 nf 15 30 ns t f,gate power switch gate driver fall time (80 to20%) 714 t ss internal soft-start duration 2.7 3.5 4.6 ms k s slope compensation constant 3 5 7 a/s v csns,ocp power switch ocp detection threshold csns pin to pgnd 300 360 400 mv table 6. electrical characteristics (continued) symbol parameter conditions min. typ. max. unit
docid026965 rev 1 11/26 aled6001 electrical characteristics 26 output current sensing section v fb feedback voltage (v vfbp - v vfbn differential current sensing voltage) v adim = 0.3 v 20 30 40 mv v adim = 0.6 v 110 120 130 v adim = 1.2 v 280 300 304 feedback reference voltage accuracy v adim to ldo3 290 300 310 v adim,off adim pin voltage turn off threshold 240 270 290 adim pin voltage turn off hysteresis 1 10 20 i vfbp feedback positive input current v vfbp = 12.0 v v vfbn = 11.7 v -32 -25 -18 ? a i vfbn feedback negative input current v vfbp = 12.0 v v vfbn = 11.7 v -7 -5 -4 pwm dimming control r pwmo pwmo gate driver output resistance pull-up 14 25 ? pull-down 3 8 t r,pwmo pwmo gate driver rise time (20 to 80%) v vdr = 5 v, c l = 3.3 nf 50 130 ns t f,pwmo pwmo gate driver fall time (80 to 20%) 30 60 fault management section xfault output low level i xfault = 4 ma 0.12 0.2 v xfault high level leakage current v xfault = 5 v 1 4 a v ovfb,th ovfb input overvoltage detection threshold 1.14 1.20 1.25 v ovfb input overvoltage detection hysteresis 70 100 130 mv ovfb pull-up current v ovfb = 1 v 0.7 1 1.2 a open load/vfbp pin disconnection detection threshold (differential) (v vfbp - v vfbn ) -190 -120 -80 mv overload /vfbn pin disconnection detection threshold (differential) 550 600 650 vfbx undervoltage detection threshold v vfbx respect to sgnd 3.1 3.5 4.1 v table 6. electrical characteristics (continued) symbol parameter conditions min. typ. max. unit
device description aled6001 12/26 docid026965 rev 1 7 device description the aled6001 device is a led driver that integrates a boost controller, a high-side current sensing circuitry and a gate driver for an ex ternal dimming switch. it has been specifically designed for driving a single string of high-brightness leds. the device can support boost, floating buck-boost and sepic topologies in order to cover most of applications. a single pin, pwmi, combines both the device enable and pwm dimming control functions. the brightness of the led string can be co ntrolled through pwm modulation, analog control of the output current level (by means of a dedicated pin) or a combination of the two. 7.1 device supply the aled6001 device integrates two low dropout linear regulators to derive the + 3.3 v (typ.) main supply and the +5 v supply for the gate drivers. the vin pin is the input terminal for both linear regulators. both the linear regulators are enabled when a pwm signal is applied to the pmwi pin. if the pwmi pin is held low for more than 10 ms (min.), the shutdown mode is automatically entered and both the ldos are turned-off for minimum power consumption. an undervoltage lockout (uvl o) protection is associated to each linear regulator: in case the output voltage of ldo3 and vdr is below their respective nominal value, the device is no allowed to operate and the xfault pin is tied low. when an external +5 v rail is available, the related internal ldo can be bypassed by connecting together the vin and vdr pins: in th is case the vdr pin is used as supply input. 7.2 boost controller 7.2.1 turn on and power-down sequences the aled6001 is turned on and off by acting on the pwmi pin. this digital input combines two functions at the same time: device turn on/off and pwm dimming control. when a high pulse having a 100 s (typ.) mi nimum duration appears at the pwmi pin, the ldos are turned on and, after the vdr has reached its nominal value, a soft-start sequence on the boost controller takes place. the output voltage is smoothly increased by releasing in steps the current limit of the boost converter within a fixed 3 ms (typ.) period, unless the feedback voltage reaches 75% of the nominal value in advance.
docid026965 rev 1 13/26 aled6001 device description 26 figure 4. turn on and turn off waveforms suddenly after the pulse detection at the pwmi pin, an internal timer is enabled and cleared. the timer starts counti ng down on every subsequent fa lling edge. if the pwmi pin is held low for more than 10 ms (typ.), the timer is allowed to expire and the aled6001 automatically turns off minimizing the current consumption. the start-up time, defined as the delay between the rising edge at the pwmi pin and the first pulse at the gate pin, clearly depends on the bypass capacitors connected on both ldo3 and vdr pins. with a typical 1 f mlcc for both pins, the start-up time is in the order of 100 s. 7.2.2 boost cont roller operation the boost controller of the aled6001 device is based on peak current mode control architecture and can easily su pport boost, floating buck-b oost and sepic t opologies. the switching frequency of the conv erter is set through the fsw pi n (external clock source or setting resistor toward ground) while the switching duty cyc le is modulated by the control loop in order to keep the output (led) curr ent constant. as a consequence, the output voltage of the boost converter is determined by the led string. 3:0, /'2 9'5 9 287 , /(' w 67$57 w 6+'1 w 66 $0
device description aled6001 14/26 docid026965 rev 1 figure 5. simplified output regulation circuitry the boost controller regulates the output (led) current by measuring the voltage across the external sensing resistor. the internal circui try related to the two pins connected to the sensing resistor (vfbp and vfbn) has been de signed to implement a high-side sensing scheme and can sustain a relatively high voltage. the voltage drop across the sensing resistor is the actual feedback voltage for the boost regulator control loop and it can be linearly varied by means of the adim pin (see section 7.3: led curr ent regulation and brightness control on page 17 for details). the comp pin is the output of the transconductance amplifier involved in the regulation loop and a simple rc series must be connected between this pin and sgnd to ensure proper loop stability. 7.2.3 boost converter stabil ity and slope compensation as visible in figure 5 , the difference between the feedback voltage and the programmed is converted into an error current by the transconductance amplifier. this current, provided at the comp pin, is turned into a voltage ac ross the compensation network externally connected to the same pin. this voltage, in tu rn, determines the trip current for th e following error amplifier. when the boost converter operates in continuous conduction mode (ccm) and the switching duty cycle is higher than 50%, sub-harmonic instability may occur. in order to prevent this, the trip current has to be properly shaped by summing a negative sawtooth ramp voltage (slope compensation) with the amplified error voltage. *$7( &616 3*1' 9)%3 9)%1 &203 $',0 3:0, )6: 9 ,1 5 9)% 5 616 5 )6: 5 &203 & &203 9 287 5 6/23( 6\qf ghwhfwru 26& b b j p p9 p9 (qdeoh ghwhfwrudqg dxwrvkxwgrzq frxqwhu )hhgedfn uhihuhqfh vhwwlqj 5 6 4 (1 (1 (1 &xuuhqw udps jhqhudwru ?$ , 6/ , 6/ 3:02 9 $',0 & ,1 & 287 / 4 6: 4 ',0 $0
docid026965 rev 1 15/26 aled6001 device description 26 in the aled6001 the slope compensation is ac hieved by injecting a sawtooth current into the csns pin. therefore the voltage across the csns pin is given by: equation 1 v csns (t) = i mos (t) ?? r shunt + i sl (t) ? r csns the r sns resistor is usually designed so that the peak voltage is about 15% of the overcurrent threshold at the csns pin in or der to have a good s/n ratio, while the r slope resistor is calculated for the desired slope comp ensation amount (typically at least half the downslope of the inductor current during the switching off-time): equation 2 equation 3 where i sl = 50 a is the maximum current injected by the slope compensation circuitry in the csns pin. figure 6. power switch current sensing scheme r sns 50mv i l peak ? ------------------- - ? r slope v out v ? in min ? f sw ? l ---------------------------------------- ? r sns i sl -------------- ? *$7( &616 9 ,1 5 616 5 6/23( ?$ , 6/ , 6/ 9 616 9 6& b p9 2&3 $0
device description aled6001 16/26 docid026965 rev 1 7.2.4 switching frequency oscill ator and external synchronization the switching frequency of the boost controlle r is simply set by connecting a resistor between the fsw pin and ground. the resistor can be calculated according to equation 4 : equation 4 where k fsw = 5 ?? 10 10 hz ?? ? (typ.) and 100 khz ? f sw ? 1 mhz. figure 7. switching frequency vs. setting resistor at the fsw pin if the fsw pin is tied high (e.g.: connecting it to ldo3), a 600 khz (typ.) default switching frequency is set. in case the boost controller of the aled6001 has to be externally synchronized, the fsw pin can be used as synchronization clock input. in this case the external clock must have a frequency in the 100 khz - 1 mhz range and a 250 ns minimum pulse duration in order to ensure internal oscillator locking. r k fsw f sw -------------- - = 5 )6: i 6: n+] $0
docid026965 rev 1 17/26 aled6001 device description 26 figure 8. external synchroni zation signal timing diagram 7.3 led current regulation and brightness control the brightness of the leds connected at the output of the aled6001 can be controlled by applying the desired pwm signal at the pwmi pi n. the boost controller is turned on and off according to the duty cycle of the pwmi contro l signal. when the pwmi is high (and the soft-start has been completed), the output (led ) current is regulated by keeping constant the voltage drop across the external sensing resistor connected between the vfbp and vfbn pins. a buffered replica of pwmi is available at the pwmo for driving a dimming n-channel mosfet when superior dimming performance is required. in some applications a high-side dimming switch could be desirable (e.g.: protecti on against output short-circuit to ground or led strings using the chassis as return) and a p-channel mosfet can be used as shown in figure 9 . some additional components may be needed to avoid excessive voltage between the gate and the source of such mosfet. 9 9 qv w 9 )6: $0
device description aled6001 18/26 docid026965 rev 1 figure 9. high-side dimming control by using a p-channel mosfet the regulation loop continuously compares the di fferential voltage drop with an internal reference and adjusts the switching duty cycle accordingly. in order to provide design flexibility and analog dimming ca pability, the internal feed back reference can be changed through the adim pin. as visible in figure 10 , the reference voltage is proportional to the voltage at the adim pin within a limited range. equation 5 $09 $/(' 9'5 9,1 *$7( &616 3*1' 9)%3 9)%1 3:02 29)% /'2 &203 ;)$8/7 $',0 6*1' 3:0, )6: 9 ,1 & ,1 & 287 5 9)% 5 29)%+ 5 29)%/ 5 *$7( 5 */ 4 6: 4 ',0/ 4 ',0+ 5 616 5 )6: 5 &203 ' = & /'2 & 9'5 & &203 9 29)% 9 29)% 9 287 5 6/23( 9 /'2 9 /'2 5 *+ / %2267 ' ):
docid026965 rev 1 19/26 aled6001 device description 26 figure 10. differential feedback reference voltage vs. adim pin voltage in case a fixed output (led) current is neede d or simple pwm dimming is used, the adim pin must be connected to the central tap of a re sistor divider (supplied by the ldo3 pin) for the desired led current level. because of t he best led current accuracy overtemperature is obtained at full scale, a voltage higher than 1.2 v should be applied at the adim pin in case the analog dimming is not needed. if an analog dimming control is required, the voltage at the adim pin can be changed runtime within its functional range. a simple way to perform an analog dimming is easily achieved by extracting the average value of a pwm signal through a simple rc low-pass filter ( figure 10 ). figure 11. simple adim pin voltage control through a filtered pwm signal if the voltage at the adim pin is lower than 240 mv, both the pwmo and gate pins are forced low and the boost converter is temporary disabled. as soon as the adim pin voltage is driven inside the operating range, normal operation is resumed. p9 p9 p9 9 p9 9 $',0 9 5() $0 $/(' $',0 6*1' 3:0, & i 5 i $09
device description aled6001 20/26 docid026965 rev 1 7.4 device protections 7.4.1 linear regulator s undervoltage lockout both the 5 v and 3.3 v linear regulators of the aled6001 are equipped with an undervoltage lockout (uvlo) protection. th e uvlo protections avoid improper device operation in case at least one of the two outputs (vdr and ldo3) is below the allowed level. in particular, the aled6001 performs t he soft-start sequence only after both vdr and ldo3 cross their respective upper uvlo threshold. 7.4.2 power switch overcurrent the current flowing through the external powe r mosfet is monitored, cycle-by-cycle, by sensing the voltage across the sh unt resistor in series with it s source. if the voltage drop exceeds the overcurrent protection (ocp) leve l, the ongoing switching cycle is suddenly terminated (cycle-by-cycle power mosfet ocp). normal operatio n is automatically resumed once the root cause has been removed. the xfault pin is not affected by ocp. as explained in section 7.2 on page 12 the slope compensation is added by injecting a sawtooth current at the csns pin. as a consequence, the ocp threshold depends on both the slope compensation amount and the boost converter's operating point: equation 6 where v csns,ocp = 360 mv (typ.), i sl = 50 a (typ.) and d is the switching duty cycle. 7.4.3 output overvoltage and ovfb pin disconnection the output overvoltage fault detection is achi eved by comparing the voltage at the ovfb pin with an internal threshold. because of th is fault can potentially damage both the device and the external components, a latched turn off condition is triggered once this event has been detected. a resistor divider connected to the output of the boo st converter sets the desired ovp threshold. the ovfb is internally pulled-up in order to protect the device against an ovfb pin disconnection fault: if the pin is left floating, the ovp is suddenly triggered regardless of the output voltage level. this small pull-up current (i ovfb,pu ) must be taken into account when designing an ovp output divider involving high resistance values. equation 7 allows setting the desired output ovp level (r ovph and r ovpl are the two resistors of the output divider whose central tap is connected to the ovfb pin of the aled6001): equation 7 where v th,ovfb = 1.2 v (typ.) and i ovfb,pu = 1 a (typ.). once the ovp faulty condition is detected, the aled6001 device suddenly stops switching. both gate and pwmo are forced low and the xfault pin is lowered. the condition is latched and normal operation is resumed by toggling the pwmi pin (pwmi has to be low for more than 10 ms) after the root cause has been removed. i mos ocp ? v csns ocp ? di sl r slope ? ? ? r sns ---------------------------------------------------------------------------------- = v out ovp ? r ovph r ovpl + r ovpl ------------------------------------------ - v th ovfb ? r ovpl i ovfb pu ? ? ? =
docid026965 rev 1 21/26 aled6001 device description 26 7.4.4 output rail disconne ction detection or output short-circuit to ground if the connection between the output rail and the ou tput sensing resistor is lost, the voltage of both the vfbp and vfbn pins falls down to zero. the aled6001 detects this faulty condition by comparing the absolute voltage of both vfbp and vfbn pins with an internal 3.3 v threshold and latches-off as a consequence (the gate and pwmo pins forced low, xfault pin lowered). normal operation is re sumed by toggling the pwmi pin (pwmi has to be low for more than 10 ms) after the root cause has been removed. when the aled6001 is operating with a boost topo logy, a similar condition occurs in case of output-to-ground short-circuit. of course, because of the inherent path between input and output, a real protection against this faulty condition can be achieved only if the device is capable of disconnecting the boost output by means of the dimming switch (e.g.: in case a p-channel mosfet is used as a high-side dimming switch). figure 12. load disconnection (1 and 5), open feedback (2 and 3) and open ovfb faulty conditions $/(' 9'5 9,1 *$7( &616 3*1' 9)%3 9)%1 3:02 29)% /'2 &203 ;)$8/7 $',0 6*1' 3:0, )6: 9 ,1 9 /'2 & ,1 & 287 5 9)% 5 29)%+ 5 29)%/ 5 *$7( 4 6: 4 ',0 5 616 5 $',0+ 5 )6: 5 &203 / %2267 ' ): & 9'5 & /'2 & &203 9 29)% 9 287 5 6/23( 9 /'2 5 $',0/ 9 287 9 )% $09
device description aled6001 22/26 docid026965 rev 1 7.4.5 thermal shutdown the aled6001 implements an autorestarting th ermal protection in order to avoid damages due to excessive die temperature. once the chip temperature reaches the upper overtemperature protection (otp) threshold, the ongoing operation is suddenly stopped, both the pwmo and xfault pins are held low and the 5 v linear regulator (vdr pin) is turned off. as soon as the die temperature dr ops below the autorestarting threshold, a new soft-start sequence takes place if the pwmi pin is still high and a 1 ms (typ.) deglitch delay has expired. the xfault pin goes low as soon as the otp threshold is crossed a nd it is released once the device temperature drops below a third threshold, lower than the restart one, in order to provide a stable information to the host system. table 7. faulty conditions management summary faulty condition detection mechanism consequence 1 output rail/load disconnection v vfbx <3.5 v device turning-off (latched condition). gate, pwmo and xfault pins are forced low. 2 open feedback (vfbp) v vfbp - vvfbn <-120 mv 3 open feedback (vfbn) v vfbp - vvfbn > 600 mv led overcurrent output to gnd short-circuit (1) 4 open ovfb path v ovfb > 1.2 v (internal pull-up) 5 open pwmo (loss of dimming mosfet control) v ovfb > 1.2 v output overvoltage power switch overcurrent v csns > 360 mv ongoing switching cycle terminated ic overtemperature t j > 160 c (typ.) device turning-off (vdr off, ldo3 active). gate, pwmo and xfault pins are forced low. autorestart if t j < 140 c (typ.) and pwmi still high. xfault pin is released if t j <120 c (typ.). 1. output-to-ground short-circuit protecti on can be achieved only if the device can effectively disconnect the output by acting on the pwmo pin (e.g.: a high-side p-chan nel mosfet is used as a dimming switch).
docid026965 rev 1 23/26 aled6001 package information 26 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. figure 13. htssop-16 package outline
package information aled6001 24/26 docid026965 rev 1 ) table 8. htssop-16 package mechanical data (1) symbol dimensions (mm) note min. typ. max. a1.20 (1) 1. htssop stands for ?thermally enhanced variations?. a1 0.15 a2 0.80 1.00 1.05 b0.19 0.30 c0.09 0.20 d 4.90 5.00 5.10 (2) 2. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. d1 3.00 (3) 3. the size of exposed pad is variable depending of leadf rame design pad size. end user should verify ?d1? and ?e2? dimensions fo r each device application. e 6.20 6.40 6.60 e1 4.30 4.40 4.50 (4) 4. dimension ?e1? does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.25 mm per side. e2 3.00 (3) e0.65 l 0.45 0.60 0.75 l1 1.00 k0.00 8.00 aaa 0.10
docid026965 rev 1 25/26 aled6001 revision history 26 9 revision history table 9. document revision history date revision changes 01-oct-2014 1 initial release.
aled6001 26/26 docid026965 rev 1 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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