View ATA5823-14_8302652.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4829f-rke-05/14 features high fsk sensitivity: ?105.5dbm at 20kbit/s/?109dbm at 2.4kbit/s (433.92mhz) high ask sensitivity: ?111.5dbm at 10kbit/s/?116dbm at 2.4kbit/s (100% ask, carrier level 433.92mhz) low supply current: 10.5ma in rx and tx mode (3v/tx with 5dbm/433.92mhz) data rate 1 to 20kbit/s manchester fsk, 1 to 10kbit/s manchester ask ask/fsk receiver uses a low if architecture with high selectivity, blocking and low intermodulation (typical 3db blocking 55.5dbc at 750khz/60.5dbc at 1.5mhz and 67dbc at 10mhz, system i1dbcp = ?30dbm/system iip3 = ?20dbm) wide bandwidth agc to handle large outband blockers above the system i1dbcp 226khz if (intermediate frequency) with 30db image rejection and 220khz system bandwidth to support tpm transmitters using atmel ? ata5756/ata5757 transmitters with standard crystals transmitter uses closed loop fsk modulati on with fractional-n synthesizer with high pll bandwidth and an excellent isolation between pll and pa tolerances of xtal compensated by fractional-n synthesizer with 800hz rf resolution integrated rx/tx-switch, single-ended rf input and output rssi (received signal strength indicator) communication to microcontroller with spi interface working at 500kbit/s maximum configurable self polling and rx/tx protocol handling with fifo-ram buffering of received and transmitted data 1 push button input and 1 wake-up input are active in power-down mode integrated xtal capacitors pa efficiency: up to 38% (433.92mhz/10dbm/3v) low in-band sensitivity change of typically 2.0db within 75khz center frequency change in the complete temperature and supply voltage range ata5823/ata5824 uhf ask/fsk transceiver datasheet
ata5823/ata5824 [datasheet] 4829f?rke?05/14 2 fully integrated pll with low phase noise vco, pll loop filt er and full support of multi-channel operation with arbitrary channel distance due to fractional-n synthesizer sophisticated threshold control and quasi-peak detector circuit in the data slicer 433.92mhz, and 315mhz without external vco and pll components efficient xto start-up circuit (> ?1.5k worst case start impedance) changing of modulation type ask/fsk and data rate without co mponent changes to allow different modulation schemes in tpm and rke minimal external circuitry requirements for complete system solution adjustable output power: 0 to 10dbm adjusted and stabilized with external resistor, programmable output power with 0.5db steps with internal resistor clock and interrupt generation for microcontroller esd protection at all pins (2.5kv hbm, 200v mm, 500v fcdm) supply voltage range: 2.15v to 3.6v or 4.4v to 5.25v typical power-down current < 10na temperature range: ?40c to +105c small 7mm 7mm qfn48 package applications automotive keyless entry and passive entry go (handsfree car access) tire pressure monitoring systems remote control systems alarm and telemetering systems energy metering home automation benefits no saw device needed in key fob designs to meet automotive specifications low system cost due to very high system integration level only one crystal needed in system less demanding specification for the microcontroller due to handling of power-down mode, delivering of clock and complete handling of receive/transmit protocol and polling single-ended design with high isolation of pll/vco from pa and the power supply allows a loop antenna in the key fob to surround the whole application integration of tire pressure monitoring, passive entry and remote keyless entry
3 ata5823/ata5824 [datasheet] 4829f?rke?05/14 1. general description the atmel ? ata5823/ata5824 is a highly integr ated uhf ask/fsk multi-c hannel half-duplex transceiver with low power consumption supplied in a small 7mm 7mm qfn48 package. the receive part is built as a fully integrated low-if receiver, whereas direct pll modulation with the fractional-n synthesizer is used for fsk transmission and switching of the power amplifier for ask transmission. the device supports data rates of 1kbit/s to 20kbit/s (fsk) and 1kbit/s to 10kb it/s (ask) in manchester, bi-phase and other codes in transparent mode. the atmel ata5824 can be used in the 433mhz to 435mhz band and the atmel ata5823 in the 313mhz to 316mhz band. the very high s ystem integration level results in few numbers of external components needed. due to its blocking and selectivity perfor mance, together with a typical narrow- band key-fob loop antenna with 15db to 20db loss, a bulky blocking saw is not needed in the key fob application. additionally, the building blocks needed for a typical rke and access control system on both sides, the base a nd the mobile stations , are fully integrated. its digital control logic with self polling and protocol generati on provides a fast challenge response system without using a high-performance microcontroller. theref ore, the atmel ata5823/at a5824 contains a fifo buffer ram and can compose and receive the physical messages themselves. this provides more time for the microcontroller to carry out other functions such as calculating crypto algorithms, composing the logical messages and controlling other devices. due to that, a standard 4-/8-bit microcontroller without special peri phery and clocked with the delivered clk ou tput of about 4.5mhz is sufficient to control the communication link. this is es pecially valid for passive entry go and access control systems, where within less than 100 ms several communication responses with arbitration of the communication partner have to be handled. it is hence possible to design bi-directional rke and passive entry go systems with a fast challenge re sponse crypto function and prevention against relay attacks. figure 1-1. system block diagram xto ata5823/ata5824 a ntenna 4 to 8 power supply micro- controller matching/ rf switch digital control logic rf transceiver microcontroller interface
ata5823/ata5824 [datasheet] 4829f?rke?05/14 4 2. pin configuration figure 2-1. pinning qfn48 table 2-1. pin description pin symbol function 1 nc not connected 2 nc not connected 3 nc not connected 4 rf_in rf input 5 nc not connected 6 433_n868 selects rf input/output frequency range 7 nc not connected 8 r_pwr resistor to adjust output power 9 pwr_h pin to select output power 10 rf_out rf output 11 nc not connected 12 nc not connected 13 nc not connected 14 nc not connected 15 nc not connected 16 avcc blocking of the analog voltage supply 17 vs2 power supply input for voltage range 4.4v to 5.6v 18 vs1 power supply input for voltage range 2.15v to 3.6v 19 setpwr internal programmable resistor to adjust output power 20 test1 test input, at gnd during operation 21 dvcc blocking of the digital voltage supply rssi cs sck sdi_tmdi sdo_tmdo ata5823/ata5824 clk vsint xtal2 25 nc pout irq test3 nc nc rf_in nc 433_n868 nc rf_out nc pwr_h r_pwr nc nc nc avcc vs2 vs1 setpwr test1 dvcc cs_pol test2 txal1 nc rx_active n_pwr_on sck_pha sck_pol nc nc pwr_on rx_tx1 rx_tx2 cdem 1 2 3 4 9 10 11 5 6 8 7 36 35 34 33 28 27 26 32 31 29 30 nc 12 47 46 45 44 38 37 39 41 40 42 43 14 nc nc 48 13 15 16 17 23 24 22 20 21 19 18
5 ata5823/ata5824 [datasheet] 4829f?rke?05/14 22 cs_pol select polarity of pin cs 23 test2 test input, at gnd during operation 24 xtal1 reference crystal 25 xtal2 reference crystal 26 nc not connected 27 vsint microcontroller interface supply voltage 28 pout programmable output 29 irq interrupt request 30 clk clock output to connect a microcontroller 31 sdo_tmdo serial data out/transparent mode data out 32 sdi_tmdi serial data in/transparent mode data in 33 sck serial clock 34 test3 test output open during operation 35 cs chip select for serial interface 36 rssi output of the rssi amplifier 37 cdem capacitor to adjust the lower cut-off frequency data filter 38 rx_tx2 has to be connected gnd 39 rx_tx1 switch pin to decouple lna in tx mode (rke mode) 40 pwr_on input to switch on the system (active high) 41 nc not connected 42 nc not connected 43 sck_pol polarity of the serial clock 44 sck_pha phase of the serial clock 45 n_pwr_on keyboard input (can also be used to switch on the system, active low) 46 rx_active indicates rx operation mode 47 nc not connected 48 nc not connected gnd ground/backplane (exposed die pad) table 2-1. pin description (continued) pin symbol function
ata5823/ata5824 [datasheet] 4829f?rke?05/14 6 figure 2-2. block diagram signal processing (mixer if-filter if-amplifier fsk/ask demodulator, data filter data slicer) tx/rx- data buffer control register status register polling circuit bit-check logic synchronous logic (full duplex operation mode) digital control logic power supply switches regulators wake-up reset rf transceiver fractional-n frequency synthesizer vs2 vs1 433_n868 pwr_h cs sdo_tmdo irq pout clk test3 xtal2 xtal1 rssi cdem rf_in rx_tx2 rx_tx1 rf_out set_pwr r_pwr dvcc rx_active avcc gnd vsint lna spi xto reset pa rx/tx switch frontend enable pa_enable (ask) demod_out fref freq rx/tx 13 tx_data (fsk) microcontroller interface sck sdi_tmdi test2 test1 sck_pha cs_pol sck_pol n_pwr_on pwr_on
7 ata5823/ata5824 [datasheet] 4829f?rke?05/14 3. typical key fob applicat ion for bi-dir ectional rke figure 3-1. typical key fob app lication for bi-directional rke wi th 5dbm tx power, 433.92mhz figure 3-1 shows a typical 433.92mhz rke key fob application. t he external components are 10 capacitors, 1 resistor, 2 inductors and a crystal. c 1 to c 3 are 68nf voltage supply blocking capacitors. c 5 is a 10nf supply blocking capacitor. c 6 is a 15nf fixed capacitor used for the internal quasi-peak det ector and for the high-pass frequency of the data filter. c 7 to c 11 are rf matching capacitors in the range of 1pf to 33pf. l 1 is a matching inductor of about 5.6nh to 56nh. l 2 is a feed inductor of about 120nh. a load capacitor of 9pf for the crystal is integrated. r 1 is typically 22k and sets the output power to about 5.5dbm. the loop antenna?s quality factor is somewhat reduced by this applic ation due to the quality factor of l 2 and the rx/tx switch. on the other hand, this lowe r quality factor is necessary to have a robust design with a bandwidth that is wide enough for production tolerances. due to the single-ended and ground-referenced design, the loop antenna can be a free- form wire around the application as it is usually employed in rke unidirectional systems. the atmel ? ata5823/ ata5824 provides sufficient isolation a nd robust pulling behavior of internal circuits fr om the supply voltage as well as an integrated vco inductor to allow this. since the efficiency of a loop antenn a is proportional to the square of the surrounded area, it is beneficial to have a large loop around the application board with a lower quality factor to rela x the tolerance specification o f the rf matching components and to get a high antenn a efficiency in spite of their lower quality factor. cs nc rssi cdem sck test3 sdi_tmdi sdo_tmdo ata5823/ata5824 clk vcc vss vsint xtal2 + lithium cell loop antenna avcc 20 mm x 0.4 mm microcontroller 13.25311 mhz pout irq nc nc rf_in c 7 c 11 c 6 c 3 c 1 c 2 433_n868 nc nc nc rf_out pwr_h r_pwr nc avcc vs2 nc nc nc vs1 setpwr test1 dvcc cs_pol test2 txal1 nc nc nc nc rx_active n_pwr_on sck_pha sck_pol pwr_on rx_tx1 rx_tx2 nc c 9 c 10 r 1 l 2 l 1 c 8 c 5
ata5823/ata5824 [datasheet] 4829f?rke?05/14 8 4. typical car applicati on for bi-directional rke figure 4-1. typical car application for bi-dir ectional rke with 10dbm tx power, 433.92mhz figure 4-1 shows a typical 433.92mhz v cc = 4.4v to 5.25v rke car application. the external components are 11 capacitors, 1 resistor, 4 inducto rs, a saw filter and a crystal. c 1 , c 3 and c 4 are 68nf voltage supply blocking capacitors. c 2 is a 2.2f supply blocking capacitor for the internal voltage regulator. c 5 is a 10nf supply blocking capacitor. c 6 is a 15nf fixed capacitor used for the internal quasi-peak detector and for the high-pass frequency of the data filter. c 7 to c 11 are rf matching capacitors in the range of 1pf to 33pf. l 2 to l 4 are matching inductors of about 5.6nh to 56nh. a load capacitor for the crystal of 9pf is integrated. r 1 is typically 22k and sets the output power at rf out to about 10dbm . since a quarter wave or pcb antenna, which has high efficiency and wideband oper ation, is typically used here , it is recommended to use a saw filter to achieve high sensitivity in case of powerful out-of-band blockers. l 1 , c 10 and c 9 together form a low-pass filter, which is needed to filter out the harmonics in the transmitted signal to meet regulations. cs nc rssi cdem sck test3 sdi_tmdi sdo_tmdo clk vsint xtal2 avcc 50 connector saw-filter 20 mm x 0.4 mm 13.25311 mhz v cc = 4.4v to 5.25v pout irq nc nc rf_in c 7 c 11 c 6 c 3 c 2 c 1 c 4 433_n868 nc nc nc rf_out pwr_h r_pwr nc avcc vs2 nc nc nc vs1 setpwr test1 dvcc cs_pol test2 txal1 nc nc nc nc sck_ph sck_pol rx_active n_pwr_on pwr_on rx_tx1 rx_tx2 nc c 10 c 9 rf out r 1 l 2 l 1 l 4 c 8 c 5 l 3 vcc vss microcontroller ata5823/ata5824
9 ata5823/ata5824 [datasheet] 4829f?rke?05/14 5. rf transceiver in half-duplex mode according to figure 2-2 on page 6 , the rf transceiver consists of an lna (l ow-noise amplifier), pa (power amplifier), rx/tx switch, fractional-n frequency synthesizer and the signal processing part with mixer, if f ilter, if amplifier with analog rssi, fsk/ask demodulator, dat a filter and data slicer. in receive mode the lna pre-amplifies the received signal whic h is converted down to 226k hz intermediate frequency (if), filtered and amplified before it is fed into an fsk/ask demodul ator, data filter and data slic er. the rssi (received signal strength indicator) signal and the raw digital output signal of the demodulator are available at the pins rssi and on test3 (open drain output). the demodulated data signal demod_out is fed into the digital control logic where it is evaluated and buffered as described in section ?digital control logic? on page 32 . in transmit mode the fractional-n frequency synthesizer generates the tx frequency which is fed into the pa. in ask mode the pa is modulated by the signal pa_enable. in fsk mode the pa is enabled and the signal tx_data (fsk) modulates the fractional-n frequency synthesizer. the frequency deviation is digitally controlled and internally fixed to about 19.5khz (see table 6-1 on page 25 for exact values). the transmit data can also be buffered as described in section ?digital control logic? on page 32 . a lock detector within the synthesizer ensures that the transmission will only star t if the synthesizer is locked. in half-duplex mode the rx/tx switch can be used to combin e the lna input and the pa output to a single antenna with a minimum of losses. transparent modes without buf fering of rx and tx data are also available to allow protocols and coding schemes other than the internal supported manchester enc oding, like pwm and pulse position coding. 5.1 low-if receiver the receive path consists of a fully integrated low-if receiver . it fulfills the sensitivity, bl ocking, selectivity, supply vol tage and supply current specification needed to manufacture an automo tive key fob for rke and peg systems without the use of a saw blocking filter (see figure 3-1 on page 7 ). the receiver can be connected to t he roof antenna in the car when using an additional blocking saw front-end filter as shown in figure 4-1 on page 8 . at 433.92mhz the receiver has a typical system noise figure of 6.5db, a system i1dbcp of ?30dbm and a system iip3 of ?20dbm. the signal path is linear for disturbers up to th e i1dbcp and there is hence no agc or switching of the lna needed to achieve a better blocking performance. this receiver uses an if of about 226khz (see section 14. ?electrical characteristics: general? on page 61 number 2.10 for exact values), the typica l image rejection is 30db and the typical 3db system bandwidth is 220khz (f if = 226khz 110khz, f lo_if = 116khz and f hi_if = 336khz). the demodulator needs a signal to noise ratio of 8db for 20kbit/s manchester with 19.5khz frequen cy deviation in fsk mode, thus, the resulting sensitivity at 433.92mhz is typically ?105.5dbm. due to the low phase noise and spurious of the synthesizer in receive mode (1) together with the eight h order integrated if filter the receiver has a better selectiv ity and blocking performance than more co mplex double superhet receivers, without using external components and without nu merous spurious receiving frequencies. note: 1. ?120dbc/hz at 1mhz and ?72dbc at f xto at 433.92mhz a low-if architecture is also less sens itive to second-order intermodulation (iip2) than direct conversion receivers where every pulse or amplitude modulated signal (especially the signals from tdma systems like gsm) demodulates to the receiving signal band at second-order non-linearities.
ata5823/ata5824 [datasheet] 4829f?rke?05/14 10 5.2 input matching at rf_in the measured input impedances as well as t he values of a parallel equivalent circuit of these impedances can be seen in table 5-1 . the highest sensitivity is achieved with power matc hing of these impedances to the source impedance of 50 . the matching of the lna input to 50 was done with the circuit according to figure 5-1 and with the values of the matching elements given in table 5-2 . the reflection coef ficients were always ?10db. note that value changes of c 1 and l 1 may be necessary to compensate individual board layout para sitics. the measured typical fsk and ask manchester code sensitivities with a bit error rate (ber) of 10 -3 are shown in table 5-3 on page 10 and table 5-4 on page 10 . these measurements were done with multilayer indu ctors having quality factors according to table 5-2 , resulting in estimated matching losses of 0.8db at 315mhz and 0. 8db at 433.92mhz. these losses can be es timated when calculating the parallel equivalent resistance of the inductor with r loss =2 f l q l and the matching loss with 10 log(1+r in_p /r loss ). with an ideal inductor, for example, the sensitivity at 433. 92mhz/fsk/20kbit/s/ 19.5khz/man chester can be improved from ?105.5dbm to ?106.7dbm. the sensitivity also depends on the valu es in the registers of the control logic which examines the incoming data stream. the examination limits must be progra mmed in control registers 5 and 6. the measurements in table 5-3 and table 5-4 on page 10 are based on the values of registers 5 and 6 according to table 11-3 on page 55 . figure 5-1. input matching to 50 table 5-1. measured input impedances of the rf_in pin f rf /mhz z in (rf_in) r in_p //c in_p 315 (44-j233) 1278 //2.1pf 433.92 (32-j169) 925 //2.1pf table 5-2. input matching to 50 f rf /mhz c 1 /pf l 1 /nh q l1 315 2.4 47 65 433.92 1.8 27 67 table 5-3. measured typical sens itivity 433.92mhz, fsk, 19.5khz, manchester, ber = 10 -3 rf frequency br_range_0 1.0 kbit/s br_range_0 2.4 kbit/s br_range_1 5.0 kbit/s br_range_2 10 kbit/s br_range_3 20 kbit/s 315mhz ?109.5dbm ?110.0dbm ?109.0dbm ?107.5dbm ?106.5dbm 433.92mhz ?108.5dbm ?109.0dbm ?108.0dbm ?106.5dbm ?105.5dbm table 5-4. measured typical sensitivity 433. 92 mhz, 100% ask, manchester, ber = 10 -3 rf frequency br_range_0 1.0 kbit/s br_range_0 2.4 kbit/s br_range_1 5.0 kbit/s br_range_2 10 kbit/s 315mhz ?117.0dbm ?117.0dbm ?114.5dbm ?112.5dbm 433.92mhz ?116.0dbm ?116.0dbm ?113.5dbm ?111.5dbm l 1 c 1 4 rf_in ata5823/ata5824
11 ata5823/ata5824 [datasheet] 4829f?rke?05/14 5.3 sensitivity versus supply voltage, temperature and frequency offset to calculate the behavior of a transmission system it is important to know the redu ction of the sensitivity due to several influences. the most important are frequency offset due to crystal oscillator (xto) and crystal frequency (xtal) errors, temperature and supply voltage dependency of the noise fi gure and if filter bandwidth of the receiver. figure 5-2 shows the typical sensitivity at 433.92mhz/fsk/20kbi t/s/19.5khz/manchester versus the fr equency offset between transmitter and receiver at t amb = ?40c, +25c and +105c and supply voltage v s =v s1 =v s2 = 2.15v, 3.0v and 3.6v. figure 5-2. measured sensitivity 433. 92mhz/fsk/20kbit/s/19.5khz/manchester versus frequency offset, temper- ature and supply voltage as can be seen in figure 5-2 on page 11 the supply voltage has almost no influ ence on the sensitivity. the temperature has an influence of about +1.5/?0.7db and a fr equency offset of 85khz also influences by about 1db. all these influences, combined with the sensitivity of a typical ic (?105.5 dbm), are then within a range of ?102.5dbm and ?107dbm overtemperature, supply voltage and frequency offset. the int egrated if filter has an additi onal production tolerance of 10khz, hence, a frequency offset between the receiver and t he transmitter of 75khz can be accepted for xtal and xto tolerances. note: for the demodulator used in the atmel ata5823/ata5824, the tolerable frequency of fset does not change with the data frequency, hence, the value of 75khz is valid for 1kbit/s to 20kbit/s. this small sensitivity change over supply voltage, frequency offs et and temperature is very unusual in such a receiver. it is achieved by an internal, very fast and automatic frequency corre ction in the fsk demodulator after the if filter, which leads to a higher system margin. this frequency correction tracks the i nput frequency very quickly, if however, the input frequency makes a larger step (e.g., if the system changes between di fferent communication partners), the receiver has to be restarted. this can be done by switching back to idle mode and then again to rx mode. fo r that purpose, an automatic mode is also available. this automatic mode switches to idle mode and back into rx mode every time a bit error occurs (see section ?digital control logic? on page 32 ). 5.4 frequency accuracy of the crystals in bi-directional rke/peg the xto is an amplitude regulated pierce type oscillator with inte grated load capacitors. the initial tolerances (due to the frequency tolerance of the xtal, the in tegrated capacitors on xtal1, xtal2 an d the xto?s initial transconductance gm) can be compensated to a value within 0.5ppm by m easuring the clk output frequency and tuning of f rf by programming the control registers 2 and 3 (see table 9-7 on page 34 and table 9-10 on page 35 ). the xto then has a remaining influence of less than 2ppm overtemperature and s upply voltage due to the bandgap contro lled gm of the xto. thus only 2.5ppm add to the frequency stability of the used crystals overtemperature and aging. the needed frequency stability of the used crystals overtemperature and aging is hence 75khz/433.92mhz ? 2 2.5ppm = 167.84ppm for 433.92mhz. thus, the used crystals in receiver and transmitter each need to be better than 83.9ppm for 433.92mhz. -109 -108 -107 -106 -105 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 -110 sensitivity (dbm) -60 40 60 100 80 -40 -80 -100 0 frequency offset (khz) 20 -20 v s = 3.0v t amb = -40c v s = 3.6v t amb = -40c v s = 3.0v t amb = +25c v s = 3.6v t amb = +25c v s = 2.15v t amb = +105c v s = 3.0v t amb = +105c v s = 3.6v t amb = +105c v s = 2.15v t amb = +25c v s = 2.15v t amb = -40c
ata5823/ata5824 [datasheet] 4829f?rke?05/14 12 5.5 frequency accuracy of the crystals in a combined rke/peg and tpm system in a tire pressure measurement system workin g at 433.92mhz and using a tpm transmitter atmel ? ata5757 and a transceiver atmel ata5824 as a receiver, the higher frequency to lerances and the tolerance of the frequency deviation of this transmitter has to be considered. in the tpm transmitter the crystal has an frequency error over temperature ?40c to +125c, ag ing and tolerance of 80ppm (34.7khz at 433.92mhz). the tolerances of the xto, the capacitors used for f sk-modulation and the stray capacitors, causing an additional frequency error of 30ppm (13khz at 43 3.92mhz). the frequency deviat ion of such a transmitter varies between 16khz and 24khz, since a higher frequency devi ation is equivalent to an frequency error, this has to be considered as an additional 24khz ? 19.5khz = 4.5khz frequen cy tolerance. all toleranc es added, these transmitters have a worst case frequency offset of 52.2khz. for the transceiver in the car a tolerance of 75khz ? 52.2khz = 22.8khz (52.5ppm) remains. the needed frequency stability of the used crystals overtemperature and aging is 52.5ppm ? 2.5ppm = 50ppm. the aging of such a crystal is 10ppm leaving reasonable 40ppm for the temperat ure dependency of the crystal frequency in the car. since the transceiver in the car is able to receive these tp m transmitter signals with high frequency offsets, the component specification in the key can be largely relaxed. this system calculation is based on worst case tolerances of all the components, this leads in practice to a system with margin. for a 315mhz tpm system using a tpm transmitter atmel ata5756 and a transceiver atmel ata5823 as receiver the same calculation must be done, but since the rf frequency is lower, every ppm of cryst al tolerances results in less frequency offset and either the system can have higher tolerances or a higher margin there. 5.6 rx supply current versus temperature and supply voltage table 5-5 shows the typical supply current at 433.92mhz of th e transceiver in rx mode versus supply voltage and temperature with v s =v s1 =v s2 . as can be seen the supply current at v s = 2.15v and t amb = ?40c is less than at v s =3v/t amb = 25 which helps to enlarge the battery lifetime within a key fob application because this is also the operation point where a lithium cell has the worst perfo rmance. the typical supply current at 31 5mhz in rx mode is about the same as for 433.92mhz. table 5-5. measured 433.92mhz recei ve supply current in fsk mode v s = v s1 = v s2 2.15v 3.0v 3.6v t amb = ?40c 8.2ma 8.8ma 9.2ma t amb = 25c 9.7ma 10.3ma 10.8ma t amb = 105c 11.2ma 11.9ma 12.4ma
13 ata5823/ata5824 [datasheet] 4829f?rke?05/14 5.7 blocking, selectivity as can be seen in figure 5-3 , figure 5-4 and figure 5-5 on page 13 , the receiver can receive signals 3db higher than the sensitivity level in presence of large blockers of ?44.5dbm/-36.0dbm with sma ll frequency offsets of 1 / 10mhz. figure 5-3 and figure 5-4 on page 13 shows the close-in and narrow-band blocking and figure 5-5 on page 13 the wide- band blocking characteristic. the measurem ents were done with a useful signal of 433.92mhz/fsk/20kbit/s/19.5khz/manc hester with a level of ?105.5dbm + 3db = ?102.5dbm which is 3db above the sensitivity level. the figures show by how much a continuou s wave signal can be larger than ?102.5dbm until the ber is higher than 10 -3 . the measurements were done at the 50 input according to figure 5-1 on page 10 . at 1mhz, for example, the blocker can be 58dbc higher than ?102.5dbm which is ?102.5dbm +58dbc = ?44.5dbm. these blocking figures, together with the good intermodulation perf ormance, avoid the additional need of a saw filter in the key fob application. figure 5-3. close in 3db blocking characte ristic and image response at 433.92mhz figure 5-4. narrow band 3db blo cking characteristic at 433.92mhz figure 5-5. wide band 3db blocki ng characteristic at 433.92mhz -0.2 0 0.2 0.4 -1.0 -0.8 -0.6 -0.4 distance of interfering to receiving signal (mhz) 0.6 0.8 1.0 70 50 60 40 20 30 blocking level (dbc) 10 -10 0 70 50 60 40 20 30 blocking (dbc) 10 -10 0 -1 0 1 2 -5 -4 -3 -2 distance of interfering to receiving signal (mhz) 345 -10 0 10 20 -50 -40 -30 -20 distance of interfering to receiving signal (mhz) 30 40 50 70 80 50 60 40 20 30 blocking (dbc) 10 -10 0
ata5823/ata5824 [datasheet] 4829f?rke?05/14 14 table 5-6 shows the blocking performance measured relative to ?1 02.5dbm for some frequencies. note that sometimes the blocking is measured relative to the sensitivity level ?105.5dbm (denoted dbs) instead of the carrier ?102.5dbm (denoted dbc). the atmel ? ata5823/ata5824 can also receive fsk and ask modu lated signals if they are mu ch higher than the i1dbcp. it can typically receive useful signals at +10dbm. this is often referred to as the nonlinear dynamic range which is the maximum to minimum receiving signal which is 115.5db for 433.92mhz/fsk/20kbit/s /19.5khz/ manchester. this value is useful if two transceivers have to comm unicate and are very close to each other. in a keyless entry system there is another blocking characteristic that has to be considered. a keyless entry system has a typical service range of about 30 m with a receiver sensitivity of about ?106dbm to ?109dbm. in some cases, large blockers limit this service range, and it is import ant to know how large this blockers can be until the system doesn ?t work anymore and the user has to use its key. with a recommended sensitiv ity of about ?85dbm, the system works just around the car. figure 5-6 and figure 5-7 on page 15 show the blocking performance in this important case with a useful signal of ?85dbm 433.92mhz/fsk/20kbit/s/19.5khz/ manchester. as can be seen the system works even with blockers above the compression point. this is due to a wide bandwidth automatic gain control that begins to wo rk if blockers above the compression poi nt are at the antenna input and increasing the current in the lna/mixer to get a better compre ssion point needed to handle these large blockers. figure 5-6. 2.5mhz blocking characteristic for ?85dbm useful signal at 433.92mhz table 5-6. blocking 3 db above sensitivity level with ber < 10 -3 frequency offset blocker level blocking +0.75mhz ?47.5dbm 55.0dbc/58.0dbs ?0.75mhz ?47.5dbm 55.0dbc/58.0dbs +1.0mhz ?44.5dbm 58.0dbc/61.0dbs ?1.0mhz ?44.5dbm 58.0dbc/61.0dbs +1.5mhz ?42.0dbm 60.5dbc/63.5dbs ?1.5mhz ?42.0dbm 60.5dbc/63.5dbs +10mhz ?35.5dbm 67.0dbc/70.0dbs ?10mhz ?35.5dbm 67.0dbc/70.0dbs -0.5 0 0.5 1.0 -2.5 -2.0 -1.5 -1.0 distance of interfering to receiving signal (mhz) 1.5 2.0 2.5 -20 -40 -30 -50 -70 -60 blocker level (dbm) -80 -90
15 ata5823/ata5824 [datasheet] 4829f?rke?05/14 figure 5-7. 50mhz blocking characteristi c for ?85dbm useful signal at 433.92mhz this high blocking performance makes it even possible for some applications using quarter wave whip antennas to use a simple lc band-pass filter instead of a saw filter in the receiv er. when designing such a lc filter, take into account that the 3db blocking at 433.92mhz/2 = 216.96mhz is 42dbc and at 43 3.92mhz/3 = 144.64mhz is 47dbc a . and especially that at 3 (433.92mhz + 226khz)+226khz = 1302.664mhz t he receiver has a second lo harmonic receiving frequency with only 17dbc blocking. 5.8 inband disturbers, data filter, quasi-peak detector, data slicer if a disturbing signal falls into the received band, or a blo cker is not a continuous wave, the performance of a receiver strongly depends on the circuits after the if filter. hence the demodulator, data filt er and data slicer ar e important in that case. the data filter of the atmel ? ata5823/ata5824 implies a quasi-peak detector. this results in a good suppression of above mentioned disturbers and exhibits a good carrier to noise performance. the required ratio of useful signal to disturbing signal, at a ber of 10 -3 is less than 12db in ask mode and less than 3db (br_range_0 ... br_range_2) and 6db (br_range_3) in fsk mode. due to the many different possib le waveforms these numbers are measured for signal as well as for disturbers with peak amplitude va lues. note that these values are worst ca se values and are valid for any type of modulation and modulating frequency of the disturbing signal as well as the receiving signal. for many combinations, lower carrier to disturbing signal ratios are needed. 5.9 test3 output the internal raw output signal of the demodulator demod_out is available at pin test3. test3 is an open drain output and must be connected to a pull-up resi stor if it is used (typically 100k ), otherwise no signal is present at that pin. this signal is mainly used for debugging purposes during the setup of a new ap plication, since the received data signal can be seen there without any digital processing. -10 0 10 20 -50 -40 -30 -20 distance of interfering to receiving signal (mhz) 30 40 50 -20 -10 0 -40 -30 -50 -70 -60 blocker level (dbm) -80 -90
ata5823/ata5824 [datasheet] 4829f?rke?05/14 16 5.10 rssi output the output voltage of the pin rssi is an analog voltage, proportional to the input power level. using the rssi output signal, the signal strength of different transmitters can be distingui shed. the usable dynamic range of the rssi amplifier is 70db, the input power range p rfin is ?115dbm to ?45dbm and the gain is 8mv/db. figure 5-8 on page 16 shows the rssi characteristic of a typical device at 433.92mhz with v s1 = v s2 = 2.15v to 3.6v and t amb = ?40c to +105c with a matched input according to table 5-2 on page 10 and figure 5-1 on page 10 . at 315mhz about 1db less signal level is needed for the same rssi results. figure 5-8. typical rssi charac teristic at 433.92mhz versus temperature and supply voltage 5.11 frequency synthesizer and channel selection the synthesizer is a fully integrated frac tional-n design with internal loop filters for receive and transmit mode. the xto frequency f xto is the reference frequency fref for the synthesizer. the bits fr0 to fr12 in control registers 2 and 3 (see table 9-7 on page 34 and table 9-10 on page 35 ) are used to adjust the deviation of f xto . in half-duplex transmit mode, at 433.92mhz, the carrier has a phase noise of ?111dbc/hz at 1mhz and spurious at fref of ?70dbc with a high pll loop bandwidth allowing the direct modulation of the carrier with 20 kbit/s manchester data. due to the closed loop modulation, any spurious caused by this modulation are ef fectively filtered out as can be seen in figure 5-11 on page 18 . in rx mode the synthesizer has a phase noise of ?120dbc/ hz at 1mhz and spurious of ?72dbc. the initial tolerances of the crystal osc illator due to crystal frequency tolerances , internal capacitor tolerances and the parasitics of the board have to be comp ensated at manufacturing setu p with control registers 2 and 3 as can be seen in table 6-1 on page 25 . the other control words for the synthesizer needed for ask, fsk and receive/transmit switching are calculated internally. the rf (radio frequency) resolution is equal to the xto frequency divided by 16384 which is 777.1hz at 315.0mhz and 808. 9hz at 433.92mhz. the frequency control word freq in contro l registers 2 and 3 can be programmed in the range of 1000 to 6900, hence every frequency within the 433mhz ism bands can be programmed as receive and as transmit frequency and the position of channels within these ism bands can be chosen arbitrarily (see table 6-1 on page 25 ). care must be taken regarding the harmonics of the clk output signal as well as to the harmonics produced by a microprocessor clocked with it, since thes e harmonics can disturb the reception of signals. in a single channel system using freq = 3803 to 4053 ensures that harmonics of this signal, do not disturb the receive mode. 400 500 600 700 800 900 1000 1100 -80 -70 -60 -50 -120 -110 -100 -90 p rf_in (dbm) v rssi (mv) -40 max. min. typ.
17 ata5823/ata5824 [datasheet] 4829f?rke?05/14 5.12 fsk/ask transmission due to the fast modulation capability of the synthesizer and the high resolution, the carrier can be internally fsk modulated which simplifies the application of the tr ansceiver. the deviation of the transmitted signal is 24 digital frequency steps of the synthesizer which is equal to 18.65khz for 315mhz and 19.41khz for 433.92mhz. due to closed loop modulation with pll filt ering, the modulated spectrum is very clean, meeting etsi and cept regulations when using a simple lc filter for the power amplifier harmonics as it is shown in figure 4-1 . in ask mode the frequency is internally connected to the center of the fsk transmission and the power amplifier is switched on and off to perform the modulation. figure 5-9 to figure 5-11 on page 18 show the spectrum of the fsk modulation with pseudo-random data with 20kbit/s/19.41khz/manchest er and 5dbm output power. figure 5-9. fsk-modulated tx spectrum (433.92mhz/20kbit/s/ 19.41khz/manchester code) atten 20 db vavg 50 s3 fc w1 s2 ref 10 dbm span 30 mhz sweep 7.5 ms (401 pts) center 433.92 mhz vbw 100 khz res bw 100 khz samp log db/ 10
ata5823/ata5824 [datasheet] 4829f?rke?05/14 18 figure 5-10. unmodulated tx sp ectrum 433.92mhz - 19.41khz (f fsk_l ) figure 5-11. fsk-modulated tx spectrum (433 .92mhz/20kbit/s/19.41 khz/manchester code) atten 20 db vavg 50 s3 fc w1 s2 ref 10 dbm span 1 mhz sweep 27.5 ms (401 pts) center 433.92 mhz vbw 10 khz res bw 10 khz samp log db/ 10 atten 20 db vavg 50 s3 fc w1 s2 ref 10 dbm span 1 mhz sweep 27.5 ms (401 pts) center 433.92 mhz vbw 10 khz res bw 10 khz samp log db/ 10
19 ata5823/ata5824 [datasheet] 4829f?rke?05/14 5.13 output power setting and pa matching at rf_out the power amplifier (pa) is a single-ended open collector st age which delivers a current pulse which is nearly independent of supply voltage, temperature and toleranc es due to band-gap stabilization. resistor r 1 (see figure 5-12 on page 20 ) sets a reference current which controls the curre nt in the pa. a higher resistor value results in a lower reference current, a lower output power and a lower current consumpt ion of the pa. the usable range of r 1 is 15k to 56k . the pwr_h pin switches the output power range between about 0dbm to 5dbm (pwr_h = gnd) and 5dbm to 10dbm (pwr_h = avcc) by multiplying this reference current with a factor 1 (pwr_h = gnd) and 2.5 (pwr _h = avcc) which corresponds to about 5db more output power. if the pa is switched off in tx mode, the curr ent consumption without output stage and with v s1 =v s2 =3v, t amb =25c is typically 6.95ma for 315mhz and 433.92mhz. the maximum output power is achiev ed with optimum load resistances r lopt according to table 5-7 on page 20 . the compensation of the 1.0pf output capaci tance of the rf_out pin will be achiev ed by absorbing it into the matching network, consisting of l 1 , c 1 , c 3 as shown in figure 5-12 on page 20 . there must be also a low resistive dc path to avcc to deliver the dc current of the power am plifier's last stage. the matching of the pa output was done with the circuit according to figure 5-12 on page 20 with the values in table 5-7 . note that value changes of these elements may be necessary to compensate individual board layout parasitics. example: according to table 5-7 on page 20 , with a frequency of 433.92mhz and out put power of 11dbm, the overall current consumption is typically 17.8m a. hence the pa needs 17.8ma - 6.95ma = 10.85ma in this mode which corresponds to an overall power amplifier efficiency of the pa of (10 (11dbm/10) 1mw)/(3v 10.85ma) 100% = 38.6% in this case. using a higher resistor in this example of r1 = 1.091 22k =24k results in 9.1% less current in the pa of 10.85ma/1.091 = 9.95ma and 10 log(1.091) = 0.38db less output power if using a new load resistance of 300 ? 1.091 = 327 . the resulting output power is then 11dbm ? 0.38d b = 10.6dbm and the overal l current consumption is 6.95ma + 9.95ma = 16.9ma. the values of table 5-7 on page 20 were measured with standard multi-layer chip inductors with quality factors q according to table 5-7 on page 20 . looking to the 433.92mhz/11dbm case with the quality factor of q l1 = 43 the loss in this inductor l 1 is estimated with the parallel equivalent resistance of the inductor r loss =2 f l1 q l1 and the matching loss with 10 log (1 + r lopt /r loss ) which is equal to 0.32db losses in this inductor. taking th is into account the pa efficiency is then 42% instead of 38.6%. be aware that the high power mode (pwr_h = avcc) can only be used with a supply voltage higher than 2.7v, whereas the low power mode (pwr_h = gnd) can be used do wn to 2.15v as can be seen in the section ?electrical characteristics: general? on page 61 . the supply blocking capacitor c 2 (10nf) in figure 5-12 on page 20 has to be placed close to the matching network because of the rf current flowing through it. an internal programmable resistor setpwr is progra mmable with the control regi ster 8, described in table 9-25 on page 39 . it can be used in conjunction with an external resistor to adj ust the output power by connecti on it. to do that the output power should be adjusted with an external resistor about 50% lower than needed for the tar get output power and reduced with the programmable resistor during produc tion test until the target power is as close as possible to the target. for example, if using 433.92m hz at 5dbm, a resistor of 12k in stead of 24k is used and values of pwset between 25 and 29 can be used to achieve an output power within 5dbm 0.5db over pro duction. note that this resist or is temperature stable but has tolerances of 20% and introduces, therefore, additional output power tolerances, it is recommended to adjust output power during the production test if using the setpwr resistor.
ata5823/ata5824 [datasheet] 4829f?rke?05/14 20 figure 5-12. power setting and output matching 5.14 output power and tx supply current versus supply voltage and temperature table 5-8 shows the measurement of the output power for a typical device with v s1 =v s2 =v s in the 433.92mhz and 6.2dbm case versus temperature and supply voltage measured according to figure 5-12 on page 20 with components according to table 5-7 on page 20 . as opposed to the receiver sensitivity the supply voltage has here the major impact on output power variations because of the large signal behavior of a power amplif ier. thus a 5v system using the internal voltage regulator shows much less vari ation than a 2.15v to 3.6v battery system because the avcc supply voltage is 3.25v 0.25v for a 5v system. the reason is that the amplitude at th e output rf_out with optimum load resistance is avcc ? 0.4v and the power is proportional to (avcc ? 0.4v) 2 if the load impedance is not ch anged. this means that the theo retical output power reduction if reducing the supply voltage from 3.0v to 2.15v is 10 log ((3v ? 0.4v) 2 /(2.15v ? 0.4v) 2 ) = 3.4db. table 5-8 shows that principle behavior in the measurements. this is not the same case for higher voltages, since here, increasing the supply voltage from 3v to 3.6v should theoretical increase the power by 1.8db, but only 0.9db in t he measurements shows that the amplitude does not increase with the supply voltage because the load impedance is optimized for 3v and the output amplitude stays more constant because of the current source nature of the output. table 5-7. measured output power and current consumption with v s1 = v s2 = 3v, t amb = 25c frequency (mhz) tx current (ma) output power (dbm) r1 (k ) vpwr_h r lopt ( ) l 1 (nh) q l1 c 1 (pf) c 3 (pf) 315 8.5 0.4 56 0 2500 82 28 1.5 0 315 10.5 5.7 27 0 920 68 32 2.2 0 315 16.7 10.5 27 avcc 350 56 35 3.9 0 433.92 8.6 0.1 56 0 2300 56 40 0.75 0 433.92 11.2 6.2 22 0 890 47 38 1.5 0 433.92 17.8 11 22 avcc 300 33 43 2.7 0 rf out 10 rf_out vpwr_h avcc ata5823/ata5824 9 pwr_h 8 r_pwr c 2 c 1 l 1 c 3 r 1
21 ata5823/ata5824 [datasheet] 4829f?rke?05/14 . table 5-9 shows the relative changes of the output power of a typical device compared to 3.0v/25c. as can be seen, a temperature change to ?40c as well as to +105c reduces the power by less than 1db due to the band-gap regulated output current. measurements of all the cases in table 5-7 on page 20 overtemperature and su pply voltage have shown about the same relative behavior as shown in table 5-9 . 5.15 rx/tx switch the rx/tx switch decouples the lna from the pa in tx mode, and directs the received power to the lna in rx mode. to do this, it has a low impedance to gnd in tx mode and a hi gh impedance to gnd in rx mode. the pin 38 (rx_tx2) must always be connected to gnd in the application. to design a proper rx/tx decoupling a linear simulation tool for radio frequency design together with t he measured device impedances of table 5-1 on page 10 , table 5-7 on page 20 , table 5-10 on page 21 and table 5-11 on page 22 should be used. the exact element values have to be found on board. figure 5-13 on page 21 shows an approximate equivalent circuit of the switch. th e principal switching operation is described here according to the application of figure 3-1 on page 7 . the application of figure 4-1 on page 8 works similarly. . figure 5-13. equivalent circuit of the switch table 5-8. measured output power and supply current at 433.92mhz, pwr_h = gnd v s = v s1 = v s2 2.15v 3.0v 3.6v t amb = ?40c 9.25ma 3.2dbm 10.19ma 5.5dbm 10.78ma 6.2dbm t amb = +25c 10.2ma 3.4dbm 11.19ma 6.2dbm 11.79ma 7.1dbm t amb = +105c 10.9ma 3.0dbm 12.02ma 5.4dbm 12.73ma 6.3dbm table 5-9. measurements of typical output power relative to 3v/25c v s = v s1 = v s2 2.15v 3.0v 3.6v t amb = ?40c ?3.0db ?0.7db 0db t amb = +25c ?2.8db 0db +0.9db t amb = +105c ?3.2db ?0.8db +0.1db table 5-10. impedance of the rx/tx switch rx_tx2 shorted to gnd frequency z(rx_tx1) tx mode z(rx_tx1) rx mode 315 mhz (4.8 + j3.2) (11.3 ? j214) 433.92 mhz (4.5 + j4.3) (10.3 ? j153) 1.6 nh 2.5 pf rx_tx1 tx 11 5
ata5823/ata5824 [datasheet] 4829f?rke?05/14 22 5.16 matching network in tx mode in tx mode the 20mm long and 0.4mm wide transmission line which is much shorter than /4 is approximately switched in parallel to the capacitor c 9 to gnd. the antenna connection between c 8 and c 9 has an impedance of about 50 looking from the transmission line into t he loop antenna with pin rf_out, l 2 , c 10 , c 8 and c 9 connected (using a c 9 without the added 7.6pf capacitor as discussed later). the transmission line can be approximated with a 16nh inductor in series with a 1.5 resistor, the closed switch can be approximated according to table 5-10 with the series connection of 1.6nh and 5 in this mode. to have a parallel resonant hi gh impedance circuit with little rf power go ing into it looking, from the loop antenna into the transmission line a capacitor of about 7.6pf to gnd is needed at the beginning of the transmission line (this capacitor is later absorbed into c 9 , which is then higher as needed for 50 transformation). to keep the 50 impedance in rx mode at the end of this transmission line c 7 has to be also about 7.6pf. this reduc es the tx power by about 0.5db at 433.92mhz compared to the case where t he lna path is completely disconnected. 5.17 matching network in rx mode in rx mode the rf_out pin has a high impedance of about 7k in parallel with 1.0pf at 4 33.92mhz as can be seen in table 5-11 on page 22 . this together with the losses of the inductor l 2 with 120nh and q l2 = 25 gives about 3.7k loss impedance at rf_out. since the optimum load impedance in tx mode for the power amplifier at rf_out is 890 the loss associated with the inductor l 2 and the rf_out pin can be estimated to be 10 log(1 + 890/3700) = 0.95db compared to the optimum matched l oop antenna without l 2 and rf_out. the switch represents, in this mode at 433.92mhz, about an inductor of 1.6nh in series with t he parallel connection of 2.5pf and 2.0k . since the impedance level at pin rx_tx1 in rx mode is about 50 there is only a negligible damping of the receiv ed signal by about 0.1db. wh en matching the lna to the loop antenna the transmission line and the 7.6pf part of c 9 has to be taken into account when choosing the values of c 11 and l 1 so that the impedance seen from the loop antenna into th e transmission line with the 7.6pf capacitor connected is 50 . since the loop antenna in rx mode is loaded by the lna inpu t impedance the loaded q of the loop antenna is lowered by about a factor of 2 in rx mode hence the antenna bandwidth is higher than in tx mode. . note that if matching to 50 , like in figure 4-1 on page 8 , a high q wire wound inductor with a q > 70 should be used for l 2 to minimize its contribution to rx losses which will otherwise be dominant. the rx and tx losses will be in the range of 1.0db there. table 5-11. impedance rf_out pin in rx mode frequency z(rf_out)rx r p //c p 315 mhz 36 ? j 502 7k // 1.0pf 433.92 mhz 19 ? j 366 7k // 1.0pf
23 ata5823/ata5824 [datasheet] 4829f?rke?05/14 6. xto the xto is an amplitude regulated pierce oscilla tor type with integrated load capacitances (2 18pf with a tolerance of 17%) hence c lmin = 7.4pf and c lmax = 10.6pf. the xto oscillation frequency f xto is the reference frequency fref for the fractional-n synthesizer. when designing the system in terms of receiving and transmitting frequency offset the accuracy of the crystal and xto have to be considered. the synthesizer can adjust the local oscillator frequency for the initial frequency error in f xto . this is done at nominal supply voltage and temperature with the control registers 2 and 3 (see table 9-7 on page 34 and table 9-10 on page 35 ). the remaining local oscillator tolerance at nominal supply voltage and temperature is then < 0. 5ppm. the xto?s gm has very low influence of less than 2ppm on the frequency at nominal supply voltage and temperature. in a single channel system less than 150ppm should be correct ed to avoid that harmonics of the clk output disturb the receive mode. if the clk is not used, or carefully layout ed on the application pcb (as needed for multi channel systems), more than 150ppm can be compensated. the additional xto pulling is only 2ppm, overtemperature and supply voltage. the xtal vers us temperature and its aging is then the main source of frequency error in the local oscillator. the xto frequency depends on xtal properties and the load capacitances c l1, 2 at pin xtal1 and xtal2. the pulling of f xto from the nominal f xtal is calculated using the following formula : ppm. c m is the crystal's motional, c 0 the shunt and c ln the nominal load capacitance of t he xtal found in its datasheet. c l is the total actual load capacitance of the cr ystal in the circuit and consists of c l1 and c l2 in series connection. figure 6-1. xtal with load capacitances with c m 14ff, c 0 1.5pf, c ln = 9pf and c l = 7.4pf to 10.6pf the pulling amounts to p 100ppm and with c m 7ff, c 0 1.5pf, c ln = 9pf and c l = 7.4pf to 10.6pf the pulling is p 50ppm. since typical crystals have less than 50ppm tolerance at 25c, t he compensation is not critical and can, in both cases, be done with the 150ppm. c 0 of the xtal has to be lower than c lmin /2 = 3.7pf for a pierce oscillator type in order to not enter the steep region of pulling versus load capacitance where there is a risk of an unstable oscillation. to ensure proper start-up behavior the small signal gain, and thus the negative resistan ce provided by this xto at start is very large. for example oscillation st arts up, even in worst case, with a crystal series resistance of 1.5k at c 0 2.2pf with this xto. the negative resistance is approximately given by with z 1 , z 2 as complex impedances at pin xtal1 and xtal2 hence z 1 =?j/(2 f xto c l1 ) + 5 and z 2 = ?j/(2 f xto c l2 ) + 5 . z 3 consists of crystals c 0 in parallel with an internal 110k resistor hence z 3 =?j/(2 f xto c 0 ) /110k , gm is the internal transconductance betw een xtal1 and xtal2 with typically 19ms at 25c. p c m 2 ------- c ln c l ? c 0 c ln + () c 0 c l + () ---------------------------------------------------------- - 10 6 = c 0 c l2 c l1 c m l m r m c l = c l1 x c l2 / (c l1 + c l2 ) xtal crystal equivalent circuit re z xtocore {} re z 1 z 3 z 2 z 3 z 1 + z 2 z 3 g m + z 1 z 2 z 3 z 1 z 2 g m +++ ---------------------------------------------------------------------------------------------- ?? ?? ?? =
ata5823/ata5824 [datasheet] 4829f?rke?05/14 24 with f xto = 13.5mhz, gm = 19ms, c l =9pf, c 0 = 2.2pf this results in a ne gative resistance of about 2k . the worst case for technological, supply voltage and tem perature variations is then for c 0 2.2pf always higher than 1.5k . due to the large gain at start, the xto is able to meet a very low start-up time. the oscillation start-up time can be estimate d with the time constant . after 10 to 20 , an amplitude detector detects the oscillation amplitude and sets xto_ok to high if the amplitude is large enough. this activates the clk output if clk_on and clk_en in control register 3 are high (see table 9-12 on page 35 ). note that the necessary conditions of t he dvcc voltage also have to be fulfilled (see figure 6-2 on page 24 and figure 7-1 on page 27 ). to save current in idle and sleep mode, the load capac itors partially are switched off in this modes with s 1 and s 2 seen in figure 6-2 on page 24 . it is recommended to use a crystal with c m = 3.0ff to 7.0ff, c ln = 9pf, r m <120 and c 0 = 1.0pf to 2.2pf. lower values of c m can be used, this increases slightly the start-up time. lower values of c 0 or higher values of c m (up to 15ff) can also be used, this has only little influence to pulling. figure 6-2. xto block diagram to find the right values used in the control registers 2 and 3 (see table 9-7 on page 34 and table 9-10 on page 35 ) the relationship between f xto and the f rf is shown in table 6-1 . to determine the right content, the frequency at pin clk, as well as the output frequency at rf _out in ask mode can be meas ured, than the freq value can be calculated according to table 6-1 so that f rf is exactly the desired radio frequency. 2 4 2 f m 2 c m re z xtocore () r m + () --------------------------------------------------------------------------------------------------- - = 8 pf 8 pf xtal1 divider /16 clk_en (control register 3) clk_on (control register 3) dvcc_ok (from power supply) baud1 in idle mode and during sleep mode (rx_polling) the switches s1 and s2 are open. xlim baud0 & divider /3 xto_ok (to reset logic) divider /1 /2 /4 /8 /16 10 pf 10 pf amplitude detector s2 s1 f xdclk xtal2 clk c l2 c l1 f xto f dclk
25 ata5823/ata5824 [datasheet] 4829f?rke?05/14 the variable freq depends on the bit pll_mode in control register 1 and the parameter freq2 and freq3, which are defined by the bits fr0 to fr12 in control register 2 and 3 and is calculated as follows: freq = freq2 + freq3 care must be taken with the harmonics of the clk output signal f clk , as well as to the harmonics produced by an microprocessor clocked with it, since these ha rmonics can disturb the reception of signal s if they get to the rf input. in a single channel system the use of freq = 3803 to 4053 ensures t hat harmonics of this signal do not disturb the receive mode. in a multichannel system the clk si gnal can either be not used or carefully layouted on the application pcb. the supply voltage of the microcontroller must also be carefully blocked in a multichannel system. 6.1 pin clk pin clk is an output to clock a connect ed microcontroller. the clock frequency f clk is calculated as follows: the signal at clk output has a nominal 50% duty cycle. if the bit clk_en in control register 3 is se t to 0, the clock is disabled permanently. if the bit clk_en is set to 1 and bit clk_on (control register 3) is set to 0, the clock is disabl ed as well. if bit clk_on is s et to 1 and thus the clock is enabled if the bit-check is ok (r x, rx polling, fd mode (slave)), an event on pin n_pwr_on occurs or the bit power_on in the status register is 1. figure 6-3. clock timing table 6-1. calculation of f rf frequency (mhz) pin 6 433_n868 creg1 bit(4) fs f xto (mhz) f rf = f tx_ask = f rx f tx_fsk_l = f tx_fsk_l(fd) f tx_fsk_h f tx_fsk_h(fd) frequency resolution 315.0 avcc 1 12.73193 f rf ? 18.65khz f rf + 18.65 khz f rf + 208.23khz 777.1hz 433.92 avcc 0 13.25311 f rf ? 19.41khz f rf + 19.41khz f rf + 203.74khz 808.9hz f xto 24 5 freq 24,5 + 16384 ------------------------------- - + , ?? ?? f xto 32 5 freq 24,5 + 16384 ------------------------------- - + , ?? ?? f clk f xto 3 ----------- = clk_on (control register 3) clk_en (control register 3) clk dvcc v dvcc = 1.6v (typ)
ata5823/ata5824 [datasheet] 4829f?rke?05/14 26 6.2 basic clock cycle of the digital circuitry the complete timing of the digital circuitry is derived from one clock. according to figure 6-2 on page 24 , this clock cycle t dclk is derived from the crystal oscillator (xto) in combination with a divider. t dclk controls the following application relevant parameters: timing of the polling circuit including bit-check tx bit rate the clock cycle of the bit-check and the tx bit rate depends on the selected bit-rate range (br_range) which is defined in control register 6 (see table 9-19 on page 37 ) and x lim which is defined in control register 4 (see table 9-16 on page 36 ). this clock cycle t xdclk is defined by the following formulas for further reference: br_range ? br_range 0: t xdclk = 8 t dclk x lim br_range 1: t xdclk = 4 t dclk x lim br_range 2: t xdclk = 2 t dclk x lim br_range 3: t xdclk = 1 t dclk x lim f dclk f xto 16 ----------- =
27 ata5823/ata5824 [datasheet] 4829f?rke?05/14 7. power supply figure 7-1. power supply the supply voltage range of the atmel ? ata5823/ata5824 is 2.15v to 3.6v or 4.4v to 5.25v. pin vs1 is the supply voltage input for the range 2.15v to 3.6v and is used in battery applications using a single lithium 3v cell. pin vs2 is the voltage input for the range 4.4v to 5.25v (car applications), in this ca se the voltage regulator v_reg regulates vs1 to typically 3.25v. if the vo ltage regulator is active, a blocking capacitor of 2.2f has to be connected to vs1. pin vsint is the voltage input for the microcontroller_inte rface and must be connected to the power supply of the microcontroller. the voltage range of v vsint is 2.25v to 5.25v (see figure 7-5 and figure 7-6 on page 30 ). avcc is the internal operation voltage of the rf transcei ver and is feed via the switch sw_avcc by vs1. avcc must be blocked on pin avcc with a 68nf capacitor (see figure 3-1 on page 7 and figure 4-1 on page 8 ). dvcc is the internal operation voltage of the digital control lo gic and is fed via the switch sw_dvcc by vs1. dvcc must be blocked on pin dvcc with 68nf (see figure 3-1 on page 7 and figure 4-1 on page 8 ). pin pwr_on is an input to switch on the transceiver (active high). pin n_pwr_on is an input for a push button and can al so be used to switch on the transceiver (active low). for current consumption reasons it is recommended to set n_pwr_on to gnd only temporarily. otherwise an additional current flows because of a 50k pull-up resistor. a voltage monitor generates the signal dvcc_ok if dvcc 1.6v typically. v_monitor (1.6v typ.) v_reg1 3.25v typ. sw_dvcc dvcc_ok (to xto and reset logic) sw_avcc out r s ff1 q vsint dvcc_ok xto_ok offcmd (command via spi) r 0 1 0 1 q no change 0 1 1 s 0 0 1 1 avcc dvcc vs2 n_pwr_on pwr_on vs1 in en 1 & 1
ata5823/ata5824 [datasheet] 4829f?rke?05/14 28 figure 7-2. flow chart operation modes 7.1 off mode after connecting the power supply (battery) to pin vs1 and/or vs2 and vsint, the transceiver is in off mode. in off mode avcc and dvcc are disabled, resulting in very low power consumption (i s_off is typically 10na in the key fob application figure 3-1 on page 7 and 0.5a in the car application figure 4-1 on page 8 ). in off mode the transceiver is not programmable via the 4-wire serial interface. 7.2 idle mode in idle mode avcc and dvcc are conne cted to the battery voltage (vs1). from off mode the transceiver changes to idle mode if pin pwr_ on is set to 1 or pin n_pwr_ on is set to 0. this state transition is indicated by an interrupt at pin irq and the status bits power_on = 1 or n_power_on = 1. in idle mode the rf transceiver is disabled and the power consumption i idle_vs1,2 is about 270 a (clk output off vs1 = vs2 = 3v). the exact value of this current is strongly dependent on the application and the exact operation mode, therefore check the section ?electrical characte ristics? for the appropriate application case. via the 4-wire serial interface a connected microcontrolle r can program the required parameter and enable the tx, rx polling, rx or fd mode.the transceiver can be set back to off mode by an off command via the 4-wire serial interface (the input level of pin pwr_on must be 0 and pin n_pwr_on = 1 before writing the off command) off mode avcc = off dvcc = off idle mode avcc = vs1 dvcc = vs1 rx mode rx polling mode fd mode (slave) fd mode (master) tx mode avcc = vs1; dvcc = vs1 off command and pin pwr_on = 0 and pin n_ pwr_on = 1 pin pwr_on = 1 or pin n_ pwr_on = 0 opm2 opm2 = 0 and opm1 = 0 and opm0 = 0 opm1 opm0 001 010 011 101 111 tx mode rx polling mode rx mode fd mode (maaster) fd mode (slave) table 7-1. control register 1 opm2 opm1 opm0 function 0 0 0 idle mode
29 ata5823/ata5824 [datasheet] 4829f?rke?05/14 7.3 reset timing and reset logic if the transceiver is switched on (o ff mode to idle mode) dvcc and avcc are ramping up as illustrated in figure 7-3 . the internal signal dvcc_reset resets the digi tal control logic and sets the control r egister to default va lues. bit dvcc_rst in the status register is set to 1. after v dvcc exceeds 1.6v (typically) and the start-up time of the xto is elapsed, the output clock at pin clk is available. dvcc_rst in the status register is set to 0 if v dvcc exceeds 1.6v, the start-up time of the xto is elapse d and the status register is read via the 4-wire serial interface. if v dvcc drops below 1.6v (typically) and pin n_pwr_on = 1 and pin pwr_on = 0 the transceiver switches to off mode. figure 7-3. reset timing figure 7-4. reset logic dvcc, avcc dvcc_reset clk read status register 1.6v (typ) off mode off mode idle mode idle, tx, rx, rx polling, fd mode v dvcc > 1.6v and the xto is running dvcc_rst (status register) dvcc_ok dvcc_reset xto_ok &
ata5823/ata5824 [datasheet] 4829f?rke?05/14 30 7.4 battery application the supply voltage range is 2.15v to 3.6v. figure 7-5. battery application 7.5 car application the supply voltage range is 4.4v to 5.25v. figure 7-6. car application vs in out in out out in vsint clk irq cs sck sdi_tmdi sdo_tmdo dvcc rf transceiver digital control logic ata5823/ata5824 microcontroller microcontroller_interface avcc vs2 2.15v to 3.6v vs1 vs in out in out out in vsint clk irq cs sck sdi_tmdi sdo_tmdo dvcc rf transceiver digital control logic ata5823/ata5824 microcontroller microcontroller_interface avcc vs2 4.4v to 5.25v vs1
31 ata5823/ata5824 [datasheet] 4829f?rke?05/14 8. microcontroller interface the microcontroller interface is a level converter which converts all internal digital signals which are referred to the dvcc voltage, into the voltage used by the microc ontroller. therefore, the pin vsint can be connected to the supply voltage of the microcontroller in the case the microcontro ller has another supply voltage than the atmel ? ata5823/ ata5824.
ata5823/ata5824 [datasheet] 4829f?rke?05/14 32 9. digital control logic 9.1 register structure the configuration of the tran sceiver is stored in ram cells. the ram contains a 16 8-bit tx/rx data buffer and a 8 8-bit control register and is write and readable via a 4-wir e serial interface (cs, sck, sdi_tmdi, sdo_tmdo). the 1 8-bit status register is not pa rt of the ram and is readable via the 4-wire serial interface. the ram and the status information is stor ed as long as the transceiver is in any ac tive mode (dvcc = vs1) and gets lost if the transceiver is in the off mode (dvcc = off). after the transceiver is turned on via pin pwr_on = high or pi n n_pwr_on = low the control registers are in the default state. figure 9-1. register structure ir1 fs ir0 opm1 opm2 opm0 control register 1 (adr 0) control register 2 (adr 1) control register 3 (adr 2) control register 4 (adr 3) control register 5 (adr 4) control register 6 (adr 5) control register 7 (adr 6) pll_ mode t_ mode tx/rx data buffer: 16 8 bit lsb msb fr3 fr2 fr0 fr1 fr6 fr5 fr4 p_ mode fr9 fr8 xlim xsleep fr7 fr12 fr11 fr10 clk_ en clk_ on n_ power _on dvcc _rst power _on sleep 3 sleep 1 sleep 0 sleep 2 sleep 4 ask_ nfsk lim_ min5 lim_ min3 lim_ min0 lim_ min1 lim_ min2 lim_ min4 bitchk 0 bitchk 1 lim_ max5 lim_ max3 lim_ max0 lim_ max1 lim_ max2 lim_ max4 baud 0 baud 1 tx5 tx4 tx3 tx2 tx1 tx0 pout_ data pout_ select status register (adr 16) - = don?t care control register 8 (adr 7) - ---- - fe_ mode pws elect pws et4 pws et3 pws et2 pws et1 pws et0
33 ata5823/ata5824 [datasheet] 4829f?rke?05/14 9.2 tx/rx data buffer the tx/rx data buffer is used to handle the data transfer during rx and tx operations. 9.3 control register to use the transceiver in different applications the transceiver can be configured by a microcontroller connected via the 4- wire serial interface. 9.3.1 control register 1 (adr 0) table 9-1. control register 1 (function of bit 7 and bit 6 in rx mode) ir1 ir0 function (rx mode) 0 0 pin irq is set to 1 if 1 received byte is in th e tx/rx data buffer or a receiving error occurred 0 1 pin irq is set to 1 if 2 received bytes are in the tx/rx data buffer or a receiving error occurred 1 0 pin irq is set to 1 if 4 received bytes are in the tx/rx data buffer or a receiving error occurred (default) 1 1 pin irq is set to 1 if 12 received bytes are in the tx/rx data buffer or a receiving error occurred table 9-2. control register 1 (function of bit 7 and bit 6 in tx mode) ir1 ir0 function (tx mode) 0 0 pin irq is set to 1 if 1 byte still is in the tx/rx data buffer or the tx data buffer is empty 0 1 pin irq is set to 1 if 2 bytes still are in the tx /rx data buffer or the tx data buffer is empty 1 0 pin irq is set to 1 if 4 bytes still are in the tx/rx data buffer or the tx data buffer is empty (default) 1 1 pin irq is set to 1 if 12 bytes still are in the tx /rx data buffer or the tx data buffer is empty note: the bits ir0 and ir1 have no function in fd mode table 9-3. control register 1 (function of bit 5) pll_mode function 0 adjustable range of freq: 3072 to 4095 (default), see table 9-10 on page 35 1 adjustable range of freq: 0 to 8191, see table 9-11 on page 35 table 9-4. control register 1 (function of bit 4) fs function (rx mode, tx mode, fd mode) 0 selected frequency 433mhz (default) 1 selected frequency 315mhz
ata5823/ata5824 [datasheet] 4829f?rke?05/14 34 9.3.2 control register 2 (adr 1) table 9-5. control register 1 (fun ction of bit 3, bit 2 and bit 1) opm2 opm1 opm0 function 0 0 0 idle mode (default) 0 0 1 tx mode 0 1 0 rx polling mode 0 1 1 rx mode 1 0 0 - 1 0 1 - 1 1 0 - 1 1 1 - table 9-6. control register 1 (function of bit 0) t_mode function 0 tx and rx function via tx/rx data buffer (default) 1 transparent mode, tx/rx data buff er disabled, tx modulation data stream via pin sdi_tmdi, rx modulation data stream via pin sdo_tmdo table 9-7. control register 2 (function of bi t 7, bit 6, bit 5, bit 4, bit 3, bit 2 and bit 1) fr6 2 6 fr5 2 5 fr4 2 4 fr3 2 3 fr2 2 2 fr1 2 1 fr0 2 0 function 0 0 0 0 0 0 0 freq2 = 0 0 0 0 0 0 0 1 freq2 = 1 . . . . . . . 1 0 1 0 1 0 0 freq2 = 84 (default) . . . . . . . 1 1 1 1 1 1 1 freq2 = 127 note: tuning of f rf lsb?s (total 13 bits), frequency trimming, resolution of f rf is f xto /16384 which is approximately 800hz (see section ?xto?, table 6-1 on page 25 ) table 9-8. control register 2 (function of bit 0 in rx mode) p_mode function (rx mode) 0 pin irq is set to 1 if the bi t-check is successful (default) 1 no effect on pin irq if the bit-check is successful table 9-9. control register 2 (function of bit 0 in tx mode) p_mode function (tx mode) 0 manchester modulator on (default) 1 manchester modulator off (nrz mode) note: bit p_mode has no function in fd mode
35 ata5823/ata5824 [datasheet] 4829f?rke?05/14 9.3.3 control register 3 (adr 2) table 9-10. control register 3 (function of bit 7, bit 6, bit 5, bit 4, bit 3 and bit 2 if bit pll_mode = 0 (in control register 1) fr12 2 12 fr11 2 11 fr10 2 10 fr9 2 9 fr8 2 8 fr7 2 7 function x x x 0 0 0 freq3 = 3072 x x x 0 0 1 freq3 = 3200 x x x 0 1 0 freq3 = 3328 x x x 0 1 1 freq3 = 3456 x x x 1 0 0 freq3 = 3584 x x x 1 0 1 freq3 = 3712 x x x 1 1 0 freq3 = 3840(default) x x x 1 1 1 freq3 = 3968 note: tuning of f rf msb?s table 9-11. control register 3 (function of bit 7, bit 6, bit 5, bit 4, bit 3 and bit 2 if bit pll_mode = 1 (in control register 1) fr12 2 12 fr11 2 11 fr10 2 10 fr9 2 9 fr8 2 8 fr7 2 7 function 0 0 0 0 0 0 freq3 = 0 0 0 0 0 0 1 freq3 = 128 0 0 0 0 1 0 freq3 = 256 . . . . . . . 0 1 1 1 1 0 freq3 = 3840 (default) . . . . . . . 1 1 1 1 1 0 freq3 = 7936 1 1 1 1 1 1 freq3 = 8064 note: tuning of f rf msb?s table 9-12. control register 3 (function of bit 1 and bit 0) clk_en clk_on function (rx mode, tx mode, fd mode) 0 x clock output off (pin clk) 1 0 clock output off (pin clk). clock switched on by an event: bit-check ok or event on pin n_pwr_on or bit power_on in the status register is 1 1 1 clock output on (default) note: bit clk_on is set to 1 if the bit-check is ok (r x_polling, rx mode), an event at pin n_pwr_on occurs or the bit power_on in the status register is 1.
ata5823/ata5824 [datasheet] 4829f?rke?05/14 36 9.3.4 control register 4 (adr 3) table 9-13. control register 4 (function of bit 7) ask_nfsk function (tx mode, rx mode) 0 fsk mode (default) 1 ask mode note: bit ask_nfsk has no function in fd mode table 9-14. control register 4 (function of bit 6, bit 5, bit 4, bit 3 and bit 2) sleep4 2 4 sleep3 2 3 sleep2 2 2 sleep1 2 1 sleep0 2 0 function (rx mode) sleep (t sleep = sleep 1024 t dclk x sleep ) 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . 1 1 0 0 0 24 (t sleep = 24 1024 t dclk x sleep ) (default) . . . . . 1 1 1 1 1 31 note: bits sleep0 ... sleep4 have no function in tx mode and fd mode table 9-15. control register 4 (function of bit 1) xsleep function 0 x sleep = 1; extended t sleep off (default) 1 x sleep = 8; extended t sleep on note: bit x sleep has no function in tx mode and fd mode table 9-16. control register 4 (function of bit 0) xlim function 0 x lim = 1; extended t lim_min , t lim_max off (default) 1 x lim = 2; extended t lim_min , t lim_max on note: bit x lim has no function in tx mode and fd mode
37 ata5823/ata5824 [datasheet] 4829f?rke?05/14 9.3.5 control register 5 (adr 4) bits lim_min0 to lim_min5 have no function in tx mode and fd mode master. 9.3.6 control register 6 (adr 5) table 9-17. control register 5 (function of bit 7 and bit 6) bitchk1 bitchk0 function 0 0 n bit-check = 0 (0 bits checked during bit-check) 0 1 n bit-check = 3 (3 bits checked during bit-check) (default) 1 0 n bit-check = 6 (6 bits checked during bit-check) 1 1 n bit-check = 9 (9 bits checked during bit-check) note: bits bitchk0 and bitchk1 have no function in tx mode and fd mode master table 9-18. control register 5 (function of bit 5, bit 4, bit 3, bit 2, bit 1 and bit 0) lim_min5 2 5 lim_min4 2 4 lim_min3 2 3 lim_min2 2 2 lim_min1 2 1 lim_min0 2 0 function (rx mode, fd mode slave) lim_min (lim_min < 10 are not applicable) (t lim_min = lim_min t xdclk ) 0 0 1 0 1 0 10 0 0 1 0 1 1 11 (t lim_min = 11 t xdclk ) (default) . . . . . . 1 1 1 1 1 1 63 table 9-19. control register 6 (function of bit 7 and bit 6) baud1 baud0 function (rx mode, tx mode, fd mode) 0 0 bit-rate range 0 (b0) 1.0 kbit/s to 2.5 kbit/s; t xdclk = 8 t dclk x lim 0 1 bit-rate range 1 (b1) 2.0 kbit/s to 5.0 kbit/s; t xdclk = 4 t dclk x lim bit-rate in fd mode = 1 / (168 t dclk ) 1 0 bit-rate range 2 (b2) 4.0 kbit/s to 10.0 kbit/s; t xdclk = 2 t dclk x lim (default) 1 1 bit-rate range 3 (b3) 8.0 kbit/s to 20.0 kbit/s; t xdclk = 1 t dclk x lim note that the receiver is not working with >10 kbit/s in ask mode
ata5823/ata5824 [datasheet] 4829f?rke?05/14 38 9.3.7 control register 7 (adr 6) table 9-20. control register 6 (function of bit 5, bit 4, bit 3, bit 2, bit 1 and bit 0) lim_max5 2 5 lim_max4 2 4 lim_max3 2 3 lim_max2 2 2 lim_max1 2 1 lim_max0 2 0 function (rx mode, fd mode slave) lim_max (lim_max < 12 are not applicable) (t lim_max = (lim_max - 1) t xdclk ) 0 0 1 1 0 0 12 0 0 1 1 0 1 13 . . . . . . 1 0 0 0 0 0 32 (t lim_max = (32 ? 1) t xdclk ) (default) . . . . . . 1 1 1 1 1 1 63 note: bits lim_max0 to lim_max5 have no function in tx mode and fd mode master table 9-21. control register 7 (function of bit 7 and bit 6) pout_select pout_data function (rx mode, tx mode, fd mode) 0 0 output level on pin pout = 0 (default) 0 1 output level on pin pout = 1 1 x output level on pin pout = n_rx_active (1) note: 1. idle, tx, fd mode: n_rx_active = 1 rx mode: n_rx_active = 0 table 9-22. control register 7(function of bit 5, bit 4, bit 3, bi t2, bit1 and bit0) tx5 2 5 tx4 2 4 tx3 2 3 tx2 2 2 tx1 2 1 tx0 2 0 function (tx mode) tx (tx < 10 are not applicable) (tx_bitrate = 1/(tx + 1) t xdclk 2) 0 0 1 0 1 0 10 0 0 1 0 1 1 11 . . . . . . 0 1 0 1 0 0 20 (tx_bitrate = 1/(20 + 1) t xdclk 2) (default) . . . . . . 1 1 1 1 1 1 63 note: bits tx0 to tx5 have no function in rx mode and fd mode
39 ata5823/ata5824 [datasheet] 4829f?rke?05/14 9.3.8 control register 8 (adr 7) normally the setpwr resistor at pin 19 is used in full-duplex m ode to decrease the output power until the level at rf_in is low enough for reception of signals (pwselect = 0). with pwselect = 1 this resistor can also be used in normal half-duplex tx operation to adjust the output power for production tolerances. table 9-23. control register 8 (function of bit 6) fe_mode function 0 for future use 1 bit for internal use, must always set to 1 (default) table 9-24. control register 8 (function of bit 5) pwselect function (tx mode, fd mode) 0 r pwset = 140 typically in tx-mode and as defined by the bits pwset0 to pwset4 in fd mode (default) 1 r pwset as defined by the bits pwset0 to pwset4 table 9-25. control register 8 (function of bit 4, bit 3, bit 2, bit 1, bit 0) pwset4 2 4 pwset3 2 3 pwset2 2 2 pwset1 2 1 pwset0 2 0 function (tx mode, fd mode) (setpwr: programmable internal resistor to reduce the output power in fd and tx mode) pwset setpwr = 800 + (31 ? pwset) 3 k (typically) 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . 1 0 0 0 0 16 (default) setpwr = 800 + (31 ? 16) 3 k (typically) . . . . . 1 1 1 1 0 30 1 1 1 1 1 31
ata5823/ata5824 [datasheet] 4829f?rke?05/14 40 9.3.9 status register (adr 16) the status register indicates the current status of the transceiver and is readable via the 4-wire serial interface. setting power_on or an event on n_power_on is indicated by an irq. reading the status register resets t he bits power_on, dvcc_rst and the irq. 9.4 pin n_pwr_on to switch the transceiver from off to idle mo de, pin n_pwr_on must be set to 0 (maximum 0.2 v vs2 ) for at least t n_pwr_on_irq (see figure 9-2 ). the transceiver recognizes the negat ive edge and switches on dvcc and avcc. if v dvcc exceeds 1.6v (typically) and the xto is settled, the digital control logic is active and sets the status bit n_power_on to 1, an interrupt is issued (t n_pwr_on_irq ) and the output clock on pin clk is available. if the level on pin n_pwr_on was set to 1 before the interrupt is issued, the transceiver stays in off mode. note: it is not possible to se t the transceiver to off-mode by setting pin n_pwr_on to 1. if pin n_pwr_on is not used, it should be left open because of the internal pull-up resistor figure 9-2. timing pin n_pwr_on, status bit n_power_on if the transceiver is in any of the active modes (idle, tx, rx, rx_polling, fd), an integrated debounce logic is active. if there is an event on pin n_pwr_on, a debounce counter is set to 0 (t = 0) and started. the st atus is updated, an interrupt is issued and the debounce counter is stoppe d after reaching the counter value t = 8195 t dclk . table 9-26. status register status bit function n_power_on status of pin n_pwr_on pin n_pwr_on = 0 n_power_on = 1 pin n_pwr_on = 1 n_power_on = 0 ( figure 9-3 on page 41 ) power_on indicates that the transceiver was woken up by pin pwr_on (rising edge on pin pwr_on). during power_on = 1, the bit clk_on in control register 3 is set to 1 ( figure 9-4 on page 42 ). dvcc_rst dvcc_rst is set to 1 if the supply voltage of the ram (v dvcc ) was too low and the information in the ram may be lost. dvcc_rst = 0 supply voltage of the ram ok dvcc_rst = 1 supply voltage of the ram was too low (typically v dvcc <1.6v) if the transceiver changes from off mode to idle mode, dvcc_rst will be set to 1. reading the status register resets dvcc_rst to 0. n_power_on (status register) irq clk dvcc, avcc n_pwr_on idle mode off mode t n_pwr_on_irq 1.6v (typ)
41 ata5823/ata5824 [datasheet] 4829f?rke?05/14 an event on n_pwr_on before reaching t = 8195 t dclk stops the debounce counter. while the debounce counter is running, the bit clk_on in control register 3 is set to 1. the interrupt is deleted after reading the status register or executes the command delete_irq. if pin n_pwr_on is not used, it can be left open becau se of an internal pull-up resistor (typically 50k ). figure 9-3. timing flow pin n_pwr_on, status bit n_power_on 9.5 pin pwr_on to switch the transceiver from off to idle mode, pin pwr_on must set to 1 (minimum 0.8 v vsint ) for at least t pwr_on (see figure 9-4 on page 42 ). the transceiver recognizes the positi ve edge and switches on dvcc and avcc. if v dvcc exceeds 1.6v (typically) and the xto is settled, the digital control logic is active and sets the status bit power_on to 1, an interrupt is issued (t pwr_on_irq_1 ) and the output clock on pin clk is available. if the level on pin pwr_on was set to 0 before the in terrupt is issued, the transceiver stays in off mode. if the transceiver is in any of the ac tive modes (idle, rx, rx_polling, tx, fd), a positive edge on pin pwr_on sets power_on to 1 (after t pwr_on_irq_2 ). the state transition power_on 0 1 generates an interrupt. if power_on is still 1 during the positive edge on pin pwr_on, no interrupt is issued. power_on and the interrupt is deleted after reading the status register. during power_on = 1, th e bit clk_en in control register 3 is set to 1. note: it is not possible to set the transce iver to off mode by setting pin pwr_on to 0. if pin pwr_on is not used, it must be connected to gnd. idle mode or tx mode or rx polling mode or rx mode or fd mode stop debounce counter n_power_on = 1; irq = 1 stop debounce counter n_power_on = 0; irq = 1 stop debounce counter t = 0 start debounce counter event on pin n_pwr_on ? event on pin n_pwr_on ? pin n_pwr_on = 0 ? n n n y y y y n t = 8195 t dclk ?
ata5823/ata5824 [datasheet] 4829f?rke?05/14 42 figure 9-4. timing pin pwr_on, status bit power_on 9.6 dvcc_rst the status bit dvcc_rst is set to 1 if the voltage on pin dvcc v dvcc drops under 1.6v (typically). dvcc_rst is set to 0 if v dvcc exceeds 1.6v (typically) and t he status register is read via the 4-wire serial interface (see figure 7-3 on page 29 ). figure 9-5. timing flow status bit dvcc_rst power_on (status register) irq clk dvcc, avcc pwr_on off mode idle mode idle, rx, rx polling, tx, fd mode t pwr_on > t pwr_on_irq_2 t pwr_on > t pwr_on_irq_1 t pwr_on_irq_2 t pwr_on_irq_1 1.6v (typ) idle, tx, rx rx polling mode, fd mode read status register vdvcc < 1.6v (typ) ? pin pwr_on = 1 or pin n_pwr_on = 0 ? y y n n dvcc_rst = 1; off_mode
43 ata5823/ata5824 [datasheet] 4829f?rke?05/14 10. transceiver configuration the configuration of the transceiver takes place via a 4-wir e serial interface (cs, sck, sdi_tmdi, sdo_tmdo) and is organized in 8-bit units. the configuration is initiated with a 8-bit command. while shifting the command into pin sdi_tmdi, the number of bytes in the tx/rx data buffer are availabl e on pin sdo_tmdo. the read and write commands are followed by one or more 8-bit data units. each 8- bit data transmission begins with the msb. 10.1 command: read tx/rx data buffer during a rx operation the user can read the received bytes in the tx/rx data buffer successively. figure 10-1. read tx/rx data buffer 10.2 command: write tx/rx data buffer during a tx operation the user can write the bytes in the tx/rx data buffer successively. figure 10-2. write tx/rx data buffer 10.3 command: read control/status register the control and status registers can be read individually or successively. figure 10-3. read cont rol/status register sck cs sdo_tmdo sdi_tmdi msb msb lsb lsb lsb msb rx data byte 1 rx data byte 1 no. bytes in the tx/rx data buffer command: read tx/rx data buffer xx sck cs sdo_tmdo sdi_tmdi tx data byte 1 write tx/rx data buffer no. bytes in the tx/rx data buffer command: write tx/rx data buffer tx data byte 1 msb msb lsb lsb lsb msb tx data byte 2 sck cs sdo_tmdo sdi_tmdi data c/s register x data c/s register y no. bytes in the tx/rx data buffer command: read c/s register x msb msb lsb lsb lsb msb command: read c/s register z command: read c/s register y
ata5823/ata5824 [datasheet] 4829f?rke?05/14 44 10.4 command: write control register the control registers can be writt en individually or successively. figure 10-4. write control register 10.5 command: off command if the input level on pin pwr_on is low and on the key input n_pwr_on is high, the off command sets the transceiver to the off mode. figure 10-5. off command 10.6 command: delete irq the delete irq command sets pin irq to low. figure 10-6. delete irq sck cs sdo_tmdo sdi_tmdi write control register x data control register x no. bytes in the tx/rx data buffer command: write control register x msb msb lsb lsb lsb msb command: write control register y data control register x sck cs sdo_tmdo sdi_tmdi no. bytes in the tx/rx data buffer command: off command lsb msb sck cs sdi_tmdi no. bytes in the tx/rx data buffer command: delete irq lsb msb
45 ata5823/ata5824 [datasheet] 4829f?rke?05/14 10.7 command structure the three most significant bits of the command (bit 5 to bit 7) indicates the comm and type. bit 0 to bit 4 describes the target address when reading or writing to a control or status register. bit 0 to bit 4 in the command write tx/rx data buffer defines the value n (0 n 16). the tx operatio n only will be started if the number of by tes in the tx buffer n. this function makes sure that the dat astream will be sent without gaps. the tx operation only will be started if at least 1 byte are in the tx buffer. this means that n = 0 and n = 1 have the same function. in all other commands bit 0 to bit 4 have no effect and should be set to 0 for compatibility reasons with future products. 10.8 4-wire serial interface the 4-wire serial interface consists of the chip select (cs) , the serial clock (sck), the serial data input (sdi_tmdi) and the serial data output (sdo_tmdo). data is transmitted/received bit by bit in synchronization with the serial clock. pin cs_pol defines the active level of the cs: when cs is inactive and the transceiver is not in rx transparent mode, sdo_tmdo is in a high-impedance state. pins sck_pol and sck_pha defines the polarity and the phase of the serial clock sck. figure 10-7. serial timing sck_pol = 0, sck_pha = 0 table 10-1. command structure command msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read tx/rx data buffer 0 0 0 x x x x x write tx/rx data buffer 0 0 1 n4 n3 n2 n1 n0 read control/status register 0 1 0 a4 a3 a2 a1 a0 write control register 0 1 1 a4 a3 a2 a1 a0 off command 1 0 0 x x x x x delete irq 1 0 1 x x x x x not used 1 1 0 x x x x x not used 1 1 1 x x x x x table 10-2. active level of the cs cs_pol function 0 cs active high 1 cs active low msb msb-1 lsb msb msb-1 x x x x x x cs sck sdo_tmdo sdi_tmdi t cs_disable t sck_setup2 t sck_hold t sck_setup1 t cycle x can be either v il or v ih t cs_setup t out_enable t out_delay t setup t hold t out_disable
ata5823/ata5824 [datasheet] 4829f?rke?05/14 46 figure 10-8. serial timing sck_pol = 0, sck_pha = 1 figure 10-9. serial timing sck_pol = 1, sck_pha = 0 figure 10-10.seri al timing sck_pol = 1, sck_pha = 1 msb lsb msb-1 xx msb lsb msb-1 x x x x cs sck sdo_tmdo sdi_tmdi t sck_setup1 t sck_hold x can be either v il or v ih t out_enable t out_disable t setup t hold t cycle t cs_setup t cs_setup2 t cs_disable t out_delay msb msb-1 lsb msb msb-1 x x x x x x cs sck sdo_tmdo sdi_tmdi t cs_disable t sck_setup2 t sck_hold t sck_setup1 t cycle x can be either v il or v ih t cs_setup t out_enable t out_delay t setup t hold t out_disable msb lsb msb-1 xx msb lsb msb-1 x x x x cs sck sdo_tmdo sdi_tmdi t sck_setup1 t sck_hold x can be either v il or v ih t out_enable t out_disable t setup t hold t cycle t cs_setup t cs_setup2 t cs_disable t out_delay
47 ata5823/ata5824 [datasheet] 4829f?rke?05/14 11. operation modes 11.1 rx operation the transceiver is set to rx operation with the bits opm0, opm1 and opm2 in control register 1 the transceiver is designed to consume less than 1ma in rx o peration while being sensitive to signals from a corresponding transmitter. this is achieved via the polling circuit. this ci rcuits enable the signal path periodically for a short time. duri ng this time the bit-check logic verifies the presence of a valid trans mitter signal. only if a valid signal is detected the transceive r remains active and transfers the data to the connected microcontroller. this trans fer take place either via the tx/rx data buffer or via the pin sdo_tmdo. if there is no valid signal presen t the transceiver is in sleep mode most of the time resulting in low current consumption. this condition is called rx polling mode. a connected microcontroller can be disabled during this time. all relevant parameters of the polling logic can be configured by the connected microcontroller . this flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc. in rx mode the rf transceiver is enabled permanently and th e bit-check logic verifies the presence of a valid transmitter signal. if a valid signal is detected the transceiver transfers t he data to the connected microcontroller. this transfer takes place either via the tx/rx data buffer or via the pin sdo_tmdo. 11.1.1 rx polling mode if the transceiver is in rx polling mode, it stays in a continuous cycle of three differ ent modes. in sleep mode, the rf transceiver is disabled for the time period t sleep while consuming low current of i s =i idle_x . during the start-up period, t startup_pll and t startup_sig_proc , all signal processing circuits are enabled and settled. in the following bit-check mode, the incoming data stream is analyzed bit by bit versus a valid tr ansmitter signal. if no valid signal is present, the transceiver i s set back to sleep mode after the period t bit-check . this period varies check by check as it is a statistical process. an average value for t bit-check is given in the electrical characteristics. during t startup_pll the current consumption is i s =i rx_x . during t startup_sig_proc and t bit-check the current consumption is i s =i startup_sig_proc_x . the condition of the transceiver is indicated on pin rx_active (see figure 11-1 ). the average current consum ption in rx polling mode i poll is different in battery application or car application. to calculate i poll the index x must be replaced by vs1,2 in battery application or vs2 in car application (see section ?electrical characteristi cs: general? on page 61 ). to save current it is recommended clk be disabled during rx polling mode. i p does not include the current of the microcontroller_interface i vsint . if clk is enabled during the rx polling mo de the current consumption is calculated as follows: during t sleep , t startup_pll and t startup_sig_proc the transceiver is not sensitive to a transmitter signals. to guarantee the reception of a transmitted command the transmitter must start the telegram with an adequate preburst. the required length of the preburst t preburst depends on the polling parameters t sleep , t startup_pll , t startup_sig_proc and t bit-check . thus, t bit-check depends on the actual bit rate and the number of bits (n bit-check ) to be tested. table 11-1. control register 1 opm2 opm1 opm0 function 0 1 0 rx polling mode 0 1 1 rx mode i poll i idle_x t sleep i startup_pll_x t startup_pll i rx_x t startup_sig_proc t bitcheck + () ++ t sleep t startup_pll t startup_sig_proc t bitcheck ++ + ------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------- = i s_poll i poll i vsint + = t preburst t sleep t startup_pll t startup_sig_proc t bitcheck ++ +
ata5823/ata5824 [datasheet] 4829f?rke?05/14 48 11.1.2 sleep mode the length of period t sleep is defined by the 5-bit word sleep in co ntrol register 4, the extension factor x sleep defined by the bit x sleep in control register 4 and the basic clock cycle t dclk . it is calculated to be: in us and european applications, the maximum value of t sleep is about 38 ms if x sleep is set to 1 (which is done by setting the bit x sleep in control register 4 to 0). the time resolution is a bout 1.2ms in that case. the sleep time can be extended to about 300 ms by setting x sleep to 8 (which is done by setting x sleep in control register 4 to 1), the time resolution is then about 9.6 ms. 11.1.3 start-up mode during t startup_pll the pll is enabled and starts up . if the pll is locked, the signa l processing circuit starts up (t startup_sig_proc ). after the start-up time all circuits are in stable condition and ready to receive. t sleep sleep 1024 t dclk x sleep =
49 ata5823/ata5824 [datasheet] 4829f?rke?05/14 figure 11-1. flow chart rx polling mode/rx mode start rx mode start rx polling mode start-up pll: the pll is enabled and locked. output level on pin rx_active -> high; i s = i startup_pll_x ; i startup_pll start-up signal processing: the signal processing circuit are enabled. output level on pin rx_active -> high; i s = i rx_x ; t startup_sig_proc the incomming data stream is analyzed. if the timing indicates a valid transmitter signal, the control bit clk_on and opm0 are set to 1 and the transceiver is set to receiving mode. otherwise it is set to sleep mode or to start_up mode. output level on pin rx_active -> high bit-check mode: sleep: defined by bits sleep 0 to sleep 4 in control register 4 798.5 t dclk (typ) t startup_pll : (br_range 0) is defined by the selected baud rate range and t dclk .the bit-rate range is defined by bit baud 0 and baud 1 in control register 6. if the bit check is ok, t bit-check depends on the number of bits to be checked (n bit-check ) and on the utilized data rate. 930 t dclk (br_range 1) 546 t dclk (br_range 2) 354 t dclk (br_range 3) 258 t dclk t startup_sig_proc : defined by bit xsleep in control register 4 basic clock cycle t dclk : x sleep : depends on the result of the bit check. t bit-check : all circuits for analog signal processing are disabled. only xto and polling logic is enabled. output level on pin rx_active -> low; i s = i idle_x t sleep = sleep 1024 t dclk x sleep sleep mode: start-up mode: t_mode = 0 and p_mode = 0 ? bit check ok ? set irq no yes yes yes yes no no no set clk_on = 1 set opm0 = 1 t sleep = 0 ? opm0 = 1 ? i s = i startup_sig_proc_x t bit-check the incomming data stream is passed via the tx/rx data buffer or via pin sdo_tmdo to the connected microcontroller. if an bit error occurs the transceiver is set back to start-up mode. output level on pin rx_active -> high receiving mode: bit error ? start bit detected ? yes yes no no no rx data stream is written into the tx/rx data buffer t_mode = 1 and level on pin cs = inactive ? rx data stream available on pin sdo_tmdo i s = i rx_x if the bit check fails, the average time period for that check despends on the selected bit-rate range and on t xdclk . the bit-rate range is defined by bit baud 0 and baud 1 in control register 6. if the transparent mode is not active and the transceiver detects a bit errror after a successful bit check and before the start bit is detected pin irq will be set to high and the transceiver is set back to start-up mode.
ata5823/ata5824 [datasheet] 4829f?rke?05/14 50 11.1.4 bit-check mode in bit-check mode the incoming data st ream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. this is done by subseq uent time frame checks where the distance between 2 signal edges are continuously compared to a programmable time windo w. the maximum count of this edge to edge test before the transceiver switches to receivin g mode is also programmable. 11.1.5 bit-check configuration assuming a modulation scheme that contains 2 edges per bit, tw o time frame checks are verifying one bit. this is valid for manchester, bi-phase and most ot her modulation schemes. the maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable n bit-check in control register 5. this implies 0, 6, 12 and 18 edge to edge checks respectively. if n bit- check is set to a higher value, the transceiver is less likely to swit ch to receiving mode due to noise. in the presence of a valid transmitter signal, the bit- check takes less time if n bit-check is set to a lower value. in rx polling mode, the bit-check time is not dependent on n bit-check if no valid signal is present. figure 11-2 shows an example where 3 bits are tested successful. figure 11-2. timing diagram for complete successful bit-check according to figure 11-3 , the time window for the bit-check is defined by two separate time limits. if the edge to edge time t ee is in between the lower bit-check limit t lim_min and the upper bit-check limit t lim_max , the check will be continued. if t ee is smaller than limit t lim_min or exceeds t lim_max , the bit-check will be terminated and the transceiver switches to sleep mode. figure 11-3. valid time window for bit-check for the best noise immunity it is re commended to use a low span between t lim_min and t lim_max . this is achieved using a fixed frequency at a 50% duty cycle for the transmitter prebur st. a ?11111...? or a ?10101...? sequence in manchester or bi- phase is a good choice concerning that advice. a good compro mise between sensitivity and susceptibility to noise regarding the expected edge to edge time t ee is a time window of 38%. to get the maximum sensitivity the time window should be 50% and then n bit-check 6. using preburst patterns that contain various edge to edge time periods, the bit-check limits must be programmed according to the required span. bit check mode bit check ok start-up mode receiving mode 1/2 bit 1/2 bit 1/2 bit 1/2 bit 1/2 bit 1/2 bit rx_active (number of checked bits: 3) demod_out bit check t startup_sig_proc t bit-check demod_out 1/f signal t ee t lim_min t lim_max
51 ata5823/ata5824 [datasheet] 4829f?rke?05/14 the bit-check limits are determined by means of the formula below: t lim_min = lim_min t xdclk t lim_max = (lim_max -1) t xdclk lim_min is defined by the bits lim_min 0 to lim_min 5 in control register 5. lim_max is defined by the bits lim_ma x 0 to lim_max 5 in control register 6. using the above formulas, lim_min and lim_max can be determined according to the required t lim_min , t lim_max and t xdclk . the time resolution defining t lim_min and t lim_max is t xdclk . the minimum edge to edge time t ee is defined according to the section ?receiving mode? on page 53 . the lower limit should be set to lim_min 10. the maximum value of the upper limit is lim_max = 63. figure 11-4 , figure 11-5 and figure 11-6 on page 52 illustrate the bit-check for the bit-check limits lim_min = 14 and lim_max = 24. the signal processing circuits are enabled during t startup_pll and t startup_sig_proc . the output of the ask/fsk demodulator (demod_out) is undefined duri ng that period. when the bit-check bec omes active, the bit-check counter is clocked with the cycle t xdclk . figure 11-4 shows how the bit-check proceeds if the bit-check counter value cv_lim is within t he limits defined by lim_min and lim_max at the occurrence of a signal edge. in figure 11-5 on page 52 the bit-check fails as the value cv_lim is lower than the limit lim_min. the bit-check also fails if cv_lim reaches lim_max. this is illustrated in figure 11-6 on page 52 . figure 11-4. timing diagram during bit-check bit check ok bit check ok bit-check mode start-up mode 1/2 bit 1/2 bit 1/2 bit rx_active (lim_min = 14, lim_max = 24) demod_out bit-check counter bit-check t startup_sig_proc t bit-check t xdclk 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5 6 7 8 9 10 11 0 12 13 14 15 1 2 3 4 5 67
ata5823/ata5824 [datasheet] 4829f?rke?05/14 52 figure 11-5. timing diagram for failed bi t-check (condition cv_lim < lim_min) figure 11-6. timing diagram for fail ed bit-check (con dition: cv_lim lim_max) 11.1.6 duration of the bit-check if no transmitter is present during the bit-check, the outpu t of the ask/fsk demodulator delivers random signals. the bit- check is a statistical process and t bit-check varies for each check. therefore, an average value for t bit-check is given in the electrical characteristics. t bit-check depends on the selected bit-rate range and on t xdclk . a higher bit-rate range causes a lower value for t bit-check resulting in a lower current consumption in rx polling mode. in the presence of a valid transmitter signal, t bit-check is dependent on the frequency of that signal, f signal , and the count of the bits, n bit-check . a higher value for n bit-check thereby results in a longer period for t bit-check requiring a higher value for the transmitter pre-burst t preburst . start-up mode t sleep t bit_check t startup_sig_proc bit-check mode sleep mode 1/2 bit rx_active demod_out bit-check counter bit check (lim_min = 14, lim_max = 24) bit check failed (cv_lim < lim_min) 1 2345678123456789101112 0 0 13 14 15 16 17 18 19 20 21 22 23 24 start-up mode t sleep t bit_check t startup_sig_proc bit-check mode sleep mode 1/2 bit rx_active demod_out bit-check counter bit check (lim_min = 14, lim_max = 24) bit check failed (cv_lim < lim_min) 1 2345678123456789101112 0 0
53 ata5823/ata5824 [datasheet] 4829f?rke?05/14 11.1.7 receiving mode if the bit-check was successful for all bits specified by n bit-check , the transceiver switches to receiving mode. to activate a connected microcontroller, bit clk_on in cont rol register 3 is set to 1. an interrupt is issued at pin irq if the control bits t_mode = 0 and p_mode = 0. if the transparent mode is active (t_mode = 1) and the level on pi n cs is inactive (no data transf er via the serial interface), the rx data stream is available on pin sdo_tmdo ( figure 11-7 ). figure 11-7. receivin g mode (tmode = 1) if the transparent mode is inactive (t_m ode = 0), the received data stream is buffered in the tx/rx data buffer (see figure 11-8 on page 54 ). the tx/rx data buffer is only usable for manchester and bi-phase coded sig nals. it is permanently possible to transfer the data from the data buffer via the 4-wire serial interface to a microcontroller (see figure 10-1 on page 43 ). buffering of the data stream: after a successful bit-check, the transceiver switches from bi t-check mode to receiving mode. in receiving mode the tx/rx data buffer control logic is active and ex amines the incoming data str eam. this is done, like in t he bit-check, by subsequent time frame checks where the di stance between two edges is continuously compared to a programmable time window as illustrated in figure 11-8 on page 54 . only two distances between two edges in manchester and bi-phase coded signals are valid (t and 2t). the limits for t are the same as used for the bit-check. they can be programmed in control register 5 and 6 (lim_min, lim_max). the limits for 2t are calculated as follows: lower limit of 2t: upper limit of 2t: if the result of lim_min_2t or lim_max_2t is not an integer value, it will be round up. if the tx/rx data buffer contro l logic detects the start bit, the data stream is written in the tx/rx data buffer byte by byte. the start bit is part of the first data byte and must be differen t from the bits of the preburst. if the preburst consists of a sequence of ?00000...?, the start bit must be a 1. if the preburst consists of a sequence of ?11111...?, the start bit must be a 0. if the data stream consists of more than 16 bytes, a buffer overflow occurs and the tx/rx data buffer control logic overwrites the bytes already stored in the tx /rx data buffer. so it is very important to ens ure that the data is read in time so that no buffer overflow occurs in that case (see figure 10-1 on page 43 ). there is a counter that indicates the number of received bytes in the tx/rx data buffer (see section ?transceiver configuration? on page 43 ). if a byte is transferred to the microcontroller, the counter is de cremented, if a byte is received, the counter is increment ed. the counter value is available via the 4-wire serial interface. an interrupt is issued if the counter whil e counting forwards reaches the value defi ned by the control bits ir0 and ir1 in control register 1. sdo_tmdo demod_out bit check ok preburst byte 2 byte 1 start bit '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '0' '0' '0' '0' '0' '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0' bit-check mode receiving mode byte 3 lim_min_2t lim_min lim_max + () lim_max lim_min ? () 2 ? ? = t lim_min_2t lim_min_2t t xdclk = lim_max_2t lim_min lim_max + () lim_max lim_min ? () 2 ? + = t lim_max_2t (lim_max_2t 1 ) ? t xdclk =
ata5823/ata5824 [datasheet] 4829f?rke?05/14 54 figure 11-8. receiving mode (tmode = 0) if the tx/rx data buffer control logic detects a bit error, an in terrupt is issued and the transce iver is set back to the start -up mode (see figure 11-1 on page 49 and figure 11-9 ). bit error: a) t ee < t lim_min or t lim_max < t ee < t lim_min_2t or t ee > t lim_max_2t b) logical error (no edge detected in the bit center) note: the byte consisting of the bit error will not be stored in the tx/rx data buffer. thus it is not available via the 4- wire serial interface. writing the control register 1, 4, 5, 6 or 7 during receiving m ode resets the tx/rx data buffer control logic and the counter which indicates the number of received bytes. if the bits opm0 and opm1 are still 1 and opm2 is still 0 after writing to a control register, the transceiver changes to t he start-up mode (start-up signal processing). figure 11-9. bit error (tmode = 0) table 11-2. rx demodulation scheme mode ask/_nfsk t_mode rf in bit in tx/rx data buffer level on pin sdo_tmdo rx 0 0 f fsk_l f fsk_h 1 x 0 f fsk_h f fsk_l 0 x 1 f fsk_h - 1 1 f fsk_l - 0 1 0 f ask off f ask on 1 x 0 f ask on f ask off 0 x 1 f ask on - 1 1 f ask off - 0 demod_out bit check ok preburst byte 2 lsb readable via 4-wire serial interface tx/rx data buffer msb byte 1 start bit t 2t '0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '1' '0' '0' '0' '0' '0' byte 14, byte 30, ... byte 13, byte 29, ... byte 10, byte 26, ... byte 9, byte 25, ... byte 8, byte 24, ... byte 3, byte 19, ... byte 1, byte 17, ... byte 2, byte 18, ... byte 4, byte 20, ... byte 5, byte 21, ... byte 6, byte 22, ... byte 7, byte 23, ... byte 11, byte 27, ... byte 12, byte 28, ... byte 16, byte 32, ... byte 15, byte 31, ... 11 1 1 10 0 1 11 0 0 00 0 0 '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0' bit-check mode receiving mode byte 3 demod_out bit-check ok byte n-1 byte 1 byte n+1 preburst byte n start-up mode bit-check mode receiving mode receiving mode bit error
55 ata5823/ata5824 [datasheet] 4829f?rke?05/14 11.1.8 recommended lim_min and li m_max for maximum sensitivity the sensitivity measurement in the section ?low-if receiver? on page 9 , in table 5-3 and table 5-4 on page 10 have been done with the lim_min and lim_max values according to table 11-3 . these values are optimized for maximum sensitivity. note that since these limits are optimized for sensitivity the number of checked bit n bit-check has to be at least 6 to prevent the circuit from waking up too often in polling mode due to noise. 11.2 tx operation the transceiver is set to tx operation by using the bi ts opm0, opm1 and opm2 in the control register 1. before activating the tx mode, the tx parameters (bit rate, modulation scheme...) must be selected as illustrated in figure 11-10 on page 56 . the bit rate depends on baud0 and baud1 in control register 6 and tx0 to tx5 in control register 7 (see section ?control register? on page 33 ). the modulation is selected with ask_nfsk in control register 4. the fsk frequency deviation is fixed to about 19khz (see table 6-1 on page 25 ). if p_mode is set to 1, the manchester modulator is disabled and pattern mode is active (nrz, see table 11-5 on page 58 ). after the transceiver is set to tx mode the start-up mode is ac tive and the pll is enabled. if the pll is locked, the tx mode is active. if the transceiver is in start-up or tx mode, the tx/rx data bu ffer can be loaded via the 4-wire serial interface. after n byte s are in the buffer and the tx mode is active, the transceiver st arts transmitting automatically (beginning with the msb). bit 0 to bit 4 in the command write tx/rx data buffer defines the value n (0 n 16; see section ?command structure? on page 45 ). while transmitting, it is permanently possible to load new data in the tx/rx data buffer. to prevent a buffer overflow or interruptions during transmitting the user must ensure that data is loaded at the same speed as it is transmitted. there is a counter that indicates the numbe r of bytes to be transmitted (see section ?transceiver configuration? on page 43 ). if a byte is loaded, the counter is increm ented, if a byte is transm itted, the counter is decreme nted. the counter value is available via the 4-wire serial interface. an irq is issued if the counter reaches t he value defined by the control bits ir0 an d ir1 in control register 1. note: writing to the control register 1, 4, 5, 6 or 7 dur ing tx mode, resets the tx/rx data buffer and the counter which indicates the number of bytes to be transmitted. if t_mode in control register 1 is set to 1, the transceiver is in tx transparent mode. in this mode the tx/rx data buffer is disabled and the tx data stream must be applied on pin sdi_tmdi. figure 11-10 on page 56 illustrates the flow chart of the tx transparent mode. table 11-3. recommended lim_min and lim_max values for different bit rates f rf (f xtal )/mhz 1.0kbit/s br_range_0 xlim = 1 2.4kbit/s br_range_0 xlim = 0 5kbit/s br_range_1 xlim = 0 10kbit/s br_range_2 xlim = 0 20kbit/s br_range_3 xlim = 0 315 (12.73193) lim_min = 13 (251s) lim_max = 38 (715s) lim_min = 12 (121s) lim_max = 34 (332s) lim_min = 11 (55s) lim_max = 32 (156s) lim_min = 11 (28s) lim_max = 32 (78s) lim_min = 11 (14s) lim_max = 32 (39s) 433.92 (13.25311) lim_min = 13 (251s) lim_max = 38 (715s) lim_min = 11 (106s) lim_max = 32 (299s) lim_min = 11 (53s) lim_max = 32 (150s) lim_min = 11 (27s) lim_max = 32 (75s) lim_min = 11 (13s) lim_max = 32 (37s) table 11-4. control register 1 opm2 opm1 opm0 function 0 0 1 tx mode
ata5823/ata5824 [datasheet] 4829f?rke?05/14 56 figure 11-10. tx operation (t_mode = 0) write tx/rx data buffer (max. 16 - number of bytes still in the tx/rx data buffer) write tx/rx data buffer (max. 16 byte) baud1, baud0: lim_max0 to lim_max5: select bit rate range don't care write control register 6 pout_select, pout_data: tx0 to tx5: application defined. select the bit rate write control register 7 bit_ck1, bit_ck0: lim_min0 to lim_min5: don?t care don't care write control register 5 set idle opm2, opm1, opm0: write control register 1 n y n y y n pin irq = 1 ? idle mode tx mode start-up mode (tx) idle mode command: delete_irq tx more data bytes ? fr7, fr8, fr9: clk_en, clk_on: adjust rf application defined. write control register 3 fr0 to fr6: p_mode: adjust rf enable or disable the manchester modulator write control register 2 ir1, ir0: pll_mode: fs: opm2, opm1, opm0: t_mode: select an event which activates an interrupt set pll_mode = 0 select operation frequency set opm2 = 0, opm1 = 0 and opm0 = 1 set t_mode = 0 write control register 1 ask/_nfsk: sleep0 to sleep4: xsleep: xlim: select modulation don't care don't care don?t care write control register 4 fe_mode: pwselect: pwset0 to pwset4: set fe_mode = 1 set pwselect = 1 to reduce the output power with setpwr adjust setpwr. don?t care if pwselect = 0. write control register 8 pin irq = 1 ? t startup = 331.5 t dclk
57 ata5823/ata5824 [datasheet] 4829f?rke?05/14 figure 11-11. tx transparent mode (t_mode = 1) baud1, baud0: lim_max0 to lim_max5: don't care don't care write control register 6 pout_select, pout_data: tx0 to tx5: application defined. don't care write control register 7 bit_ck1, bit_ck0: lim_min0 to lim_min5: don?t care don't care write control register 5 idle mode tx mode start-up mode (tx) idle mode fr7, fr8, fr9: clk_en, clk_on: adjust rf application defined. write control register 3 fr0 to fr6: p_mode: adjust rf don?t care write control register 2 ir1, ir0: pll_mode: fs: opm2, opm1, opm0: t_mode: don?t care set pll_mode = 0 select operation frequency set opm2 = 0, opm1 = 0 and opm0 = 1 set t_mode = 0 write control register 1 ask/_nfsk: sleep0 to sleep4: xsleep: xlim: select modulation don't care don't care don?t care write control register 4 fe_mode: pwselect: pwset0 to pwset4: set fe_mode = 1 set pwselect = 1 to reduce the output power with setpwr adjust setpwr. don?t care if pwselect = 0. write control register 8 t startup = 331.5 t dclk apply tx data on pin sdi_tmdi opm2, opm1, opm0: set idle write control register 1
ata5823/ata5824 [datasheet] 4829f?rke?05/14 58 11.3 interrupts via pin irq, the transceiver signals different operating conditi ons to a connected microcontrol ler. if a specific operating condition occurs, pin irq is set to a high level. if an interrupt occurs, it is recommended to delete the interrupt immediately by readi ng the status register, thus the next possible interrupt doesn?t get lost. if the interrupt pin doesn?t switch to a low level by reading the status register, the int errupt was triggered by the rx/tx data buffer. in this case , read or write the rx/tx data buffer according to table 11-6 . table 11-5. tx modulation schemes mode ask/_nfsk p_mode t_mode bit in tx/rx data buffer level on pin sdi_tmdi rf out tx 0 0 0 1 x f fsk_l f fsk_h 0 0 0 x f fsk_h f fsk_l 1 0 1 x f fsk_h 1 0 0 x f fsk_l x 1 x 1 f fsk_h x 1 x 0 f fsk_l 1 0 0 1 x f ask off f ask on 0 0 0 x f ask on f ask off 1 0 1 x f ask on 1 0 0 x f ask off x 1 x 1 f ask on x 1 x 0 f ask off table 11-6. interrupt handling operating conditions which sets pin irq to high level operations which sets pin irq to low level events in status register state transition of status bit n_power_on (0 1; 1 0) read status register or command delete irq appearance of status bit power_on (0 1) events during tx operation (t_mode = 0) 1, 2, 4 or 12 bytes are in the tx data buffer or the tx data buffer is empty (depends on ir0 and ir1 in control register 1) write tx data buffer or write control register 1 or write control register 4 or write control register 5 or write control register 6 or write control register 7 or command delete irq note: 1. during reading of the rx/tx buffer, no irq is issued, due to the received bytes or a receiving error.
59 ata5823/ata5824 [datasheet] 4829f?rke?05/14 events during rx operation (t_mode = 0) 1, 2, 4 or 12 received bytes are in the rx data buffer or a receiving error is occurred (depends on ir0 and ir1 in control register 1) read rx data buffer (1) or write control register 1 or write control register 4 or write control register 5 or write control register 6 or write control register 7 or command delete irq successful bit-check (p_mode = 0) events during fd operation tx data buffer empty read rx data buffer (1) or write control register 1 or write control register 4 or write control register 5 or write control register 6 or write control register 7 or command delete irq table 11-6. interrupt handling (continued) operating conditions which sets pin irq to high level operations which sets pin irq to low level note: 1. during reading of the rx/tx buffer, no irq is issued, due to the received bytes or a receiving error.
ata5823/ata5824 [datasheet] 4829f?rke?05/14 60 12. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol min. max. unit junction temperature t j 150 c storage temperature t stg ?55 +125 c ambient temperature t amb ?40 +105 c supply voltage vs2 v maxvs2 ?0.3 +7.2 v supply voltage vs1 v maxvs1 ?0.3 +4 v supply voltage vsint v maxvsint ?0.3 +5.5 v esd (human body model esd s.5.1) every pin hbm ?2.5 +2.5 kv esd (machine model jedec a115a) every pin mm ?200 +200 v esd (field induced charge device model esd stm 5.3.1-1999) every pin fcdm ?500 500 v maximum input level, input matched to 50 p in_max 10 dbm 13. thermal resistance parameters symbol value unit junction ambient r thja 25 k/w
61 ata5823/ata5824 [datasheet] 4829f?rke?05/14 14. electrical characteristics: general all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 =v vs2 =v vsint = 3v and t amb =25c, f rf = 433.92mhz (battery application) unless othe rwise specified. details about current co nsumption, timing and digital pin properti es can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* 1 rx_tx_idle mode 1.1 rf operating frequency range atmel ata5824 v 433_n868 =avcc 4, 10 f rf 433 435 mhz a ata5823 v 433_n868 =avcc 4, 10 f rf 314 316 mhz a 1.2 supply current off mode v vs1 =v vs2 =v vsint = 3v (battery) 17, 18, 27 i s_off <10 na a v vs2 =v vsint =5v (car) 17, 27 i s_off <10 na a 1.3 supply current idle mode xto running v vs1 =v vs2 =v vsint = 3v (battery) clk disabled 17, 18, 27 i s_idle 260 a b xto running v vs2 =v vsint =5v (car) clk disabled 17, 27 i s_idle 350 a b 1.4 system start-up time from off mode to idle mode including reset and xto start-up (see figure 9-4 on page 42 ) xtal: c m = 5ff, c 0 = 1.8pf, r m = 15 t pwr_on_irq_1 0.3 ms c 1.5 rx start-up time from idle mode to receiving mode n bit-check = 3 bit rate = 20kbit/s, br_range_3 (see figure 11-1 on page 49 and figure 11-2 on page 50 ) t startup_pll + t startup_sig_proc + t bit-check 1.39 ms a 1.6 tx start-up time from idle mode to tx mode (see figure 11-10 on page 56 ) t startup 0.4 ms a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 (rf in ) and rf_out matched to 50 according to figure 5-12 on page 20 with component values according to table 5-7 on page 20 (rf out ).
ata5823/ata5824 [datasheet] 4829f?rke?05/14 62 2 receiver/rx mode 2.1 supply current rx mode f rf = 433.92mhz and f rf = 315mhz 17, 18, 27 i s_rx 10.5 ma a 2.2 supply current rx polling mode t sleep = 49.45ms x sleep = 8, sleep = 5 bit rate = 20kbit/s fsk, clk disabled 17, 18, 27 i s_poll 484 a c 2.3 input sensitivity fsk f rf = 433.92mhz fsk deviation f dev = 19.5khz limits according to ta b l e 11 - 3 on page 55 , ber = 10 -3 t amb = 25c bit rate 20kbit/s (4) s ref_fsk ?103.5 ?105.5 ?107.0 dbm b bit rate 2.4kbit/s (4) s ref_fsk ?107.0 ?109.0 ?110.5 dbm b 2.4 input sensitivity ask f rf = 433.92mhz ask 100% level of carrier, limits according to ta b l e 11 - 3 on page 55 , ber = 10 -3 t amb = 25c bit rate 10kbit/s (4) p ref_ask ?109.5 ?111.5 ?113.0 dbm b bit rate 2.4kbit/s (4) p ref_ask ?113.5 ?115.5 ?117.0 dbm b 2.5 sensitivity change at f rf = 315mhz compared to f rf = 433.92mhz f rf = 433.92mhz to f rf = 315mhz f rf = 433.92mhz to s = s ref_ask + s ref1 s = s ref_fsk + s ref1 (4) s ref1 ?1.0 +2.7 db b 2.6 sensitivity change versus temperature, supply voltage and frequency offset fsk f dev = 19.5khz f offset 75khz ask 100% f offset 75khz s = s ref_ask + s ref1 + s ref2 s = s ref_fsk + s ref1 + s ref2 (4) s ref2 +4.5 ?1.5 b 14. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 =v vs2 =v vsint = 3v and t amb =25c, f rf = 433.92mhz (battery application) unless othe rwise specified. details about current co nsumption, timing and digital pin properti es can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 (rf in ) and rf_out matched to 50 according to figure 5-12 on page 20 with component values according to table 5-7 on page 20 (rf out ).
63 ata5823/ata5824 [datasheet] 4829f?rke?05/14 2.7 rssi output dynamic range (4), 36 d rssi 70 db a lower level of range f rf = 315mhz f rf = 433.92mhz (4), 36 p rfin_low ?116 ?115 dbm dbm a upper level of range f rf = 315 mhz f rf = 433.92 mhz (4), 36 p rfin_high ?46 ?45 dbm dbm a gain (4), 36 5.5 8.0 10.5 mv/db a output voltage range (4), 36 ov rssi 350 1100 mv a 2.8 output resistance rssi pin rx mode tx mode 36 r rssi 8 32 10 40 12.5 50 k c 2.9 maximum frequency offset in fsk mode maximum frequency difference of f rf between receiver and transmitter in fsk mode (f rf is the center frequency of the fsk signal with f dev = 19.5khz) p rf_in +10dbm p rf_in p rfin_high (see figure 5-2 on page 11 ) (4) f offset1 f offset2 ?69 ?75 +69 +75 khz b 2.10 supported fsk frequency deviation with up to 2db loss of sensitivity. note that the tolerable frequency offset is for f dev = 28khz, 8.5khz lower than for f dev = 19.5khz hence f offset2 = 66.5khz (4) f dev 14 19.5 28 khz b 2.11 system noise figure f rf = 315mhz (4) nf 5.5 db b f rf = 433.92mhz (4) nf 6.5 db b 2.12 intermediate frequency f rf = 315mhz f if 227 khz a f rf = 433.92mhz f if 223 khz a 2.13 system bandwidth this value is for information only! note that for crystal and system frequency offset calculations, f offset must be used. (4) sbw 220 khz a 2.14 system out-band 2 nd -order input intercept point with respect to f if f meas1 = 1.800mhz f meas2 = 2.026mhz f if = f meas2 ? f meas1 (4) iip2 +50 dbm c 14. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 =v vs2 =v vsint = 3v and t amb =25c, f rf = 433.92mhz (battery application) unless othe rwise specified. details about current co nsumption, timing and digital pin properti es can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 (rf in ) and rf_out matched to 50 according to figure 5-12 on page 20 with component values according to table 5-7 on page 20 (rf out ).
ata5823/ata5824 [datasheet] 4829f?rke?05/14 64 2.15 system outband 3 rd -order input intercept point f meas1 = 1.8mhz f meas2 = 3.6mhz f rf = 315mhz (4) iip3 ?22 dbm c f rf = 433.92mhz (4) iip3 ?21 dbm c 2.16 system outband input 1db compression point f meas1 = 10mhz f rf = 315mhz this values are for information only, for blocking behavior see figure 5-3 on page 13 to figure 5-7 on page 15 (4) i1dbcp ?31 dbm c f rf = 433.92mhz (4) i1dbcp ?30 dbm c 2.17 lna input impedance f rf = 315mhz 4 z in_lna (44 ? j233) c f rf = 433.92mhz 4 z in_lna (32 ? j169) c 2.18 allowable peak rf input level, ask and fsk ber < 10 -3 , ask: 100% (4) p in_max +10 ?10 dbm c fsk: f dev = 19.5khz (4) p in_max +10 ?10 dbm c 2.19 lo spurious at lna_in f < 1 ghz (4) ?57 dbm c f >1 ghz (4) ?47 dbm c f rf = 315mhz (4) ?100 dbm c f rf = 433.92mhz (4) ?98 dbm c 2.20 image rejection within the complete image band f rf = 315mhz (4) 25 30 db a f rf = 433.92mhz (4) 25 30 db a 2.21 useful signal to interferer ratio peak level of useful signal to peak level of interferer for ber < 10 -3 with any modulation scheme of interferer. fsk br_ranges 0, 1, 2 (4) snr fsk0-2 2 3 db b fsk br_range_3 (4) snr fsk3 4 6 db b ask (p rf < p rfin_high ) (4) snr ask 10 12 db b 2.22 maximum frequency offset in ask mode maximum frequency difference of f rf between receiver and transmitter in ask mode p rf_in +10dbm p rf_in p rf_in_high f offset1 f offset2 ?79 ?85 +79 +85 khz b 14. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 =v vs2 =v vsint = 3v and t amb =25c, f rf = 433.92mhz (battery application) unless othe rwise specified. details about current co nsumption, timing and digital pin properti es can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 (rf in ) and rf_out matched to 50 according to figure 5-12 on page 20 with component values according to table 5-7 on page 20 (rf out ).
65 ata5823/ata5824 [datasheet] 4829f?rke?05/14 2.23 blocking according to etsi regulations, the sensitivity (ber = 10 -3 ) is reduced by 3 db if a continuous wave blocking signal at f is p block higher than the useful signal level (bit rate = 20kbit/s, fsk, f dev 19.5khz, manchester code) f rf = 315mhz f 0.75mhz f 1.0mhz f 1.5mhz f 5.0mhz f 10.0mhz blocking behavior see figure 5-3 to figure 5-5 on page 13 (4) p block 55 57 60 66 73 dbc c f rf = 433.92mhz f 0.75mhz f 1.0mhz f 1.5mhz f 5.0mhz f 10.0mhz blocking behavior see figure 5-3 to figure 5-5 on page 13 (4) p block 54 56 59 65 67 dbc c 2.24 cdem capacitor connected to pin 37 (cdem) 37 ?5% 15 +5% nf d 3 power amplifier/tx mode 3.1 supply current tx mode power amplifier off f rf = 433.92mhz and f rf = 315mhz 17,18, 27 i s_tx_paoff 6.95 ma a 14. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 =v vs2 =v vsint = 3v and t amb =25c, f rf = 433.92mhz (battery application) unless othe rwise specified. details about current co nsumption, timing and digital pin properti es can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 (rf in ) and rf_out matched to 50 according to figure 5-12 on page 20 with component values according to table 5-7 on page 20 (rf out ).
ata5823/ata5824 [datasheet] 4829f?rke?05/14 66 3.2 output power 1 v vs1 = v vs2 = 3v t amb = 25c v pwr_h = gnd f rf = 315mhz r r_pwr = 56k r lopt = 2.5k f rf = 433.92mhz r r_pwr = 56k r lopt = 2.3k rf_out matched to r lopt // j/(2 f rf 1.0pf ) (10) p ref1 ?2.5 0 +2.5 dbm b 3.3 supply current tx mode power amplifier on 1 0dbm pa on/0dbm f rf = 315mhz 17, 18, 27 i s_tx_paon1 8.5 ma b f rf = 433.92mhz 17, 18, 27 i s_tx_paon1 8.6 ma b 3.4 output power 2 v vs1 = v vs2 = 3 v t amb = 25c v pwr_h = gnd f rf = 315mhz r r_pwr = 30k r lopt = 1.0k f rf = 433.92mhz r r_pwr = 27k r lopt = 1.1k rf_out matched to r lopt // j/(2 f rf 1.0pf ) (10) p ref2 3.5 5.0 6.5 dbm b 3.5 supply current tx mode power amplifier on 2 5dbm pa on/5dbm f rf = 315mhz 17, 18, 27 i s_tx_paon2 10.3 ma b f rf = 433.92mhz 17, 18, 27 i s_tx_paon2 10.5 ma b 14. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 =v vs2 =v vsint = 3v and t amb =25c, f rf = 433.92mhz (battery application) unless othe rwise specified. details about current co nsumption, timing and digital pin properti es can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 (rf in ) and rf_out matched to 50 according to figure 5-12 on page 20 with component values according to table 5-7 on page 20 (rf out ).
67 ata5823/ata5824 [datasheet] 4829f?rke?05/14 3.6 output power 3 v vs1 = v vs2 = 3v t amb = 25c v pwr_h = avcc f rf = 315mhz r r_pwr = 30k r lopt = 0.38k f rf = 433.92mhz r r_pwr = 27k r lopt = 0.36k rf_out matched to r lopt // j/(2 f rf 1.0pf ) (10) p ref3 8.5 10 11.5 dbm b 3.7 supply current tx mode power amplifier on 3 10dbm pa on/10dbm f rf = 315mhz 17, 18, 27 i s_tx_paon3 15.7 ma b f rf = 433.92mhz 17, 18, 27 i s_tx_paon3 15.8 ma b 3.8 output power variation for full temperature and supply voltage range t amb = ?40c to +105c p out = p refx + p ref x = 1, 2 or 3 v vs1 = v vs2 = 3.0v (10) p ref ?0.8 ?1.5 db b v vs1 = v vs2 = 2.7v (10) p ref ?2.5 db b v vs1 = v vs2 = 2.4v (10) p ref ?3.5 db c v vs1 = v vs2 = 2.15v (10) p ref ?4.5 db b 3.9 impedance rf_out in rx mode f rf = 315mhz 10 z rf_out_rx (36 ? j502) c f rf = 433.92mhz 10 z rf_out_rx (19 ? j366) c 3.10 noise floor power amplifier at 10mhz/at 5dbm f rf = 433.92mhz (10) l tx10m ?126 dbc/hz c f rf = 315mhz (10) l tx10m ?128 dbc/hz c 3.11 ask modulation rate this corresponds to 10kbit/s manchester coding and 20kbit/s nrz coding f data_ask 1 10 khz c 14. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 =v vs2 =v vsint = 3v and t amb =25c, f rf = 433.92mhz (battery application) unless othe rwise specified. details about current co nsumption, timing and digital pin properti es can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 (rf in ) and rf_out matched to 50 according to figure 5-12 on page 20 with component values according to table 5-7 on page 20 (rf out ).
ata5823/ata5824 [datasheet] 4829f?rke?05/14 68 5 xto 5.1 pulling xto due to xto, c l1 and c l2 tolerances pulling at nominal temperature and supply voltage f xtal = resonant frequency of the xtal c 0 1.0pf r m 120 24, 25 c m 7.0ff c m 14ff f xto1 ?50 ?100 f xtal +50 +100 ppm a 5.2 transconductance xto at start at start-up, after start-up the amplitude is regulated to v ppxtal 24, 25 g m, xto 19 ms b 5.3 xto start-up time c 0 2.2pf c m < 14ff r m 120 24, 25 t pwr_on_irq_1 300 800 s a 5.4 maximum c 0 of xtal required for stable operation with internal load capacitors 24, 25 c 0max 3.8 pf d 5.5 internal capacitors c l1 and c l2 24, 25 c l1 , c l2 14.8 18 pf 21.2 pf b 5.6 pulling of radio frequency f rf due to xto, c l1 and c l2 versus temperature and supply changes 1.0pf c 0 2.2pf c m = 14ff r m 120 pll adjusted with freq at nominal temperature and supply voltage 4, 10 f xto2 ?2 +2 ppm c 5.7 amplitude xtal after start-up c m = 5ff, c 0 = 1.8pf r m = 15 v(xtal1, xtal2) peak-to-peak value 24, 25 v ppxtal 700 mvpp c v(xtal1) peak-to-peak value 24 v ppxtal 350 mvpp c 5.8 real part of xto impedance at start-up c 0 2.2pf, small signal start impedance, this value is important for crystal oscillator startup 24, 25 re xto ?2000 ?1500 b 5.9 maximum series resistance r m of xtal after start-up c 0 2.2pf c m 14ff 24, 25 r m_max 15 120 b 5.10 nominal xtal load resonant frequency f rf = 433.92mhz f rf = 315mhz 24, 25 f xtal 13.25311 12.73193 mhz mhz d 14. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 =v vs2 =v vsint = 3v and t amb =25c, f rf = 433.92mhz (battery application) unless othe rwise specified. details about current co nsumption, timing and digital pin properti es can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 (rf in ) and rf_out matched to 50 according to figure 5-12 on page 20 with component values according to table 5-7 on page 20 (rf out ).
69 ata5823/ata5824 [datasheet] 4829f?rke?05/14 5.11 external clk frequency 30 f clk mhz d f rf = 433.92mhz clk division ratio = 3 clk has nominal 50% duty cycle 30 f clk 4.418 mhz d f rf = 315mhz clk division ratio = 3 clk has nominal 50% duty cycle 30 f clk 4.244 mhz d 5.12 dc voltage after start-up v dc (xtal1, xtal2) xto running (idle mode, rx mode and tx mode) 24, 25 v dcxto ?150 ?30 me c 6 programmable inter nal resistor setpwr 6.1 setpwr in tx- and fd mode setpwr = 800 + (31 ? pwset) 3k pwset = 16 (see table 9-25 on page 39 ) 19 setpwr 45.8 k b 6.2 tolerance of setpwr versus temperature and supply voltage range 19 setpwrtol ?20% 500 +20% 500 b 7 synthesizer 7.1 spurious tx mode at f clk , clk enabled f rf = 315mhz f rf = 433.92mhz sp tx ata5823/ata5824 [datasheet] 4829f?rke?05/14 70 7.4 phase noise at 1m rx mode f rf = 315mhz f rf = 433.92mhz l rx1m ?121 ?120 dbc/hz a 7.5 phase noise at 1m tx mode f rf = 315mhz f rf = 433.92mhz l tx1m ?113 ?111 dbc/hz a 7.6 phase noise at 10m rx mode noise floor l rx10m < ?132 dbc/hz b 7.7 loop bandwidth pll tx mode frequency where the absolute value loop gain is equal to 1 f loop_pll 70 khz b 7.8 frequency deviation tx mode f rf = 315mhz f rf = 433.92mhz f dev_tx 18.65 19.41 khz d 7.9 frequency resolution f rf = 315mhz f rf = 433.92mhz 4, 10 f step_pll 777.1 808.9 hz d 7.10 fsk modulation rate this corresponds to 20kbit/s manchester coding and 40kbit/s nrz coding f data_fsk 1 20 khz b 8 rx/tx switch 8.1 impedance rx mode rx mode, pin 38 with short connection to gnd , f rf = 0hz (dc) 39 z switch_rx 23000 a f rf = 315mhz 39 z switch_rx (11.3 ? j214) c f rf = 433.92mhz 39 z switch_rx (10.3 ? j153) c 8.2 impedance tx mode tx mode, pin 38 with short connection to gnd , f rf = 0hz (dc) 39 z switch_tx 5 a f rf = 315mhz 39 z switch_tx (4.8 + j3.2) c f rf = 433.92mhz 39 z switch_tx (4.5 + j4.3) c 14. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 =v vs2 =v vsint = 3v and t amb =25c, f rf = 433.92mhz (battery application) unless othe rwise specified. details about current co nsumption, timing and digital pin properti es can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 (rf in ) and rf_out matched to 50 according to figure 5-12 on page 20 with component values according to table 5-7 on page 20 (rf out ).
71 ata5823/ata5824 [datasheet] 4829f?rke?05/14 9 microcontroller interface 9.1 voltage range for microcontroller interface 27, 28, 29, 30, 31, 32, 33, 34, 35 2.15 5.25 v a 9.2 clk output rise and fall time f clk < 4.5mhz c l = 10pf c l = load capacitance on pin clk 2.15v v vsint 5.25v 20% to 80% v vsint 30 t rise t fall 20 20 30 30 ns ns b b 9.3 current consumption of the microcontroller interface clk enabled clk disabled c l = load capacitance on pin clk (all interface pins, except pin clk, are in stable conditions and unloaded) 27 i vsint <10a b 9.4 internal equivalent capacitance used for current calculation 30, 27 c clk 8 pf b 14. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v (car application). typical values are given at v vs1 =v vs2 =v vsint = 3v and t amb =25c, f rf = 433.92mhz (battery application) unless othe rwise specified. details about current co nsumption, timing and digital pin properti es can be found in the specific sections of the ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter note: 1. pin numbers in brackets mean they were measured with rf_in matched to 50 according to figure 5-1 on page 10 with component values according to table 5-2 on page 10 (rf in ) and rf_out matched to 50 according to figure 5-12 on page 20 with component values according to table 5-7 on page 20 (rf out ). i vsint c clk c l + () v vsint f xto 3 -------------------------------------------------------------------------- =
ata5823/ata5824 [datasheet] 4829f?rke?05/14 72 15. electrical characterist ic: battery application all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.15v to 3.6v typical values at v vs1 =v vs2 =3v and t amb = 25c. application according to figure 3-1 on page 7 . f rf = 315.0mhz/ 433.92mhz unle ss otherwise specified. microcontroller interface current i vsint has to be added. no. parameters test conditions pin symbol min. typ. max. unit type* 10 battery application 10.1 supported voltage range (every mode except high power tx mode) battery application pwr_h = gnd 17, 18 v vs1 , v vs2 2.15 3.6 v a 10.2 supported voltage range (high power tx mode) battery application pwr_h = avcc 17, 18 v vs1 , v vs2 2.7 3.6 v a 10.3 supply voltage for microcontroller interface 27 v vsint 2.15 5.25 v a 10.4 supply current off mode v vs1,2 =v vsint 3.6v i s_off = i off_vs1,2 + i off_vsint 17,18, 27 i s_off 2 350 na a 10.5 current in idle mode on pin vs1 and vs2 v vs1 =v vs2 3v clk enabled clk disabled 17, 18 i idle_vs1, 2 330 270 570 490 a a a b 10.6 supply current idle mode clk enabled 17, 18, 27 i s_idle i s_idle = i idle_vs1,2 + i vsint 10.7 current in rx mode on pin vs1and vs2 v vs1 = v vs2 3v 17, 18 i rx_vs1, 2 10.5 14 ma a 10.8 supply current rx mode clk enabled 17, 18, 27 i s_rx i s_rx = i rx_vs1, 2 + i vsint 10.9 current during t startup_pll on pin vs1 and vs2 v vs1 = v vs2 3v 17, 18 i startup_pll_vs1, 2 8.8 11.5 ma c 10.10 current in rx polling mode on pin vs1 and vs2 10.11 supply current rx polling mode 17, 18, 27 i s_poll i poll = i p + i vsint 10.12 current in tx mode on pin vs1 and vs2 v vs1 = v vs2 3v 315mhz/5dbm 315mhz/10dbm 433.92mhz/5dbm 433.92mhz/10dbm 17, 18 i tx_vs1_vs2 10.3 15.7 10.5 15.8 13.4 20.5 13.5 20.5 ma b 10.13 supply current tx mode 17, 18, 27 i s_tx i s_tx = i tx_vs1_vs 2 + i vsint *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter i idle_vs1,2 or i rx_vs1,2 or i startup_pll_vs1,2 or i tx_vs1,2 or i fd1,2_vs1,2 vs1 vs2 i poll i idle_v s 1,2 t s leep i startup_pll_vs1,2 t startup_pll i rx_vs1,2 t startup_sig_proc t bit check + () + + t sleep t startup_pll t startup_sig_proc t bitcheck ++ + ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------- ------------------------------ - =
73 ata5823/ata5824 [datasheet] 4829f?rke?05/14 16. electrical characteristics: car application all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs2 = 4.4v to 5.6v, v vsint = 4.4v to 5.25v. typical values at v vs2 = 5v and t amb = 25c. application according to figure 4-1 on page 8 . f rf = 315.0mhz/433.92mhz unless otherwise specified. microcontroller interface current i vsint has to be added. no. parameters test conditions pin symbol min. typ. max. unit type* 12 car application 12.1 supported voltage range car application 17 v vs2 4.4 5.6 v a 12.2 supply voltage for microcontroller- interface 27 v vsint 2.15 5.25 v a 12.3 supply current off mode v vs2 =v vsint 5.25vi s _off = i off_vs2 + i off_vsint 17,27 i s_off 0.5 6 a a 12.4 current in idle mode on pin vs2 v vs2 5v clk enabled clk disabled 17 i idle_vs2 430 360 600 520 a a a b 12.5 supply current idle mode clk enabled 17, 27 i s_idle i s_idle = i idle_vs2 + i vsint 12.6 current in rx mode on pin vs2 v vs2 = 5v 17 i rx_vs2 10.8 14.5 ma b 12.7 supply current rx mode clk enabled 17, 27 i s_rx i s_rx = i rx_vs2 + i vsint 12.8 current during t startup_pll on pin vs2 v vs2 = 5v 17 i startup_pll_vs2 9.1 12 ma c 12.9 current in rx polling mode on pin vs2 12.10 supply current rx polling mode 17, 27 i s_poll i s_poll = i poll + i vsint 12.11 current in tx mode on pin vs2 v vs2 = 5v 315mhz/5dbm 315mhz/10dbm 433.92mhz/5dbm 433.92mhz/10dbm 17 i tx_vs2 10.7 16.2 10.9 16.3 13.9 21.0 14.0 21.0 ma b 12.12 supply current tx mode 17, 27 i s_tx i s_tx = i tx_vs2 + i vsint *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter vs2 i idle_vs2 or i rx_vs2 or i startup_pll_vs2 or i tx_vs2 or i fd3,4_vs2 i poll "" i idle_vs2 t sleep i startup_pll_vs2 t startup_pll i rx_vs2 t startup_sig_proc t bit check + () + + t sleep t startup_pll t startup_sig_proc t bit check ++ + ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------ =
ata5823/ata5824 [datasheet] 4829f?rke?05/14 74 17. digital timing characteristics all parameters refer to gnd and are valid for t amb = ?40c to +105c. v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 =v vsint = 4.4v to 5.25v (car application), typical values at v vs1 =v vs2 =v vsint = 3v and t amb = 25c unless otherwise specified. no. parameters test conditions pin symbol min. typ. max. unit type* 14 basic clock cycle of the digital circuitry 14.1 basic clock cycle t dclk 16/f xto 16/f xto s a 14.2 extended basic clock cycle xlim = 0 br_range_0 br_range_1 br_range_2 br_range_3 xlim = 1 br_range_0 br_range_1 br_range_2 br_range_3 t xdclk 8 4 2 1 t dclk 16 8 4 2 t dclk 8 4 2 1 t dclk 16 8 4 2 t dclk s s a a 15 rx mode/rx polling mode 15.1 sleep time sleep and xsleep are defined in control register 4 t sleep sleep x sleep 1024 t dclk sleep x sleep 1024 t dclk ms a 15.2 start-up pll rx mode from idle mode t startup_pll 798.5 t dclk 798.5 t dclk s a 15.3 start-up signal processing br_range_0 br_range_1 br_range_2 br_range_3 t startup_sig_proc 930 546 354 258 t dclk 930 546 354 258 t dclk a 15.4 time for bit-check average time during polling. no rf signal applied. f signal = 1/(2 t ee ) signal data rate manchester (lim_min and lim_max up to 50% of t ee , see figure 11-3 on page 50 ) bit-check time for a valid input signal f signal n bit-check = 0 n bit-check = 3 n bit-check = 6 n bit-check = 9 t bit_check 3/f signal 6/f signal 9/f signal 1/f signal 3.5/f signal 6.5/f signal 9.5/f signal ms c *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
75 ata5823/ata5824 [datasheet] 4829f?rke?05/14 15.5 bit-rate range br_range = br_range0 br_range1 br_range2 br_range3 br_range 1.0 2.0 4.0 8.0 2.5 5.0 10.0 20.0 kbit/s a 15.6 minimum time period between edges at pin sdo_tmdo in rx transparent mode xlim = 0 br_range_0 br_range_1 br_range_2 br_range_3 xlim = 1 br_range_0 br_range_1 br_range_2 br_range_3 31 t data_min 10 t xdclk s a 15.7 edge-to-edge time period of the data signal for full sensitivity in rx mode br_range_0 br_range_1 br_range_2 br_range_3 t data 200 100 50 25 500 250 125 62.5 s b 16 tx mode 16.1 start-up time from idle mode t startup 331.5 t dclk 331.5 t dclk s a 17 configuration of the transceiver with 4-wire serial interface 17.1 cs set-up time to rising edge of sck 33, 35 t cs_setup 1.5 t dclk s a 17.2 sck cycle time 33 t cycle 2 s a 17.3 sdi_tmdi set-up time to rising edge of sck 32, 33 t setup 250 ns c 17.4 sdi_tmdi hold time from rising edge of sck 32, 33 t hold 250 ns c 17.5 sdo_tmdo enable time from rising edge of cs 31, 35 t out_enable 250 ns c 17.6 sdo_tmdo output delay from falling edge of sck c l = 10 pf 31, 35 t out_delay 250 ns c 17.7 sdo_tmdo disable time from falling edge of cs 31, 33 t out_disable 250 ns c 17.8 cs disable time period 35 t cs_disable 1.5 t dclk s a 17. digital timing characteristics (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c. v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 =v vsint = 4.4v to 5.25v (car application), typical values at v vs1 =v vs2 =v vsint = 3v and t amb = 25c unless otherwise specified. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata5823/ata5824 [datasheet] 4829f?rke?05/14 76 17.9 time period sck low to cs high 33, 35 t sck_setup1 250 ns c 17.10 time period sck low to cs low 33, 35 t sck_setup2 250 ns c 17.11 time period cs low to sck high 33, 35 t sck_hold 250 ns c 18 start time push button n_pwr_on and pwr_on timing of wake-up via pwr_on or n_pwr_on 18.1 pwr_on high to positive edge on pin irq ( figure 9-4 on page 42 ) from off mode to idle mode, applications according to figure 3-1 on page 7 , figure 4-1 on page 8 xtal: c m < 14ff (typ. 5ff) c 0 < 2.2pf (typ. 1.8pf) r m 120 (typ. 15 ) battery application c 1 = c 2 = c 3 = 68nf c 5 = c 7 = 10nf car application c 1 = c 3 = c 4 = 68nf c 2 = 2.2f c 5 = 10nf 29, 40 t pwr_on_irq_1 0.3 0.45 0.8 1.3 ms b 17. digital timing characteristics (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c. v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 =v vsint = 4.4v to 5.25v (car application), typical values at v vs1 =v vs2 =v vsint = 3v and t amb = 25c unless otherwise specified. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
77 ata5823/ata5824 [datasheet] 4829f?rke?05/14 18.2 pwr_on high to positive edge on pin irq ( figure 9-4 on page 42 ) from every mode except off mode 29, 40 t pwr_on_irq_2 2 t dclk s a 18.3 n_pwr_on low to positive edge on pin irq ( figure 9-2 on page 40 ) from off mode to idle mode, applications according to figure 3-1 on page 7 , figure 4-1 on page 8 xtal: c m < 14ff (typ 5ff) c 0 < 2.2pf (typ 1.8pf) r m 120 (typ 15 ) battery application c 1 = c 2 = 68nf c 3 = c 4 = 68nf c 5 = 10nf car application c 1 = c 4 = 68nf c 2 = c 3 = 2.2f c 5 = 10nf 29, 45 t n_pwr_on_irq 0.3 0.45 0.8 1.3 ms b 18.4 push button debounce time every mode except off mode 29, 45 t debounce 8195 t dclk 8195 t dclk s a 17. digital timing characteristics (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c. v vs1 = v vs2 = v vsint = 2.15v to 3.6v (battery application), and v vs2 =v vsint = 4.4v to 5.25v (car application), typical values at v vs1 =v vs2 =v vsint = 3v and t amb = 25c unless otherwise specified. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata5823/ata5824 [datasheet] 4829f?rke?05/14 78 18. digital port characteristics all parameter refer to gnd and valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.15v to 3.6v (battery application) and v vs2 = 4.4v to 5.25v (car application) typical values at v vs1 = v vs2 = 3v (battery application) and t amb = 25c unless otherwise specified. v vsint = 2.15v to 5.25v can be used independent from v vs1 and v vs2 in the case the microcontroller uses an different supply voltage. no. parameters test conditions pin symbol min. typ. max. unit type* 20 digital ports 20.1 cs input - low level input voltage v vsint = 2.15v to 5.25v 35 v il 0.2 v vsint v a - high level input voltage v vsint = 2.15v to 5.25v 35 v ih 0.8 v vsint v a 20.2 sck input - low level input voltage v vsint = 2.15v to 5.25v 33 v il 0.2 v vsint v a - high level input voltage v vsint = 2.15v to 5.25v 33 v ih 0.8 v vsint v a 20.3 sdi_tmdi input - low level input voltage v vsint = 2.15v to 5.25v 32 v il 0.2 v vsint v a - high level input voltage v vsint = 2.15v to 5.25v 32 v ih 0.8 v vsint v a 20.4 test1 input test1 input must always be directly connected to gnd 20 0 0 v 20.5 test2 input test2 input must always be direct connected to gnd 23 0 0 v 20.6 pwr_on input - low level input voltage v vsint = 2.15v to 5.25v 40 v il 0.2 v vsint v a - high level input voltage v vsint = 2.15v to 5.25v 40 v ih 0.8 v vsint v a 20.7 n_pwr_on input - low level input voltage v vsint = 2.15v to 5.25v internal pull-up resistor of 50k 20% 45 v il 0.2 v vsint v a - high level input voltage v vsint = 2.15v to 5.25v internal pull-up resistor of 50k 20% 45 v ih 0.8 v vsint v a 20.8 cs_pol input -low level input voltage 22 v il 0.2 v dvcc v a - high level input voltage 22 v ih 0.8 v dvcc v dvcc v a 20.9 sck_pol input - low level input voltage 43 v il 0.2 v dvcc v a - high level input voltage 43 v ih 0.8 v dvcc v dvcc v a 20.10 sck_pha input - low level input voltage 44 v il 0.2 v dvcc v a - high level input voltage 44 v ih 0.8 v dvcc v dvcc v a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
79 ata5823/ata5824 [datasheet] 4829f?rke?05/14 20.11 433_n868 input - low level input voltage 6 v il 0.25 v a - high level input voltage 6 v ih 1.7 avcc v a 20.12 pwr_h input - low level input voltage 9 v il 0.25 v a - high level input voltage 9 v ih 1.7 avcc v a 20.13 sdo_tmdo output - saturation voltage low v vsint = 2.15v to 5.25v i sdo_tmdo = 250a 31 v ol 0.15 0.4 v b - saturation voltage high v vsint = 2.15v to 5.25v i sdo_tmdo = ?250a 31 v oh v vsint ? 0.4 v vsint ? 0.15 v b 20.14 irq output - saturation voltage low v vsint = 2.15v to 5.25v i irq = 250a 29 v ol 0.15 0.4 v b - saturation voltage high v vsint = 2.15v to 5.25v i irq = ?250a 29 v oh v vsint ? 0.4 v vsint ? 0.15 v b 20.15 clk output - saturation voltage low v vsint = 2.15v to 5.25v i clk = 100a internal series resistor of 1k for spurious reduction in pll 30 v ol 0.15 0.4 v b - saturation voltage high v vsint = 2.15v to 5.25v i clk = ?100a internal series resistor of 1k for spurious reduction in pll 30 v oh v vsint ? 0.4 v vsint ? 0.15 v b 20.16 pout output - saturation voltage low v vsint = 2.15v to 5.25v i pout = 250a 28 v ol 0.15 0.4 v b pout output - saturation voltage low v vsint = 5v i pout = 1000a 28 v ol 0.4 0.6 v b pout output - saturation voltage high v vsint = 2.15v to 5.25v i pout = ?1500a 28 v oh v vsint ? 0.4 v vsint ? 0.15 v b 20.17 rx_active output - saturation voltage low i rx_active = 25a 46 v ol 0.25 0.4 v b rx_active output - saturation voltage high i rx_active = ?1500a 46 v oh v avcc ? 0.5 v avcc ? 0.15 v b 20.18 test3 output test3 output must always be directly connected to gnd 34 0 0 v 18. digital port characteristics (continued) all parameter refer to gnd and valid for t amb = ?40c to +105c, v vs1 = v vs2 = 2.15v to 3.6v (battery application) and v vs2 = 4.4v to 5.25v (car application) typical values at v vs1 = v vs2 = 3v (battery application) and t amb = 25c unless otherwise specified. v vsint = 2.15v to 5.25v can be used independent from v vs1 and v vs2 in the case the microcontroller uses an different supply voltage. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata5823/ata5824 [datasheet] 4829f?rke?05/14 80 20. package information 19. ordering information extended type number package remarks ata5823c-plqw qfn48 7mm x 7mm, pb-free ata5824c-plqw qfn48 7mm x 7mm, pb-free package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6.543-5089.02-4 1 01/14/03 package: qfn48_7x7 exposed pad 5.1x5.1 0.4 0.1 7 5.5 5.1 0.5 nom. 48 12 1 48 37 13 24 25 36 12 1 not indicated tolerances 0.05 0.23 0.05 -0.05 1 max. +0 specifications according to din technical drawings dimensions in mm
81 ata5823/ata5824 [datasheet] 4829f?rke?05/14 21. revision history please note that the following page numbers re ferred to in this section re fer to the specific revision mentioned, not to this document. revision no. history 4829f-rke-05/14 ? removal of the 868mhz option and the full-duplex operation mode 4829e-rke-07/13 ? section 22 ?ordering information? on page 93 updated 4829d-rke-06/06 ? put datasheet in a new template ? kbaud replaced through kbit/s ? baud replaced through bit ? table 14-8 ?interrupt handling? on page 70 changed
x x xx x x atmel corporation 1600 technology drive, san jose, ca 95110 usa t: (+1)(408) 441.0311 f: (+1)(408) 436.4200 | www.atmel.com ? 2014 atmel corporation. / rev.: rev.: 4829f?rke?05/14 atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , and others are registered trademarks or trademarks of atmel corporation in u.s. and other countries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in c onnection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and condit ions of sales located on the atmel website, atmel assumes no liability wh atsoever and disclaims any express, implied or statutory warranty relating to its p roducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, pu nitive, special or incidental damages (including, without limi tation, damages for loss and profits, business interruption, or loss of information ) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no r epresentations or warranties with respect to the accuracy or c ompleteness of the contents of this document and reserves the right to make changes to specificatio ns and products descriptions at any time without notice. atmel d oes not make any commitment to update the information contained herein. unless specifically provided otherwise, atme l products are not suitable for, and shall not be used in, automo tive applications. atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. safety-critical, military, and automotive applications disclaim er: atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to re sult in significant personal inju ry or death (?safety-critical a pplications?) without an atmel officer's specific written consent. safety-critical applications incl ude, without limitation, life support devices and systems, equipment or systems for t he operation of nuclear facilities and weapons systems. atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by atmel as military-grade. atmel products are not designed nor intended for use in automot ive applications unless spec ifically designated by atmel as automotive-grade.

▲Up To Search▲

Price & Availability of ATA5823-14

	To Download ATA5823-14 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .