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april 2013 doc id 023929 rev 1 1/23 AN4205 application note ac/dc converter to drive leds with mixed linear and switching regulation by vittorio giuffrida introduction the most recent developments in energy savings fit perfectly with led lighting as leds have an almost unlimited operating life and a smaller size as well as better efficiency when compared to their incandescent counterparts. nowadays these advantages make the use of led lighting very attractive, but the higher cost is delaying widespread introduction in the lighting market. in this context an led lighting driver has been designed in order to offer a cheap board in the consumer market. the ac/dc converter for led lighting acts on linear regulation to control the led current and on the switching regulation to minimize the power losses. in particular this application note presents the design guidelines of a 7 w led driver. the solution lies in the output stage that implements a simple circuit able to keep the led current constant and at same time to keep down the power losses in the power mosfet that works in the linear zone. www.st.com
contents AN4205 2/23 doc id 023929 rev 1 contents 1 system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 input stage of the ac/dc converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 flyback transformer design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 output capacitor selection and post filter . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.3 clamp circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 uc3842 driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 overvoltage protection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 output stage description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 output stage setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 switching regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AN4205 list of figures doc id 023929 rev 1 3/23 list of figures figure 1. electrical schematic of ac/dc converter for l.e.d. lighting . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. input stage of ac/dc converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. details of the power mosfet drain voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. c out and output post filter for ripple reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. clamp circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. uc3842 pwm driver and network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. deal time vs c9 (r5>5k). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. time resistance vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. over voltage protection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. electrical schematic of the double regulation (output stage) . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. i c 1 setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 12. the operating point of power mosfet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 13. details of switching regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14. the main waveforms of the current linear regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 15. the main signals of output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
system description AN4205 4/23 doc id 023929 rev 1 1 system description figure 1. electrical schematic of ac/dc converter for led lighting the ac/dc converter system is divided mainly into two sections, the input stage and the output stage. the input stage consists of a flyback topology able to transfer the energy to the secondary stage and to fix the output voltage. the output stage implements mixed linear regulation of the led and switching current in order to decrease the power losses during linear current control. ac 3 6 5 4 8 1 2 7 uc3842 + - + - fly-back topology pwm driver over voltage protection output stage l.e.d.s am16367v1
AN4205 input stage of the ac/dc converter doc id 023929 rev 1 5/23 2 input stage of the ac/dc converter figure 2. input stage of ac/dc converter the input stage consists of a flyback topology where the main active elements are the standard std3nk80z power mosfet device and the reliable uc3842 pwm driver. as a power conversion topology, the flyback has been chosen because the control is easier, it's cheap and doesn't need an inductive input filter. in fact the main transformer works as an inductive filter itself. therefore, the properties of the flyback meet the cost saving target of this project. next, the specifications and the design of the input stage will be shown. the first step is to define the specifications that the user must set for the ac/dc converter. the flyback operation, with reference to the basic circuit in figure 2 , is a two-step process. the first step is the on-time of the switch, where the energy is taken from the input and stored in the primary winding of the flyback transformer. at the secondary stage, the diode is reverse-biased and the load is supplied by the energy of the bulk capacitor. then the switch turns off (off-time) and the energy stored in the primary is transferred to the transformer secondary. so through the diode, forward-biased, the stored energy is delivered to the out capacitor. the output voltage v out is reflected back to the primary through the transformer table 1. input stage specifications data name symbol value minimum dc input voltage v dcmin 250 v maximum dc input voltage v dcmax 370 v dc output voltage v bus ~19 v output power p out ~7 w electrical efficiency 80% switching frequency f s 100 khz ac 3 6 5 4 8 1 2 7 uc3842 + - fly-back topology pwm driver input stage b ri d ge c1 r1 c2 c3 c4 c5 c 6 c8 c7 c9 c10 c11 r2 r3 r4 r5 r6 r8 r9 r7 d3 dz1 d1 d2 d4 d5 l1 t1 m1 am16368v1
input stage of the ac/dc converter AN4205 6/23 doc id 023929 rev 1 ratio and adds to the input voltage v in , giving a much higher voltage on the drain of the power mosfet. equation 1 before starting the design of the converter, some parameters need to be set. figure 3. details of the power mosfet drain voltage the drain voltage of the power mosfet device is: equation 2 the v fl reflected voltage depends on a proper n p /n s transformer ratio. in particular the maximum voltage rating of the power mosfet and the v r reverse voltage across the output diode relates to this transformer ratio. a lower n p /n s requires a higher v r on the diode, while v ds of the power mosfet is decreased. however, a higher transformer ratio implies a higher voltage stress on the power mosfet, while v r is decreased. the v spike leakage inductance overvoltage is due to energy stored in the mutual inductance of the transformer primary side which is not completely transferred to the secondary. when the leakage inductance is demagnetized, the energy can be transferred to the secondary. in order to minimize this delay, the voltage across the primary inductance should be as high as possible. the v margin should be 20% of the v dss of the power mosfet device. in accordance with these explanations we have chosen: v spike =160 v v margin =160 v hence, a device with v dss = 800 v (std3nk80z) has been chosen. this selection will allow using a clamp circuit with a lower operation time and having a safety margin around the voltage rating on the drain pin. v fl v out v diode + () n p n s ------ - = vds t vin vdsmin vdss vr vr llk & cd lp & cd am16369v1 v dss v in v fl v spike v min arg ++ + =
AN4205 input stage of the ac/dc converter doc id 023929 rev 1 7/23 equation 3 therefore, from equation 1 we can easily calculate the transformer ratio. equation 4 the other step is to ensure that the energy on the primary coil will be completely transferred to the secondary before the next cycle occurs. t on is the time during which the power mosfet operates, t reset is the time to demagnetize the transformer inductance (power mosfet is off) and t s is the switching time. the next formula gives a safe margin in order to demagnetize the primary side. equation 5 combining equation 2 and equation 3 results in: equation 6 the next step is to calculate the current peak. the output power is set to 7 w and the efficiency to 80% and using an approximate formula, we have: equation 7 therefore: equation 8 now we can calculate the peak current on the primary and on the secondary: equation 9 equation 10 v fl v dss v dcmax ? v spike ? v min arg 110v ? ? = n p n s ------- v dss v dcmax ? v spike ? v min arg ? v out v f diode , ? ----------------------------------------------------------------------------------------- - 800 370 ? 160 ? 160 ? 19 1 + --------------------------------------------------------- - 5.5 === t on t reset t s < + t on t reset 0.8t s = + t onmax v fl 0.8t s v dcmin v fl + -------------------------------- - 2.4 s == p in p out 0.8 -------------- l p i p 2t s ----------- - v dcmin t onmax 2l p t s ---------------------------------------- - === 2 2 2 l p v dcmin t onmax 2.5t s p out ---------------------------------------- - 2mh ? = 2 2 i p peak , v dcmin t onmax l p ---------------------------------------- - 300ma == i s peak , i p n p n s ------- 1.65a ==
input stage of the ac/dc converter AN4205 8/23 doc id 023929 rev 1 then the value of the i rms current must be determined: equation 11 equation 12 2.1 flyback transformer design the transformer design mainly consists of fixing the magnetic core, its geometry and the exact number of primary turns. the standard soft ferrite with gapped core and e-type geometry is a common choice for flyback topology because it is low cost and suitable for low/medium power applications. for this project e16/8/5 n87 material has been chosen. first the power losses of the ferrite with regard to the maximum magnetic flux bmax must be determined. from the datasheet of the n87 material, the dynamic magnetization curve shows that bmax = 380 mt (@ t=100 c) but we impose a bmax = 200 mt to have a safety margin. so, knowing the switching frequency (f s =100 khz) and the magnetic flux, we can determine the relative core losses ( referring to the datasheet of n87, see the figure "relative core losses versus frequency"): therefore the power losses of the ferrite are: equation 13 where v e =0.75 cm 3 is the total volume of the core. knowing that the thermal resistance r th of the selected core is 65 c/w, we have: equation 14 this result provides the thermal condition regarding the hypothesis of bmax. next we have to add the power losses due to the winding. now the number of primary turns must be calculated. equation 15 where a min = 19.4 mm2 is the minimum area of ferrite. i prms i p 3 ------ - t onmax t s -------------------- - 85ma ? = i srms i s peak , 3 ------------------ t reset t s --------------- 713ma ? = p v 400mw cm 3 ? = p fe p v v e = p fe p v v e 0.75 400 ? 300mw == = p fe t r th -------- = t19.5 c = n p v dcmin t onmax b max a min ---------------------------------------- - =
AN4205 input stage of the ac/dc converter doc id 023929 rev 1 9/23 from equation 4 , we can determine the number of secondary turns: we can also calculate the auxiliary needed to supply the driver. the driver used is the uc3842 which is driven by 15 v. equation 16 the next step is to determine the air gap length (l g ) of the core and the inductance of a single turn (a l ). knowing the primary inductance, the inductance of a single turn can be calculated: equation 17 in this case we chose the standard value a l =100 nh. now the air gap length is known: equation 18 from the datasheet of the core k1 = 42.2 and k2 = -0.701 before proceeding to calculate the wire dimension, we can verify if the selected core is acceptable (safety condition) with regard to thermal operation. using ampere's law we can calculate the b field: equation 19 the magnetic permeability fe is much higher than 0 (the magnetic permeability in the air), so we can neglect the last term in equation 19 . equation 20 this result confirms the accuracy of the hypothesis about bmax. n p 155 () ------------ - v fl v aux v f diode , + ----------------------------------------- 100 15 1 + --------------- - 6.25 === n aux 25 = l p n p a l = a l l p n p ------- 85nh == 2 2 l g a l k 1 ------ ?? ?? 1k 2 ? = l g 0.3mm = n p i p hdl ? h i l i h g l g h fe l fe + b 0 ----- - l g b fe ------- l fe + === = n p i p b 0 ----- - l g = b194mt =
input stage of the ac/dc converter AN4205 10/23 doc id 023929 rev 1 in order to calculate the wire dimension, we have to impose the maximum losses on the copper. in this case we choose a dissipation level similar to the one of the core (p fe ) plus a safety margin, for practical purposes we have chosen 0.5 w. now we assume that the primary and secondary winding losses are half of the selected total power: p cuprimary = 0.25 w, p cusecondary = 0.25 w from joule?s law, we have: equation 21 equation 22 knowing the copper resistivity at 100 c ( 100=2.303*10-6 cm) and the average winding length (l t =3.4 cm, from the datasheet of the core), we have: equation 23 equation 24 therefore, the diameter of the wire is: equation 25 equation 26 in accordance with the above specifications, the final transformer has been provided by magnetica. the following table summarizes the most important parameters of this transformer. p cuprimary r p i prms , r p 35 ? = 2 p cu ondary sec r s i prms , r s 0.5 ? = 2 a pcu 100 n p l t r p ------------------------ 3.46 10 05 ? cm 2 ? == a scu 100 n s l t r s ------------------------ 4.5 10 04 ? cm 2 ? == d p 6.6 10 03 ? cm ? = d s 23.4 10 03 ? cm ? =
AN4205 input stage of the ac/dc converter doc id 023929 rev 1 11/23 2.2 output capacitor selection and post filter the ac current in the output capacitor causes power dissipation on its series resistance (esr), resulting in a rise in temperature. thus, it is important to not operate the output capacitor beyond its ac current ripple rating, otherwise its lifetime will be very short. in general, a low esr capacitor is a good choice as it provides excellent energy storage and improves the transient performance. for this project the requirement on esr is very tight, so we have used a c out output capacitor and an l c post filter, like the one shown in figure 4 that attenuates the ripple to the desired level. figure 4. c out and output post filter for ripple reduction in this case we have chosen a capacitor supplier with: equation 27 since we want v ripple ~0.4 v (2% of v out =20 v), hence: equation 28 therefore, table 2. key transformer characteristics name symbol value inductance l primary 2.18 mh 15% l secondary 93 h 15% l auxiliary 35 h 15% transformer ratio n p /n s 4.85 leakage inductance l leakage 3.5% nom parasitic capacitance c parasitic 38 pf saturation current i sat 0.45 a max switching frequency f s 100 khz l1 c6 c5 d5 stth2r02u am16370v1 esr c ? 32 10 06 ? s ? = esr ripple v ripple i s peak , ------------------ 0.24 == c out 32 10 ? 06 ? esr -------------------------- - 135 f =
input stage of the ac/dc converter AN4205 12/23 doc id 023929 rev 1 the choice of the correct size of the post filter has been an iterative process that has required some trials before finding the optimal level of the desired ripple. 2.3 clamp circuit figure 5. clamp circuit the drain pin of the power mosfet device (std3nk80z) has to be properly clamped to prevent a spike due to the transformer leakage inductance from exceeding the breakdown voltage. an rcd clamp is a cheap solution but it dissipates power. therefore we have preferred to use a zener or transil? clamp which is recommended to minimize the power losses during the power mosfet commutation. imposing a safety margin of 15%, we have: equation 29 hence: in accordance with this specification the transil? is stp6ke300a. clamp circuit dz1 d1 t1 m1 r3 am16371v1 v zener v dcmax v dss 15 ? = + % v dss v zener 300v ?
AN4205 input stage of the ac/dc converter doc id 023929 rev 1 13/23 2.4 uc3842 driver a simple pwm driver has been chosen to drive the gate of the std3nk80z device and direct the flyback topology requested by the converter. the driver is the common uc3842 and it provides all the essential features necessary to the operation of the basic current mode controller. the uc3842 needs 15 v for its correct biasing and this voltage reference is supplied by the auxiliary output of the transformer. figure 6. uc3842 pwm driver and network the next step is to design the network for the pwm driver pins. the first step is to determine the required circuit dead time in order to select the oscillator components. once obtained, figure 7 is used to pinpoint the nearest standard value of c9. next, the appropriate r5 value is interpolated using the parameters for c9 and oscillator frequency. figure 8 illustrates the r5/c9 combinations versus oscillator frequency. 3 6 5 4 8 1 2 7 uc3842 + - pwm driver r1 c2 c3 c4 c8 c7 c9 c10 c11 r2 r3 r4 r5 r6 r8 r9 r7 d3 d2 d4 m1 am16372v1 figure 7. dead time vs. c9 (r5>5k) figure 8. time resistance vs. frequency 0.3 1 3 10 30 12.24.7102247100 td=(us) c9=(nf) am16373v1 3 10 30 100 100 1k 10k 100k 10m r5 (ko) frequency (hz) am16374v1
input stage of the ac/dc converter AN4205 14/23 doc id 023929 rev 1 the timing resistor can be calculated from the following formula: equation 30 the uc3842 current sensing input is done externally with ground-referenced resistor r3. under normal operation the peak voltage across r3 is controlled by the error amplifier according to the following formula: equation 31 where v c = e/a output voltage. the next step is the error amplifier (e/a) configuration. the r6, r7 and c7 error amplifier compensation circuit is chosen in order to ensure converter stability while providing good dynamic response. 2.5 overvoltage protection circuit figure 9. overvoltage protection circuit the overvoltage protection circuit is required in order to not damage the led lamps. it is connected between the output and ground. the zener diode voltage has been chosen to be slightly above that of the output voltage. when the zener diode voltage is reached, current flows into the resistor and as soon as the voltage, through the diode, exceeds one of the internal silicon diodes (1 v) of the uc3842 driver, the pwm is stopped. in this way the voltage across the output capacitor decreases. when the input of the error amplifier of uc3842 is lower than 2.5 v (internal reference voltage), the pwm restarts. so this overvoltage protection circuit temporarily stops the pwm driver, but it ensures system operation as soon as the condition of the error amplifier is reached. f osc khz () 1.72 r5 k () c9 f () ? ------------------------------------------ = i p peak , v c 1.4v ? 3r s ------------------------- - = 3 6 5 4 8 1 2 7 uc38 42 dz3 d6 r17 vbus am16375v1
AN4205 output stage description doc id 023929 rev 1 15/23 3 output stage description figure 10. electrical schematic of the double regulation (output stage) the solution, shown in figure 10 , performs the linear regulation of the current of the leds and the switching regulation which adjusts the v ds voltage of the power mosfet (m2) device in order to decrease the power losses during the linear regulation. this last result is the main feature of this solution because it compensates for the cost of efficiency due to standard linear regulation. the voltage control depends on the switching regulation that first reads the v ds voltage of power mosfet in series to the led components and then controls the out voltage (v bus ) in order to minimize v ds . this feature allows power losses lower than those of typical linear regulation and very low voltage ripple across led components. the linear regulation of the current consists of a bipolar device which, connected to the power mosfet gate, controls the v gs voltage so that this power mosfet operates in the linear region. so the i ds current and the current of the leds are regulated very well. + - vcc vbus input switching control mosfet m2 bipolar q 1 leds output switching control r2 r1 r3 r19 r4 r6 r5 c8 dz3 am16376v1
output stage setting AN4205 16/23 doc id 023929 rev 1 4 output stage setting the goals of this output stage of the led driver are the constant current on the led components and low power losses during the linear regulation. next, the setting and the project of the output stage will be shown. the first step is to define the output stage specifications that the user must set for the innovative led driver. the bipolar device (q1), connected to the power mosfet gate ( figure 10 ), controls the v gs voltage and consequently the i ds current using the following formula: equation 32 in order to perform the linear regulation, the bipolar q1 operates in forward active mode (common emitter), therefore for small base current variations, the emitter-collector voltage changes depending on the h fe parameter of the transistor. the collector variations cause a negative feedback. if the base voltage of the bipolar implies a rise in the collector voltage, the gate of the power mosfet decreases because the emitter node is fixed by the zener device, vice versa if the collector voltage decreases. the base current variations depend on the i out (i ds ) current through the voltage, across the r2 sensing resistor, which is boosted by the i c 1 amplifier. the i c 1 setting guarantees the forward active mode operation of the bipolar. table 3. output stage specifications data name symbol value light emitter diode led 6 leds of 3.2 v & 1.2 w dc output current i out (i ds ) 350 ma dc output voltage v bus 19 v mosfet drain-source voltage v ds 300 mv output voltage p out 7 w i ds kv gs v th ? () 2 ? 1 v ds + () ? =
AN4205 output stage setting doc id 023929 rev 1 17/23 figure 11. i c 1 setting the bipolar q1, operating in forward active mode, guarantees the linear region for the power mosfet device and so the linear regulation of the i ds (i out ) current can occur thanks to equation 1 . the q1 transistor is basically a common-emitter amplifier where the base terminal serves as the input and the collector terminal as the output. the voltage gain depends on the r1/r3 resistors and on the transconductance g m . the r1 resistor in figure 10 and the vz voltage of dz3 zener fix the collector variations in function of the v eb voltage and consequently determine the peak-to-peak amplitude of the regulation signal. on the other hand, the r3 and r19 resistors in figure 10 set the feedback time of the bipolar q1 and power mosfet m2. to s u m m a r i ze , figure 12 clarifies the linear current regulation of this simple and innovative solution. + - vcc r4 r6 r5 r2 c8 8 . 41 ) 2 . 1 49 1 ( ) 1 ( 4 6 2 ? + = + = k k r r g v mv v g v r o 1 . 5 120 * 8 . 41 2 2 ? = = 2 r v o v am16377v1 v ec v eb --------- g m r eq =
output stage setting AN4205 18/23 doc id 023929 rev 1 figure 12. operating point of the power mosfet 4.1 switching regulation the switching regulation adjusts the v ds voltage of the power mosfet (m2) device in order to decrease the power losses during the linear regulation. in particular this type of regulation first reads the v ds voltage of the power mosfet in series to the led components and then controls the out voltage (v bus ) in order to fix v ds in order to minimize the power losses in the power transistor. when the v ds voltage reaches the maximum threshold (fixed by the specification), the i ds (i out ) current has already reached the 350 ma value, thus triggering the switching regulation. vds t ids(iout) t ids=350ma vds=300 mv v gs =2. 2 v vgs t vds [v] ids(iout) [a] am16378v1
AN4205 output stage setting doc id 023929 rev 1 19/23 figure 13. details of switching regulation the v ds signal is processed by an operational amplifier (a.o.) and is then sent to the ?non- inverting input? of the ?uc3842? driver, which decides the state of the power mosfet m1 put in a flyback topology figure 13 . if the v ds value is greater than the threshold (fixed by specification), the "uc3842" driver stops the pwm regulation and the output voltage decreases, vice versa the pwm regulation starts again. the main advantages for processing the v ds signal rather than the v bus as in other standard linear regulation systems, are listed as follows: 1. to keep the ripple output voltage low 2. to fix the average value of the v ds voltage in order to minimize the power losses of the power transistor 3. to guarantee the v ds value lower than the threshold even if one or more led components are short rs 3 6 5 4 8 1 2 7 uc3 842 + - vcc + - vcc vbus input switching control mosfet m2 bipolar q 1 leds output switching control r2 r1 r3 r19 r4 r6 r5 c8 dz3 mosfet m1 am16379v1
test results AN4205 20/23 doc id 023929 rev 1 5 test results to verify the validity of this innovative solution, a prototype of an ac/dc converter driver of leds has been built and tested. the following test results show the main advantages of the linear current regulation and the switching regulation. figure 14. main waveforms of the linear current regulation am16380v1
AN4205 test results doc id 023929 rev 1 21/23 figure 15. main signals of the output stage figure 14 shows the details of the linear current regulation. when the value of v b (base voltage of bipolar q1) rises, v gs of the power mosfet m2 decreases and the i ds (i out ) current decreases. that allows fixing the current variations to approximately 350 ma. figure 15 shows the features of the output stage main signals. the i out ripple current (red waveform) is very low and the v ds average value is around the voltage threshold fixed by specification: targeting higher energy conservation, the main features of the led driver result in an almost constant i ds (i out ) current, ensuring a very long lifetime for the led components and a regulated v ds signal in order to minimize the power losses during linear regulation which is the most important feature of the led driver because it compensates for the cost of efficiency of the standard. am16381v1 v ds average () v dground vr2 300mv ? =
revision history AN4205 22/23 doc id 023929 rev 1 6 revision history table 4. document revision history date revision changes 19-apr-2013 1 initial release.
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