KL5KUSB102 ?one chip?- usb to ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 1 ver. 2.0 preliminary general description the KL5KUSB102 design provides the smallest available solution for connectivity between usb and ethernet with phy. this has been accomplished by its highly integrated functionality. the usb controller consists of a central 16-bit processor, mask rom, ram buffer, clock generator, ethernet interface, uart, irq, watchdog timer, serial interface, sram and phy. the sie (serial interface engine) is fully compatible with the usb specification. this usb to ethernet controller is ideal for lan (local area network), han (home area network), cable modem, set top boxes, or mobile networking applications. features advanced 16 bit processor for usb transaction processing and control data processing usb interface ver. 1.0/1.1 compliant transceivers and sie (serial interface engine) internal clock generation utilizes low cost external crystal circuitry internal ram buffer serial interface for external eeprom one chip solution includes ethernet mac, sram, and phy. phy for 10base-t. watchdog timer fully ieee 802.3 compliant 10 mbit/sec ethernet mac layer. uart 100 pin lqfp package block diagram 10mb/s ethernet interface ram timer 0 usb interface 16 bit address / data bus data - data + serial interface engine mask rom (8kb) timer 1 watchdog timer 16 bit processor uart txd rxd eeprom serial interface dio ck sram x2 x1 pll & clock generator irq int 1-0 2 10mb/s ethernet phy 8 tpon tpip tpop tpin 4 led signals
KL5KUSB102 ?one chip?- usb to ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 2 ver. 2.0 preliminary KL5KUSB102 application block diagram pin diagram 100qfp serial eeprom KL5KUSB102 usb / ethernet transformer usb full duplex 10 base ? t ethernet pllen ntst xd_0 xd_1 xd_2 xd_3 xd_4 xd_5 gnd xd_6 xd_7 vdd xd_8 xd_9 xd_10 xd_11 xd_12 gnd xd_13 xd_14 xd_15 gpio10 gpio11 txd vdd vdd rxd ledlink ledr ledt ledcol pu#1 gnd scl sda led_on npdn gnd phyclk_i phyclk_o iref avdd agnd atst2 atst1 atst0 gnd rxdn rxdp vdd vdd xa_2 xa_1 nxrom _sel nxwr nxrd nxram _sel nxbhe xa_0 xa_14 xa_15 test gnd test gpio8 gpio6 gpio7 gpio5 gpio9 gnd txdn txdp vdd gnd vdd gnd vm vp vdd vdd cp_out vco_in gnd x2 clk gnd nreset xa_13 xa_12 xa_11 xa_10 xa_9 xa_8 xa_7 xa_6 xa_5 gnd xa_4 xa_3 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 KL5KUSB102_l
KL5KUSB102 ?one chip?- usb to ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 3 ver. 2.0 preliminary pin description pin # qfp i/o pin name description 1 in pllen pll enable 2 in ntst test pin (active low) 3 in/out xd_0 external data pin 4 in/out xd_1 external data pin 5 in/out xd_2 external data pin 6 in/out xd_3 external data pin 7 in/out xd_4 external data pin 8 in/out xd_5 external data pin 9 gnd ground 10 in/out xd_6 external data pin 11 in/out xd_7 external data pin 12 - vdd supply voltage 13 in/out xd_8 external data pin 14 in/out xd_9 external data pin 15 in/out xd_10 external data pin 16 in/out xd_11 external data pin 17 in/out xd_12 external data pin 18 - gnd ground 19 in/out xd_13 external data pin 20 in/out xd_14 external data pin 21 in/out xd_15 external data pin 22 in/out gpio10 irq0 or gpio 23 in/out gpio11 irq1or gpio 24 out txd uart txd 25 - vdd supply voltage 26 - vdd supply voltage 27 in rxd uart rxd 28 out ledlink led for link 29 out ledr led for receive 30 out ledt led for transmit 31 out ledcol led for collision 32 in/out pu#1 usb pull-up control 33 - gnd ground 34 in/out scl serial rom clock 35 in/out sda serial rom data 36 in/out led_on led on 37 in/out npdn phy power down 38 - gnd ground 39 in phyclk_i phy clock - 25mhz oscillator input 40 out phyclk_0 phy clock - 25mhz oscillator output 41 - iref analog phy - current reference. must be connected to ground by a ____ ohm resistor 42 - avdd analog phy - vdd 43 - agnd analog phy - ground 44 - atst2 analog phy - no connect
KL5KUSB102 ?one chip?- usb to ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 4 ver. 2.0 preliminary pin # qfp i/o pin name description 45 - atst1 analog phy - no connect 46 - atst0 analog phy - no connect 47 - gnd analog phy - ground 48 - rxdn analog phy - twisted pair data input. 49 - rxdp analog phy - twisted pair data input. 50 - vdd analog phy - supply voltage 51 - vdd analog phy - supply voltage 52 - gnd analog phy - ground 53 - vdd analog phy - supply voltage 54 - txdp analog phy - twisted pair data output. 55 - txdn analog phy - twisted pair data output. 56 - gnd analog phy - ground 57 in/out gpio9 transmit data to external phy to gpio 58 in/out gpio5 collision input from external phy or gpio 59 in/out gpio7 transmit enable to external phy or gpio 60 in/out gpio6 external phy carrier sense or gpio 61 in/out gpio8 external phy receive data or gpio 62 in test external phy transmit clock input or fixed to ground 63 - gnd ground 64 in test external phy receive clock input or fixed to ground 65 out xa_15 external address pin 66 out xa_14 external address pin 67 out xa_0 external address pin 68 out nxbhe external sram byte high enable (active low) 69 out nxram_sel external sram byte low enable (active low) 70 out nxrd external memory read (active low) 71 out nxwr external memory write (active low) 72 out nxrom_sel external rom cs (active low) 73 out xa_1 external address pin 74 out xa_2 external address pin 75 - vdd supply voltage 76 - vdd supply voltage 77 out xa_3 external address pin 78 out xa_4 external address pin 79 - gnd ground 80 out xa_5 external address pin 81 out xa_6 external address pin 82 out xa_7 external address pin 83 out xa_8 external address pin 84 out xa_9 external address pin 85 out xa_10 external address pin 86 out xa_11 external address pin 87 out xa_12 external address pin 88 out xa_13 external address pin 89 in nreset reset pin (active low) 90 - gnd ground 91 in clk 12mhz oscillator input 92 out x2 12mhz oscillator output 93 - gnd ground
KL5KUSB102 ?one chip?- usb to ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 5 ver. 2.0 preliminary pin # qfp i/o pin name description 94 in vco_in pll vco in 95 out cp_out pll cp out 96 - vdd supply voltage 97 - vdd supply voltage 98 in/out vp usb d+ pin 99 in/out vm usb d- pin 100 - gnd ground function description 16 bit processor the integrated 16 bit processor serves as a micro controller for usb peripherals. the processor can execute approximately five million instructions per second. with this processing power it allows the design of intelligent peripherals that can process data prior to passing it on to the host pc, thus improving overall performance of the system. the masked rom (8k x 16) in the KL5KUSB102 or external memory contains a specialized instruction set that has been designed for highly efficient coding of processing algorithms and usb transaction processing. the 16-bit processor is designed for efficient data execution by having direct access to the ram buffer, external memory, i/o interfaces, and all the control and status registers. the divide/multiply feature expands the capability of usb peripherals. the processor supports prioritized vectored hardware interrupts. in addition, as many as 240 software interrupt vectors are available. the processor provides six addressing modes, supporting memory-to-memory, memory-to- register, register-to-register, immediate-to-register or immediate-to-memory operations. register, direct, immediate, indirect, and indirect indexed addressing modes are supported. in addition, there is an auto-increment mode in which a register, used as an address pointer is automatically incremented after each use, making repetitive operations more efficient both from a programming and a performance standpoint. the processor features a full set of program control, logical, and integer arithmetic instructions. all instructions are sixteen bits wide, although some instructions require operands, which may occupy another one or two words. several special ? short immediate? instructions are available, so that certain frequently used operations with small constant operand will fit into a 16-bit instruction. ram buffer the usb controller contains a 28k byte internal buffer memory. the memory is used to buffer data and usb packets and accessed by the 16 bit processor and the sie. usb transactions are automatically routed to the memory buffer. the 16-bit processor has the ability to set up pointers and block sizes in buffer memory for usb transactions. data is read from the interface and is processed and packetized by the 16-bit i/o processor.
KL5KUSB102 ?one chip?- usb to ethernet controller kawasaki lsi 2570 north first street suite 301 san jose, ca 95131 tel: (408) 570-0555 fax: (408) 570-0567 www.klsi.com 6 ver. 2.0 preliminary pll clock generator the pll circuitry is provided to generate the internal 48mhz clock requirements. this circuitry is designed to allow use of a low cost 12 mhz external crystal which is connected to the clk and x2 pins. usb interface the usb controller meets the universal serial bus (usb) specification ver 1.0/1.1. the transceiver is capable of transmitting and receiving serial data at the usb?s full speed, 12 mbits/sec data rate. the driver portion of the transceiver is differential, while the receive section is comprised of a differential receiver and two single ended receivers. internally, the transceiver interfaces to the sie logic. externally, the transceiver connects to the physical layer of the usb. 10mb/sec ethernet interface the KL5KUSB102 controller has a built in 10 mbit/sec 10-base t ethernet mac (media access controller) which is fully compliant with the ieee 802.3 ethernet standard. the KL5KUSB102 controller 16-bit processor has direct access to the registers of the mac. uart interface supports a transfer rate of 900 to 115.2k baud. serial eeprom support the usb controller serial interface is used to provide access to external eeprom?s. the interface can support a variety of serial eeprom formats. 10 base-t phy interface provides the physical layer for 10base-t. drives the 10base-t twisted pair cable with an isolation transformer. march 2000 copyright 2000 kawasaki lsi printed in u.s.a kawasaki lsi assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or consequential damages. there are no warranties extended or granted by this document. the information herein is subject to change without notice form kawasaki lsi
|
