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msm30r/32r/92r 0.5m sea of gates and customer structured arrays august 2002 oki asic products d ata s heet
0 oki semiconductor CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC contents description ................................................................................................................... .............................................1 features ..................................................................................................................... ...............................................1 msm30r/32r/92r family listing ................................................................................................. ......................2 array architecture ............................................................................................................ .......................................3 msm92r000 csa layout methodology .............................................................................................. ..........3 electrical characteristics .................................................................................................... .....................................5 macro library ................................................................................................................. ........................................10 macrocells for driving clock trees ............................................................................................ ..................11 oki advanced design center cad tools .......................................................................................... ................1 2 design process ................................................................................................................ .................................13 automatic test pattern generation ............................................................................................. .................14 floorplanning design flow ..................................................................................................... ......................14 ieee jtag boundary scan support ............................................................................................... ..............15 package options ............................................................................................................... ......................................16
1 oki semiconductor msm30r/32r/92r second-generation 0.5 m sea of gates and customer structured arrays description oki's second-generation 0.5m asic products are available in both sea of gates (sog) and customer structured array (csa) architectures. the msm30r series, msm32r series, and msm92r series all offer increased density over their first-generation counterparts, as well as 3-v i/o buffers that are 5-v tolerant. both the sog-based msm30r series and the csa-based msm92r series use a three-layer metal process on 0.5m drawn (0.4m l-effective) cmos technology. the sog-based msm32r series uses the same sog base-array architecture as the msm30r series, but offers two metal layers instead of three. the semiconductor process is adapted from oki's production-proven 16-mbit dram manufacturing process. the second-generation 0.5m family retains the high speed and low power of okis first-generation 0.5m msm13r/12r/98r family. the second-generation 0.5m family also shares the same die sizes for arrays with corresponding i/o counts, but the second-generation arrays can contain up to 60% more gates than their first-generation counterparts. the second-generation family is optimized for 3-v core operation, with optimized 3-v i/o buffers and 3-v i/o buffers that are 5-v tolerant, whereas the first- generation family offers separate i/o buffers for mixed 3-v and 5-v operation. oki's first-generation and second-generation 0.5m families together offer an unusually flexible mixed-voltage asic capability. the 3-layer-metal msm30r sog series contains 8 array bases, offering up to 448 i/o pads and over 600k raw gates. the 2-layer metal msm32r sog series contains five array bases, offering up to 320 i/o pads and over 300k raw gates. these sog array sizes are designed to fit the most popular quad flat pack (qfp) and plastic ball grid array (pbga) packages. the msm30r and msm32r series sog architec- ture allows rapid prototyping turnaround times, additionally offering the most cost-effective solution for pad-limited circuits (particularly the 2-layer metal msm32r series). the 3-layer-metal msm92r csa series contains 36 array bases, offering a wider span of gate and i/o counts than sog series. oki uses the epoch memory compiler from cascade design automation to generate optimized single- and dual-port ram macrocells for csa designs. as such, the msm92r series is suited to memory-intensive asics and high-volume designs where fine tuning of package size pro- duces significant cost or real-estate savings. features ?0.5 m drawn two and three-layer metal cmos ? optimized 3.3-v core ? optimized 3-v i/o and 3-v i/o that is 5-v tolerant ? sog and csa architecture availability ? 120-ps typical gate propagation delay (for a 2-input 4x-drive nand gate with a fan-out of 2 and 0mm of wire, operating at 3.3 v) ? up to 1.2m raw gates and 624 pads ? user-configurable i/o with v ss , v dd , ttl, 3-state, and 1 ma ~ 24 ma options ? slew-rate-controlled outputs for low-radiated noise ? clock tree cells with 0.5-ns clock skew, worst-case (fan-out 9000 at 75 mhz) ? user-configurable single and dual-port memories ? specialized macrocells, including phase-locked loop, gtl, pecl, and pci cells ? floorplanning for front-end simulation, back-end layout controls, and link to synthesis ? jtag boundary scan and scan-path atpg ? support for popular cae systems, including cadence, ikos, mentor graphics, synopsys, viewlogic, and zycad
2 oki semiconductor msm30r/32r/92r CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC msm30r/32r/92r family listing csa part# csa master# sog part# i/o pads raw gates rows [1] 1. row and column numbers are used to evaluate the number and size of mega macrocells that may be included into each array. columns usable gates [2] 2. usable gate count is design dependent and varies based upon the number of fan-outs per net, internal busses, floor plan, ram/rom blocks, etc. msm92rb01 b92r020x020 80 14,688 72 204 11,750 msm92rb02 b92r024x024 96 22,784 89 256 18,227 msm92rb03 b92r026x026 msm30r0020 104 27,440 98 280 21,952 msm92rb04 b92r030x030 120 37,720 115 328 30,176 msm92rb05 b92r032x032 128 43,296 123 352 34,637 msm32r0050 144 56,000 140 400 26,880 msm92rb06 b92r036x036 msm30r0050 144 56,000 140 400 42,000 msm92rb07 b92r038x038 152 63,176 149 424 47,382 msm92rb08 b92r040x040 160 70,336 157 448 52,752 msm92rb09 b92r042x042 168 78,352 166 472 58,764 msm32r0080 176 86,304 174 496 38,837 msm92rb10 b92r044x044 msm30r0080 176 86,304 174 496 60,413 msm92rb11 b92r048x048 192 103,904 191 544 72,733 msm92rb12 b92r050x050 200 114,400 200 572 80,080 msm32r0120 208 123,968 208 596 49,587 msm92rb13 b92r052x052 msm30r0120 208 123,968 208 596 86,778 msm92rb14 b92r056x056 224 144,900 225 644 101,430 msm92rb15 b92r060x060 240 167,464 242 692 117,225 msm32r0190 256 191,660 259 740 72,831 msm92rb16 b92r064x064 msm30r0190 256 191,660 259 740 126,496 msm92rb17 b92r068x068 272 217,488 276 788 143,542 msm92rb18 b92r072x072 288 244,948 293 836 161,666 msm92rb19 b92r076x076 304 274,040 310 884 180,866 msm32r0300 320 306,072 327 936 110,186 msm92rb20 b92r080x080 msm30r0300 320 306,072 327 936 195,886 msm92rb21 b92r084x084 336 338,496 344 984 216,637 msm92rb22 b92r088x088 352 372,552 361 1032 238,433 msm92rb23 b92r092x092 368 408,240 378 1080 261,274 msm92rb24 b92r096x096 msm30r0440 384 445,560 395 1128 276,247 MSM92RB25 b92r100x100 400 484,512 412 1176 300,397 msm92rb26 b92r104x104 416 525,096 429 1224 325,560 msm92rb27 b92r108x108 432 569,096 446 1276 352,840 msm92rb28 b92r112x112 448 613,012 463 1324 367,807 msm92rb29 b92r118x118 472 682,644 489 1396 409,586 msm92rb30 b92r122x122 488 730,664 506 1444 438,398 msm92rb31 b92r126x126 504 780,316 523 1492 468,190 msm92rb32 b92r132x132 528 857,072 548 1564 514,243 msm92rb33 b92r138x138 552 941,360 574 1640 564,816 msm92rb34 b92r144x144 576 1,025,488 599 1712 615,293 msm92rb35 b92r150x150 600 1,115,000 625 1784 669,000 msm92rb36 b92r156x156 624 1,206,400 650 1856 723,840
3 oki semiconductor CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC msm30r/32r/92r array architecture the primary components of a 0.5 m msm30r/32r/92r circuit include: ? i/o base cells ? configurable i/o pads for v dd , v ss , or i/o (optimized 3-v i/o and 3-v i/o that is 5-v tolerant) ?v dd and v ss pads dedicated to wafer probing ? separate power bus for output buffers ? separate power bus for internal core logic and input buffers ? core base cells containing n-channel and p-channel pairs, arranged in column of gates ? isolated gate structure for reduced input capacitance and increased routing flexibility each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads per corner. the arrays also have separate power rings for the internal core functions (v ddc and v ssc ) and output drive transistors (v ddo and v sso ). figure 7. msm30r0000 array architecture msm92r000 csa layout methodology the procedure to design, place, and route a csa follows. 1. select suitable base array frame from the available predefined sizes. to select an array size: - identify the macrocell functions required and the minimum array size to hold the macrocell functions. core base cell with 4 transistors separate power bus (v ddo , v sso ) over i/o cell for output buffers(2nd metal/3rd metal) v dd , v ss pads (4) in each corner for wafer probing only configurable i/o pads for v dd , v ss , or i/o separate power bus (v ddc , v ssc ) for internal core logic (2nd metal/3rd metal i/o base cells 1,2, or 3 layer metal interconnection in core area
4 oki semiconductor msm30r/32r/92r CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC - add together all the area occupied by the required random logic and macrocells and select the optimum array. 2. make a floor plan for the designs megacells. - oki design center engineers verify the master slice and review simulation. - oki design center or customer engineers floorplan the array using okis proprietary floor- planner or hld dp3 and customer performance specifications. - using oki cad software, design center engineers remove the sog transistors and replace them with diffused memory macrocells to the customers specifications. figure 8 shows an array base after placement of the optimized memory macrocells. figure 8. optimized memory macrocell floor plan 3. place and route logic into the array transistors. - oki design center engineers use layout software and customer performance specifications to connect the random logic and optimized memory macrocells. figure 9 marks the area in which placement and routing is performed with cross hatching. figure 9. random logic place and route mega macrocell early mask high-density rom high-density ram multi-port ram
5 oki semiconductor CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC msm30r/32r/92r electrical characteristics absolute maximum ratings (v ss = 0 v, t j = 25 c) [1] 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions in the other specifications of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol conditions rated value unit power supply voltage v dd - -0.3 ~ +4.6 v input voltage (normal buffer) - -0.3 ~ v dd +0.3 (5v tolerant buffer) v i v dd = +0.3 ~ 3.6v -0.3 ~ 6.0 v dd < 3.0v -0.3 ~ v dd +0.3 output voltage (normal buffer) v o - -0.3 ~ v dd +0.3 (5v tolerant buffer) v dd = +0.3 ~ 3.6v -0.3 ~ 6.0 v dd < 3.0v -0.3 ~ v dd +0.3 input current (normal buffer) i i - -10 ~ + 10 ma (5v tolerant buffer) - -6 ~ + 6 output current 1ma buffer i o - -6 ~ + 6 2ma buffer - -6 ~ +6 4ma buffer - -8 ~ +8 6ma buffer - -12 ~ + 12 8ma buffer - -16 ~ + 16 12ma buffer - -24 ~ + 24 24ma buffer - -48 ~ + 48 storage temperature tj - -65 ~ +150 c recommended operating conditions (v ss = 0 v) parameter symbol rated value unit min typ. max power supply voltage core v dd +3.0 +3.3 +3.6 v junction temperature tj -40 - +85 c input rise time/fall time tr, tf - 2 20 ns
6 oki semiconductor msm30r/32r/92r CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC dc characteristics (v dd = 3.0 v ~ 3.6 v, v ss = 0 v, t j = -40 c ~ +85 c) parameter symbol conditions rated value unit min typ [1] max high-level input voltage vih ttl normal input 2.0 - v dd +0.3 v ttl 5v tolerant input 2.0 - 5.5 low-level input voltage vil ttl normal input -0.3 - 0.8 ttl 5v tolerant input -0.3 - 0.8 ttl-level schmitt trigger threshold voltage (normal buffer) vt+ ttl normal input --2.0 vt- 0.7 - - ? vt vt+ - vt- 0.4 - - ttl-level schmitt trigger threshold voltage (5v tolerant buffer) vt+ ttl 5v tolerant input --2.0 vt- 0.7 - - ? vt vt+ - vt- 0.4 - - high-level output voltage (normal buffer) voh ioh=-100 a v dd -0.2 - - ioh=-1,-2,-4,-6,-8, -12,-24 ma 2.4 - - high-level output voltage (5v tolerant buffer) ioh=-100 a v dd -0.2 - - ioh=-1,-2,-4,-6,-8, -12 ma 2.4 - - low-level output voltage (normal buffer) vol iol=100 a - - 0.2 iol=1,2,4,6,8,12,24 ma --0.4 low-level output voltage (5v tolerant buffer) iol=100 a - - 0.2 iol=1,2,4,6,8,12 ma - - 0.4
7 oki semiconductor CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC msm30r/32r/92r high-level input current (normal buffer) iih vih=v ddio --1 a vih=v ddio (50k ? pull down) 15 66 170 high-level input current (5v tolerant buffer) vih=v ddio --10 vih=v ddio (50k ? pull down) 15 66 170 vih=5.5v - - 10 vih=5.5v (3k/50k ? pull up) - - 250 vih=5.5v (50k ? pull down) - - 170 low-level_input current (normal buffer) iil vil=v ss -1 - - vil=v ss (50k ? pull up) -170 -66 -15 vil=v ss (3k ? pull up) -3.3 -1.1 -0.3 ma low-level_input current (5v tolerant buffer) vil=v ss -1 - - a vil=v ss (50k ? pull up) -170 -66 -15 vil=v ss (3k ? pull up) -3.3 -1.1 -0.3 ma 3-state output_ leakage current (normal buffer) iozh voh=v ddio --1 a voh=v ddio (50k ? pull down) 15 66 170 iozl vol=v ss -1 - - vol=v ss (50k ? pull up) -170 -66 -15 vol=v ss (3k ? pull up) -3.3 -1.1 -0.3 ma dc characteristics (v dd = 3.0 v ~ 3.6 v, v ss = 0 v, t j = -40 c ~ +85 c) (continued) parameter symbol conditions rated value unit min typ [1] max
8 oki semiconductor msm30r/32r/92r CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 3-state output_ leakage current (5v tolerant buffer) iozh voh=v ddio --1 a voh=v ddio (50k ? pull down) 15 66 170 voh=5.5v - - 10 voh=5.5v (3k/50k ? pull up) - - 250 voh=5.5v (50k ? pull down) - - 170 iozl vol=v ss -1 - - vol=v ss (50k ? pull up) -170 -66 -15 vol=v ss (3k ? pull up) -3.3 -1.1 -0.3 ma dc characteristics (v dd = 3.0 v ~ 3.6 v, v ss = 0 v, t j = -40 c ~ +85 c) (continued) parameter symbol conditions rated value unit min typ [1] max
9 oki semiconductor CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC msm30r/32r/92r . ac characteristics (v dd = 3.3 v, v ss = 0 v, t j = 25 c) parameter driving type conditions [1] [2] 1. input transition time in 0.2ns / 3.3v 2. typical condition in vdd=3.3v and tj=25c. rated value [3] 3. rated value is calculated as an average of the l-h and h-l delay times of each macro type on a typical process. unit internal gate propagation delay inverter 1x f/o= 2 , l= 0 mm 0.12 ns 2x 0.10 4x 0.08 2-input nand 1x 0.17 2x 0.14 4x 0.12 inverter 1x 0.28 2x 0.20 4x 0.13 2-input nand 1x f/o= 2, standard wire length 0.36 2x 0.24 4x 0.17 toggle frequency f/o= 1, l= 0 mm 630 mhz input buffer propagation delay ttl level, normal input buffer f/o= 2 , 0.41 (typ) ns ttl level, 5v tolerant input buffer standard wire length 0.61 (typ) output buffer propagation delay push-pull, normal output buffer 4 ma cl= 20 pf 1.87 (typ) 8 ma cl= 50 pf 2.14 (typ) 12 ma cl= 100 pf 2.71 (typ) 3-state, 5v tolerant output buffer 4 ma cl= 20 pf 2.29 (typ) output buffer transition times [4] 4. output rising and falling times are both specified over a 10%-90% range. push-pull, normal output buffer 12 ma cl= 75 pf 4.09 (r) (typ) 3.85 (f) (typ) 3-state, 5v tolerant output buffer 4 ma cl= 20 pf 3.18 (r) (typ) 4.00 (f) (typ)
10 oki semiconductor msm30r/32r/92r CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC macro library oki semiconductor supports a wide range of macrocells and macrofunctions, ranging from simple hard macrocells for basic boolean operations to large, user-parameterizable macrofunctions. the following figure illustrates the main classes of macrocells and macrofunctions available. figure 10. oki macrocell and macrofunction library macro library macrocells basic macrocells basic macrocells with scan test clock tree driver macrocells 3v, 5v tolerant output macrocells msi macrocells mega/special macrocells [1] 3v, 5v tolerant input macrofunctions 3v, 5v tolerant bi-directional macrofunctions msi macrofunctions oscillator macrofunctions macrofunctions examples nands nors exors latches flip-flops 3-state outputs push-pull outputs pecl outputs counters shift registers uart pll inputs inputs with pull-ups 74199 74163 gated oscillators open drain outputs slew rate control outputs pci outputs inputs with pull-downs gtl inputs pecl inputs i/o pci i/o i/o with pull-downs i/o with pull-ups 74151 sog rams: single-port rams dual-port rams 82c37 82c54 memory macrocells 82c59 flip-flops combinational logic [1] under development optimized diffused rams: single-port rams dual-port rams pci controller ethernet controller
11 oki semiconductor CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC msm30r/32r/92r macrocells for driving clock trees oki offers clock-tree drivers that guarantee a skew time of less than 0.5 ns. the advanced layout software uses dynamic driver placement and sub-trunk allocation to optimize the clock-tree implementation for a particular circuit. features of the clock-tree driver-macrocells include: ? clock skew 0.5 ns ? automatic fan-out balancing ? dynamic sub-trunk allocation ? single clock tree driver logic symbol ? single-level clock drivers ? automatic branch length minimization ? dynamic driver placement ? up to four clock trunks the clock-skew management scheme is described in detail in okis 0.5m technology clock skew manage- ment application note . figure 11. clock tree structure clock tree driver macrocell clock drivers sub trunk clocked cell input buffer pad branch main trunk
12 oki semiconductor msm30r/32r/92r CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC oki advanced design center cad tools okis advanced design center cad tools include support for the following: ? floorplanning for front-end simulation and back-end layout control ? clock tree structures improve first-time silicon success by eliminating clock skew problems ? jtag boundary scan support ? power calculation which predicts circuit power under simulation conditions to accurately model package requirements oki design kit availability vendor platform operating system [1] 1. contact oki application engineering for current software versions. vendor software/revision [1] description cadence sun ? [2] 2. sun or sun-compatible. solaris ambit buildgates nc-verilog? verilog xl design synthesis design simulation design simulation syntest sun ? [2] solaris turbo fault fault simulation synopsys sun ? [2] solaris design compiler ultra + tetramax/atpg primetime dft compiler/test compiler rtl analyzer vcs design synthesis test synthesis static timing analysis (sta) test synthesis rtl check design simulation model technology inc. (mti) sun ? [2] nt solaris winnt4.0 mti-vhdl mti-verilog design simulation design simulation oki sun ? [2] solaris floorplanner floor planning verplex sun ? [2] solaris conformal formal verification
13 oki semiconductor CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC msm30r/32r/92r design process the following figure illustrates the overall ic design process, also indicating the three main interface points between external design houses and oki asic application engineering. floorplanning scan insertion (optional) cdc [1] functional test vectors vhdl/hdl description test vector conversion (oki tpl [3] ) netlist conversion (edif 200) tdc [2] pre-layout simulation layout / timing driven layout (optional) [6] automatic test pattern generation static timing analysis post-layout simulation manufacturing prototype test program conversion level 1 [4] level 2 level 2.5 [4] level 3 [4] cae front-end oki interface [1] okis circuit data check program (cdc) verifies logic design rules [2] okis test data check program (tdc) verifies test vector rules [3] okis test pattern language (tpl) [4] alternate customer-oki design interfaces available in addition to standard level 2 [5] standard design process includes fault simulation [6] requires synopsys timing script for oki timing driven layout gate-level simulation floorplanning synthesis fault simulation [5] figure 12. okis design process synopsys timing script (optional) formal verification verification (design rule check/formal verification)
14 oki semiconductor msm30r/32r/92r CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC automatic test pattern generation okis 0.5 m asic technologies support automatic test pattern generation (atpg) using full scan-path design techniques, including the following: ? increases fault coverage 95% ? uses synopsys test compiler ? automatically inserts scan structures ? connects scan chains ? traces and reports scan chains ? checks for rule violations ? generates complete fault reports ? allows multiple scan chains ? supports vector compaction atpg methodology is described in detail in okis 0.5m scan path application note . figure 13. full scan path con?guration floorplanning design flow okis floorplanner can be classified as both a front-end floorplanner and a back-end floorplanner. during front-end floorplanning, logic designers use the floorplanner to generate two files: a capacitance file for pre-layout simulation, and a floorplanner interface file for layout. during back-end floorplanning, the layout engineer transfers the floorplanner interface file to okis pro- prietary layout software, code-named pegasus. the floorplanner interface file contains information about the placement of blocks and groups of blocks. the back-end floorplanner is automated and is transparent to logic designers. figure 14 shows a diagram of front-end floorplanning. figure 15 shows a diagram of back-end floorplan- ning. scan data in scan select d c sd ss q qn d c sd ss a b combinational logic fd1as fd1as scan data out q qn
15 oki semiconductor CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC msm30r/32r/92r figure 14. front-end floorplanning figure 15. back-end floorplanning ieee jtag boundary scan support boundary scan offers efficient board-level and chip-level testing capabilities. benefits resulting from incorporating boundary-scan logic into a design include: ? improved chip-level and board-level testing and failure diagnostic capabilities ? support for testing of components with limited probe access ? easy-to-maintain testability and system self-test capability with on-board software ? capability to fully isolate and test components on the scan path ? built-in test logic that can be activated and monitored ? an optional boundary scan identification (id) register okis boundary scan methodology meets the jtag boundary scan standard, ieee 1149.1-1990. oki sup- ports boundary scan on both sea of gates (sog) and customer structured array (csa) asic technologies. either the customer or oki can perform boundary-scan insertion. more information is available in okis jtag boundary scan application note. contact the oki application engineering depart- ment for interface options. set design edif edif netlist plt pinlist file pre-floor plan floorplan floorplanner rcest simulation interface file fpi floorplanner interface file pre-layout edif edif netlist gcd layout pegasus fpi floorplanner interface file fif layout interface file
16 oki semiconductor msm30r/32r/92r CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC package options msm30r/32r/92r package menu product name msm92. . sog i/o pad s [1] qfp tqfp lqfp pbga fbga msm 32r msm 30r 44 64 80 100 128 160 208 240 304 44 64 80 100 128 144 176 208 256 352 420 560 144 224 rb01 80 ?? rb02 96 ??? rb03 0020 104 ?? rb04 120 ?? rb05 128 ??? rb06 0050 0050 144 ? rb07 152 ?? rb08 160 ??? rb09 168 ??? ? rb10 0080 0080 176 ?? rb11 192 ??? ? rb12 200 ???? ? rb13 0120 0120 208 ??? rb14 224 ?? rb15 240 ?? rb16 0190 0190 256 ? rb17 272 ?? rb18 288 ??? rb19 304 ??? rb20 0300 0300 320 ? rb21 336 ??? rb22 352 ?? rb23 368 rb24 0440 384 rb25 400 rb26 416 ? rb27 432 rb28 448 rb29 472 ? rb30 488 ? rb31 504 ??? rb32 528 rb33 552 rb34 576 rb35 600 rb36 624
17 oki semiconductor CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC msm30r/32r/92r body size (mm) 9x10 14x1414x2014x2028x2828x2828x2832x3240x4010x1010x1012x1214x1414x1420x2024x2428x2827x2735x3535x3535x3513x1315x15 lead pitch (mm) 0.8 0.8 0.8 0.65 0.8 0.65 0.5 0.5 0.5 0.8 0.5 0.5 0.5 0.4 0.5 0.5 0.5 1.27 1.27 1.27 1.00 0.8 0.8 ball count 256 352 420 560 144 224 signal i/o 231 304 352 400 144 224 power balls 12 16 32 80 - - ground balls 13 32 36 80 - - 1. i/o pads can be used for input, output, bi-directional, power, or ground. = available now; ? = in development msm30r/32r/92r package menu (continued) product name msm92. . sog i/o pad s [1] qfp tqfp lqfp pbga fbga msm 32r msm 30r 44 64 80 100 128 160 208 240 304 44 64 80 100 128 144 176 208 256 352 420 560 144 224
18 oki semiconductor msm30r/32r/92r CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC notes
oki semiconductor the information contained herein can change without notice owing to product and/or technical improvements. please make sure before using the product that the information you are referring to is up-to-date. the outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. when you actually plan to use the product, please ensure that the outside conditions are reflec ted in the actual circuit and assembly designs. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, b ut not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in con nection with the use of product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringemen t of a third party's right which may result from the use thereof. when designing your product, please use our product below the specified maximum ratings and within the specified operating rang es, including but not limited to operating voltage, power dissipation, and operating temperature. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,of fice automation, communication equipment, measurement equipment, consumer electronics, etc.).these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medica l, including life support and maintenance. certain parts in this document may need governmental approval before they can be exported to certain countries. the purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. copyright 2002 oki semiconductor oki semiconductor reserves the right to make changes in specifications at anytime and without notice. this information furnishe d by oki semiconductor in this publication is believed to be accurate and reliable. however, no responsibility is assumed by oki semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. no lic ense is granted under any patents or patent rights of oki.
oki r egional s ales o ffices northwest area 785 n. mary avenue sunnyvale, ca 94085 tel: 408/720-8940 fax:408/720-8965 northeast area shattuck office center 138 river road andover, ma 01810 tel: 978/688-8687 fax:978/688-8896 southwest area san diego, ca tel: 760/214-6512 760/214-6414 fax:408/737-6568 408/737-6567 south central area park creek ii 2007 n. collins blvd., suite 305 richardson, tx 75080 tel: 972/238-5450 fax:972/238-0268 corporate headquarters 785 n. mary avenue sunnyvale, ca 94085-2909 tel: 408/720-1900 fax:408/720-1918 oki stock no: oki web site: http://www.okisemi.com/us silicon solutions 010053-003

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