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this is information on a product in full production. november 2014 docid025716 rev 5 1/25 25 STGIPN3H60T-H sllimm?-nano (small low-loss intelligent molded module) ipm, 3 a - 600 v 3-phase igbt inverter bridge datasheet - production data features ? ipm 3 a, 600 v, 3-phase igbt inverter bridge including control ics for gate driving and freewheeling diodes ? optimized for low electromagnetic interference ? v ce(sat) negative temperature coefficient ? 3.3 v, 5 v, 15 v cmos/ttl inputs comparators with hysteresis and pull down/pull up resistors ? undervoltage lockout ? internal bootstrap diode ? interlocking function ? smart shutdown function ? comparator for fault protection against overtemperature and overcurrent ? op amp for advanced current sensing ? optimized pin out for easy board layout ? ntc for temperature control (ul 1434 ca 2 and 4) applications ? 3-phase inverters for motor drives ? dish washers, refrigerator compressors, heating systems, air-conditioning fans, draining and recirculation pumps description this intelligent power module implements a compact, high performance ac motor drive in a simple, rugged design. it is composed of six igbts with freewheeling diodes and three half- bridge hvics for gate driving, providing low electromagnetic interference (emi) characteristics with optimized switching speed. the package is optimized for thermal performance and compactness in built-in motor applications, or other low power applications where assembly space is limited. this ipm includes an operational amplifier, completely uncommitted, and a comparator that can be used to design a fast and efficient protection circuit. sllimm? is a trademark of stmicroelectronics. ndip-26l table 1. device summary order code marking package packaging STGIPN3H60T-H gipn3h60t-h ndip-26l tube www.st.com
contents STGIPN3H60T-H 2/25 docid025716 rev 5 contents 1 internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . 3 2 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.1 ntc thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
docid025716 rev 5 3/25 STGIPN3H60T-H internal schematic diagram and pin configuration 1 internal schematic diagram and pin configuration figure 1. internal schematic diagram 23 9ff: +,1: 76'2' +,19 9ff9 +,18 9ff8 /,1: /,18 92879 :287: 82878 3 1: 23287 76'2' *1' &,1 23 /,19 19 18 9errw8 9errw9 9errw: 17& *1' 23287 /,1 9&& +9* 23 23 6'2' 287 /9* 9errw +,1 *1' /,1 9&& +9* &,1 6'2' 287 /9* 9errw +,1 *1' /,1 9&& +9* 6'2' 287 /9* 9errw +,1
internal schematic diagram and pin configuration STGIPN3H60T-H 4/25 docid025716 rev 5 table 2. pin description pin symbol description 1 gnd ground 2t/sd /od ntc thermistor terminal / shut down logic input (active low) / open drain (comparator output) 3v cc w low voltage power supply w phase 4 hin w high side logic input for w phase 5 lin w low side logic input for w phase 6 op+ op amp non inverting input 7op out op amp output 8 op- op amp inverting input 9v cc v low voltage power supply v phase 10 hin v high side logic input for v phase 11 lin v low side logic input for v phase 12 cin comparator input 13 v cc u low voltage power supply for u phase 14 hin u high side logic input for u phase 15 t/sd /od ntc thermistor terminal / shut down logic input (active low) / open drain (comparator output) 16 lin u low side logic input for u phase 17 v boot u bootstrap voltage for u phase 18 p positive dc input 19 u, out u u phase output 20 n u negative dc input for u phase 21 v boot v bootstrap voltage for v phase 22 v, out v v phase output 23 n v negative dc input for v phase 24 v boot w bootstrap voltage for w phase 25 w, out w w phase output 26 n w negative dc input for w phase
docid025716 rev 5 5/25 STGIPN3H60T-H internal schematic diagram and pin configuration figure 2. pin layout (top view) (*) dummy pin internally connec ted to p (positive dc input).
electrical ratings STGIPN3H60T-H 6/25 docid025716 rev 5 2 electrical ratings 2.1 absolute maximum ratings table 3. inverter part symbol parameter value unit v ces each igbt collector emitter voltage (v in (1) = 0) 1. applied between hin i , lin i and gnd for i = u, v, w 600 v i c (2) 2. calculated according to the iterative formula: each igbt continuous collector current at t c = 25c 3a i cp (3) 3. pulse width limited by max junction temperature each igbt pulsed collector current 18 a p tot each igbt total dissipation at t c = 25c 8 w table 4. control part symbol parameter min. max. unit v out output voltage applied between out u , out v , out w - gnd v boot - 21 v boot + 0.3 v v cc low voltage power supply - 0.3 21 v v cin comparator input voltage - 0.3 v cc +0.3 v v op+ opamp non-inverting input - 0.3 v cc +0.3 v v op- opamp inverting input - 0.3 v cc +0.3 v v boot bootstrap voltage - 0.3 620 v v in logic input voltage applied between hin, lin and gnd - 0.3 15 v v t/sd /od open drain voltage - 0.3 15 v v out/dt allowed output slew rate 50 v/ns table 5. total system symbol parameter value unit v iso isolation withstand voltage applied between each pin and heatsink plate (ac voltage, t = 60 sec.) 1000 v t j power chips operating junction temperature -40 to 150 c t c module case operation temperature -40 to 125 c i c t c () t jmax () t c ? r thj c ? v ce sat () max () t jmax () i c t c () , () ------------------------------------------------------------------------------------------------------- =
docid025716 rev 5 7/25 STGIPN3H60T-H electrical ratings 2.2 thermal data table 6. thermal data symbol parameter value unit r thja thermal resistance junction-ambient 50 c/w
electrical characteristics STGIPN3H60T-H 8/25 docid025716 rev 5 3 electrical characteristics t j = 25 c unless otherwise specified. figure 3. switching time test circuit table 7. inverter part symbol parameter test conditions min. typ. max. unit i ces collector-cut off current (v in (1) = 0 ?logic state?) v ce = 550 v, v cc = 15 v; v bs = 15 v - 250 a v ce(sat) collector-emitter saturation voltage v cc = v boot = 15 v, v in (1) = 0 - 5 v, i c = 1 a - 2.15 2.6 v v cc = v boot = 15 v, v in (1) = 0 - 5 v, i c = 1 a, t j = 125 c -1.65 v f diode forward voltage v in (1) = 0 ?logic state?, i c = 1 a - 1.7 v inductive load switching time and energy (2) t on turn-on time v dd = 300 v, v cc = v boot = 15 v, v in (1) = 0 - 5 v, i c = 1 a (see figure 4 ) -275 ns t c(on) crossover time (on) - 90 t off turn-off time - 890 t c(off) crossover time (off) - 125 t rr reverse recovery time - 50 e on turn-on switching losses - 18 j e off turn-off switching losses - 13 1. applied between hin i , lin i and gnd for i = u, v, w. 2. t on and t off include the propagation delay time of the internal drive. t c(on) and t c(off) are the switching time of igbt itself under the internally giv en gate driving condition. am06019v2
docid025716 rev 5 9/25 STGIPN3H60T-H electrical characteristics note: figure 4 ?switching time definition? refers to hin, lin inputs (active high). 3.1 control part figure 4. switching time definition v ce i c i c v in t on t c(on) v in(on) 10% i c 90% i c 10% v ce (a) turn-on (b) turn-off t rr 100% i c 100% i c v in v ce t off t c(off) v in(off) 10% v ce 10% i c am09223v1 table 8. low voltage power supply (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v cc_hys v cc uv hysteresis 1.2 1.5 1.8 v v cc_thon v cc uv turn on threshold 11.5 12 12.5 v v cc_thoff v cc uv turn off threshold 10 10.5 11 v i qccu undervoltage quiescent supply current v cc = 10 v t/sd/ od = 5 v; lin = 0; h in = 0, c in = 0 150 a i qcc quiescent current v cc = 15 v t/sd/ od = 5 v; lin = 0; h in = 0, c in = 0 1ma v ref internal comparator (cin) reference voltage 0.5 0.54 0.58 v
electrical characteristics STGIPN3H60T-H 10/25 docid025716 rev 5 table 9. bootstrapped voltage (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v bs_hys v bs uv hysteresis 1.2 1.5 1.8 v v bs_thon v bs uv turn on threshold 11.1 11.5 12.1 v v bs_thoff v bs uv turn off threshold 9.8 10 10.6 v i qbsu undervoltage v bs quiescent current v bs < 9 v t/sd/ od = 5 v; lin = 0; and hin = 5 v; c in = 0 70 110 a i qbs v bs quiescent current v bs = 15 v t/sd/ od = 5 v; lin = 0; and hin = 5 v; c in = 0 200 300 a r ds(on) bootstrap driver on resistance lvg on 120 table 10. logic inputs (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v il low logic level voltage 0.8 1.1 v v ih high logic level voltage 1.9 2.25 v i hinh hin logic ?1? input bias current hin = 15 v 20 40 100 a i hinl hin logic ?0? input bias current hin = 0 v 1 a i linh lin logic ?1? input bias current lin = 15 v 20 40 100 a i linl lin logic ?0? input bias current lin = 0 v 1 a i sdh sd logic ?0? input bias current sd = 15 v 220 295 370 a i sdl sd logic ?1? input bias current sd = 0 v 3 a dt dead time see figure 9 180 ns
docid025716 rev 5 11/25 STGIPN3H60T-H electrical characteristics table 11. op amp characteristics (v cc = 15 v unless otherwise specified) symbol parameter test condition min. typ. max. unit v io input offset voltage v ic = 0 v, v o = 7.5 v 6 mv i io input offset current v ic = 0 v, v o = 7.5 v 440na i ib input bias current (1) 100 200 na v icm input common mode voltage range 0v v ol low level output voltage r l = 10 k to v cc 75 150 mv v oh high level output voltage r l = 10 k to gnd 14 14.7 v i o output short-circuit current source, v id = +1; v o = 0 v 16 30 ma sink, v id = -1; v o = v cc 50 80 ma sr slew rate v i = 1 - 4 v; c l = 100 pf; unity gain 2.5 3.8 v/ s gbwp gain bandwidth product v o = 7.5 v 8 12 mhz a vd large signal voltage gain r l = 2 k 70 85 db svr supply voltage rejection ratio vs. v cc 60 75 db cmrr common mode rejection ratio 55 70 db 1. the direction of input current is out of the ic. table 12. sense comparator characteristics (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit i ib input bias current v cin = 1 v 3 a v od open drain low level output voltage i od = 3 ma 0.5 v r on_od open drain low level output resistance i od = 3 ma 166 ? r pd_sd sd pull down resistor (1) 125 k ? t d_comp comparator delay t/sd /od pulled to 5 v through 100 k resistor 90 130 ns sr slew rate c l = 180 pf; r pu = 5 k 60 v/sec
electrical characteristics STGIPN3H60T-H 12/25 docid025716 rev 5 3.1.1 ntc thermistor figure 5. internal structure of sd and ntc (a) t sd shutdown to high / low side driver propagation delay v out = 0, v boot = v cc , v in = 0 to 3.3 v 50 125 200 ns t isd comparator triggering to high / low side driver turn-off propagation delay measured applying a voltage step from 0 v to 3.3 v to pin cin 50 200 250 1. equivalent value derived from the resi stances of three drivers in parallel table 12. sense comparator characteristics (v cc = 15 v unless otherwise specified) (continued) symbol parameter test conditions min. typ. max. unit table 13. truth table condition logic input (v i ) output t/sd /od lin hin lvg hvg shutdown enable half-bridge tri-state lx (1) x (1) ll interlocking half-bridge tri-state hhhl l 0 ?logic state? half-bridge tri-state hllll 1 ?logic state? low side direct driving hhlhl 1 ?logic state? high side direct driving hlhlh 1. x = don?t care a. rpd_sd: equivalent value as result of resistances of three drivers in parallel. 76'2 ' 9 9eldv 53'b6' 17& /,1 +,1 9&& *1' &,1 /9* 287 +9* 9errw 6'2' 56' &6'
docid025716 rev 5 13/25 STGIPN3H60T-H electrical characteristics figure 6. equivalent resistance (ntc//r pd _ sd ) figure 7. equivalent resistance (ntc//r pd _ sd ) zoom (txlydohqw5hvlvwdqfhn 7hpshudwxuh?& (txlydohqw5hvlvwdqfhn 7hpshudwxuh?&
electrical characteristics STGIPN3H60T-H 14/25 docid025716 rev 5 figure 8. voltage of t1/sd /od pin according to ntc temperature 9 6' 9 7hpshudwxuh?& 9 %ldv 9 5 6' n 6'2'kljk 9 %ldv 9 5 6' n
docid025716 rev 5 15/25 STGIPN3H60T-H electrical characteristics 3.2 waveform definitions figure 9. dead time and interlocking waveform definitions interl ocking interl ocking interl ocking interl ocking g
smart shutdown function STGIPN3H60T-H 16/25 docid025716 rev 5 4 smart shutdown function the device integrates a comparator for fault sensing purposes. the comparator has an internal voltage reference v ref connected to the inverting input, while the non-inverting input on pin (cin) can be connected to an external shunt resistor for simple overcurrent protection. when the comparator triggers, the device is set to the shutdown state and both its outputs are switched to the low-level setting, causing the half bridge to enter a tri-state. in common overcurrent protection architectures, the comparator output is usually connected to the shutdown input through an rc network that provides a mono-stable circuit which implements a protection time following a fault condition. our smart shutdown architecture immediately turns off the output gate driver in case of overcurrent along a preferential path for the fault signal which directly switches off the outputs. the time delay between the fault and output shutdown no longer depends on the rc values of the external network connected to the shutdown pin. at the same time, the dmos connected to the open-drain output (pin t1/sd /od) is turned on by the internal logic, which holds it on until the shutdown voltage is lower than the logic input lower threshold (vil). also, the smart shutdown function allows increasing the real disable time without increasing the constant time of the external rc network. an ntc thermistor for temperature monitoring is internally connected in parallel to the sd pin. to avoid undesired shutdown, keep the voltage v t1/sd /od higher than the high-level logic threshold by setting the pull-up resistor r sd to 1 k ? or 2.2 k ? for the 3.3 v or 5 v mcu power supplies, respectively.
docid025716 rev 5 17/25 STGIPN3H60T-H smart shutdown function figure 10. smart shutdown timing waveforms please refer to table 12 for internal propagation delay time details. shut down circuit an approximation of the disable time is given by: hin/lin hvg/lvg open drain gate (internal) comp vref cp+ protection fast shut down : the driver outputs are set to the sd state as soon as the comparator triggers even if the sd signal hasn?t reached the lower input threshold disable time sd/od gipg080920140931fsr t1/sd/od v smart sd logic t1/sd/od rpd_sd c sd r sd vbias ntc ron_od
application information STGIPN3H60T-H 18/25 docid025716 rev 5 5 application information figure 11. typical application circuit 0 3:5b*1 ' 6*1b*1 ' 9 9 9 9 23 9ff: +,1: 76'2' +,19 9ff9 +,18 9ff8 /,1: /,18 92879 :287: 82878 3 1: 23287 76'2' *1' &,1 23 /,19 19 18 9errw8 9errw9 9errw: 56 56 $'& 56 '= '= & 5 56' & 0,&52&21752//( 5 7h p s 0rqlwrulqj +,18 /,18 /,19 +,19 /,1: +,1: 6' $'& *1' /,1 9&& /9* 6'2' 287 +9* 9errw +,1 & & &errw8 5vkxqw 5 9&& 5 &6' 5 & 5 5 & &ygf *1' /,1 9&& /9* &,1 6'2' 287 +9* 9errw +,1 9'& 56) &23 &yff 5 5 *1' 23287 /,1 9&& /9* 23 23 6'2' 287 +9* 9errw +,1 5 &errw9 17& 5 & &6) &errw: & & & '= 5 '=
docid025716 rev 5 19/25 STGIPN3H60T-H application information 5.1 recommendations ? hin and lin are active-high logic input signals, each having an integrated 500 k ? (typ.) pull-down resistor. wire each input as short as possible and use rc filters (r1, c1) on each to prevent input signal oscillation. the filters should have a time constant of approximately 100 ns and must be placed as close as possible to the ipm input pins. ? use a bypass capacitor cvcc (aluminum or tantalum) to reduce the transient circuit demand on the power supply and a decoupling capacitor c2 (from 100 to 220 nf, ceramic with low esr), placed as close as possible to each vcc pin and in parallel to the bypass capacitor, to reduce high frequency switching noise distributed on the power supply lines. ? to prevent circuit malfunction, place an rc filter (rsf, csf) with a time constant (rsf x csf) of 1s as close as possible to the cin pin. ? the sd is an input/output pin (open drain type if used as output). an integrated ntc thermistor is connected internally between the sd pin and gnd. the pull-up resistor rsd causes the voltage vsd-gnd to decrease as the temperature increases. to always maintain the voltage above the high-level logic threshold, use a 1 k ? or 2.2 k ? pull-up resistor for a 3.3 v or 5 v mcu power supply, respectively. size the filter on sd appropriately to obtain the desired re-start time after a fault event, and locate it as close as possible to the sd pin. ? filter high-frequency disturbances by placing the decoupling capacitor c3 (from 100 to 220 nf, ceramic with low esr) in parallel with each cboot. ? prevent overvoltage with zener diodes dz1 between the v cc pins and gnd and in parallel with each cboot. ? locate the decoupling capacitor c4 (from 100 to 220 nf, ceramic with low esr) in parallel with the electrolytic capacitor cvdc to prevent surge destruction. place capacitors c4 (especially) and cvdc as close as possible to the ipm. ? by integrating an application-specific type hvic inside the module, direct coupling to the mcu terminals without an opto-coupler is possible. ? use low inductance shunt resistors for phase leg current sensing. ? the wiring between n pins, the shunt resistor and pwr_gnd should be as short as possible. ? connect sgn_gnd to pwr_gnd at only one point (near the shunt resistor terminal), to avoid any malfunction due to power ground fluctuation. table 14. recommended operating conditions symbol parameter test conditions min. typ. max. unit v pn supply voltage applied between p-nu, nv, nw 300 500 v v cc control supply voltage applied between v cc - gnd 13.5 15 18 v v bs high side bias voltage applied between v booti - out i for i = u, v, w 13 18 v t dead blanking time to prevent arm-short for each input signal 1.5 s
application information STGIPN3H60T-H 20/25 docid025716 rev 5 f pwm pwm input signal -40c < t c < 100c -40c < t j < 125c 25 khz t c case operation temperature 100 c table 14. recommended operating conditions (continued) symbol parameter test conditions min. typ. max. unit
docid025716 rev 5 21/25 STGIPN3H60T-H package mechanical data 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 12. ndip-26l drawing b1,b3 b,b2 c c1 base metal with plating d e eb1 eb2 e b d1 a3 e1 d2 a1 a4 pin 1 pin 16 pin 1 pin 26 pin 17 pin 26 pin 17 l a a2 ff g g b2 d3 pin 16 0.075 0.075 pin#1 id 8278949c
package mechanical data STGIPN3H60T-H 22/25 docid025716 rev 5 table 15.ndip-26l mechanical data dim. mm. min. typ. max. a 4.40 a1 0.80 1.00 1.20 a2 3.00 3.10 3.20 a3 1.70 1.80 1.90 a4 5.70 5.90 6.10 b 0.53 0.72 b1 0.52 0.60 0.68 b2 0.83 1.02 b3 0.82 0.90 0.98 c 0.46 0.59 c1 0.45 0.50 0.55 d 29.05 29.15 29.25 d1 0.50 0.77 1.00 d2 0.35 0.53 0.70 d3 29.55 e 12.35 12.45 12.55 e 1.70 1.80 1.90 e1 2.40 2.50 2.60 eb1 16.10 16.40 16.70 eb2 21.18 21.48 21.78 l 1.24 1.39 1.54
docid025716 rev 5 23/25 STGIPN3H60T-H package mechanical data figure 13. ndip-26l tube dimensions (in mm.) note: base quantity 17 pcs, bulk quantity 476 pcs. antistatic s 03 pvc am10474v1 8313150_a
revision history STGIPN3H60T-H 24/25 docid025716 rev 5 7 revision history table 16. document revision history date revision changes 19-dec-2013 1 initial release. 23-apr-2014 2 updated figure 1: internal schematic diagram and section 3: electrical characteristics . minor text changes. 05-may-2014 3 updated features in cover page. 04-nov-2014 4 updated: ? figure 1: internal schematic diagram ? table 10: logic inputs (vcc = 15 v unless otherwise specified) ? table 12: sense comparator characteristics (vcc = 15 v unless otherwise specified) ? section 3.1.1: ntc thermistor ? section 4: smart shutdown function description ? figure 10: smart shutdown timing waveforms ? figure 11: typical application circuit ? section 5.1: recommendations ? minor text changes 07-nov-2014 5 minor text and formatting edits throughout document.
docid025716 rev 5 25/25 STGIPN3H60T-H important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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