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mobile intel ? pentium ? 4 processor supporting hyper-threading technology on 90-nm process technology datasheet january 2005 document number: 302424-003
2 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet information in this document is provided in connection wi th intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, in tel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products includi ng liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instruct ions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the mobile intel? pentium? 4 processor may contain design defects or errors known as errata whic h may cause the product to devi ate from published specifications. current characte rized errata are available on request. contact your local intel sales office or your distributor to obt ain the latest specifications and before placing your product o rder. 1 hyper-threading technology requires a computer system with a mob ile intel pentium 4 processor, a chipset and bios that utilize this technology, and an operating system that includes optimizations for this technology. performance will vary depending on the specific hardwa re and software you use. see for information. copies of documents which have an ordering number and are refere nced in this document, or other intel literature, may be obtain ed by calling 1-800- 548-4725 or by visiting intel's website at intel, pentium, intel netburst, intel speedstep and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2005 intel corporation.
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 3 contents 1 introduction.................................................................................................................. ....... 7 1.1 terminology........................................................................................................... 8 1.1.1 processor packaging terminology.. ......................................................... 8 1.2 references ............................................................................................................ 9 2 electrical specifications.................................................................................................... 1 1 2.1 power and ground pins ...................................................................................... 11 2.2 decoupling guidelines ........................................................................................ 11 2.2.1 vcc decoupling ...................................................................................... 11 2.2.2 front side bus gtl+ decoupling........................................................... 11 2.2.3 front side bus clock (bclk[1:0]) and processor clocking ................... 11 2.3 voltage identification ........................................................................................... 12 2.3.1 phase lock loop (pll) power and filter............................................... 14 2.4 reserved, unused, and testhi pins.................................................................15 2.5 front side bus signal groups............................................................................. 15 2.6 asynchronous gtl+ signals............................................................................... 17 2.7 test access port (tap) connection.................................................................... 17 2.8 front side bus frequenc y select signals (bsel[1:0]) ................. ............ .......... 18 2.9 absolute maximum and minimum ratings .......................................................... 18 2.10 processor dc specifications............................................................................... 19 2.10.1 fixed mobile solution (fms) ..... ............................................................. 19 2.11 vcc overshoot specification.............................................................................. 25 2.11.1 die voltage validation ............................................................................ 26 3 package mechanical specifications ................................................................................. 27 3.1 package mechanical specifications .................................................................... 27 3.1.1 package mechanical drawing ................................................................ 28 3.1.2 processor component keep-out zo nes ................................................ 31 3.1.3 package loading specifications ............................................................ 31 3.1.4 package handling guidelines ................................................................ 31 3.1.5 package insertion specifications ........................................................... 32 3.1.6 processor mass specif ication ................................................................ 32 3.1.7 processor materials... ............................................................................. 32 3.1.8 processor markings................................................................................ 32 3.1.9 processor pin-ou t coordinates.............................................................. 33 4 pin listing and signal descriptions .............. .................................................................... 35 4.1 processor pin assignments ................................................................................ 35 4.2 alphabetical signals reference .......................................................................... 50 5 thermal specifications and design considerations......................................................... 59 5.1 processor thermal specific ations....................................................................... 59 5.1.1 thermal specifications ........................................................................... 59 5.1.2 thermal metrology ................................................................................. 60 5.2 processor thermal features............................................................................... 61 5.2.1 intel thermal monitor ............................................................................. 61 5.2.2 thermal monitor 2 .................................................................................. 61
4 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 5.2.3 on-demand mode.................................................................................. 63 5.2.4 prochot# signal pin .......................................................................... 63 5.2.5 thermtrip# signal pin ....................................................................... 64 5.2.6 tcontrol and fan speed reduction ....................................................... 64 5.2.7 thermal diode........................................................................................ 64 6 features ...................................................................................................................... ..... 67 6.1 power-on configuration options ........................................................................ 67 6.2 clock control and low power states..... ............................................................. 67 6.2.1 normal state?state 1 ........................................................................... 67 6.2.2 autohalt power-down state?state 2................................................. 68 6.2.3 stop-grant state?state 3 ..................................................................... 68 6.2.4 halt/grant snoop state?state 4 ........................................................ 69 6.2.5 sleep state?state 5.............................................................................. 69 6.2.6 deep sleep state?state 6 .................................................................... 70 6.2.7 deeper sleep state?state 7 ................................................................. 70 6.3 enhanced intel speedstep? technology . .......................................................... 70 7 debug tools specifications.............................................................................................. 73 7.1 logic analyzer interface (lai) ............................................................................. 73 7.1.1 mechanical considerations .................................................................... 73 7.1.2 electrical considerations........................................................................ 73
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 5 figures 2-1 phase lock loop (pll) f ilter requirements ...................................................... 14 2-2 vcc static and transient tolerance1, 2, 3 .......................................................... 22 2-3 vcc overshoot example waveform................................................................... 26 3-1 processor package assembly sketch.... .............................................................27 3-2 processor package drawing sheet 1 of 2........................................................... 29 3-3 processor package drawing sheet 2 of 2........................................................... 30 3-4 processor top-side markings ................ ............................................................. 32 3-5 processor pin-out coordinates, top view.......................................................... 33 4-1 pinout diagram (top view?left side) ............................................................... 48 4-2 pinout diagram (top view?right side) ............................................................. 49 5-1 case temperature (tc) measurement loc ation................................................. 60 5-2 intel thermal monitor 2 frequency and voltage ordering .................................. 62 6-1 stop clock state machine ................................................................................... 68 tables 1-1 references ............................................................................................................ 9 2-1 core frequency to front side bus multiplier configur ation ................................ 12 2-2 voltage identification definition ....... .................................................................... 13 2-3 front side bus pin groups.................................................................................. 16 2-4 signal description table . .................................................................................... 17 2-5 signal reference voltages .................................................................................. 17 2-6 bsel[1:0] freq uency table for bclk[1:0].......... ............. ............. ............ .......... 18 2-7 absolute maximum and minimum ratings .......................................................... 19 2-8 voltage and current specifications ..................................................................... 20 2-9 vcc core deep sleep state voltage re gulator static and transient tolerance (deep sleep vid offset = 1.7%) ......................................................................... 22 2-10 gtl+ signal group dc specifications ................................................................ 23 2-11 asynchronous gtl+ signal group dc specifications ........................................ 23 2-12 pwrgood and tap signal group dc specifications....................................... 24 2-13 vccvid dc specifications ................................................................................. 24 2-14 vidpwrgd dc specifications ........................................................................... 24 2-15 bsel [1:0] and vid[5:0] dc specificatio ns.................. ................. ............ .......... 25 2-16 bootselect dc specifications....................................................................... 25 2-17 vcc overshoot specifications ............................................................................ 25 3-1 processor load ing specifications ....................................................................... 31 3-2 package handling guidelines ................... .......................................................... 31 3-3 processor materials ............................................................................................. 32 4-1 alphabetical pin assignments ............................................................................. 35 4-2 numerical pin assignment .................................................................................. 42 4-3 signal description ............................................................................................... 50 5-1 processor thermal specifications....................................................................... 60 5-2 thermal diode parameters ....................... .......................................................... 64 5-3 thermal diode interface.. .................................................................................... 65 6-1 power-on configuration op tion pins .................................................................. 67
6 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet revision history revision number description date 001 ? initial release june 2004 002 ? added mobile intel? pentium? 4 proc essor 548 specifications (3.33 ghz) ? updated references table september 2004 003 ? added mobile intel? pentium? 4 processo r 552 specifications (3.46 ghz) january 2005
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 7 introduction 1 introduction the mobile intel ? pentium ? 4 processor supporting hyper-threading technology on 90-nm process technology is a follow on to the mobile intel pentium 4 processor on 130-nm process technology in the 478-pin package with enhancemen ts to the intel netburst ? microarchitecture. the processor utilizes flip-chip pin grid array (fc-mpga4) package technology, and plugs into a zero insertion force (zif) socket. the mobile intel pentium 4 processor supporting hyper- threading technology on 90-nm process technology , like its predecessor, the mobile intel pentium 4 processor in the 478-pin package, is based on the same intel 32-bit microarchitecture and maintains the tradition of compatibility with ia-32 software. in this document the mobile intel pentium 4 processor supporting hyper-threading technology on 90-nm process technology will be referred to as the ?the processor.? the mobile intel pentium 4 processor on 90-n m process technology supports hyper-threading technology. hyper-threading technology allows a single, physical processor to function as two logical processors. while some execution resources such as caches , execution units, and buses are shared, each logical processor has its own architecture state with its own set of general-purpose registers, control registers to provide incr eased system responsi veness in multitasking environments, and headroom for next generation multi threaded applications. intel recommends enabling hyper-threading technology with microsoft windows* xp professional or windows*xp home, and disabling hyper-threading technology via the bios for all previous versions of windows operating systems. for more information on hyper-threading technology, see www.intel.com/info/hyperthreading. refer to section 6.1 for hyper-threading technology configuration details. in addition to supporting all the existing streaming simd extensions 2 (sse2), there are 13 new instructions, which further exte nd the capabilities of intel pr ocessor technology. these new instructions are called streaming simd extensions 3 (sse3).these new instructions enhance the performance of optimized applicat ions for the digital home such as video, image processing and media compression technology. 3d graphics and ot her entertainment applications such as gaming will take advantage of these new instructions as platforms with the mobile intel pentium 4 processor supporting hyper-threading technology on 90-nm process technology and sse3 become available in the market place. the processor?s intel netburst microarchitecture fr ont side bus (fsb) utilizes a split-transaction, deferred reply protocol like the previous mobile intel pentium 4 processor. the intel netburst microarchitecture front side bus uses source-synchr onous transfer (sst) of address and data to improve performance by transferring data four time s per bus clock (4x data transfer rate, as in agp 4x). along with the 4x data bus, the address bus can deliver addresses two times per bus clock and is referred to as a ?double-clocked? or 2x address bus. working together, the 4x data bus and 2x address bus provide a data bus bandwidth of up to 4.3 gb/s. the processor will feature enhanced intel speedstep ? technology, which will enable real-time dynamic switching between multiple voltage and operating frequency points. this results in optimal performance without compromising low power . the processor features the auto halt, stop grant, deep sleep, and deep er sleep low power states. the processor includes an address bus powerdown capability which removes power from the address and data pins when the fsb is not in use. this feature is always enabled on the processor.
8 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet introduction 1.1 terminology a # symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. for example, when reset# is low, a reset has been requested. conversely, when nmi is high, a nonmaskable inte rrupt has occurred. in th e case of signals where the name does not imply an active state but de scribes part of a binary sequence (such as address or data ), the # symbol implies that the signal is invert ed. for example, d[3:0] = hlhl refers to a hex a, and d[3:0]# = lhlh also refers to a hex a (h= high logic level, l= low logic level). front side bus (fsb) refers to the interface betw een the processor and system core logic (the chipset components). the fsb is a multiprocessi ng interface to processors, memory, and i/o. 1.1.1 processor packaging terminology commonly used terms are explained here for clarification: ? mobile intel pentium 4 processor supporting hyper-threading technology on 90-nm process technology ? processor in the micro-fcp ga package with a 1-mb l2 cache. ? processor ? for this document, the term processor is the generic form of the mobile intel pentium 4 processor supporting hyper-threading technology on 90-nm process technology. ? keep-out zone ? the area on or near the processor that system design can not utilize. ? intel 852gm/852gme/852pm chipsets ? intel?s portability chipsets which support ddr memory technology for the mobile intel pentium 4 processor supporting hyper-threading technology on 90-nm process technology . ? processor core ? processor core die with integrated l2 cache. ? fc-mpga4 package ? the mobile intel pentium 4 processor supporting hyper-threading technology on 90-nm process technology is ava ilable in a flip-chip micro pin grid array 4 package, consisting of a processor core mounted on a pinned substrate with an integrated heat spreader (ihs). this packaging technology empl oys a 1.27 mm [0.05 in] pitch for the substrate pins. ? mpga479 socket ? the mobile intel pentium 4 processor supporting hyper-threading technology on 90-nm process technology mates with the system board through a surface mount, 479-pin, zero insertion force (zif) socket. ? integrated heat spreader (ihs) ?a component of the processo r package used to enhance the thermal performance of th e package. component thermal solutions interface with the processor at the ihs surface. ? storage conditions ? refers to a non-operational state. the processor may be installed in a platform, in a tray, or loose. processors may be sealed in packaging or exposed to free air. under these conditions, processor pins should not be connected to any supply voltages, have any i/os biased, or receive any clocks. upon exposure to ?free air? (i.e., unsealed packaging or a device re moved from packaging material) the processor must handled in accordan ce with moisture sens itivity labe ling (msl) as indicated on the packaging material. ? functional operation ? refers to normal operating conditions in which all processor specifications, including dc, ac, fsb, signal qua lity, mechanical and thermal, are satisfied.
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 9 introduction 1.2 references material and concepts available in the following documents may be beneficial when reading this document: table 1-1. references document reference number intel? 852gme and intel? 852pm chipset platforms design guide 253026 intel? architecture software developer's manual volume 1: basic architecture 253665 volume 2a: instruction set reference, a-m 253666 volume 2b: instruction set reference, n=z 253667 volume 3: system programming guide 253668 itp700 debug port design guide 249679
10 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet introduction
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 11 electrical specifications 2 electrical specifications 2.1 power and ground pins for clean on-chip power distribution, the processor has 85 v cc (power) and 179 v ss (ground) pins. all power pins must be connected to v cc , while all v ss pins must be connect ed to a system ground plane.the processor v cc pins must be supplied the voltage determined by the vid (voltage identification) pins. 2.2 decoupling guidelines due to its large number of transistors and high inte rnal clock speeds, the pr ocessor is capable of generating large current swings between low and full power states. this may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. care must be taken in the board design to ensure that the volt age provided to the pro cessor remains within the specifications listed in table 2-8 . failure to do so can result in timing violations or reduced lifetime of the component. for further information and design guidelines, refer to the intel ? 852gme and intel ? 852pm chipset platforms design guide . 2.2.1 vcc decoupling regulator solutions need to provide bulk capacita nce with a low effective series resistance (esr) and keep a low interconnect resi stance from the regulator to the socket. bulk decoupling for the large current swings when the pa rt is powering on, or entering/exiting low power states, must be provided by the voltage regulator solution (vr). for more details on this topic, refer to the intel ? 852gme and intel ? 852pm chipset platforms design guide . 2.2.2 front side bus gtl+ decoupling the processor integrates signal termination on th e die as well as incorporating high frequency decoupling capacitance on the processor package. decoupling must also be provided by the system baseboard for proper gtl+ bus operation. for more information, refer to the intel ? 852gme and intel ? 852pm chipset platforms design guide . 2.2.3 front side bus clock (bcl k[1:0]) and pro cessor clocking bclk[1:0] directly controls the fr ont side bus interface speed as we ll as the core frequency of the processor. as in previous generation processors, th e processor core frequency is a multiple of the bclk[1:0] frequency. no user in tervention is necessary, and the processor will au tomatically run at the speed indicated on the pack age. the processor uses a differ ential clocking implementation.
12 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet electrical specifications note: individual processors operate only at or below the rated frequency. 2.3 voltage identification the voltage set by the vid signals is the reference vr output voltage to be delivered to the processor vcc pins. a minimum voltage is provided in table 2-8 and changes with frequency. this allows processors running at a higher frequency to have a relaxed minimum voltage specification. the specifications have been set such that one voltage regulator can work with all supported frequencies. individual processor vid values may be calibrate d during manufacturing such that two devices at the same speed may have different vid settings. the processor uses six voltage identification pins , vid[5:0], to support automatic selection of power supply voltages. table 2-2 specifies the voltage level corresponding to the state of vid[5:0]. a 1 in this table refers to a high voltage level an d a 0 refers to low voltage level. if the processor socket is empty (vid[5:0] = x11111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable. the processor?s voltage identification circuit requ ires an independent 1.2-v supply and some other power sequencing considerations. table 2-1. core frequency to front side bus multiplier configuration multiplication of system core frequency to front side bus frequency core frequency (133 mhz bclk/533 mhz fsb) 1/14 1.86 ghz 1/15 2.00 ghz 1/16 2.13 ghz 1/17 2.26 ghz 1/18 2.40 ghz 1/19 2.53 ghz 1/20 2.66 ghz 1/21 2.80 ghz 1/22 2.93 ghz 1/23 3.06 ghz 1/24 3.20 ghz 1/25 3.33 ghz 1/26 3.46 ghz 1/27 3.60 ghz
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 13 electrical specifications table 2-2. voltage identification definition vid5 vid4 vid3 vid2 vid1 vid0 vid vid5 vid4 vid3 vid2 vid1 vid0 vid 001010 0. 8375 0110101.2125 101001 0. 8500 1110011.2250 001001 0. 8625 0110011.2375 101000 0. 8750 1110001.2500 001000 0. 8875 0110001.2625 100111 0. 9000 1101111.2750 000111 0. 9125 0101111.2875 100110 0. 9250 1101101.3000 000110 0. 9375 0101101.3125 100101 0. 9500 1101011.3250 000101 0. 9625 0101011.3375 100100 0. 9750 1101001.3500 000100 0. 9875 0101001.3625 100011 1. 0000 1100111.3750 000011 1. 0125 0100111.3875 100010 1. 0250 1100101.4000 000010 1. 0375 0100101.4125 100001 1. 0500 1100011.4250 000001 1. 0625 0100011.4375 100000 1. 0750 1100001.4500 000000 1. 0875 0100001.4625 111111vr output off1011111.4750 011111vr output off0011111.4875 111110 1. 1000 1011101.5000 011110 1.1125 0011101.5125 111101 1. 1250 1011011.5250 011101 1. 1375 0011011.5375 111100 1. 1500 1011001.5500 011100 1. 1625 0011001.5625 111011 1. 1750 1010111.5750 011011 1. 1875 0010111.5875 111010 1. 2000 1010101.6000
14 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet electrical specifications 2.3.1 phase lock loop (pll) power and filter v cca and v cciopll are power sources required by the pll clock generators on the processor silicon. since these plls are analog in nature, th ey require low noise power supplies for minimum jitter. jitter is detrimental to the system: it degrad es external i/o timings as well as internal core timings (i.e., maximum frequency). to prevent th is degradation, these supplies must be low pass filtered from v cc . the ac low-pass requirements, with input at v cc are as follows: ? < 0.2 db gain in pass band ? < 0.5 db attenuation in pass band < 1 hz ? > 34 db attenuation from 1 mhz to 66 mhz ? > 28 db attenuation from 66 mhz to core frequency the filter requirements are illustrated in figure 2-1 . for recommendations on implementing the filter refer to the intel ? 852gme and intel ? 852pm chipset platforms design guide . . notes: 1. diagram not to scale. 2. no specification exists for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 mhz. figure 2-1. phase lock loop (pll) filter requirements 0 db -28 db -34 db 0.2 db forbidden zone -0.5 db forbidden zone 1 mhz 66 mhz f core f pea k 1 hz dc passband high frequency band
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 15 electrical specifications 2.4 reserved, unused, and testhi pins all reserved pins must remain unconnected. connection of these pins to v cc , v ss , or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. see chapter 4 for a pin listing of the processor and the location of all reserved pins. for reliable operation, always connect unused inpu ts or bidirectional signals to an appropriate signal level. in a system level design, on-die te rmination has been includ ed on the processor to allow signals to be terminated within the processor silicon. most unused gtl+ inputs should be left as no connects, as gtl+ termination is provided on the processor silicon. however, see table 2-4 for details on gtl+ signals that do not include on-die termination. unused active high inputs should be connected through a resistor to ground (v ss ). unused outputs can be left unconnected, however this may interfere with some test access port (tap ) functions, complicate debug probing, and prevent boundary scan tes ting. a resistor must be used when tying bidirectional signals to power or ground. when tyin g any signal to power or ground, a resistor will also allow for system testability. for unused gtl+ input or i/o signals, use pull-up resistors of the same value as the on-die termination resistors (r tt ). tap, asynchronous gtl+ inputs, and asynchronous gtl+ outputs do not include on-die termination. inputs and used outputs must be term inated on the system bo ard. unused outputs may be terminated on the system board or left unconnected. note that leaving unused outputs unterminated may interfere with some tap func tions, complicate debug probing, and prevent boundary scan testing. signal termination for these signal types is discussed in the intel ? 852gme and intel ? 852pm chipset platforms design guide . the testhi pins must be tied to the processor v cc using a matched resistor, where a matched resistor has a resistance value within +/-20% of the impedance of the board transmission line traces. for example, if th e trace impedance is 60 ? , then a value between 48 ? and 72 ? is required. the testhi pins may use individual pull-up resistor s or be grouped together as detailed below. a matched resistor should be used for each group: ? testhi[1:0] ? testhi[7:2] ? testhi8 - cannot be grouped with other testhi signals ? testhi9 - cannot be grouped with other testhi signals ? testhi10 - cannot be grouped with other testhi signals ? testhi11 - cannot be grouped with other testhi signals 2.5 front side bus signal groups the front side bus signals have been combined into groups by buffer type. gtl+ input signals have differential input buffers, which use gtlref as a reference level. in this document, the term "gtl+ input" refers to the gtl+ input group as well as the gtl+ i/o group when receiving. similarly, "gtl+ output" refers to the gtl+ output group as well as the gtl+ i/o group when driving.
16 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet electrical specifications with the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. one set is for common clock signals which are dependent upon the rising edge of bclk0 (ads#, hit#, hitm#, etc.) and the se cond set is for the source synchronous signals which are relative to their respective strobe lines (d ata and address) as well as the rising edge of bclk0. asychronous signals are still present (a 20m#, ignne#, etc.) and can become active at any time during the clock cycle. table 2-3 identifies which signals are common clock, source synchronous, and asynchronous. notes: 1. refer to section 4.2 for signal descriptions. 2. in processor systems where there is no debug port im plemented on the system board, these signals are used to support a debug port interposer. in systems with the debug port implemented on the system board, these signals are no connects. 3. the value of these pins during the active-to-inacti ve edge of reset# defines the processor configuration options. see section 6.1 for details. table 2-3. front side bus pin groups signal group type signals 1 gtl+ common clock input synchronous to bclk[1:0] bpri#, defer#, reset#, rs[2:0]#, rsp#, trdy# gtl+ common clock i/o synchronous to bclk[1:0] ap[1:0]#, ads#, binit#, bnr#, bpm[5:0]#, br0#, dbsy#, dp[3:0]#, drdy#, hit#, hitm#, lock#, mcerr# gtl+ source synchronous i/o synchronous to assoc. strobe gtl+ strobes synchronous to bclk[1:0] adstb[1:0]#, dstbp[3:0]#, dstbn[3:0]# asynchronous gtl+ input a20m#, dpslp#, ignne#, init#, lint0/intr, lint1/nmi, smi#, slp#, stpclk# asynchronous gtl+ output ferr#/pbe#, ierr#, thermtrip# asynchronous gtl+ input/output prochot# tap input synchronous to tck tck, tdi, tms, trst# tap output synchronous to tck tdo front side bus clock clock bclk[1:0], itp_clk[1:0] 2 power/other v cc , v cca , v cciopll , vid[5:0], v ss , v ssa , gtlref[3:0], comp[1:0], reserved, testhi[11:0], thermda, thermdc, vcc_sense, vss_sense, vccvid, vccvidlb, bsel[1:0], sktocc#, dbr# 2 , vidpwrgd, bootselect, optimized/compat# , pwrgood signals associated strobe req[4:0]#, a[16:3]# 3 adstb0# a[35:17]# 3 adstb1# d[15:0]#, dbi0# dstbp0#, dstbn0# d[31:16]#, dbi1# dstbp1#, dstbn1# d[47:32]#, dbi2# dstbp2#, dstbn2# d[63:48]#, dbi3# dstbp3#, dstbn3#
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 17 electrical specifications notes: 1. signals that do not have r tt , nor are actively driven to their high-voltage level. 2. the optimized/compat# and bootselect pins have a 500-5000 ? pullup to vccvid rather than r tt . note: these signals also have hysteresis added to the reference voltage. see table 2-12 for more information. 2.6 asynchronous gtl+ signals legacy input signals such as a20m#, dpsl p#, ignne#, init#, smi#, slp#, and stpclk# utilize cmos input buffers. all of these signa ls follow the same dc requirements as gtl+ signals, however the outputs are no t actively driven high (during a logical 0 to 1 transition) by the processor. these signals do not have setup or hold time specifications in relation to bclk[1:0]. 2.7 test access port (tap) connection due to the voltage levels supported by other components in the test access port (tap) logic, it is recommended that the processor be first in the tap chain and followed by any other components within the system. a translation buffer should be us ed to connect to the rest of the chain unless one of the other components is capab le of accepting an input of the ap propriate voltage level. similar considerations must be made for tck, tms, tr st#, tdi, and td o. two copies of each signal may be required, with each driv ing a different voltage level. table 2-4. signal description table signals with r tt signals with no r tt a[35:3]#, ads#, adstb[1:0]#, ap[1:0]#, binit#, bnr#, bootselect 2 , bpri#, d[63:0]#, dbi[3:0]#, dbsy#, defer#, dp[3:0]#, drdy#, dstbn[3:0]#, dstbp[3:0]#, hit#, hitm#, lock#, mcerr#, optimized/compat# 2 , prochot#, req[4:0]#, rs[2:0]#, rsp#, trdy# a20m#, bclk[1:0], bpm[5:0]#, br0#, bsel[1:0], comp[1:0], dpslp#, ferr#/pbe#, ierr#, ignne#, init#, lint0/intr, lint1/nmi, pwrgood, reset#, sktocc#, slp#, smi#, stpclk#, tdo, testhi[11:0], thermda, thermdc, thermtrip#, vid[5:0], vidpwrgd, gtlref[3:0], tck, tdi, trst#, tms open drain signals 1 bsel[1:0], vid[5:0], thermtrip#, ferr#/pbe#, ierr#, bpm[5:0]#, br0#, tdo table 2-5. signal reference voltages gtlref v cc /2 vccvid/2 bpm[5:0]#, lint0/intr, lint1/nmi, reset#, binit#, bnr#, hit#, hitm#, mcerr#, prochot#, br0#, a[35:0]#, ads#, adstb[1:0]#, ap[1:0]#, bpri#, d[63:0]#, dbi[3:0]#, dbsy#, defer#, dp[3:0]#, drdy#, dstbn[3:0]#, dstbp[3:0]#, lock#, req[4:0]#, rs[2:0]#, rsp#, trdy# a20m#, dpslp#, ignne#, init#, pwrgood 1 , slp#, smi#, stpclk#, tck 1 , tdi 1 , tms 1 , trst# 1 vidpwrgd, bootselect, optimized/ compat#
18 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet electrical specifications 2.8 front side bus frequency select signals (bsel[1:0]) the bsel[1:0] signals are used to select the freq uency of the processor in put clock (bclk[1:0]). table 2-6 defines the possible combinations of the si gnals and the frequency associated with each combination. the required frequency is determ ined by the processor, chipset, and clock synthesizer. all agents must op erate at the same frequency. the processor currently operates at a 533-mh z front side bus frequency (selected by a 133-mhz bclk[1:0] frequency). individual processors will only operate at their specified front side bus frequency. for more information about these pins refer to section 4.2 and the appropriat e platform design guidelines. 2.9 absolute maximum and minimum ratings table 2-7 specifies absolute maximum and minimum ratings. within functional operation limits, functionality and long-term re liability can be expected. at conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-t erm reliability can be expected. if a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded de pending on exposure to conditions exceeding the functional operation condition limits. at conditions exceeding ab solute maximum and minimum ratings , neither functiona lity nor long- term reliability can be expected. moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded. although the processor contains pr otective circuitry to re sist damage from stat ic electric discharge, precautions should always be taken to avoid high static voltages or electric fields. table 2-6. bsel[1:0] frequency table for bclk[1:0] bsel1 bsel0 function l l reserved l h 133 mhz h l reserved h h reserved
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 19 electrical specifications notes: 1. for functional operation, all processo r electrical, signal quality, mechanical and thermal specifications must be satisfied. 2. overshoot and undershoot voltage guidelines for input, output and i/o signals are outlined in section 3 . excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 3. storage temperature is applicable to storage conditions only. in this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias . storage within these limits will not affect the long- term reliability of the device. fo r functional operation, please refer to the processor case temperature specifications. 4. this rating applies to the processor a nd does not include any tray or packaging. 5. contact intel for storage requirements in excess of one year. 2.10 processor dc specifications the processor dc specifica tions in this section are defined at the processor core silicon and not at the package pins unless noted otherwise. see section 4 for the pin signal definitions and signal pin assignments. most of the signals on the processor front side bus are in the gtl+ signal group. the dc specifications fo r these signals are listed in table 2-10 . previously, legacy signals and te st access port (tap) signals to the processor used low-voltage cmos buffer types. however, these interfaces now follow dc specifications similar to gtl+. the dc specifications for these signal groups are listed in table 2-11 and table 2-12 . table 2-8 through table 2-16 list the dc specifications for the processor and are valid only while meeting specifications for case temp erature, clock frequency, and input voltages. care should be taken to read all notes asso ciated with each parameter. 2.10.1 fixed mobile solution (fms) the fms guidelines are estimates of the maximu m values the mobile processor will have over certain time periods. the values are only estimates and actual speci fications for future processors may differ. the processor may or may not have specifications equal to the fms value in the foreseeable future. system designers should meet th e fms values to ensure their systems will be compatible with future releases of the mobile processor. table 2-7. absolute maximum and minimum ratings symbol parameter min max unit notes v cc any processor supply voltage with respect to v ss - 0.3 1.55 v 1, 2 t c processor case temperature see section 5 see section 5 c 3, 4 t storage processor storage temperature ?10 +45 c 3, 4, 5
20 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet electrical specifications notes: 1. individual processor vid values may be calibrated du ring manufacturing such that two devices at the same speed may have different vid settings. 2. unless otherwise noted, all specifications in this t able are based on estimates and simulations or empirical data. these specifications will be updated with characte rized data from silicon measurements at a later date. table 2-8. voltage and current specifications symbol parameter min typ max unit notes 2 hfm vid vid range for hfm (highest frequency mode) 1.250 1.400 v 1 lfm vid vid for lfm (lowest frequency mode) n/a 1.150 n/a v vid transition vid step size during a transition n/a n/a 12.5 mv 12 v cc v cc for fms0.5 processors see table and figure 2-2 vid - i cc (max) * 1.45 m ? v 3, 4, 5 i cc processor number core frequency 44 80 80 80 80 80 80 a7, 10 518 532 538 548 552 i cc for processor with vid = 1.15 v: 1.86 ghz i cc for processor with multiple vid: 2.80 ghz 3.06 ghz 3.20 ghz 3.33 ghz 3.46 ghz fms0.5 v ccdprslp static and transient deeper sleep voltage 0.95 1.0 1.05 v 2, 3 i sgnt i slp processor number core frequency 31 40 40 40 40 40 a 6, 9, 13 518 532 538 548 552 i cc stop-grant 1.86 ghz 2.80 ghz 3.06 ghz 3.20 ghz 3.33 ghz 3.46 ghz i tcc i cc tcc active i cc a8 i cc _ vcca i cc for pll pins 60 ma 11 i cc _ vcciopll i cc for i/o pll pin 60 ma 11 i cc _ gtlref i cc for gtlref pins (all pins) 200 a i cc _ vccvid / vccvidlb i cc for vccvid/vccvidlb 150 ma 11
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 21 electrical specifications 3. these voltages are targets only. a variable voltage source should exist on systems in the event that a different voltage is required. see section 2.3 and table 2-2 for more information. 4. the voltage specification requirements are measured across v cc _ sense and v ss _ sense pins at the socket with a 100mhz bandwidth oscilloscope, 1.5 pf maximum probe capacitance, and 1 m ? minimum impedance. the maximum length of ground wire on the probe should be less than 5 mm. ensure external noise from the system is not coupled into the oscilloscope probe. 5. refer to table , table 2-9 , and figure 2-2 for the minimum, typical, and maximum v cc allowed for a given current. the processor should not be subjected to any v cc and i cc combination wherein v cc exceeds v cc _ max for a given current. moreover, v cc should never exceed the vid voltage. failure to adhere to this specification can shorten the processor lifetime. 6. the current specified is also for autohalt state. 7. fms is the fixed mobile solution guideline. thes e guidelines are for estima tion purposes only. see section 2.10.1 for further details on fms guidelines 8. the maximum instantaneous current the processor will dr aw while the thermal contro l circuit is active as indicated by the assertion of prochot# is the same as the maximum i cc for the processor. 9. i cc stop-grant and i cc sleep are specified at v cc _ max . 10.i cc _ max is specified at v cc _ max . 11.these parameters are based on desig n characterization and are not tested. 12.this specification represents the v cc reduction due to each vid transition. see section 2.3 . ac timing requirements will be included in future revisions of this document. 13.the specifications for the battery optimized mode (1.86 ghz at 1.15 vid) are not 100% tested. these specifications are determined by c haracterization of the processor curr ents at higher voltage and frequency and extrapolating the values for the battery optimized mode voltage and frequency. notes: 1. the loadline specification in cludes both static and transient limits e xcept for overshoot allowed as shown in section 2.11 . 2. this table is intended to aid in reading discrete points on figure 2-2 . 3. the loadlines specify voltage limi ts at the die measured at the v cc _ sense and v ss _ sense pins. 4. voltage regulation feedback for voltage regulator circuits must be taken from processor v cc and v ss pins. vcc static and transient tolerance icc (a) voltage deviation from vid setting (v) 1,2,3 maximum typical minimum 0 0.000 -0.025 -0.050 5 -0.007 -0.033 -0.059 10 -0.015 -0.041 -0.068 15 -0.022 -0.049 -0.077 20 -0.029 -0.058 -0.086 25 -0.036 -0.066 -0.095 30 -0.044 -0.074 -0.104 35 -0.051 -0.082 -0.113 40 -0.058 -0.090 -0.122 45 -0.065 -0.098 -0.131 50 -0.073 -0.106 -0.140 55 -0.080 -0.114 -0.149 60 -0.087 -0.123 -0.158 65 -0.094 -0.131 -0.167 70 -0.102 -0.139 -0.176 75 -0.109 -0.147 -0.185 80 -0.116 -0.155 -0.194
22 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet electrical specifications notes: 1. the loadline specifications incl ude both static and transient limits. 2. this table is intended to aid in reading discrete points on figure 2-2 . 3. the loadlines specify voltage limits at the die measured at the v cc _ sense and v ss _ sense pins. voltage regulation feedback for voltage regulator ci rcuits must be taken from processor v cc and v ss pins. 4. the voltage used in deep sleep mode must first be of fset by 1.7% from the vid setting before reading the voltage deviation on respective loadline. notes: 1. the loadline specification includes both static and transi ent limits except for overshoot allowed as shown in section 2.11 . 2. this loadline specific ation shows the deviation from the vid set point. table 2-9. v cc core deep sleep state voltage regulator static and transient tolerance (deep sleep vid offset = 1.7%) icc (a) voltage deviation from (vid setting - 1.7% of vid setting) (v) 1,2,3,4 maximum typical minimum 0 0.000 -0.025 -0.050 5 -0.007 -0.033 -0.059 10 -0.015 -0.041 -0.068 15 -0.022 -0.049 -0.077 20 -0.029 -0.058 -0.086 25 -0.036 -0.066 -0.095 30 -0.044 -0.074 -0.104 35 -0.051 -0.082 -0.113 40 -0.058 -0.090 -0.122 figure 2-2. vcc static and transient tolerance 1, 2, 3 vid - 0.000 vid - 0.025 vid - 0.050 vid - 0.075 vid - 0.100 vid - 0.125 vid - 0.150 vid - 0.175 vid - 0.200 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 icc [a] vcc [v] vcc typical vcc maximu m vcc minimu m
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 23 electrical specifications 3. the loadlines specify voltage limi ts at the die measured at the v cc _ sense and v ss _ sense pins. voltage regulation feedback for voltage regulator circ uits must be taken from processor v cc and v ss pins. notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. v il is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. 3. v ih is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. 4. v ih and v oh may experience excursions above v cc . however, input signal drivers must comply with the signal quality specifications. 5. refer to processor i/o buffer models for i/v characteristics. 6. the v cc referred to in these specifications is the instantaneous v cc . 7. leakage to v ss with pin held at v cc . 8. leakage to v cc with pin held at 300 mv. notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. all outputs are open drain. 3. v il is defined as the voltage range at a receiving agent t hat will be interpreted as a logical low value. 4. v ih is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. 5. refer to the processor i/o buff er models for i/v characteristics. 6. the v cc referred to in these specifications refers to instantaneous v cc . 7. the maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. 8. leakage to vss with pin held at v cc . 9. leakage to v cc with pin held at 300 mv. 10.lint0/intr and lint1/nmi use gtlref as a reference voltage. for these two signals v ih = gtlref + (0.10 * v cc ) and v il = gtlref - (0.10 * vcc). table 2-10. gtl+ signal group dc specifications symbol parameter min max unit notes 1 v il input low voltage 0.0 gtlref - (0.10 * v cc )v2, 6 v ih input high voltage gtlref + (0.10 * v cc ) v cc v 3, 4, 6 v oh output high voltage 0.90*v cc v cc v4, 6 i ol output low current n/a v cc / [(0.50*r tt _ min )+(r on _ min )] a i li input leakage current n/a 200 a 7 i lo output leakage current n/a 200 a 8 r on buffer on resistance 8 12 ? 5 table 2-11. asynchronous gtl+ signal group dc specifications symbol parameter min max unit notes 1 v il input low voltage 0.0 v cc /2 - (0.10 * v cc )3, 11 v ih input high voltage v cc /2 + (0.10 * v cc )v cc 4, 5, 7, 11 v oh output high voltage 0.90*v cc v cc v 2, 5, 7 i ol output low current v cc /[(0.50*r tt _ min )+(r on _ min )] a 8 i li input leakage current n/a 200 a 9 i lo output leakage current n/a 200 a 10 r on buffer on resistance 8 12 ? 6
24 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet electrical specifications . notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. all outputs are open drain. 3. refer to the processor i/o buff er models for i/v characteristics. 4. the v cc referred to in these specifications refers to instantaneous v cc . 5. the maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. 6. v hys represents the amount of hysteresis, nominally centered about 0.5 * v cc for all tap inputs. 7. leakage to vss with pin held at v cc . 8. leakage to v cc with pin held at 300 mv. table 2-12. pwrgood and tap si gnal group dc specifications symbol parameter min max unit notes 1, 2 v hys input hysteresis 200 350 mv 7 v t+ input low to high threshold voltage 0.5 * (v cc + v hys_min ) 0.5 * (v cc + v hys_max )v 5 v t- input high to low threshold voltage 0.5 * (v cc - v hys_max ) 0.5 * (v cc - v hys_min )v 5 v oh output high voltage n/a v cc v3, 5 i ol output low current 45 ma 6 i li input leakage current 200 a i lo output leakage current 200 a r on buffer on resistance 7 12 ? 4 table 2-13. vccvid dc specifications symbol parameter min typ max unit notes vccvid voltage 1.14 1.2 1.26 v vccvidlb voltage 1.14 1.2 1.26 v table 2-14. vidpwrgd dc specifications symbol parameter min typ max unit notes v il input low voltage 0.3 v v ih input high voltage 0.9
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 25 electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. these parameters are not tested and are based on design simulations. 3. leakage to vss with pin held at 2.5 v. note: these parameters are not tested and are based on design simulations. 2.11 v cc overshoot specification the processor can tolerate short tr ansient overshoot events where v cc exceeds the vid voltage when transitioning from a high to low current load condition. th is overshoot cannot exceed vid + v os _ max (v os _ max is the maximum allowable overshoot voltage). the time duration of the overshoot event mu st not exceed t os _ max (t os _ max is the maximum allowable time duration above vid). these specifications apply to the processor die voltage as measured across the vcc_sense and vss_sense pins. table 2-15. bsel [1:0] and vid[5:0] dc specifications symbol parameter max unit notes 1 r on (bsel) buffer on resistance 60 ? 2 r on (vid) buffer on resistance 60 ? 2 i ol max pin current 8 ma i lo output leakage current 200 a 3 v tol voltage tolerance 3.3 + 5% v table 2-16. bootselect dc specifications symbol parameter min typ max unit notes v il input low voltage 0.2 * vccvid v 1 v ih input high voltage 0.8 * vccvid 60 v 1 table 2-17. v cc overshoot specifications symbol parameter min typ max unit figure notes v os _ max magnitude of v cc overshoot above vid 0.050 v 2-3 t os _ max time duration of v cc overshoot above vid 25 s 2-3
26 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet electrical specifications notes: 1. vos is measured overshoot voltage. 2. tos is measured time duration above vid. 2.11.1 die voltage validation overshoot events from applicatio n testing on real processors mu st meet the specifications in table 2-17 when measured across the vcc_sense and vss_sense pins . overshoot events that are < 10 ns in duration may be ignored. these measurements of processor die level overshoot should be taken with a 100-mhz bandwidth limited oscilloscope. figure 2-3. v cc overshoot example waveform time example overshoot waveform voltage (v) vid vid + 0.050 t os v os t os : overshoot time above vid v os : overshoot above vid
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 27 package mechanical specifications 3 package mechanical specifications 3.1 package mechanical specifications the mobile processor is packaged in a flip -chip pin grid array (f c-mpga4) package that interfaces with the motherboard via a mpga479 sock et. the package consists of a processor core mounted on a substrate pin carrier. an integrated heat spreader (i hs) is attached to the package substrate and core and serves as the mating surface for proce ssor component thermal solutions, such as a heatsink. figure 3-1 shows a sketch of the processor package components and how they are assembled together. refer to the mpga479, mpga478a, mp ga478b, mpga478c, and mpga476 socket design guidelines for complete details on the mpga479 socket. the package components shown in figure 3-1 include the following: 1. integrated heat spreader (ihs) 2. thermal interface material (tim) 3. processor core (die) 4. package substrate 5. capacitors note: socket and motherboard are included for referenc e and are not part of processor package. figure 3-1. processor package assembly sketch socket substrate ihs capacitors core (die) motherboard tim socket substrate ihs capacitors core (die) motherboard tim tim substrate socket capacitors ihs motherboard core (die)
28 mobile intel? pentium? 4 processo r supporting hyper-threading technology on 90-nm process technology datasheet package mechanical specifications 3.1.1 package mechanical drawing the package mechanical drawings are shown in figure 3-2 and figure 3-3 . the drawings include dimensions necessary to design a thermal solution for the processor. these dimensions include: 1. package reference with tolerances (total height, length, width, etc.) 2. ihs parallelism and tilt 3. pin dimensions 4. top-side and back-side component keep-out dimensions 5. reference datums all drawing dimensions are in mm [in].
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 29 package mechanical specifications figure 3-2. processor package drawing sheet 1 of 2
30 mobile intel? pentium? 4 processo r supporting hyper-threading technology on 90-nm process technology datasheet package mechanical specifications figure 3-3. processor package drawing sheet 2 of 2
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 31 package mechanical specifications 3.1.2 processor compon ent keep-out zones the processor may contain components on the substrate that define component keep-out zone requirements. a thermal and mechan ical solution design must not intrude into the required keep- out zones. decoupling capacitors are typically moun ted to either the topside or pin-side of the package substrate. see figure 3-2 and figure 3-3 for keep-out zones. the location and quantity of pack age capacitors may change due to manufacturing efficiencies but will remain within the component keep-in. 3.1.3 package loading specifications table 3-1 provides dynamic and static load specifi cations for the processor package. these mechanical maximum load limits should not be exceeded duri ng heatsink assembly, shipping conditions, or standard use condition. also, any mechanical system or component testing should not exceed the maximum limits. the processor pa ckage substrate should not be used as a mechanical reference or load-b earing surface for thermal and mech anical solution. the minimum loading specification must be maintained by any thermal and mechanical solutions. . notes: 1. these specifications apply to unifo rm compressive loading in a direction normal to the processor ihs. 2. this is the maximum force that can be applied by a heat sink retention clip. the clip must also provide the minimum specified load on the processor package. 3. these specifications are based on limited testing for design characteri zation. loading limits are for the package only and does not include the limits of the processor socket. 4. dynamic loading is defined as an 11 ms duration av erage load superimposed on the static load requirement. 5. transient loading is defined as a 2 second duration peak load superimposed on the static load requirement, representative of loads experienced by the package during heatsink installation. 3.1.4 package handling guidelines table 3-2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor ihs relative to a fixed substrate. these packag e handling loads may be experienced during heatsink removal. notes: 1. a shear load is defined as a load applied to the ihs in a direction parallel to the ihs top surface. 2. a tensile load is defined as a pul ling load applied to the ihs in a direction normal to the ihs surface. table 3-1. processor loading specifications parameter minimum maximum notes static 44 n [10 lbf] 445 n [100 lbf] 1, 2, 3 dynamic 890 n [200 lbf] 1, 3, 4 transient 667 n [150 lbf] 1, 3, 5 table 3-2. package handling guidelines parameter maximum recommended notes shear 356 n [80 lbf] 1, 4 tensile 156 n [35 lbf] 2, 4 torque 8 n-m [70 lbf-in] 3, 4
32 mobile intel? pentium? 4 processo r supporting hyper-threading technology on 90-nm process technology datasheet package mechanical specifications 3. a torque load is defined as a twisting load applied to th e ihs in an axis of rotation normal to the ihs top surface. 4. these guidelines are based on limited testing for design characterization. 3.1.5 package insertion specifications the processor can be inserted into and remove d from a mpga479 socket 15 times. the socket should meet the mpga479 requirements detailed in the mpga479, mpga478a, mpga478b, mpga478c, and mpga476 socket design guidelines . 3.1.6 processor mass specification the typical mass of the processor is 19 g [0.67 oz ]. this mass [weight] includes all the components that are included in the package. 3.1.7 processor materials table 3-3 lists some of the package comp onents and associated materials. 3.1.8 processor markings figure 3-4 shows the topside markings on the proces sor. these diagrams are to aid in the identification of the processor. table 3-3. processor materials component material integrated heat spreader (ihs) nickel plated copper substrate fiber reinforced resin substrate pins gold plated copper figure 3-4. processor top-side markings 2-d matrix mark m c `03 intel confidential qyyy es xxxxx i zzzzzzzz ffffffff qdf / country of assy fpo product code aaaaaaaa-nnnn atpo ? serial #
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 33 package mechanical specifications 3.1.9 processor pin-out coordinates figure 3-5 shows the top view of the processor pin co ordinates. the coordinates are referred to throughout the document to identify processor pins. figure 3-5. processor pin-out coordinates, top view processor top view af ae ad ac ab aa y w v u t r p n m k j h g f e d c b a l af ae ad ac ab aa y w v u t r p n m k j h g f e d c b a l 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 common clock v cc / v ss data address clocks v cc / v ss async/tap = v cc = v ss = signal/other = gtlref
34 mobile intel? pentium? 4 processo r supporting hyper-threading technology on 90-nm process technology datasheet package mechanical specifications
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 35 pin listing and signal descriptions 4 pin listing and signal descriptions 4.1 processor pin assignments this chapter provides the processor pinout and signal description. table 4-1 provides the pinout arranged alphabetically by signal name and table 4-2 provides the pinout arranged numerically by pin number. the pinout footprint is shown in figure 4-1 and figure 4-2 . table 4-1. alphabetical pin assignments pin name pin number signal buffer type direction pin name pin number signal buffer type direction a03# k2 source synch input/output a31# u4 source synch input/output a04# k4 source synch input/output a32# v3 source synch input/output a05# l6 source synch input/output a33# w2 source synch input/output a06# k1 source synch input/output a34# y1 source synch input/output a07# l3 source synch input/output a35# ab1 source synch input/output a08# m6 source synch input/output a20m# c6 asynch gtl+ input a09# l2 source synch input/output ads# g1 common clock input/output a10# m3 source synch input/output adstb0# l5 source synch input/output a11# m4 source synch input/output adstb1# r5 source synch input/output a12# n1 source synch input/output ap0# ac1 common clock input/output a13# m1 source synch input/output ap1# v5 common clock input/output a14# n2 source synch input/output bclk0 af22 bus clock input a15# n4 source synch input/output bclk1 af23 bus clock input a16# n5 source synch input/output binit# aa3 common clock input/output a17# t1 source synch input/output bnr# g2 common clock input/output a18# r2 source synch input/output bootselect ad1 power/other input a19# p3 source synch input/output bpm0# ac6 common clock input/output a20# p4 source synch input/output bpm1# ab5 common clock input/output a21# r3 source synch input/output bpm2# ac4 common clock input/output a22# t2 source synch input/output bpm3# y6 common clock input/output a23# u1 source synch input/output bpm4# aa5 common clock input/output a24# p6 source synch input/output bpm5# ab4 common clock input/output a25# u3 source synch input/output bpri# d2 common clock input a26# t4 source synch input/output br0# h6 common clock input/output a27# v2 source synch input/output bsel0 ad6 power/other output a28# r6 source synch input/output bsel1 ad5 power/other output a29# w1 source synch input/output comp0 l24 power/other input a30# t5 source synch input/output comp1 p1 power/other input
36 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet pin listing and signal descriptions pin name pin number signal buffer type direction pin name pin number signal buffer type direction d0# b21 source synch input/output d39# n25 source synch input/output d01# b22 source synch input/output d40# r21 source synch input/output d02# a23 source synch input/output d41# p24 source synch input/output d03# a25 source synch input/output d42# r25 source synch input/output d04# c21 source synch input/output d43# r24 source synch input/output d05# d22 source synch input/output d44# t26 source synch input/output d06# b24 source synch input/output d45# t25 source synch input/output d07# c23 source synch input/output d46# t22 source synch input/output d08# c24 source synch input/output d47# t23 source synch input/output d09# b25 source synch input/output d48# u26 source synch input/output d10# g22 source synch input/output d49# u24 source synch input/output d11# h21 source synch input/output d50# u23 source synch input/output d12# c26 source synch input/output d51# v25 source synch input/output d13# d23 source synch input/output d52# u21 source synch input/output d14# j21 source synch input/output d53# v22 source synch input/output d15# d25 source synch input/output d54# v24 source synch input/output d16# h22 source synch input/output d55# w26 source synch input/output d17# e24 source synch input/output d56# y26 source synch input/output d18# g23 source synch input/output d57# w25 source synch input/output d19# f23 source synch input/output d58# y23 source synch input/output d20# f24 source synch input/output d59# y24 source synch input/output d21# e25 source synch input/output d60# y21 source synch input/output d22# f26 source synch input/output d61# aa25 source synch input/output d23# d26 source synch input/output d62# aa22 source synch input/output d24# l21 source synch input/output d63# aa24 source synch input/output d25# g26 source synch input/output dbi0# e21 source synch input/output d26# h24 source synch input/output dbi1# g25 source synch input/output d27# m21 source synch input/output dbi2# p26 source synch input/output d28# l22 source synch input/output dbi3# v21 source synch input/output d29# j24 source synch input/output dbr# ae25 power/other output d30# k23 source synch input/outpu t dbsy# h5 common clock input/output d31# h25 source synch input/output defer# e2 common clock input d32# m23 source synch input/output dp0# j26 common clock input/output d33# n22 source synch input/output dp1# k25 common clock input/output d34# p21 source synch input/output dp2# k26 common clock input/output d35# m24 source synch input/output dp3# l25 common clock input/output d36# n23 source synch input/output dpslp# ad25 asynch gtl+ input d37# m26 source synch input/output drdy# h2 common clock input/output d38# n26 source synch input/output dstbn0# e22 source synch input/output dstbn1# k22 source synch input/output
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 37 pin listing and signal descriptions pin name pin number signal buffer type direction pin name pin number signal buffer type direction dstbn2# r22 source synch input/output rs2# f4 common clock input dstbn3# w22 source synch input/output rsp# ab2 common clock input dstbp0# f21 source synch input/output sktocc# af26 power/other output dstbp1# j23 source synch input/output slp# ab26 asynch gtl+ input dstbp2# p23 source synch input/output smi# b5 asynch gtl+ input dstbp3# w23 source synch input/output stpclk# y4 asynch gtl+ input ferr#/ pbe# b6 asynch agl+ output tck d4 tap input gtlref aa21 power/other input tdi c1 tap input gtlref aa6 power/other input tdo d5 tap output gtlref f20 power/other input testhi0 ad24 power/other input gtlref f6 power/other input testhi1 aa2 power/other input hit# f3 common clock input/output testhi10 y3 power/other input hitm# e3 common clock input/output testhi11 a6 power/other input ierr# ac3 asynch gtl+ output testhi2 ac21 power/other input ignne# b2 asynch gtl+ input testhi3 ac20 power/other input init# w5 asynch gtl+ input testhi4 ac24 power/other input itp_clk0 ac26 tap input testhi5 ac23 power/other input itp_clk1 ad26 tap input testhi6 aa20 power/other input lint0 d1 asynch gtl+ input testhi7 ab22 power/other input lint1 e5 asynch gtl+ input testhi8 u6 power/other input lock# g4 common clock input/output testhi9 w4 power/other input mcerr# v6 common clock input/output thermda b3 power/other optimized/ compat# ae26 power/other input thermdc c4 power/other prochot# c3 asynch gtl+ input/output thermtrip# a2 asynch gtl+ output pwrgood ab23 power/other input tms f7 tap input req0# j1 source synch input/output trdy# j6 common clock input req1# k5 source synch input/output trst# e6 tap input req2# j4 source synch input/output vcc a10 power/other req3# j3 source synch input/output vcc a12 power/other req4# h3 source synch input/output vcc a14 power/other reserved a22 vcc a16 power/other reserved a7 vcc a18 power/other reserved ae21 vcc a20 power/other reserved af24 vcc a8 power/other reserved af25 vcc aa10 power/other reset# ab25 common clock input vcc aa12 power/other rs0# f1 common clock input vcc aa14 power/other rs1# g5 common clock input vcc aa16 power/other
38 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet pin listing and signal descriptions pin name pin number signal buffer type direction pin name pin number signal buffer type direction vcc aa18 power/other vcc af9 power/other vcc aa8 power/other vcc b11 power/other vcc ab11 power/other vcc b13 power/other vcc ab13 power/other vcc b15 power/other vcc ab15 power/other vcc b17 power/other vcc ab17 power/other vcc b19 power/other vcc ab19 power/other vcc b7 power/other vcc ab7 power/other vcc b9 power/other vcc ab9 power/other vcc c10 power/other vcc ac10 power/other vcc c12 power/other vcc ac12 power/other vcc c14 power/other vcc ac14 power/other vcc c16 power/other vcc ac16 power/other vcc c18 power/other vcc ac18 power/other vcc c20 power/other vcc ac8 power/other vcc c8 power/other vcc ad11 power/other vcc d11 power/other vcc ad13 power/other vcc d13 power/other vcc ad15 power/other vcc d15 power/other vcc ad17 power/other vcc d17 power/other vcc ad19 power/other vcc d19 power/other vcc ad7 power/other vcc d7 power/other vcc ad9 power/other vcc d9 power/other vcc ae10 power/other vcc e10 power/other vcc ae12 power/other vcc e12 power/other vcc ae14 power/other vcc e14 power/other vcc ae16 power/other vcc e16 power/other vcc ae18 power/other vcc e18 power/other vcc ae20 power/other vcc e20 power/other vcc ae6 power/other vcc e8 power/other vcc ae8 power/other vcc f11 power/other vcc af11 power/other vcc f13 power/other vcc af13 power/other vcc f15 power/other vcc af15 power/other vcc f17 power/other vcc af17 power/other vcc f19 power/other vcc af19 power/other vcc f9 power/other vcc af2 power/other vcca ae23 power/other vcc af21 power/other vcciopll ad20 power/other vcc af5 power/other vccsense a5 power/other output vcc af7 power/other vccvid af4 power/other input
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 39 pin listing and signal descriptions pin name pin number signal buffer type direction pin name pin number signal buffer type direction vccvidlb af3 power/other input vss ab8 power/other vid0 ae5 power/other output vss ac11 power/other vid1 ae4 power/other output vss ac13 power/other vid2 ae3 power/other output vss ac15 power/other vid3 ae2 power/other output vss ac17 power/other vid4 ae1 power/other output vss ac19 power/other vid5 ad3 power/other output vss ac2 power/other vidpwrgd ad2 power/other input vss ac22 power/other vss a11 power/other vss ac25 power/other vss a13 power/other vss ac5 power/other vss a15 power/other vss ac7 power/other vss a17 power/other vss ac9 power/other vss a19 power/other vss ad10 power/other vss a21 power/other vss ad12 power/other vss a24 power/other vss ad14 power/other vss a26 power/other vss ad16 power/other vss a3 power/other vss ad18 power/other vss a9 power/other vss ad21 power/other vss aa1 power/other vss ad23 power/other vss aa11 power/other vss ad4 power/other vss aa13 power/other vss ad8 power/other vss aa15 power/other vss ae11 power/other vss aa17 power/other vss ae13 power/other vss aa19 power/other vss ae15 power/other vss aa23 power/other vss ae17 power/other vss aa26 power/other vss ae19 power/other vss aa4 power/other vss ae22 power/other vss aa7 power/other vss ae24 power/other vss aa9 power/other vss ae7 power/other vss ab10 power/other vss ae9 power/other vss ab12 power/other vss af1 power/other vss ab14 power/other vss af10 power/other vss ab16 power/other vss af12 power/other vss ab18 power/other vss af14 power/other vss ab20 power/other vss af16 power/other vss ab21 power/other vss af18 power/other vss ab24 power/other vss af20 power/other vss ab3 power/other vss af6 power/other vss ab6 power/other vss af8 power/other
40 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet pin listing and signal descriptions pin name pin number signal buffer type direction pin name pin number signal buffer type direction vss b10 power/other vss e26 power/other vss b12 power/other vss e4 power/other vss b14 power/other vss e7 power/other vss b16 power/other vss e9 power/other vss b18 power/other vss f10 power/other vss b20 power/other vss f12 power/other vss b23 power/other vss f14 power/other vss b26 power/other vss f16 power/other vss b4 power/other vss f18 power/other vss b8 power/other vss f2 power/other vss c11 power/other vss f22 power/other vss c13 power/other vss f25 power/other vss c15 power/other vss f5 power/other vss c17 power/other vss f8 power/other vss c19 power/other vss g21 power/other vss c2 power/other vss g24 power/other vss c22 power/other vss g3 power/other vss c25 power/other vss g6 power/other vss c5 power/other vss h1 power/other vss c7 power/other vss h23 power/other vss c9 power/other vss h26 power/other vss d10 power/other vss h4 power/other vss d12 power/other vss j2 power/other vss d14 power/other vss j22 power/other vss d16 power/other vss j25 power/other vss d18 power/other vss j5 power/other vss d20 power/other vss k21 power/other vss d21 power/other vss k24 power/other vss d24 power/other vss k3 power/other vss d3 power/other vss k6 power/other vss d6 power/other vss l1 power/other vss d8 power/other vss l23 power/other vss e1 power/other vss l26 power/other vss e11 power/other vss l4 power/other vss e13 power/other vss m2 power/other vss e15 power/other vss m22 power/other vss e17 power/other vss m25 power/other vss e19 power/other vss m5 power/other vss e23 power/other vss n21 power/other
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 41 pin listing and signal descriptions pin name pin number signal buffer type direction vss n24 power/other vss n3 power/other vss n6 power/other vss p2 power/other vss p22 power/other vss p25 power/other vss p5 power/other vss r1 power/other vss r23 power/other vss r26 power/other vss r4 power/other vss t21 power/other vss t24 power/other vss t3 power/other vss t6 power/other vss u2 power/other vss u22 power/other vss u25 power/other vss u5 power/other vss v1 power/other vss v23 power/other vss v26 power/other vss v4 power/other vss w21 power/other vss w24 power/other vss w3 power/other vss w6 power/other vss y2 power/other vss y22 power/other vss y25 power/other vss y5 power/other vssa ad22 power/other vsssense a4 power/other output
pin listing and signal descriptions 42 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet table 4-2. numerical pin assignment (sheet 1 of 12) pin # pin name signal buffer type direction a2 thermtrip# asynch gtl+ output a3 vss power/other a4 vss_sense power/other output a5 vcc_sense power/other output a6 testhi11 power/other input a7 reserved a8 vcc power/other a9 vss power/other a10 vcc power/other a11 vss power/other a12 vcc power/other a13 vss power/other a14 vcc power/other a15 vss power/other a16 vcc power/other a17 vss power/other a18 vcc power/other a19 vss power/other a20 vcc power/other a21 vss power/other a22 reserved a23 d2# source synch input/output a24 vss power/other a25 d3# source synch input/output a26 vss power/other b2 ignne# asynch gtl+ input b3 thermda power/other b4 vss power/other b5 smi# asynch gtl+ input b6 ferr#/pbe# asynch agl+ output b7 vcc power/other b8 vss power/other b9 vcc power/other b10 vss power/other b11 vcc power/other b12 vss power/other b13 vcc power/other b14 vss power/other b15 vcc power/other b16 vss power/other b17 vcc power/other b18 vss power/other b19 vcc power/other b20 vss power/other b21 d0# source synch input/output b22 d1# source synch input/output b23 vss power/other b24 d6# source synch input/output b25 d9# source synch input/output b26 vss power/other c1 tdi tap input c2 vss power/other c3 prochot# asynch gtl+ input/output c4 thermdc power/other c5 vss power/other c6 a20m# asynch gtl+ input c7 vss power/other c8 vcc power/other c9 vss power/other c10 vcc power/other c11 vss power/other c12 vcc power/other c13 vss power/other c14 vcc power/other c15 vss power/other c16 vcc power/other c17 vss power/other c18 vcc power/other c19 vss power/other c20 vcc power/other c21 d4# source synch input/output c22 vss power/other c23 d7# source synch input/output c24 d8# source synch input/output c25 vss power/other c26 d12# source synch input/output d1 lint0 asynch gtl+ input d2 bpri# common clock input d3 vss power/other d4 tck tap input table 4-2. numerical pin assignment (sheet 2 of 12) pin # pin name signal buffer type direction
pin listing and signal descriptions mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm pr ocess technology datasheet 43 d5 tdo tap output d6 vss power/other d7 vcc power/other d8 vss power/other d9 vcc power/other d10 vss power/other d11 vcc power/other d12 vss power/other d13 vcc power/other d14 vss power/other d15 vcc power/other d16 vss power/other d17 vcc power/other d18 vss power/other d19 vcc power/other d20 vss power/other d21 vss power/other d22 d5# source synch input/output d23 d13# source synch input/output d24 vss power/other d25 d15# source synch input/output d26 d23# source synch input/output e1 vss power/other e2 defer# common clock input e3 hitm# common clock input/output e4 vss power/other e5 lint1 asynch gtl+ input e6 trst# tap input e7 vss power/other e8 vcc power/other e9 vss power/other e10 vcc power/other e11 vss power/other e12 vcc power/other e13 vss power/other e14 vcc power/other e15 vss power/other e16 vcc power/other e17 vss power/other e18 vcc power/other table 4-2. numerical pin assignment (sheet 3 of 12) pin # pin name signal buffer type direction e19 vss power/other e20 vcc power/other e21 dbi0# source synch input/output e22 dstbn0# source synch input/output e23 vss power/other e24 d17# source synch input/output e25 d21# source synch input/output e26 vss power/other f1 rs0# common clock input f2 vss power/other f3 hit# common clock input/output f4 rs2# common clock input f5 vss power/other f6 gtlref power/other input f7 tms tap input f8 vss power/other f9 vcc power/other f10 vss power/other f11 vcc power/other f12 vss power/other f13 vcc power/other f14 vss power/other f15 vcc power/other f16 vss power/other f17 vcc power/other f18 vss power/other f19 vcc power/other f20 gtlref power/other input f21 dstbp0# source synch input/output f22 vss power/other f23 d19# source synch input/output f24 d20# source synch input/output f25 vss power/other f26 d22# source synch input/output g1 ads# common clock input/output g2 bnr# common clock input/output g3 vss power/other g4 lock# common clock input/output g5 rs1# common clock input g6 vss power/other table 4-2. numerical pin assignment (sheet 4 of 12) pin # pin name signal buffer type direction
pin listing and signal descriptions 44 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet g21 vss power/other g22 d10# source synch input/output g23 d18# source synch input/output g24 vss power/other g25 dbi1# source synch input/output g26 d25# source synch input/output h1 vss power/other h2 drdy# common clock input/output h3 req4# source synch input/output h4 vss power/other h5 dbsy# common clock input/output h6 br0# common clock input/output h21 d11# source synch input/output h22 d16# source synch input/output h23 vss power/other h24 d26# source synch input/output h25 d31# source synch input/output h26 vss power/other j1 req0# source synch input/output j2 vss power/other j3 req3# source synch input/output j4 req2# source synch input/output j5 vss power/other j6 trdy# common clock input j21 d14# source synch input/output j22 vss power/other j23 dstbp1# source synch input/output j24 d29# source synch input/output j25 vss power/other j26 dp0# common clock input/output k1 a6# source synch input/output k2 a3# source synch input/output k3 vss power/other k4 a4# source synch input/output k5 req1# source synch input/output k6 vss power/other k21 vss power/other k22 dstbn1# source synch input/output k23 d30# source synch input/output k24 vss power/other table 4-2. numerical pin assignment (sheet 5 of 12) pin # pin name signal buffer type direction k25 dp1# common clock input/output k26 dp2# common clock input/output l1 vss power/other l2 a9# source synch input/output l3 a7# source synch input/output l4 vss power/other l5 adstb0# source synch input/output l6 a5# source synch input/output l21 d24# source synch input/output l22 d28# source synch input/output l23 vss power/other l24 comp0 power/other input l25 dp3# common clock input/output l26 vss power/other m1 a13# source synch input/output m2 vss power/other m3 a10# source synch input/output m4 a11# source synch input/output m5 vss power/other m6 a8# source synch input/output m21 d27# source synch input/output m22 vss power/other m23 d32# source synch input/output m24 d35# source synch input/output m25 vss power/other m26 d37# source synch input/output n1 a12# source synch input/output n2 a14# source synch input/output n3 vss power/other n4 a15# source synch input/output n5 a16# source synch input/output n6 vss power/other n21 vss power/other n22 d33# source synch input/output n23 d36# source synch input/output n24 vss power/other n25 d39# source synch input/output n26 d38# source synch input/output p1 comp1 power/other input p2 vss power/other table 4-2. numerical pin assignment (sheet 6 of 12) pin # pin name signal buffer type direction
pin listing and signal descriptions mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm pr ocess technology datasheet 45 p3 a19# source synch input/output p4 a20# source synch input/output p5 vss power/other p6 a24# source synch input/output p21 d34# source synch input/output p22 vss power/other p23 dstbp#2 source synch input/output p24 d41# source synch input/output p25 vss power/other p26 dbi2# source synch input/output r1 vss power/other r2 a18# source synch input/output r3 a21# source synch input/output r4 vss power/other r5 adstb1# source synch input/output r6 a28# source synch input/output r21 d40# source synch input/output r22 dstbn#2 source synch input/output r23 vss power/other r24 d43# source synch input/output r25 d42# source synch input/output r26 vss power/other t1 a17# source synch input/output t2 a22# source synch input/output t3 vss power/other t4 a26# source synch input/output t5 a30# source synch input/output t6 vss power/other t21 vss power/other t22 d46# source synch input/output t23 d47# source synch input/output t24 vss power/other t25 d45# source synch input/output t26 d44# source synch input/output u1 a23# source synch input/output u2 vss power/other u3 a25# source synch input/output u4 a31# source synch input/output u5 vss power/other u6 testhi8 power/other input table 4-2. numerical pin assignment (sheet 7 of 12) pin # pin name signal buffer type direction u21 d52# source synch input/output u22 vss power/other u23 d50# source synch input/output u24 d49# source synch input/output u25 vss power/other u26 d48# source synch input/output v1 vss power/other v2 a27# source synch input/output v3 a32# source synch input/output v4 vss power/other v5 ap1# common clock input/output v6 mcerr# common clock input/output v21 dbi3# source synch input/output v22 d53# source synch input/output v23 vss power/other v24 d54# source synch input/output v25 d51# source synch input/output v26 vss power/other w1 a29# source synch input/output w2 a33# source synch input/output w3 vss power/other w4 testhi9 power/other input w5 init# asynch gtl+ input w6 vss power/other w21 vss power/other w22 dstbn3# source synch input/output w23 dstbp3# source synch input/output w24 vss power/other w25 d57# source synch input/output w26 d55# source synch input/output y1 a34# source synch input/output y2 vss power/other y3 testhi10 power/other input y4 stpclk# asynch gtl+ input y5 vss power/other y6 bpm3# common clock input/output y21 d60# source synch input/output y22 vss power/other y23 d58# source synch input/output y24 d59# source synch input/output table 4-2. numerical pin assignment (sheet 8 of 12) pin # pin name signal buffer type direction
pin listing and signal descriptions 46 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet y25 vss power/other y26 d56# source synch input/output aa1 vss power/other aa2 testhi1 power/other input aa3 binit# common clock input/output aa4 vss power/other aa5 bpm4# common clock input/output aa6 gtlref power/other input aa7 vss power/other aa8 vcc power/other aa9 vss power/other aa10 vcc power/other aa11 vss power/other aa12 vcc power/other aa13 vss power/other aa14 vcc power/other aa15 vss power/other aa16 vcc power/other aa17 vss power/other aa18 vcc power/other aa19 vss power/other aa20 testhi6 power/other input aa21 gtlref power/other input aa22 d62# source synch input/output aa23 vss power/other aa24 d63# source synch input/output aa25 d61# source synch input/output aa26 vss power/other ab1 a35# source synch input/output ab2 rsp# common clock input ab3 vss power/other ab4 bpm5# common clock input/output ab5 bpm1# common clock input/output ab6 vss power/other ab7 vcc power/other ab8 vss power/other ab9 vcc power/other ab10 vss power/other ab11 vcc power/other ab12 vss power/other table 4-2. numerical pin assignment (sheet 9 of 12) pin # pin name signal buffer type direction ab13 vcc power/other ab14 vss power/other ab15 vcc power/other ab16 vss power/other ab17 vcc power/other ab18 vss power/other ab19 vcc power/other ab20 vss power/other ab21 vss power/other ab22 testhi7 power/other input ab23 pwrgood power/other input ab24 vss power/other ab25 reset# common clock input ab26 slp# asynch gtl+ input ac1 ap0# common clock input/output ac2 vss power/other ac3 ierr# asynch gtl+ output ac4 bpm2# common clock input/output ac5 vss power/other ac6 bpm0# common clock input/output ac7 vss power/other ac8 vcc power/other ac9 vss power/other ac10 vcc power/other ac11 vss power/other ac12 vcc power/other ac13 vss power/other ac14 vcc power/other ac15 vss power/other ac16 vcc power/other ac17 vss power/other ac18 vcc power/other ac19 vss power/other ac20 testhi3 power/other input ac21 testhi2 power/other input ac22 vss power/other ac23 testhi5 power/other input ac24 testhi4 power/other input ac25 vss power/other ac26 itp_clk0 tap input table 4-2. numerical pin assignment (sheet 10 of 12) pin # pin name signal buffer type direction
pin listing and signal descriptions mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm pr ocess technology datasheet 47 ad1 bootselect power/other input ad2 vidpwrgd power/other input ad3 vid5 power/other output ad4 vss power/other ad5 bsel1 power/other output ad6 bsel0 power/other output ad7 vcc power/other ad8 vss power/other ad9 vcc power/other ad10 vss power/other ad11 vcc power/other ad12 vss power/other ad13 vcc power/other ad14 vss power/other ad15 vcc power/other ad16 vss power/other ad17 vcc power/other ad18 vss power/other ad19 vcc power/other ad20 vcciopll power/other ad21 vss power/other ad22 vssa power/other ad23 vss power/other ad24 testhi0 power/other input ad25 dpslp# asynch gtl+ input ad26 itp_clk1 tap input ae1 vid4 power/other output ae2 vid3 power/other output ae3 vid2 power/other output ae4 vid1 power/other output ae5 vid0 power/other output ae6 vcc power/other ae7 vss power/other ae8 vcc power/other ae9 vss power/other ae10 vcc power/other ae11 vss power/other ae12 vcc power/other ae13 vss power/other ae14 vcc power/other table 4-2. numerical pin assignment (sheet 11 of 12) pin # pin name signal buffer type direction ae15 vss power/other ae16 vcc power/other ae17 vss power/other ae18 vcc power/other ae19 vss power/other ae20 vcc power/other ae21 reserved ae22 vss power/other ae23 vcca power/other ae24 vss power/other ae25 dbr# power/other output ae26 optimized/ compat# power/other input af1 vss power/other af2 vcc power/other af3 vccvidlb power/other input af4 vccvid power/other input af5 vcc power/other af6 vss power/other af7 vcc power/other af8 vss power/other af9 vcc power/other af10 vss power/other af11 vcc power/other af12 vss power/other af13 vcc power/other af14 vss power/other af15 vcc power/other af16 vss power/other af17 vcc power/other af18 vss power/other af19 vcc power/other af20 vss power/other af21 vcc power/other af22 bclk0 bus clock input af23 bclk1 bus clock input af24 reserved af25 reserved af26 sktocc# power/other output table 4-2. numerical pin assignment (sheet 12 of 12) pin # pin name signal buffer type direction
48 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet pin listing and signal descriptions figure 4-1. pinout diagram (top view?left side) 26 25 24 23 22 21 20 19 18 17 16 15 14 af sktocc# reserved reserved bclk1 bclk0 vcc vss vcc vss vcc vss vcc vss af ae optimized/ compat# dbr# vss vcca vss reserved vcc vss vcc vss vcc vss vcc ae ad itp_clk1 dpslp# testhi0 vss vssa vss vcciopll vcc vss vcc vss vcc vss ad ac itp_clk0 vss testhi4 testhi5 vss testhi2 testhi3 vss vcc vss vcc vss vcc ac ab slp# reset# vss pwr good testhi7 vss vss vcc vss vcc vss vcc vss ab aa vss d61# d63# vss d62# gtlref testhi6 vss vcc vss vcc vss vcc aa y d56# vss d59# d58# vss d60# y w d55# d57# vss dstbp3# dstbn3# vss w v vss d51# d54# vss d53# dbi3# v u d48# vss d49# d50# vss d52# u t d44# d45# vss d47# d46# vss t r vss d42# d43# vss dstbn2# d40# r p dbi2# vss d41# dstbp2# vss d34# p n d38# d39# vss d36# d33# vss n m d37# vss d35# d32# vss d27# m l vss dp3# comp0 vss d28# d24# l k dp2# dp1# vss d30# dstbn1# vss k j dp0# vss d29# dstbp1# vss d14# j h vss d31# d26# vss d16# d11# h g d25# dbi1# vss d18# d10# vss g f d22# vss d20# d19# vss dstbp0# gtlref vcc vss vcc vss vcc vss f e vss d21# d17# vss dstbn0# dbi0# vcc vss vcc vss vcc vss vcc e d d23# d15# vss d13# d5# vss vss vcc vss vcc vss vcc vss d c d12# vss d8# d7# vss d4# vcc vss vcc vss vcc vss vcc c b vss d9# d6# vss d1# d0# vss vcc vss vcc vss vcc vss b a vss d3# vss d2# reserved vss vcc vss vcc vss vcc vss vcc a 26 25 24 23 22 21 20 19 18 17 16 15 14
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 49 pin listing and signal descriptions figure 4-2. pinout diagra m (top view?right side) 13 12 11 10 9 8 7 6 5 4 3 2 1 af vcc vss vcc vss vcc vss vcc vss vcc vccvid vccvidlb vcc vss af ae vss vcc vss vcc vss vcc vss vcc vid0 vid1 vid2 vid3 vid4 ae ad vcc vss vcc vss vcc vss vcc bsel0 bsel1 vss vid5 vidpwrgd boot select ad ac vss vcc vss vcc vss vcc vss bpm0# vss bpm2# ierr# vss ap0# ac ab vcc vss vcc vss vcc vss vcc vss bpm1# bpm5# vss rsp# a35# ab aa vss vcc vss vcc vss vcc vss gtlref bpm4# vss binit# testhi1 vss aa y bpm3# vss stpclk# testhi10 vss a34# y w vss init# testhi9 vss a33# a29# w v mcerr# ap1# vss a32# a27# vss v u testhi8 vss a31# a25# vss a23# u t vss a30# a26# vss a22# a17# t r a28# adstb1# vss a21# a18# vss r p a24# vss a20# a19# vss comp1 p n vss a16# a15# vss a14# a12# n m a8# vss a11# a10# vss a13# m l a5# adstb0# vss a7# a9# vss l k vss req1# a4# vss a3# a6# k j trdy# vss req2# req3# vss req0# j h br0# dbsy# vss req4# drdy# vss h g vss rs1# lock# vss bnr# ads# g f vcc vss vcc vss vcc vss tms gtlref vss rs2# hit# vss rs0# f e vss vcc vss vcc vss vcc vss trst# lint1 vss hitm# defer# vss e d vcc vss vcc vss vcc vss vcc vss tdo tck vss bpri# lint0 d c vss vcc vss vcc vss vcc vss a20m# vss thermdc prochot# vss tdi c b vcc vss vcc vss vcc vss vcc ferr#/ pbe# smi# vss thermda ignne# b a vss vcc vss vcc vss vcc reserved testhi11 vcc_sense vss_sense vss thermtrip# a 13 12 11 10 9 8 7 6 5 4 3 2 1
50 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet pin listing and signal descriptions 4.2 alphabetical signals reference table 4-3. signal description (sheet 1 of 8) name type description a[35:3]# input/ output a[35:3]# (address) define a 2 36 -byte physical memory a ddress space. in sub- phase 1 of the address phase, these pins transmit the address of a transaction. in sub-phase 2, these pins transmit trans action type information. these signals must connect the appropriate pins of all agents on the processor front side bus. a[35:3]# are protected by parity signals ap[1:0]#. a[35:3]# are source synchronous signals and are latched into th e receiving buffers by adstb[1:0]#. on the active-to-inactive transition of reset#, the processor samples a subset of the a[35:3]# pins to determine power-on configuration. see section 6.1 for more details. a20m# input if a20m# (address-20 mask) is asserted, the processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. as serting a20m# emulates the 8086 processor's address wrap-around at the 1-mbyte boundary. assertion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the trdy# assertion of the corresponding i nput/output write bus transaction. ads# input/ output ads# (address strobe) is asserted to indicate the validity of the transaction address on the a[35:3]# and req[4:0]# pins. all bus agents observe the ads# activation to begin parity checking, prot ocol checking, address decode, internal snoop, or deferred reply id match operations associated with the new transaction. adstb[1:0]# input/ output address strobes are used to latch a[35:3]# and req[4:0]# on their rising and falling edges. strobes are associat ed with signals as shown below. ap[1:0]# input/ output ap[1:0]# (address parity) are driven by the request initiator along with ads#, a[35:3]#, and the transaction type on the req[4:0]#. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this allows parity to be high when all the covered signals are high. ap[1:0]# should connect t he appropriate pins of all processor front side bus agents. the following tabl e defines the coverage model of these signals. bclk[1:0] input the differential pair bclk (bus clock) determines the front side bus frequency. all processor front side bus agents must receive these signals to drive their outputs and latch their inputs. all external timing parameters are spec ified with respect to the rising edge of bclk0 crossing v cross . signals associated strobe req[4:0]#, a[16:3]# adstb0# a[35:17]# adstb1# request signals subphase 1 subphase 2 a[35:24]# ap0# ap1# a[23:3]# ap1# ap0# req[4:0]# ap1# ap0#
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 51 pin listing and signal descriptions binit# input/ output binit# (bus initialization) may be ob served and driven by all processor front side bus agents and if used, must connect the appropriate pins of all such agents. if the binit# driver is enabled duri ng power-on configuration, binit# is asserted to signal any bus condition t hat prevents reliable future operation. if binit# observation is enabled during pow er-on configuration, and binit# is sampled asserted, symmetric agents rese t their bus lock# activity and bus request arbitration state machines. the bus agents do not reset their ioq and transaction tracking state machines upon obs ervation of binit# activation. once the binit# assertion has been observed, the bus agents will re-arbitrate for the front side bus and attempt completion of their bus queue and ioq entries. if binit# observation is disabled during power-on configuration, a central agent may handle an assertion of binit# as appropriate to the error handling architecture of the system. bnr# input/ output bnr# (block next request) is used to as sert a bus stall by any bus agent who is unable to accept new bus transactions. duri ng a bus stall, the current bus owner cannot issue any new transactions. bootselect input this input is required to determine whether the processor is installed in a platform that supports the processor. the processor will not operate if this pin is low. this input has a weak internal pullup. bpm[5:0]# input/ output bpm[5:0]# (breakpoint monitor) are breakpoint and performance monitor signals. they are outputs from the proc essor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. bpm[5:0]# should connect t he appropriate pins of all processor front side bus agents. bpm4# provides prdy# (probe ready) func tionality for the tap port. prdy# is a processor output used by debug tools to determine processor debug readiness. bpm5# provides preq# (probe request) functionality for the tap port. preq# is used by debug tools to request debug operation of the processor. please refer to the intel? 852gme and intel? 852pm chipset platforms design guide for more detailed information. these signals do not have on-die termination. refer to section 2.4 , and the intel? 852gme and intel? 852pm chipset platforms design guide for termination requirements. bpri# input bpri# (bus priority request) is used to arbitrate for ownership of the processor front side bus. it must connect the appropri ate pins of all proc essor front side bus agents. observing bpri# active (as asse rted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed, then rel eases the bus by deasserting bpri#. br0# input/ output br0# drives the breq0# signal in the sy stem and is used by the processor to request the bus. during power-on configurat ion this pin is sampled to determine the agent id = 0. this signal does not have on-die termination and must be terminated. bsel[1:0] output the bclk[1:0] frequency select signals bsel[1:0] are used to select the processor input clock frequency. table 2-6 defines the possible combinations of the signals and the frequency associated with each combination. the required frequency is determined by the processo r, chipset and clock synthesizer. all agents must operate at the same frequency. for more information about these pins, including termination recommendations refer to section 2.8 and the appropriate platform design guidelines. comp[1:0] analog comp[1:0] must be terminated on the syste m board using precision resistors. refer to the intel? 852gme and intel? 852pm chipset platforms design guide for details on implementation. table 4-3. signal description (sheet 2 of 8) name type description
52 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet pin listing and signal descriptions d[63:0]# input/ output d[63:0]# (data) are the data signals. th ese signals provide a 64-bit data path between the processor front side bus agents, and must connect the appropriate pins on all such agents. the data driver asserts drdy# to indicate a valid data transfer. d[63:0]# are quad-pumped signals and will th us be driven four times in a common clock period. d[63:0]# are latched off the falling edge of both dstbp[3:0]# and dstbn[3:0]#. each group of 16 data signals correspond to a pair of one dstbp# and one dstbn#. the following table shows the grouping of data signals to data strobes and dbi#. furthermore, the dbi# pins determine the polarity of the data signals. each group of 16 data signals corresponds to one dbi# signal. when the dbi# signal is active, the corresponding data group is inverted and therefore sampled active high. dbi[3:0]# input/ output dbi[3:0]# are source synchronous and indicate the polarity of the d[63:0]# signals.the dbi[3:0]# signals are activa ted when the data on the data bus is inverted. if more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group. dbr# output dbr# is used only in processor systems where no debug port is implemented on the system board. dbr# is used by a debug port interposer so that an in-target probe can drive system reset. if a debug port is implemented in the system, dbr# is a no connect in the system. dbr# is not a processor signal. dbsy# input/ output dbsy# (data bus busy) is asserted by t he agent responsible for driving data on the processor front side bus to indicate t hat the data bus is in use. the data bus is released after dbsy# is deasserted. this signal must connect the appropriate pins on all processor front side bus agents. defer# input defer# is asserted by an agent to i ndicate that a transaction cannot be guaranteed in-order completion. assertion of defer# is normally the responsibility of the addressed memory or input/output agent. this signal must connect the appropriate pins of all processor front side bus agents. dp[3:0]# input/ output dp[3:0]# (data parity) provide parity protection for the d[63:0]# signals. they are driven by the agent responsible for driving d[63:0]#, and must connect the appropriate pins of all processor front side bus agents. table 4-3. signal description (sheet 3 of 8) name type description quad-pumped signal groups data group dstbn#/ dstbp# dbi# d[15:0]# 0 0 d[31:16]# 1 1 d[47:32]# 2 2 d[63:48]# 3 3 dbi[3:0] assignment to data bus bus signal data bus signals dbi3# d[63:48]# dbi2# d[47:32]# dbi1# d[31:16]# dbi0# d[15:0]#
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 53 pin listing and signal descriptions dpslp# input dpslp# when asserted on the platform causes the processor to transition from the sleep state to the deep sleep state. in order to return to the sleep state, dpslp# must be deasserted and bclk[1:0] must be running. drdy# input/ output drdy# (data ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-common clock data transfer, drdy# may be deasserted to insert idle clocks. this signal must connect the appropriate pins of all processor front side bus agents. dstbn[3:0]# input/ output data strobe used to latch in d[63:0]#. dstbp[3:0]# input/ output data strobe used to latch in d[63:0]#. ferr#/pbe# output ferr#/pbe# (floating point error/pending br eak event) is a multiplexed signal and its meaning is qualified by stpclk#. when stpclk# is not asserted, ferr#/pbe# indicates a floating-point error and will be asserted when the processor detects an unmasked floating- point error. when stpclk# is not asserted, ferr#/pbe# is similar to the error# signal on the intel 387 coprocessor, and is included for compatib ility with systems using ms-dos*-type floating-point error reporting. when stpclk# is asserted, an assertion of ferr#/pbe# indicates that the processor has a pending break event waiting for service. the assertion of ferr#/pbe# indicates that the processor should be returned to the normal state. for additional information on the pending break event functionality, including the ident ification of support of the feature and enable/disable information, refer to volume 3 of the intel architecture software developer's manual and the intel processor identification and the cpuid instruction application note. gtlref input gtlref determines the signal reference le vel for gtl+ input pins. gtlref is used by the gtl+ receivers to determine if a signal is a logical 0 or logical 1. refer to the intel? 852gme and intel? 852pm chipset platforms design guide for more information. hit# hitm# input/ output input/ output hit# (snoop hit) and hitm# (hit modifi ed) convey transaction snoop operation results. any front side bus agent may assert both hit# and hitm# together to indicate that it requires a snoop stall, which can be continued by reasserting hit# and hitm# together. table 4-3. signal description (sheet 4 of 8) name type description signals associated strobe d[15:0]#, dbi0# dstbn0# d[31:16]#, dbi1# dstbn1# d[47:32]#, dbi2# dstbn2# d[63:48]#, dbi3# dstbn3# signals associated strobe d[15:0]#, dbi0# dstbp0# d[31:16]#, dbi1# dstbp1# d[47:32]#, dbi2# dstbp2# d[63:48]#, dbi3# dstbp3#
54 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet pin listing and signal descriptions ierr# output ierr# (internal error) is asserted by a pr ocessor as the result of an internal error. assertion of ierr# is usually accompanied by a shutdown transaction on the processor front side bus. this trans action may optionally be converted to an external error signal (e.g., nmi) by syst em core logic. the processor will keep ierr# asserted until the assertion of reset#. this signal does not have on-die termination. refer to section 2.4 for termination requirements. ignne# input ignne# (ignore numeric error) is asserted to force the processor to ignore a numeric error and continue to execute nonc ontrol floating-point instructions. if ignne# is deasserted, the processor gener ates an exception on a noncontrol floating-point instruction if a previous fl oating-point instruction caused an error. ignne# has no effect when the ne bit in control register 0 (cr0) is set. ignne# is an asynchronous signal. however, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the trdy# assertion of the corresponding i nput/output write bus transaction. init# input init# (initialization), when asserted, rese ts integer registers inside the processor without affecting its internal caches or floating-point registers. the processor then begins execution at the power-on reset vector configured during power-on configuration. the processor conti nues to handle snoop requests during init# assertion. init# is an asynchronous signal and must connect the appropriate pins of all processor front side bus agents. if init# is sampled active on the active to inactive transition of reset#, then the processor executes its built-in self-test (bist). itp_clk[1:0] input itp_clk[1:0] are copies of bclk that are used only in processor systems where no debug port is implemented on the system board. itp_clk[1:0] are used as bclk[1:0] references for a debug port implemented on an interposer. if a debug port is implemented in the system, itp_clk[1:0] are no connects in the system. these are not processor signals. lint[1:0] input lint[1:0] (local apic interrupt) must connect the appropriate pins of all apic bus agents. when the apic is disabl ed, the lint0 signal becomes intr, a maskable interrupt request signal, a nd lint1 becomes nmi, a nonmaskable interrupt. intr and nmi are backward compatible with the signals of those names on the pentium processor. both signals are asynchronous. both of these signals must be software configured via bios programming of the apic register space to be used either as nmi/intr or lint[1:0]. because the apic is enabled by default after reset, operat ion of these pins as lint[1:0] is the default configuration. lock# input/ output lock# indicates to the system that a transaction must occur atomically. this signal must connect the appropriate pins of all processor front side bus agents. for a locked sequence of transactions, lo ck# is asserted from the beginning of the first transaction to the end of the last transaction. when the priority agent asserts bpri# to arbitrate for ownership of the processor front side bus, it will wait until it observes lock# deasserted. this enables symmetric agents to retain ownership of the processor front side bus throughout the bus locked operation and ensure the atomicity of lock. table 4-3. signal description (sheet 5 of 8) name type description
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 55 pin listing and signal descriptions mcerr# input/ output mcerr# (machine check error) is asse rted to indicate an unrecoverable error without a bus protocol violation. it may be driven by all processor front side bus agents. mcerr# assertion conditions are config urable at a system level. assertion options are defined by the following options: ? enabled or disabled. ? asserted, if configured, for internal errors along with ierr#. ? asserted, if configured, by the reques t initiator of a bus transaction after it observes an error. ? asserted by any bus agent when it observes an error in a bus transaction. for more details regarding machine check architecture, please refer to the ia-32 software developer?s manual, volume 3: system programming guide . optimized/ compat# input this is an input to the processor to det ermine if the processor is in an optimized platform or a compatible platform. this i nput has a weak internal pullup. this pin must be left unconnected on platforms designed for use with the processor. see intel? 852gme and intel? 852pm chipset platforms design guide for more details. prochot# input/ output as an output, prochot# (processor hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. this indicates that the processor thermal control circuit (tcc) has been activated, if enabled. as an input, assertion of prochot# by the system will activate the tcc, if enabled. the tcc will remain active until the system deasserts prochot#. see section 5.2.4 for more details. pwrgood input pwrgood (power good) is a processor input. the processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ?clean? implies that the signal will remain low (capable of sinking leakage current), without gl itches, from the time that the power supplies are turned on until they come with in specification. the signal must then transition monotonically to a high stat e. pwrgood can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of pwrgood. the pwrgood signal must be supplied to t he processor; it is used to protect internal circuits against voltage sequenc ing issues. it should be driven high throughout boundary scan operation. req[4:0]# input/ output req[4:0]# (request command) must connect the appropriate pins of all processor front side bus agents. they are asserted by the current bus owner to define the currently active transac tion type. these signals are source synchronous to adstb0#. refer to the ap[1:0]# signal description for a details on parity checking of these signals. reset# input asserting the reset# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. for a power-on reset, reset# must stay active for at least one millisecond after v cc and bclk have reached their proper s pecifications. on observing active reset#, all front side bus agents will deasse rt their outputs within two clocks. reset# must not be kept asserted fo r more than 10 ms while pwrgood is asserted. a number of bus signals are sampled at the active-to-inactive transition of reset# for power-on configuration. thes e configuration options are described in the section 6.1 . this signal does not have on-die termination and must be terminated on the system board. rs[2:0]# input rs[2:0]# (response status) are driven by the response agent (the agent responsible for completion of the cu rrent transaction), and must connect the appropriate pins of all processor front side bus agents. table 4-3. signal description (sheet 6 of 8) name type description
56 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet pin listing and signal descriptions rsp# input rsp# (response parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of rs[2:0]#, the signals for which rsp# provides parity protection. it must connect to the appropriate pins of all processor front side bus agents. a correct parity signal is high if an ev en number of covered signals are low and low if an odd number of covered signals are low. while rs[2:0]# = 000, rsp# is also high, since this indicates it is no t being driven by any agent guaranteeing correct parity. sktocc# output sktocc# (socket occupied) will be pulled to ground by the processor. system board designers may use this pin to det ermine if the processor is present. slp# input slp# (sleep), when asserted in stop-grant state, causes the processor to enter the sleep state. during sleep state, the pr ocessor stops providing internal clock signals to all units, leaving only the ph ase-locked loop (pll) still operating. processors in this state will not recognize snoops or interrupts. the processor will recognize only assertion of the reset# signal, deassertion of slp# signal, and assertion of dpslp# input while in sleep state. if slp# is deasserted, the processor exits sleep state and returns to stop-grant state, restarting its internal clock signals to the bus and processor core units. if the dpslp# signal is asserted while in the sleep state, the processor will exit the sleep state and transition to the deep sleep state. smi# input smi# (system management interrupt) is asserted asynchronously by system logic. on accepting a system management interrupt, the processor saves the current state and enter system management mode (smm). an smi acknowledge transaction is issued, and the processor begins program execution from the smm handler. if smi# is asserted during the deassertion of reset# the processor will tristate its outputs. stpclk# input stpclk# (stop clock), when asserted, causes the processor to enter a low power stop-grant state. the processor issues a stop-grant acknowledge transaction, and stops providing internal cl ock signals to all processor core units except the front side bus and apic units. the processor continues to snoop bus transactions and service interrupts while in stop-grant state. when stpclk# is deasserted, the processor restarts its internal clock to all units and resumes execution. the assertion of stpclk# has no effect on the bus clock; stpclk# is an asynchronous input. tck input tck (test clock) provides the clock input for the processor test bus (also known as the test access port). tdi input tdi (test data in) transfers serial test data into the processor. tdi provides the serial input needed for jtag specification support. tdo output tdo (test data out) transfers serial test data out of the processor. tdo provides the serial output needed for jtag specification support. testhi[11:0] input testhi[11:0] must be connected to a v cc power source through a resistor for proper processor operation. see section 2.4 for more details. thermda other thermal diode anode. see section 5.2.7 . thermdc other thermal diode cathode. see section 5.2.7 . table 4-3. signal description (sheet 7 of 8) name type description
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 57 pin listing and signal descriptions thermtrip# output in the event of a catastrophic cooling fa ilure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 c above the maximum t c . assertion of thermtrip# (thermal trip) indicates the processor junction temperature has r eached a level beyond which permanent silicon damage may occur. upon asserti on of thermtrip#, the processor will shut off its internal clocks (thus halti ng program execution) in an attempt to reduce the processor junction temperature. to protect the processor, its core voltage (v cc ) must be removed following the assertion of thermtrip#. driving of the thermtrip# signal is enabled within 10 s of the assertion of pwrgood and is disabled on de-assertion of pwrgood. once activated, thermtrip# remains latched until pwrgood is de-asserted. while the de- assertion of the pwrgood signal will de-assert thermtrip#, if the processor?s junction temperature remains at or above the trip level, thermtrip# will again be asserted within 10 s of the assertion of pwrgood. tms input tms (test mode select) is a jtag spec ification support signal used by debug tools. trdy# input trdy# (target ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. trdy# must connect the appropriate pins of all front side bus agents. trst# input trst# (test reset) resets the test access port (tap) logic. trst# must be driven low during power on reset. v cca input v cca provides isolated power for the inter nal processor core plls. refer to the intel? 852gme and intel? 852pm chipset platforms design guide for complete implementation details. v cciopll input v cciopll provides isolated power for inter nal processor front side bus plls. follow the guidelines for v cca , and refer to the intel? 852gme and intel? 852pm chipset platforms design guide for complete implementation details. v ccsense output v ccsense is an isolated low impedance connec tion to processor core power (v cc ). it can be used to sense or measure volt age near the silicon with little noise. vccvid input 1.2 v is required to be supplied to the vccvid pin if the platform is going to support the processor. refer to the intel? 852gme and intel? 852pm chipset platforms design guide for more information. vccvidlb input 1.2 v is required to be supplied to the vccvidlb pin if the platform is going to support the processor. refer to the intel? 852gme and intel? 852pm chipset platforms design guide for more information. vid[5:0] output vid[5:0] (voltage id) pins are used to support automatic selection of power supply voltages (v cc ). these are open drain signals that are driven by the processor and must be pulled up to 3.3 v with 1-k ? 5% resistors. the voltage supply for these pins must be va lid before the vr can supply v cc to the processor. conversely, the vr output must be disabled until the voltage supply for the vid pins becomes valid. the vid pins are needed to support the processor voltage specif ication variations. see table 2-2 for definitions of these pins. the vr must supply the voltage that is requested by the pins, or disable itself. vidpwrgd input the processor requires this input to determine that the vccvid and vccvidlb voltages are stable and within specification. v ssa input v ssa is the isolated ground for internal plls. v sssense output v sssense is an isolated low impedance connec tion to processor core v ss . it can be used to sense or measure ground near the silicon with little noise. table 4-3. signal description (sheet 8 of 8) name type description
58 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet pin listing and signal descriptions
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 59 thermal specifications and design considerations 5 thermal specifications and design considerations 5.1 processor thermal specifications the processor requires a thermal solution to maintain temperatures within operating limits as set forth in section 5.1.1 . any attempt to operate the processo r outside these oper ating limits may result in permanent damage to the processor and potentially other components within the system. as processor technology change s, thermal management become s increasingly crucial when building computer systems. maintaining the proper thermal environment is key to reliable, long- term system operation. a complete thermal solution includes both comp onent and system level thermal management features. component level thermal solutions can incl ude active or passive heatsinks attached to the processor integrated heat spread er (ihs). typical syst em level thermal solutions may consist of system fans combined with ducting and venting. this section provides da ta necessary for developing a comp lete thermal solution. for more information on designing a component level thermal solution, consult your intel field sales representative. 5.1.1 thermal specifications to allow for the optimal operati on and long-term reliability of intel processor-based systems, the system/processor thermal solution should be designe d such that the processor remains within the minimum and maximum case temperature (t c ) specifications at the corresponding thermal design power (tdp) value listed per frequency in table 5-1 . thermal solutions not designed to provide this level of thermal cap ability may affect the long-term reliability of the processor and system. for more details on thermal solution design, please refer to the appropriate processor thermal design guidelines. the processor introduces a new methodology for managing processor temperatures through fan speed control. selection of the appropriate fan sp eed will be based on the temperature reported by the processor?s thermal diode. the fa n must be turned on to full speed when tdiode is at or above tcontrol and t c must be maintained at or below t c (max) as defined by the processor thermal specifications in table 5-1 . the fan speed may be lowered when the processor temperature can be maintained below tcontrol as measured by th e thermal diode. systems implementing fan speed control must be designed to read temperature values from the diode and tcontrol register and take appropriate action. systems that do not alter the fan speed (always at fu ll speed) only need to guarantee the case temperatur e meets specifications in table 5-1 . the case temperature is defined at the geometri c top center of the pro cessor ihs. analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. intel recommends that complete thermal solution designs target the tdp indicated in table 5-1 instead of the maximum pro cessor power consumption. the intel ? thermal monitor feature is intended to help pr otect the processor in th e unlikely event that an application exceeds the tdp recommendation for a sustained period of time. for more details on the usage of this feature, refer to section 5.2 . to ensure maximum flexibility for future
60 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet thermal specifications an d design considerations requirements, systems should be designed to the fi xed mobile solution (fms) guidelines, even if a processor with a lower thermal dissipation is currently planned. in all cases, the intel thermal monitor or intel thermal monitor 2 feature mu st be enabled for the processor to remain within specification. notes: 1. tdp should be used for processor thermal solution design targets. the tdp is not the maximum power that the processor can dissipate. 2. fms, or fixed mobile solution gui delines provide a design target for meeting future thermal requirements. 5.1.2 thermal metrology the maximum and minimu m case temperatures (t c ) are specified in table 5-1 . these temperature specifications are meant to help ensure proper operation of the processor. figure 5-1 illustrates where intel recommends t c thermal measurements should be made. table 5-1. processor thermal specifications processor number core frequency (ghz) thermal design power (w) minimum t c (c) maximum t c (c) notes 518 2.80 88 5 75 1 532 3.06 88 5 75 1 538 3.20 88 5 75 1 548 3.33 88 5 75 1 552 3.46 88 5 75 1 fms0.5 94 5 76 1, 2 figure 5-1. case temperature (t c ) measurement location 31 mm x 31 mm ihs [1.22 x 1.22 in] 35 mm x 35 mm substrate [1.378 in x 1.378 in] measure t c at this point (geometric center of ihs) measure from edge of processor ihs 15.5 mm [.61 in] 15.5 mm [.61 in]
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 61 thermal specifications and design considerations 5.2 processor thermal features 5.2.1 intel thermal monitor the intel thermal monitor feature helps control the processor temp erature by activating the tcc when the processor silicon reaches its maximum operating temperature. the tcc reduces processor power consumption as needed by modulating (starting and stopping) the internal processor core clocks. the intel thermal monitor or intel thermal monitor 2 feature must be enabled for the processor to be operating within specifications. the temperature at which the intel thermal monitor activates the thermal contro l circuit is not user configurable and is not software visible. bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the tim e that the clocks are on) while the tcc is active. when the intel thermal monitor f eature is enabled, and a high te mperature situation exists (i.e. tcc is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30-50%). clocks often will not be off for more than 3.0 microseconds when the tcc is active. cycle times are proce ssor speed dependent and will decrease as processor core frequenc ies increase. a small amount of hysteresis has been included to prevent rapid active/inactive transitions of the t cc when the processor te mperature is near its maximum operating temperature. once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the tcc goes inactive and clock modulation ceases. with a properly designed and char acterized thermal solution, it is anticipated that the tcc would only be activated for very short periods of time when running the most power intensive applications. the processor performance impact du e to these brief periods of tcc activation is expected to be so minor that it would be immeasurable. an under-designed thermal solution that is not able to prevent excessive activation of the tcc in the anticipated ambient environment may cause a noticeable performance loss, a nd in some cases may result in a t c that exceeds the specified maximum temperature an d may affect the long-term reliability of the processor. in addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the tcc is active continuously. consult your intel field sales representative for information on designing a thermal solution. the duty cycle for the tcc, when activated by the thermal monito r, is factory configured and cannot be modified. the thermal monitor does not require any additional hardware, software drivers, or interrupt handling routines. 5.2.2 thermal monitor 2 the mobile processor also supports an add itional power reduction capability known as thermal monitor 2. this mechanism provide s an efficient means for limiting the processor temperature by reducing the power consumption within the processor. consult your intel field sales representative for information on determining whether a given processor supports thermal monitor 2 and for configuration information. when the intel thermal monitor 2 is enabled, a nd a high temperature situ ation is detected, the thermal control circuit (tcc) will be activated. the tcc causes the processor to adjust its operating frequency (via the bus multiplier) and input voltage (via the vid signals). this combination of reduced frequency and vid results in a reduction to the processor power consumption.
62 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet thermal specifications an d design considerations a processor enabled for the intel thermal monitor 2 includes two operati ng points, each consisting of a specific operating frequency and voltage. the first operating point represents the normal operating condition for the processor. under this condition, the core-frequency-to-fsb multiple utilized by the processor is that contained in the ia32_cr_flex_brvid_sel msr and the vid is that specified in table 2-8 . these parameters represen t normal system operation. the second operating point consists of both a lower operating frequency and voltage. when the tcc is activated, the processor automatically transitions to the new frequency. this transition occurs very rapidly (on the order of 5 s). during the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. edge-triggered interrupts will be latched and kept pending until the pro cessor resumes operation at the new frequency. once the new operating frequency is engaged, the processor will transiti on to the new core operating voltage by issuing a new vid code to the voltage regulator. the voltage regulator must support dynamic vid steps in order to support the intel thermal monitor 2. during the voltage change, it will be necessary to transition through multiple vid codes to r each the target operating voltage. each step will likely be one vid table entry (see table 2-8 ). the processor continues to execute instructions during the vo ltage transition. operation at th e lower voltage reduces the power consumption of the processor. a small amount of hysteresis has been included to prevent rapid active/inactive transitions of the tcc when the processor temper ature is near its maximum op erating temperature. once the temperature has dropped below the maximum operat ing temperature, and th e hysteresis timer has expired, the operating frequency and voltage tran sition back to the normal system operating point. transition of the vid code will occur first, in order to insure proper operation once the processor reaches its normal operatin g frequency. refer to figure 5-2 for an illustration of this ordering. the prochot# signal is asserted when a high temperature situation is detected, regardless of whether the intel thermal monitor or intel thermal monitor 2 is enabled. figure 5-2. intel thermal monitor 2 frequency and voltage ordering vcc temperature v nom frequency time f tm2 f max t tm2 v tm2 t(hysteresis)
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 63 thermal specifications and design considerations 5.2.3 on-demand mode the processor provides an auxiliar y mechanism that allows system software to force the processor to reduce its power consumption. this mechanism is referred to as ?on-demand? mode and is distinct from the intel thermal monitor feature. on-demand mode is intended as a means to reduce system level power consumption. systems ut ilizing the processor must not rely on software usage of this mechanism to li mit the processor temperature. if bit 4 of the acpi p_cnt control register (located in the processor ia32_therm_control msr) is written to a 1, the processor will immediately reduce its power consumption via modulation (starting and stopping) of the intern al core clock, independent of the processor temperature. when using on-demand mode, th e duty cycle of the clock modulation is programmable via bits 3:1 of the same acpi p_cnt control register. in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. on-demand mode may be used in conjunction with the intel thermal monitor. if the system tries to enable on-demand mode at th e same time the tcc is engaged, the factory configured duty cycle of the tcc will override th e duty cycle selected by the on-demand mode. 5.2.4 prochot# signal pin an external signal, prochot# (p rocessor hot), is asserted when the processor die temperature has reached its maximum operating temperature. if the intel thermal m onitor or intel thermal monitor 2 is enabled (note that the thermal monitor or thermal monitor 2 must be enabled for the processor to be operating within specification), the tcc will be active when prochot# is asserted. the processor can be conf igured to generate an interrupt upon the assertion or deassertion of prochot#. refer to the intel? architecture softw are developer's manuals and consult your intel field sales representative for sp ecific register and programming details. the processor implements a bidirectional proc hot# capability to allow system designs to protect various components from over-temperature situations. the prochot# signal is bidirectional in that it can ei ther signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the tcc. the ability to activate the tcc via prochot# can provide a means for thermal protection of system components. one application is the thermal protection of voltage regulators (vr). system designers can create a circuit to monitor the vr temper ature and activate the tcc when th e temperature limit of the vr is reached. by asserting prochot# (pulled-low) and activating the tcc, the vr can cool down as a result of reduced processor power consumption. bidirectional prochot# can allow vr thermal designs to target maximum sustained curr ent instead of maximum cu rrent. systems should still provide proper cooling for the vr, and rely on bidirectional prochot# only as a backup in case of system cooling failure. the system th ermal design should allow the power delivery circuitry to operate within its temperature specific ation even while the proce ssor is operating at its tdp. with a properly designed and characterized thermal solution, it is anticipated that bidirectional prochot# would only be asserted for very short periods of time when running the most power intensive applications. an under-designed thermal solution that is not able to prevent excessive assertion of prochot# in the anticipated ambient envi ronment may cause a noticeable performance loss. refer to the intel? 852gme and intel? 852pm chipset platforms design guide for details on implementing the bidirectional prochot# feature.
64 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet thermal specifications an d design considerations 5.2.5 thermtrip# signal pin regardless of whether or not the intel thermal monitor feature is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (ref er to the thermtrip# definition in table 4-3 ). at this point, the front side bus signal thermtrip# will go active and stay active as described in table 4-3 . thermtrip# activation is independent of pro cessor activity and does not generate any bus cycles. if thermtrip# is a sserted, processor core voltage (vcc) must be removed. 5.2.6 tcontrol and fan speed reduction tcontrol is a temperature specifi cation based on a temperature read ing from the thermal diode. the value for tcontrol will be calibra ted in manufacturing and config ured for each processor. the tcontrol temperature for a given proce ssor can be obtained by reading the ia32_temperature_target msr in the processor. the tcontrol value that is read from the ia32_temperature_target msr needs to be converted from hexadecimal to decimal and added to a base value of 50 c. the value of tcontrol may vary from 00 h to 1e h (0 to 30 c). the fan must be turned on to the max rated speed of the fan or fan speed necessary to meet tc,max at tdp when tdiode is at or above tcontrol and t c must be maintained at or below t c (max) as defined by the processor thermal specifications in table 5-1 . the fan speed may be lowered when the processor temperature can be maintained belo w tcontrol as measured by the thermal diode. 5.2.7 thermal diode the processor incorporates an on -die thermal diode. a thermal sensor located on the system board may monitor the die temperature of the processor for thermal management/long term die temperature change purposes. table 5-2 and table 5-3 provide the diode parameter and interface specifications. this thermal diode is separate from the intel thermal monitor?s thermal sensor and cannot be used to predict the behavior of the intel thermal monitor. notes: 1. intel does not support or recommend operation of the thermal diode under reverse bias. 2. characterized at 75 c. 3. not 100% tested. specified by design characterization. 4. the ideality factor, n, represents the deviation fr om ideal diode behavior as exemplified by the diode equation: i fw = i s * (e qv d /nkt ?1) where i s = saturation current, q = electronic charge, v d = voltage across the diode, k = boltzmann constant, and t = absolute temperature (kelvin). table 5-2. thermal diode parameters symbol parameter min typ max unit notes i fw forward bias current 11 187 ua 1 n diode ideality factor 1.0083 1.011 1.0183 2, 3, 4 r t series resistance 3.242 3.33 3.594 ? 2, 3, 5
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 65 thermal specifications and design considerations 5. the series resistance, r t , is provided to allow for a more accurate measurement of the diode temperature. r t , as defined, includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. rt can be used by remote diode thermal sensors with automatic se ries resistance cancellation to cali brate out this error term. another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: t error = [r t * (n-1) * i fwmin ] / [nk/q * ln n] where t error = sensor temperature error, n = sensor curr ent ratio, k = boltzmann constant, q = electronic charge. table 5-3. thermal diode interface pin name pin number pin description thermda b3 diode anode thermdc c4 diode cathode
66 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet thermal specifications an d design considerations
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 67 features 6 features 6.1 power-on configuration options several configuration options can be configured by hardware. the processor samples the hardware configuration at reset, on the active-to-inactive transition of reset#. fo r specifications on these options, please refer to table 6-1 . the sampled information co nfigures the processor for subseque nt operation. th ese configuration options cannot be changed except by another reset. all resets reconfigure the processor; for reset purposes, the processor does not distinguish be tween a "warm" reset and a "power-on" reset. frequency determination function ality will exist on engineering sample processors which means that samples can run at varied frequencies. production material will have the bus to core ratio locked and can only be operated at the rated frequency. notes: 1. asserting this signal during reset# will select the corresponding option. 2. address pins not identified in this table as c onfiguration options should not be asserted during reset#. 6.2 clock control and low power states the processor allows the use of autohalt, stop -grant, sleep, deep sleep, and deeper sleep states to reduce power consumption by stopping th e clock to internal sect ions of the processor, depending on each part icular state. see figure 6-1 for a visual representation of the processor low power states. 6.2.1 normal state?state 1 this is the normal operatin g state for the processor. table 6-1. power-on co nfiguration option pins configuration option pin 1,2 output tristate smi# execute bist init# in order queue pipelining (set ioq depth to 1) a7# disable mcerr# observation a9# disable binit# observation a10# apic cluster id (0-3) a[12:11]# disable bus parking a15# disable hyper-threading technology a31# symmetric agent arbitration id br0# reserved a[6:3]#, a8#, a[14:13]#, a[16:30]#, a[32:35]#
68 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet features 6.2.2 autohalt power-down state?state 2 autohalt is a low-power state entered when th e processor executes the halt instruction. the processor will transition to the normal state upon the occurrence of smi#, binit#, init#, or lint[1:0] (nmi, intr). reset# will cause the processor to immediately initialize itself. the return from a system management interrupt (s mi) handler can be to either normal mode or the autohalt power-down state. see the intel ? architecture software developer's manual, volume iii: system programmer's guide for more information. the system can generate a stpclk# while the pro cessor is in the autohalt power-down state. when the system deasserts the stpclk# interrup t, the processor will return execution to the halt state. while in autohalt power-down state, the pr ocessor will process front side bus snoops and interrupts. 6.2.3 stop-grant state?state 3 when the stpclk# pin is asserted, the stop-grant state of the pro cessor is entered 20 bus clocks after the response phase of the processor-issu ed stop grant acknowledge special bus cycle. figure 6-1. stop clock state machine 3. sto p g ran t state bclk running. snoops and int errupt s allowed. stpclk# de-asserted slp# de-asserted 1. no rmal state normal execut ion. 5. sl eep state bclk running. no snoops or int errupt s allowed. 2. au to hal t po w er do w n state bclk running. snoops and int errupt s allowed. 4. halt/grant snoop state bclk running. service snoops t o caches. stpclk# asserted slp# asserted snoop event occurs snoop event serviced halt i nst ruct ion and halt bus cycle g enerat ed init#, binit#, intr, nmi, smi#, reset# snoop event serviced snoop event o ccurs s t p c l k # a s s e r t e d s t p c l k # d e - a s s e r t e d 6. deep sl eep state dpslp# asserted dpslp# de-asserted 7. deep er sl eep state core volt age lowered core volt age raised
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 69 features since the gtl+ signal pins receive power from the fr ont side bus, these pins should not be driven (allowing the level to return to v cc ) for minimum power drawn by the termination resistors in this state. in addition, all other input pins on the fron t side bus should be driven to the inactive state. binit# will not be serviced while the processor is in stop-grant state. the event will be latched and can be serviced by software upon exit from the stop-grant state. reset# will cause the processor to immediately initialize itself, but the processor will stay in stop-grant state. a tran sition back to the normal state will occur with the deassertion of the stpclk# signal. when re-entering the stop grant state from the sleep state, stpclk# should only be deasserted ten or more bus clocks after the de-assertion of slp#. a transition to the halt/grant snoop state will occur when the processor detects a snoop on the front side bus (see section 6.2.4 ). a transition to the sleep state (see section 6.2.5 ) will occur with the assertion of the slp# signal. while in the stop-grant state, smi#, init#, binit# and lint[1 :0] will be latched by the processor, and only serviced when the processor re turns to the normal stat e. only one occurrence of each event will be recognized u pon return to the normal state. while in stop-grant state, the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus. the pbe# signal can be driven when the processor is in stop-grant state. pbe# will be asserted if there is any pending interrupt latched within the pr ocessor. pending interrupts that are blocked by the eflags.if bit being clear will still cause asse rtion of pbe#. assertion of pbe# indicates to system logic that it should return the processor to the normal state. 6.2.4 halt/grant snoop state?state 4 the processor will respond to snoop or interrupt transactions on the front side bus while in stop- grant state or in autohalt power down state. during a snoop or interrupt transaction, the processor enters the halt/grant snoop state. the processor will stay in this state until the snoop on the front side bus has been serviced (whether by the processor or another agent on the front side bus) or the interrupt has been latched. after the sn oop is serviced or the interrupt is latched, the processor will return to the stop-grant state or autohalt power-down state, as appropriate. 6.2.5 sleep state?state 5 the sleep state is a very low power state in whic h the processor maintains its context, maintains the phase-locked loop (pll), and has stopped all in ternal clocks. the sleep state can only be entered from stop-grant state. once in the stop-gra nt state, the processor w ill enter the sleep state upon the assertion of the slp# signal. the slp# pi n should only be asserted when the processor is in the stop grant state. slp# assertions while the pr ocessor is not in the stop grant state is out of specification and may result in erroneous processor operation. snoop events that occur while in sleep state or during a transition into or out of sleep state will cause unpredictable behavior. in the sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals (with the excep tion of slp# or reset#) are allowed on the front side bus while the processo r is in sleep state. an y transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behavior.
70 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet features if reset# is driven active while the processor is in the sleep state, and held active as specified in the reset# pin specification, then the processor will reset itself, ignoring the transition through stop-grant state. if reset# is driven active while the processor is in the sleep state, the slp# and stpclk# signals should be deasserted immedi ately after reset# is asserted to ensure the processor correctly executes the reset sequence. while in the sleep state, the processor is capable of entering an even lower power state, the deep sleep state, by asserting the dpslp# pin (see section 6.2.6 ). once in the sleep or deep sleep state, the slp# pin must be de-asserted if another asynchronous front side bus event needs to occur. the slp# pin has a minimum assertion of one bclk period. when the processor is in the sleep state, it will not respond to interrupts or snoop transactions. 6.2.6 deep sleep state?state 6 deep sleep state is a very low po wer state the processor can enter while maintaining context. deep sleep state is entered by assertin g the dpslp# pin while in the sl eep state. the dpslp# pin must be de-asserted to re-enter the sleep state. a period of 30 microseconds (to allow for pll stabilization) must occur before th e processor can be cons idered to be in the sleep state. once in the sleep state, the slp# pin can be dea sserted to re-enter the stop-grant state. the clock may be stopped when th e processor is in the deep slee p state in order to support the acpi s1 state. the clock may only be stopped after dpslp# is asserted and must be restarted before dpslp# is deasserted. to provide maxi mum power conservation when stopping the clock during deep sleep, hold the bclk0 input at v ol and the bclk1 input at v oh . while in deep sleep state, the processor is in capable of responding to snoop transactions or latching interrupt signals. no transitions of si gnals are allowed on the front side bus while the processor is in deep sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behaviour. 6.2.7 deeper sleep state?state 7 the deeper sleep state is the lowest power state th e processor can enter. th is state is functionally identical to the deep sleep stat e but at a lower core voltage. th e control signals to the voltage regulator to initiate a transition to the deeper sl eep state are provided on the platform. please refer the intel? 852gme and intel? 852pm chipset platforms design guide for details. 6.3 enhanced intel speedstep ? technology the processor will feature enhanced intel speedstep technology. un like previous implementations of intel speedstep technology, this technology will enable the proce ssor to switch between multiple voltage and operating frequency points instead of two. this will enable superior performance with optimal power savings. switchin g between states will be software controlled unlike previous generation processor implementati ons where the ghi# pin was used to toggle between two states. following ar e the key features of enhanced intel speedstep technology: ? multiple voltage/frequency operat ing points provide optimal performance at the lowest power. ? voltage/frequency selection will be software controlled by writing to processor msrs (model specific registers) thus el iminating chipset dependency.
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 71 features ? if the target frequency is higher than th e current frequency, vcc is ramped up in incremental steps (+12.5 mv vi d step) by placing a new value on the vid signals and the pll then locks to the new frequency. note that the top frequency for the processor can not be exceeded. ? if the target frequency is lower than the current frequency, the pll locks to the new frequency and then vcc is ramped down in decremental steps (-12.5 mv vid step) by changing the target vid through the vid signals. ? the processor will control voltage ramp rates in ternally to ensure gl itch free transitions. ? low transition latency and large number of transitions possible per second. ? processor core (including l2 cach e) are unavailable for up to 10 s during the frequency transition ? the bus protocol (bnr# mechanism) is used to block snooping ? no bus master arbiter disabl e required prior to transition and no processor cache flush necessary.
72 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet features
mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet 73 debug tools specifications 7 debug tools specifications please refer to the appropriate pl atform design guidelines for information regarding debug tools specifications. the itp700 debug port design guide is located on http://developer.intel.com. 7.1 logic analyzer interface (lai) intel is working with two logic an alyzer vendors to provide logic an alyzer interfaces (lais) for use in debugging processor systems. tektronix and agilent should be contacted to obtain specific information about their l ogic analyzer interfaces. the following information is ge neral in nature. specific information must be obtaine d from the logic analyzer vendor. due to the complexity of mobile processor systems, the lai is critical in providing the ability to probe and capture front side bus si gnals. there are two sets of consid erations to keep in mind when designing a processor system that can make use of an lai: mechanical and electrical. 7.1.1 mechanical considerations the lai is installed between the processor socket and the mobile processor. the lai pins plug into the socket, while the processor pins plug into a socket on the lai. cabling that is part of the lai egresses the system to allow an electrical connection between the processor and a logic analyzer. the maximum volume occu pied by the lai, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. system designers must make sure that the keepout volume remains unobstruc ted inside the system. note that it is possible that the keepout volume reserved for the lai may differ from the space norm ally occupied by the processor heatsink. if this is th e case, the logic analyzer vendor will provide a cooling solution as part of the lai. 7.1.2 electrical considerations the lai will also affect the electrical performance of the front si de bus; therefore, it is critical to obtain electrical load models from each of the lo gic analyzers to be able to run system level simulations to prove that their tool will work in the system. contact the l ogic analyzer vendor for electrical specifications an d load models for the lai solution they provide.
74 mobile intel? pentium? 4 processor supporting hyper-t hreading technology on 90-nm process technology datasheet debug tools specifications

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