gnd
v dd v dd
gnd gnd gnd
nc 81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100 50
49
48
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33
32
31 80
79
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51 1
2
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20
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26
27
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29
30 CXD8804Q(1/4)
il08d c-mos 8-mpu communication controller with parallel port
?op view
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
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25 26
27
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30
31
32
33
34
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39
40
41
42
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44
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46
47
48
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50 o
i
i
i
i
i
o
i
i
i
i
i
i
i
? ? i
i
i
i
i
i
i
i
i 51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75 i
o
i
i
i
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
? o
o
i/o
i/o
i/o
i/o
i/o
i/o
i/o 76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100 i/o
o
o
o
o
o
o
o
o
o
o
o
o
o
? ? i
i
i
i
i
i
i
i
o d0 ram
a12 ram
a11 ram
a10 ram
a9 ram
a8 ram
a7 ram
a6 ram
a5 ram
a4 ram
a3 ram
a2 ram
a1 ram
a0 ram
gnd
v dd
inp 07
inp 06
inp 05
inp 04
inp 03
inp 02
inp 01
inp 00
out 27 a0 cpu
wait
cpu wr
cpu rd
mpuif cs
cont cs
d7 cpu
d6 cpu
d5 cpu
d4 cpu
d3 cpu
d2 cpu
d1 cpu
d0 cpu
ram wr
gnd
ram oe
ramce
d7 ram
d6 ram
d5 ram
d4 ram
d3 ram
d2 ram
d1 ram v sync
vsnc len
hv clk
hd
vd
s puls in
s puls out
tes 1
p on rst
system ck
cpu ck
a12 cpu
a11 cpu
a10 cpu
gnd
v dd
a9 cpu
a8 cpu
a7 cpu
a6 cpu
a5 cpu
a4 cpu
a3 cpu
a2 cpu
a1 cpu o
o
o
o
o
o
o
o
i
i
i
o
o
o
? o
o
o
o
o
o
o
o
? o out26
out25
out24
out23
out22
out21
out20
int
h snc
s rdy
s resp
sck
scmd
strb
gnd
mpucs7
mpucs6
mpucs5
mpucs4
mpucs3
mpucs2
mpucs1
mpucs0
n.c
h sync pin
no. pin
no. pin
no. pin
no. i/o signal i/o i/o i/o signal signal signal CXD8804Q(2/4)
CXD8804Q(3/4) input
a0cpu - a12cpu
cont cs
cpu ck
cpu rd
cpu wr
hd
h snc
hv clk
inp 00 - 07
mpuif cs
p on rst
s puls
s rdy
s resp
system ck
tes 1
vd
vsnc len
output
a0ram - a12ram
h sync
int
mpucs0 - mpucs7
out 20 - 27
ram ce
ram oe
ram wr
sck
scmd
s puls
strb
v sync
wait
input/output
d0cpu - d7cpu
d0ram - d7ram
; cpu address bus
; internal/parallel port
; cpu clock
; cpu read strobe
; cpu write strobe
; video horizontal synchronizing pulse
; serial receive wait
; video vertical sampling pulse (13.5 mhz)
; parallel port
; external ram chip select
; power in reset (l)
; mediocrity clock pulse
; serial transmission leady
; serial receive data
; system clock
; test (l)
; video vertical synchronizing pulse
; video vertical synchronizing pulse output
width control
; external ram address bus
; video horizontal synchronizing pulse
; serial receive end
; serial correspondence enable
; parallel port
; external ram chip select
; external ram output enable
; external ram write strobe
; serial correspondence clock
; serial transmission data
; mediocrity clock pulse frequency (1/2-1/27)
; serial transmission strobe
; video vertical synchronizing pulse
; cpu wait
; cpu data bus
; external ram data bus 55
54
53
51
50
49
48
47
46
45
44
43
42
39
38
37
64
63
62
61
60
59
58
57
34
35
36
9
10
11
56
31
99
98
97
96
95
94
93
92
30
29
28
27
33 52
65
67
68
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
23
22
21
20
19
18
17
16
8
12
13
14
32
7
6
5
4
3
2
1
100
25
26 mpuif cs
cpu rd
cpu wr
a0cpu
a1cpu
a2cpu
a3cpu
a4cpu
a5cpu
a6cpu
a7cpu
a8cpu
a9cpu
a10cpu
a11cpu
a12cpu
d0cpu
d1cpu
d2cpu
d3cpu
d4cpu
d5cpu
d6cpu
d7cpu
p on rst
system ck
cpu ck
h snc
s rdy
s resp
cont cs
s puls in
inp 00
inp 01
inp 02
inp 03
inp 04
inp 05
inp 06
inp 07
vd
hd
hv clk
vsnc len
tes 1 wait
ram wr
ram oe
ram ce
a0ram
a1ram
a2ram
a3ram
a4ram
a5ram
a6ram
a7ram
a8ram
a9ram
a10ram
a11ram
a12ram
d0ram
d1ram
d2ram
d3ram
d4ram
d5ram
d6ram
d7ram
mpucs0
mpucs1
mpucs2
mpucs3
mpucs4
mpucs5
mpucs6
mpucs7
int
sck
scmd
strb
s puls out
out 20
out 21
out 22
out 23
out 24
out 25
out 26
out 27
h sync
v sync
CXD8804Q(4/4) transmitter
p s
converter data/address
bus
control parallel port clock
prescaler sync
generator 9
10
11
55 h snc
s rdy
s resp
mpuif cs p on pst
system ck
cpu ck cpu wr
cpu rd a0cpu - a12cpu d0cpu - d7cpu inp 00 - inp 07 cont cs s puls in tes 1 hd
vd
vsnc len
hv clk 34
35
36 53
54 37 - 39,
42 - 51 57 - 64 92 - 99 56 37 33 29
30
27
28 16 - 23 mpucs0 - mpucs7 int
sck
scmd
strb wait a0ram - a12ram d0ram - d7ram out20 - out27 s puls out h sync
v sync ramwr
ramoe
ramce 8
12
13
14 52 65
67
68 77 - 89 69 - 76 1 - 7, 100 32 25
26
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