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half-bridge driver packages product summary description the irs2509 is a high-voltage, high-speed power mosfet and igbt half-bridge driver with independent high and low side referenced output channels. proprietary hvic and latch immune cmos technologies enable a ruggedized monolithic construction. the logic input is compatible with standard cmos or lsttl output, down to 3.3 v. the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. the floating channel can be used to drive an n-channel power mosfet or igbt in the high side configuration which operates up to 600v. features ? 600v half-bridge driver ? tolerant to negative transient voltages ? gate drive supply range from 10 v to 20 v ? under-voltage lock-out for both channels ? 3.3 v, 5 v and 15 v input logic compatible ? cross-conduction prevention logic ? matched propagation delay for both channels ? high side output in phase with in input ? internal 530 ns dead-time ? lower di/dt gate driver for better noise immunity ? shut down input turns off both channels ? rohs compliant november 15, 2010 IRS2509SPBF v offset 600 v max. i o+/- 120 ma / 250 ma v out 10 v ? 20 v t on/off (typ.) 750 ns & 200 ns dead time 530 ns 8-lead soic typical connection applications: *hid electronic ballasts
www.irf.com 2 IRS2509SPBF qualification information ? industrial ?? (per jedec jesd 47) qualification level comments: this ic has passed jedec?s industrial qualification. ir?s consumer qualification level is granted by extension of the higher industrial level. moisture sensitivity level soic-8n msl2 ??? (per ipc/jedec j-std-020) machine model class b (+/-200v) (per jedec standard jesd22-a115) esd human body model class 1c (+/-1000v) (per eia/jedec standar d eia/jesd22-a114) ic latch-up test class i, level a (per jesd78a) rohs compliant yes ? qualification standards can be found at international rectifier?s web site http://www.irf.com/ ?? higher qualification ratings may be available should th e user have such requirements. please contact your international rectifier sales repres entative for furt her information. ??? higher msl ratings may be available for the specific package types listed here. please contact your international rectifier sales repres entative for furt her information.
www.irf.com 3 IRS2509SPBF absolute maximum ratings absolute maximum rati ngs indicate sustained limits beyond which dam age to the device may occur. all voltage parameters are absolute voltages refe renced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. recommended operating conditions for proper operation the device should be us ed within the recommended conditions. the v s and com offset rating are tested with all supplies biased at 15 v differential. note 1: logic operational for v s of -8 v to +600 v. logic state held for v s of -8 v to ? v bs. note 2: operational for transient negative vs of com - 50 v wi th a 50 ns pulse width. guaranteed by design. refer to the application information section of this datasheet for more details. symbol definition min. max. units v b high side floating absolute voltage -0.3 620 v s high side floating supply offset voltage v b - 20 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v cc low side and logic fixed supply voltage -0.3 20 v lo low side output voltage -0.3 v cc + 0.3 v in logic input voltage (in & sd) com -0.3 v cc + 0.3 com logic ground v cc - 20 v cc + 0.3 v dv s /dt allowable offset supply voltage transient ? 50 v/ns p d package power dissipation @ ta +25 c ? 0.625 w rth ja thermal resistance, junction to ambient ? 200 c/w t j junction temperature ? 150 t s storage temperature -50 150 t l lead temperature (soldering, 10 seconds) ? 300 c symbol definition min. max. units v b high side floating supply absolute voltage v s +10 v s +20 v s static high side floating supply offset voltage com- 8(note 1) 600 v st transient high side floating supply offset voltage -50 (note2) 600 v ho high side floating output voltage v s v b v cc low side and logic fixed supply voltage 10 20 v lo low side output voltage 0 v cc v in logic input voltage (in & sd) v ss v cc v t a ambient temperature -40 125 c
www.irf.com 4 IRS2509SPBF dynamic electrical characteristics v bias (v cc , v bs ) = 15 v, com = v cc , c l = 1000 pf, t a = 25 c, dt = v ss unless otherwise specified. symbol definition min typ max units test conditions t on turn-on propagation delay ? 750 1100 v s = 0 v or 600 v t off turn-off propagation delay ? 250 400 v s = 0 v or 600 v t sd shut-down propagation delay ? 250 400 mt delay matching, hs & ls turn-on/ off ? ? 60 t r turn-on rise time ? 150 220 v s = 0 v t f turn-off fall time ? 50 80 v s = 0 v dt deadtime: lo turn-o ff to ho turn-on(dt lo-ho) & ho turn-off to lo turn-on (dt ho-lo) 350 530 800 mt delay matching time (t on , t off ) ? ? 60 mdt deadtime matching = dt lo-ho - dt ho-lo ? ? 60 ns v in = 0 v & 5 v without external deadtime static electrical characteristics v bias (v cc , v bs ) = 15 v, v cc = com, dt = v cc and t a = 25 c unless otherwise specified. the v il, v ih and i in parameters are referenced to v cc /com and are applicable to the respective input leads: in and sd. the v o, i o parameters are referenced to com and are applicable to the respective output leads: ho and lo. symbol definition min typ max units test conditions v ih logic ?1? input voltage for ho & logic ?0? for lo 2.2 ? ? v il logic ?0? input voltage for ho & logic ?1? for lo ? ? 0.8 v oh high level output voltage, v bias - v o ? 0.8 1.4 i o = 20 ma v ol low level output voltage, v o ? 0.3 0.6 v i o = 20 ma i lk offset supply leakage current ? ? 50 v b = v s = 600 v i qbs quiescent v bs supply current ? 45 70 v in = 0 v or 4 v i qcc quiescent v cc supply current 1000 2000 3000 v in = 0 v or 4 v i in+ logic ?1? input bias current ? 5 20 v in = 4 v i in- logic ?0? input bias current ? ? 2 v in = 0 v i sd, th+ sd input positive going threshold ? 15 30 i sd, th- sd input negative going threshold ? 10 20 a v ccuv+ v bsuv+ v cc and v bs supply undervoltage positive going threshold 8.0 8.9 9.8 v ccuv- v bsuv- v cc and v bs supply undervoltage negative going threshold 7.4 8.2 9.0 v ccuvh v bsuvh hysteresis ? 0.7 ? v i o+ output high short circuit pulsed current 120 200 ? v o = 0 v, pw 10 us i o- output low short circuit pulsed current 250 350 ? ma v o = 15 v, pw 10 us
www.irf.com 5 IRS2509SPBF functional block diagrams lead definitions symbol description in logic input for high and low side gate driver outputs (ho and lo), in phase sd logic input for shutdown v b high side floating supply ho high side gate drive output v s high side floating supply return v cc low side and logic fixed supply lo low side gate drive output com low side return lead assignments
www.irf.com 6 IRS2509SPBF application information and additional details i nformations regarding the following topics are included as subsections within this section of the datasheet. ? igbt/mosfet gate drive ? switching and timing relationships ? deadtime ? matched propagation delays ? shut down input ? input logic compatibility ? undervoltage lockout protection ? shoot-through protection ? negative v s transient soa ? pcb layout tips ? additional documentation igbt/mosfet gate drive the irs2509 hvic is designed to drive mosfet or igbt power dev ices. figures 1 and 2 illustrate several parameters associated with the gate drive functionality of the hvic. the output current of the hvic, used to drive t he gate of the power switch, is defined as i o . the voltage that drives the gate of th e external power switch is defined as v ho for the high-side power switch and v lo for the low- side power switch; this parameter is sometimes generically called v out and in this case does not differentiate between the high-side or low-side output voltage. figure 1: hvic sourcing current figure 2: hvic sinking current
www.irf.com 7 IRS2509SPBF switching and timing relationships the relationships between the input and output signals of the irs2 509 are illustrated below in figur es 3, 4. from these figure s, we can see the definitions of several timing parameters (i.e. t on , t off , t r , and t f ) associated with this device. figure 3: switching time waveforms figure 4: input/output timing diagram deadtime this family of hvics features integrated deadtime protection ci rcuitry. the deadtime for these ics is fixed; other ics within ir?s hvic portfolio feature programmable deadtime for greater design flexib ility. the deadtime feature inserts a time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being turned off has fully turned off before the second power switch is turned on. this minimum deadtime is automatically inserter whenever the external deadtime is shorter than dt; external deadtimes larger than dt are not modified by the gate driver. figure 5 illustra tes the deadtime period and the relationship between the output gate signals. the deadtime circuitry of the irs2509 is matched with respect to the high- and low-side outputs. figure 6 defines the two dead time parameters (i.e., dt lo-ho and dt ho-lo ); the deadtime matching parameter (mdt) associ ated with the irs2509 specifies the maximum difference between dt lo-ho and dt ho-lo . matched propagation delays the irs2509 is designed with propagation delay matching circuitry. with this feature, the ic?s response at the output to a sig nal at the input requires approximately the same time duration (i.e., t on , t off ) for both the low-side channels and the high-side channels; the maximum difference is specified by the delay matchi ng parameter (mt). the propagation turn-on delay (t on ) of the irs2509 is matched to the propagation turn-on delay (t off ).
www.irf.com 8 IRS2509SPBF shut down input the irs2509 is equipped with a shut down (/sd) input pin that is used to shutdown or enable the hvic. when the /sd pin is in th e high state the hvic is able to operate normally. when the /sd pin is in low state the hvic is tristated. in ho lo 50% 50% 90% dt lo-ho mdt = dt lo-ho -dt ho-lo dt ho-lo 10% 90% 10% figure 5: shut down figure 6: dead time definition figure 7: delay matching waveform definition input logic compatibility the inputs of this ic are compatible with standard cmos and ttl outputs. the irs2509 has been designed to be compatible with 3.3 v and 5 v logic-level signals. the irs 2509 features an integrated 5.2 v zener clamp on the /sd. figure 8 illustrates an inp ut signal to the irs2509, its input threshold values, and the logic state of the ic as a result of the input signal.
www.irf.com 9 IRS2509SPBF input signal (irs23364d) v ih v il input logic level high low low figure 8: hin & lin input thresholds undervoltage lockout protection this family of ics provides undervo ltage lockout protection on both the v cc (logic and low-side circuitry) power supply and the v bs (high-side circuitry) power supply. figure 9 is used to illustrate this concept; v cc (or v bs ) is plotted over time and as the waveform crosses the uvlo threshold (v ccuv+/- or v bsuv+/- ) the undervoltage protection is enabled or disabled. upon power-up, should the v cc voltage fail to reach the v ccuv+ threshold, the ic will not turn -on. additionally, if the v cc voltage decreases below the v ccuv- threshold during operation, the undervoltage lockout circuitry will recognize a fault condition and shutdown the high- and low-side gate drive outputs, and the fault pin will transition to the low state to inform the controller of the fault condition. upon power-up, should the v bs voltage fail to reach the v bsuv threshold, the ic will not turn -on. additionally, if the v bs voltage decreases below the v bsuv threshold during operation, the un dervoltage lockout circuitry will recognize a fault condition, and shutdown the high-side gate drive outputs of the ic. the uvlo protection ensures that the ic drives the external power devices only when the gate supply voltage is sufficient to fu lly enhance the power devices. without this feat ure, the gates of the external power swit ch could be driven with a low voltage, re sulting in the power switch conducting current while the channel impedance is high; this could result in very high conduction losses wi thin the power device and could lead to power device failure. figure 9: uvlo protection shoot-through protection the irs2509 high-voltage ic is equipped with shoot-through pr otection circuitry (also known as cross-conduction prevention circuitry).
www.irf.com 10 IRS2509SPBF negative v s transient soa a common problem in today?s high-power switching converters is t he transient response of the swit ch node?s voltage as the power switches transition on and off quickly while carrying a large current. a typical 3-phase inverter circuit is shown in figure 1 1; here we define the power switches and diodes of the inverter. if the high-side switch (e.g., the igbt q1 in figures 12 and 13) switches off, while the u phase current is flowing to an induc tive load, a current commutation occurs from high-side sw itch (q1) to the diode (d2) in parallel with the low-side switch of the same inve rter leg. at the same inst ance, the voltage node v s1 , swings from the positive dc bus volt age to the negative dc bus voltage. figure 11: three phase inverter q1 on d2 v s1 q2 off i u dc+ bus dc- bus dc+ bus q1 off d1 d2 dc- bus v s1 q2 off i u figure 12: q1 conducting figure 13: d2 conducting also when the v phase current flows from the inductive load back to the inverter (see figures 14 and 15), and q4 igbt switches on, the current commutation occurs from d3 to q4 . at the same instance, the voltage node, v s2 , swings from the positive dc bus voltage to the negative dc bus voltage.
www.irf.com 11 IRS2509SPBF dc+ bus q3 off d3 dc- bus v s2 q4 on i v figure 14: d3 conducting figure 15: q4 conducting however, in a real inverter circuit, the v s voltage swing does not stop at the level of the negative dc bus, rather it swings below the level of the negative dc bus. this undershoot voltage is called ?negative v s transient?. the circuit shown in figure 16 depicts one leg of the three phas e inverter; figures 17 and 18 show a simplified illustration of the commutation of the current between q1 and d2. the parasitic inductances in the power circuit from the die bonding to the pcb tr acks are lumped together in l c and l e for each igbt. when the high-side switch is on, v s1 is below the dc+ voltage by the voltage drops associated with the power switch and the pa rasitic elements of the circuit. when the high-side power switch turns off, the loa d current momentarily flows in the low-side freewheeling di ode due to the inductive load connected to v s1 (the load is not shown in these figures). this current flows from the dc- bus (which is connec ted to the com pin of the hvic) to the load and a negative volta ge between v s1 and the dc- bus is induced (i.e., the com pin of the hvic is at a higher potential than the v s pin). figure 16: parasitic elements figure 17: v s positive figure 18: v s negative in a typical motor drive system, dv/dt is typically designed to be in the range of 3-5 v/ns. the negative v s transient voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in normal oper ation. international rectifier?s hvics have been designed for the robustn ess required in many of today?s demanding applications. an indication of the irs2509?s robustness can be seen in figure 19, where there is represented the ir s2509 safe operating area at v bs =15v based on repetitive negative v s spikes. a negative v s transient voltage falling in the grey area (outside soa) may lead to ic permanent damage; viceversa unwanted functional anomalies or perma nent damage to the ic do not a ppear if negative vs transients fall inside soa. at v bs =15v in case of -v s transients greater than -16.5 v for a period of time greater than 50 ns; the hvic will hold by design the high-side outputs in the off state for 4.5 s.
www.irf.com 12 IRS2509SPBF figure 19: negative v s transient soa for irs2509 @ vbs=15v even though the irs2509 has been shown able to handle these large negative v s transient conditions, it is highly recommended that the circuit designer always limit the negative v s transients as much as possible by careful pcb layout and component use. pcb layout tips distance between high and low voltage components: it?s strongly recommended to place the components tied to the floating voltage pins (v b and v s ) near the respective high voltage portions of the device. please see the case outline information in this datasheet for the details. ground plane: in order to minimize noise coupling, the ground plane should not be placed under or near the high voltage floating side. gate drive loops: current loops behave like antennas and are able to rece ive and transmit em noise (see figure 20). in order to reduce the em coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as possible. moreover, current can be injected inside the gate drive loop via the igbt collector-t o-gate parasitic capacitance. th e parasitic auto-inductance of t he gate loop contributes to developing a voltage ac ross the gate-emitter, thus increasing the pos sibility of a self turn-on effect.
www.irf.com 13 IRS2509SPBF figure 20: antenna loops supply capacitor: it is recommended to place a bypass capacitor (c in ) between the v cc and com pins. a ceramic 1 f ceramic capacitor is suitable for most applications. this component should be placed as close as possible to the pins in order to redu ce parasitic elements. routing and placement: power stage pcb parasitic elements can contribute to large negative voltage trans ients at the switch node; it is recommended to limit the phase voltage negative transients. in order to avoid such conditions, it is recommended to 1) m inimize the high-side emitter to low-side collector distance, and 2) mini mize the low-side emitter to negative bus rail stray inductanc e. however, where negative v s spikes remain excessive, further steps may be take n to reduce the spike. this includes placing a resistor (5 ? or less) between the v s pin and the switch node (see figure 21), and in some cases using a clamping diode between com and v s (see figure 22). see dt04-4 at www.irf.com for more detai led information. figure 21: v s resistor figure 22: v s clamping diode additional documentation several technical documents related to the use of hvics are available at www.irf.com ; use the site search function and the document number to quickly locate them. below is a short list of some of these documents. dt97-3: managing transients in control ic driven power stages an-1123: bootstrap network analysis: focusing on the integrated bootstrap functionality dt04-4: using monolithic high voltage gate drivers an-978: hv floating mos-gate driver ics
www.irf.com 14 IRS2509SPBF figures 23-45 provide information on the experimental performanc e of the irs2509 hvic. the line plotted in each figure is generated from actual lab data. a large number of individual samples from multiple wafer lots were tested at three temperatures (-40 oc, 25 oc, and 125 oc) in order to generate th e experimental (exp.) curve. the line labeled exp. consist of three data points (one data point at each of the tested temperatur es) that have been connected together to illustrate the understood trend. the individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). fig. 23. turn-on propagation delay vs. tem p erature fig. 24. turn-off propagation delay vs. tem p erature fig. 25. turn-on rise time vs. temperature fig. 26. turn-off rise time vs. temperature 0 300 600 900 1200 1500 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on propagation delay (ns) exp . 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off propagation delay (ns ) exp. 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on rise time (ns) exp . 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off fall time (ns) exp . `
www.irf.com 15 IRS2509SPBF fig. 27. v cc supply uv hysteresis vs. temperature fig. 28. v bs supply uv hysteresis vs. temperature fig. 29. v cc quiescent supply current vs. temperature fig. 30. v bs quiescent supply current vs. temperature fig. 31. v ccuv+ threshold vs. temperature fig. 32. v ccuv- threshold vs. temperature 0 1 2 3 4 -50 -25 0 25 50 75 100 125 temperature ( o c) v ccuv hysteresis (v) exp . 0 1 2 3 4 -50 -25 0 25 50 75 100 125 temperature ( o c) v bsuv hysteresis (v) exp . 0 2 4 6 8 10 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc quiescent current (ma) exp . 0 20 40 60 80 100 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs quiescent current (a) exp . ` 0 3 6 9 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v ccuv+ threshold (v) exp . 0 3 6 9 12 -50-25 0 255075100125 temperature ( o c) v ccuv- threshold (v) exp .
www.irf.com 16 IRS2509SPBF fig. 34. v bsuv- threshold vs. temperature fig. 37. in v th+ vs. temperature fig. 33. v bsuv+ threshold vs. temperature fig. 35. low level output voltage vs. temperature fig. 36. high level output voltage vs. temperature 0 3 6 9 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v bsuv+ threshold (v) exp . 0 3 6 9 12 -50-25 0 255075100125 temperature ( o c) v bsuv- threshold (v) exp . 0 100 200 300 400 -50 -25 0 25 50 75 100 125 temperature ( o c) low level output voltage (mv) ex p. 0 100 200 300 400 -50 -25 0 25 50 75 100 125 temperature ( o c) high level output voltage (mv) exp. 0 2 4 6 8 -50 -25 0 25 50 75 100 125 temperature ( o c) in v th+ (v) exp .
www.irf.com 17 IRS2509SPBF fig. 38. lin v th- vs. temperature fig. 39. hin v th+ vs. temperature fig. 40. hin v th- vs. temperature fig. 41. tbson_v cc typ vs. temperature 0 2 4 6 8 -50 -25 0 25 50 75 100 125 temperature ( o c) in vth- (v) exp . 0 2 4 6 8 -50 -25 0 25 50 75 100 125 temperature ( o c) hin v th+ (v) exp . 0 2 4 6 8 -50 -25 0 25 50 75 100 125 temperature ( o c) hin v th- (v) exp. 0 10 20 30 40 50 -50 -25 0 25 50 75 100 125 temperature ( o c) tbson_vcctyp(ns) exp . 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) shut-down propagation delay (ns) exp. fig. 42. shut-down propagation delay vs. temperature 0 200 400 600 800 1000 -50 -25 0 25 50 75 100 125 temperature ( o c) deadtime (ns) exp . fig. 43. deadtime vs. temperature
www.irf.com 18 IRS2509SPBF 0 10 20 30 40 50 -50 -25 0 25 50 75 100 125 temperature ( o c) mt (ns) exp. fig. 44. delay matching vs. temperature 0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 125 temperature ( o c) mdt (ns) exp . fig. 45. deadtime matching vs. temperature
www.irf.com 19 IRS2509SPBF case outlines
www.irf.com 20 IRS2509SPBF tape and reel details: 8l-soic e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c carrier tape dimension for 8soicn code min max min max a 7.90 8.10 0.311 0.318 b 3.90 4.10 0.153 0.161 c 11.70 12.30 0.46 0.484 d 5.45 5.55 0.214 0.218 e 6.30 6.50 0.248 0.255 f 5.10 5.30 0.200 0.208 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 8soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 18.40 n/a 0.724 g 14.50 17.10 0.570 0.673 h 12.40 14.40 0.488 0.566 metric imperial
www.irf.com 21 IRS2509SPBF the information provided in this document is believed to be accurate and reliable. however, international rectifier assumes no responsibility for the consequences of t he use of this information. in ternational rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. no license is granted by implication or otherwise u nder any patent or patent rights of international rectifier. the specifications mentioned in this document are subject to change without notice. this document supersedes and replaces all inform ation previously supplied. for technical support, please contact ir?s technical assistance center http://www.irf.com/technical-info/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 order information 8-lead soic IRS2509SPBF 8-lead soic tape & reel irs2509strpbf s2509

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