View AN3404_8235880.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

september 2012 doc id 018847 rev 3 1/30 AN3404 application note low power considerations for stm8tl5xxx devices introduction this document is intended for touch sensing application designers who require an overview of low power modes in the stm8tl5xxx devices. it describes how to use the general features of these devices in low power modes by explaining the differences between the various modes. it focuses on how to reduce consumption when using the proxsense peripheral and demonstrates how this is managed by the stm8tl5x stmtouch library in addition to giving some code examples. this application note is not intended to replace the stm8tl 5xxx datasheet. all values given in this document are for guidance only. for guaranteed values, please refer to the stm8tl5xxx datasheet. table 1. applicable products type product sub-class microcontroller stm8tl5xxx www.st.com
contents AN3404 2/30 doc id 018847 rev 3 contents 1 power consumption factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 internal supply structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 clock system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 default clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 clock configuration and power management . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 clock selection versus power consumption . . . . . . . . . . . . . . . . . . . . . . . . 8 4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 overview of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 slowing down the clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 peripheral clock gating (pcg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5 execution from ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.6 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.6.1 entering wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.6.2 exiting wait for interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6.3 exiting wait for event mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7.1 entering halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7.2 exiting halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 active-halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8.1 entering active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8.2 exiting active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.9 activation level control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 general power management tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 choosing the optimal low power mode for your application . . . . . . . . . . . 16 5.2 gpio initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 dynamic control of pull-up resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AN3404 contents doc id 018847 rev 3 3/30 5.4 waiting loops/delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 minimizing power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 proxsense and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 possible cpu low power modes combined with proxsense . . . . . . . . . . 19 6.2 main factor of the proxsense acquisition consumption . . . . . . . . . . . . . . 19 6.3 low power features in the proxsense peripheral . . . . . . . . . . . . . . . . . . . 20 6.3.1 low_power bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3.2 stabilization time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3.3 bias parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3.4 inactive state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3.5 receiver disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 low power mode management by the stm8tl5x stmtouch library 22 7.1 configuration available in the stm8_tsl_con f.h file . . . . . . . . . . . . . . . . . . 22 7.1.1 acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1.2 low_power bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1.3 stabilization time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1.4 bias parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1.5 receiver configuration when disabled . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1.6 transmitter configuration when disabled . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 practical code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2.1 low power management with all acquisition banks . . . . . . . . . . . . . . . . 24 7.2.2 very low power management with proximity detection . . . . . . . . . . . . . 25 8 conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
power consumption factors AN3404 4/30 doc id 018847 rev 3 1 power consumption factors the stm8tl5xxx microcontrollers are digital logic devices using the complementary metal oxide semiconductor (cmos) technology. in these type of devices, power consumption is a sum of: static power (mainly caused by transistor polarization and leakage) dynamic power which depends on the supply voltage and the clock frequency dynamic power is calculated using equation 1 . equation 1 where: c is the cmos load capacitance v is the supply voltage f is the clock frequency static consumption is negligible compared to dynamic consumption when the clock is running. in some low power modes, when no clock is running, static consumption is the main consumption source. total consumption is a sum of static and dynamic consumption as given by equation 2 . equation 2 where: i dd is the supply current i dynamicrun is the current consumption dependent on the cpu frequency i static is the current consumption independent on the cpu frequency dynamic power c v 2 f ? ? = i dd fi dynamicrun ? a mhz ?? ? ?? i static a ?? + =
AN3404 power consumption factors doc id 018847 rev 3 5/30 consequently, power consumption depends on: the microcontroller unit (mcu) chip size this includes the technology used, the number of transistors, and the analog features/peripherals embedded and used in the application. the mcu supply voltage the amount of current used in cmos logic is directly proportional to the square of the power supply voltage (v2). thus, power consumption may be reduced by lowering the mcu supply voltage. this is less critic al for stm8tl5xxx devices than for other microcontrollers, as an internal voltage regulator is used. however, the mcu supply voltage could have an impact on the remaining components on the board. the clock frequency power consumption may be reduced by decreasing the clock frequency when fast processing is not required by the application. the number of active peripherals or mcu features used (such as timers, communication peripherals, watchdogs, proxsense, etc.) the greater the number of active peripherals or features, the greater the amount of power consumed. the operating mode power consumption depends on which mode a particular application is running (example: central processing un it (cpu) on/off, o scillator on/off). fo r an application powered by a battery, the consumption is very important. usually, the average consumption should be below a certain target value to ensure an optimum battery lifetime. this means that an application can consume more for short periods of time and keep its average current consumption below the target value.
power supply AN3404 6/30 doc id 018847 rev 3 2 power supply the stm8tl5xxx family embeds two regulators which provide a supply voltage (v core ) for the core and internal peripherals. figure 1. power supply overview 1. each power supply pair must be decoupled with filtering ceramic c apacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins to ensure the correct functionality of the device. 2. the 1 f capacitor must be connected to the v dd pin. 3. the 1 f ceramic capacitor connected to pxs_vreg must be low esr (esr ? 1 ? ). the main voltage regulator (mvr) provides a 1.8 v supply voltage but in case v dd is lower than 1.8 v, the mvr delivers v dd to v core . it has a high current capa bility, as it can deliver up to 25 ma. however, the consumption of this regulator is higher than the consumption of the lpvr. consequently, the mvr is used during a standard operation only. the consumption of the lpvr is very low as required for low power modes. the lpvr can deliver up to 200 a, providing 1.55 v to the digital part of the mcu. after reset, the mvr provides a supply voltage (v core ) to the internal digital parts of the microcontroller. depending on the functional mode, the mvr can be switched off. in this case, the lpvr continues to provide the v core voltage. the power supply is monitored by the power-on reset/power-down reset (por/pdr). this system ensures a proper startup and reset of the mcu, while v dd rises above the por threshold. it resets the mcu when v dd falls below the pdr threshold. 6domain 083?62%' 6 $$ ) / 6 $$ 6 33 ) / 6 33 n& 6 $$ ?& 6 $$ ?& n& ai !nalogblocks 6oltageregulator mainvoltageregulator-62 lowpowervoltageregulator,062 -(z2#oscillator(3) k(z2#oscillator,3) ,inearvoltageregulator $igitalblocks )/s 34--#5core #05 2!- &lashprogrammemory $ata%%02/- 4imers #ommunication peripherals 0rox3enseinterface 4ransmit)/s 2eceive)/s !nalog0rox3ensesystem 6 #/2%
AN3404 power supply doc id 018847 rev 3 7/30 2.1 internal supply structure stm8tl5xxx devices operate from 1.65 v up to 3.6 v, when connected to one pair of supply pins. there are no dedicated supply pins for the analog voltage domain. it is recommended to use a decoupling ceramic capacitor placed close to the supply pins . in run and wait modes, both mvr and lpvr provide the v core in halt/active-halt modes, the lpvr is aut omatically used while the mvr is switched off by the system in order to reduce current consumption.
clock management AN3404 8/30 doc id 018847 rev 3 3 clock management 3.1 clock system overview the 16 mhz high-speed internal rc oscillator (hsi) is the only clock source that can be used to drive the system clock. the 38 khz low-speed internal rc oscillator (lsi) is only used to supply the auto-wakeup unit (awu) and watchdog. each peripheral clock can be switched on or off independently, in order to optimize power consumption when the peripheral is not used. this is done by using the peripheral clock gating (pcg) feature. see the ?clock control (clk)? section of the stm8tl5xxx microcontroller family reference manual (rm0312) for more details. 3.2 default clock source the default clock source after reset is hsi/8. th e user can then switch the clock to different frequencies by choosing the prescaler (/1, /2, /4 or /8) for the internal rc 16 mhz (hsi) clock through the hsidiv[1:0] bits in the clock divider (clk_ckdivr) register. 3.3 clock configuration and power management in addition to the flexibility of the cloc k sources, different complementary clock configurations and features are available to optimize the power consumption of the device: each peripheral clock can be switched on/off through the peripheral clock gating registers 1 and 2 (clk_pckenrx). system clock dividers from 1 to 8 (hsidiv[1:0] bits in the clk_ckdivr register) are available. note: system clocks are used to supply both cpu and peripherals. the stm8tl5xxx is focused on low consumption. this is why all peripheral clocks are gated by default. before accessing any peripheral register, it is mandatory to enable the clock for the given peripheral. 3.4 clock selection versus power consumption the selected clock type and speed is one of the major factors influencing power consumption of the mcu (see section 1: power consumption factors ). total consumption for the stm8tl5xxx devices is given by equation 3 . equation 3 note: the values given in equation 3 are measured with all peripherals disabled. i dd(stm8tl5x) f 150 ?? a ?? mhz ? ?? 215 ? a ?? + =
AN3404 clock management doc id 018847 rev 3 9/30 slowing down the clock decreases the immediate consumption but, often this is not the ideal solution. by slowing down the clock, the cpu performance is also reduced and a longer time is required to perform an action or computation. if we consider the average consumption, it might be better to use the highest available clock speed to perform the required operation, and then force the mcu into one of the low power modes (like active- halt mode) for the remaining time frame. this should be taken into account during the design of application flowcharts.
low power modes AN3404 10/30 doc id 018847 rev 3 4 low power modes by default, after a reset, the microcontroller is in run mode. the default cpu clock is 2 mhz (hsi/8). several low power modes are available to save power when the cpu is not used for a standard operation (for instance: waiting for an external event). it is up to the user to select the mode that gives the best compromise between low power consumption, short startup time, good peripheral functionality, and availa bility of wakeup source s. those power modes are listed in section 4.2: overview of low power modes . power consumption in run and wait modes can be reduced by one of the following means: slowing down the system clocks executing code from ram gating the clocks to the peripherals when they are not used 4.1 flash memory on stm8tl5xxx devices, the flash is automatically switched off when halt or active-halt mode is entered. 4.2 overview of low power modes the stm8tl5xxx devices feature the following main low power modes: wait mode: cpu stopped and peripherals kept running active-halt mode: cpu stopped; proxsens e (pxs), awu, and in dependent wa tchdog (iwdg) kept running if they are already enabled. halt mode: cpu and peripheral clocks stopped in all low power modes, the general purpose i/os continue to actively drive outputs. the mcu can be woken up from these low powe r modes by specific interrupts, including through the proxsense and incoming communications on the serial peripheral interface (spi), inter-integrated circuit (i2c), and/or universal synchronous/asynchronous receiver transmitter (usart). refer to the interrupt mapping table in the stm8tl5xxx datasheet. ta bl e 2 lists the stm8tl5xxx low power modes, shows the basic behavior of stm8tl5xxx devices, and demonstrates the influence of different low power modes on the cpu, peripherals and consumption.
AN3404 low power modes doc id 018847 rev 3 11/30 4.3 slowing down the clock frequency in run mode, choosing the clock frequency is very important to ensure the best compromise between performance and consumption. the selection is done by programming the prescaler registers. these registers can also be used to slow down the peripherals before entering a low power mode. 4.4 peripheral clock gating (pcg) peripheral clock gating (pcg) can be used for additional power saving. this can be done at any time by selectively enabling or disabling the clock connection to individual peripherals through the clk_pckenrx registers. these settings are effective both in run and wait modes. note: as all peripheral clocks are gated by default after reset on stm8tl5xxx devices, it is mandatory to enable the clock for a given peripheral before accessing any peripheral register. 4.5 execution from ram the code can be executed from ram in order to save power consumption. however, due to the difference between the size of the data and the instruction bus from flash (32-bit) and ram (8-bit), performance is degraded when exec uted from ram. it is important to take into account the performance and the ratio between run/halt operations. figure 2 shows the different bus widths for flash and ram memories. table 2. low power mode summary low power modes entry instruction functions low power mode consumptions cpu peripherals hsi lsi flash ram stm8tl5xxx typical values @ 3 v/25c wait wfe or wfi off can be enabled on on on on 500 a active-halt with proxsense halt off on off on 600 a (1) 1. value during an acquisition (see the stm8tl5xxx datasheet) with 1 transmitter and 1 receiver. active-halt with awu on off on 1.0 a halt off off on 0.4 a
low power modes AN3404 12/30 doc id 018847 rev 3 figure 2. stm8tl5xxx architecture 1. legend: i-bus = instruction bus, d-bus = databus, swim = single wire interface module; itc = interrupt controller 4.6 wait mode the stm8tl5xxx devices support two different wait modes: wait for interrupt (wfi) and wait for event (wfe). both modes are de signed to reduce stm8tl5xxx device power consumption by switching off the core when it is not used. wait mode is mainly used when the stm8tl5xxx is waiting for an external or internal event so that the program execution can continue. the polling loop on an associated peripheral flag can be efficiently replaced by a wait instruction (wfi() or wfe()) after having correctly configured the interrupt related to this flag or the event in the wfe register. wait mode can be combined with peripheral clock gating and a low-speed clock source to further reduce the power consumption of the device. wait mode also offers the lowest wakeup time which is interesting for applications requesting a fast response time. 4.6.1 entering wait mode wait mode is entered by executing the wfi or wfe assembly instruction. this stops the cpu, but other peripherals and the interrupt controller can continue to run. when entering wait mode, the global interrupts are automatically enabled. before entering wfi mode, at least one interrupt must be enabled. before entering wfe mode, at least one event source must be enabled. aib bit bit bit 2!- 0eripherals -emory controller ) "us $ "us 34-core )nterruptcontrol )nterrupt 37)-protocol )4# $ebug 37)- )nstruction memory and $ata %%02/-
AN3404 low power modes doc id 018847 rev 3 13/30 4.6.2 exiting wait for interrupt mode when an internal or external interrupt request occurs, the cpu wakes up from wait mode, serves the interrupt routine and resumes processing. the following list gives examples of peripherals or features with interrupts having exit-from- wait capability: proxsense i2c usart spi awu external interrupt timers refer to the stm8tl5xxx reference manual (rm0312) for more details. 4.6.3 exiting wait for event mode when an internal or external event request occurs, the cpu wakes up from wait mode and resumes processing. the following list gives examples of peripherals or features with events having exit-from-wait capability: proxsense i2c usart spi external interrupt timers if an interrupt occurs during wait for event mode, the related interrupt service routine is executed. after this routine, the mcu goes back to wait for event mode. refer to the stm8tl5xxx reference manual (rm0312) for more details. 4.7 halt mode in this mode the system clock is stopped. this means that the cpu and all the peripherals requiring clocks are disabled, except for the following cases: the hsi clock is not stopped if used by the swim the system clock source is not stopped if a flash/ data eeprom write operation is in progress. the lsi clock is not stopped if used by the swim, by the iwdg or if the ?iwdg_halt? option bit is disabled. in halt mode, none of the peripherals is clocked and the digital part of the mcu consumes almost no power.
low power modes AN3404 14/30 doc id 018847 rev 3 4.7.1 entering halt mode the mcu enters halt mode when a halt instruction is executed. before executing a halt instruction, the application must clear any pending peripheral interrupt by clearing the interrupt pending bit in the corresponding peripheral configuration register. otherwise, the halt instruction is executed but the mcu wakes up immediately and the program execution continues. 4.7.2 exiting halt mode wakeup from halt mode is triggered by an external interrupt. this wakeup is sourced by a general purpose i/o port configured as an interrupt input or by an alternate function pin capable of triggering a peripheral interrupt. the system clock is then restarted at the la st selected clock source before the system enters halt mode. in an interrupt-based application, where most of the processing is done through the interrupt routines, the main program may be suspended by setting the activation level bit (al) in the global configuration (cfg_gcr) register. refer to section 4.9: activation level control on page 15 . 4.8 active-halt in active-halt mode, the main oscillator, the cpu, and almost all peripherals are stopped. only the lsi rc oscillator runs to dr ive the swim and iwdg, if enabled. 4.8.1 entering active-halt mode the user can enter this mode by a halt instruction, once auto-wakeup (awu) is enabled or a proxsense acquisition is ongoing. proxsense acquisition must have started or the awu must have been correctly configured and enabled, before executing the halt instruction. 4.8.2 exiting active-halt mode wakeup from active-halt mode is triggered by an external interrupt, a proxsense interrupt or an awu interrupt. the system clock is then restarted at the la st selected clock source before the system enters halt mode. in an interrupt-based application, where most of the processing is done through the interrupt routines, the main program may be suspended by setting the activation level bit (al) in the global configuration (cfg_gcr) register. refer to section 4.9: activation level control .
AN3404 low power modes doc id 018847 rev 3 15/30 4.9 activation level control stm8tl5xxx devices support an automatic acti vation level control feature. consequently, the user can configure the mcu so that it directly returns to a low power mode after it has been woken up from such a mode through interrupts. in an interrupt-based application, where most of the processing is done through the interrupt routines, the main program may be suspended by setting the activation level bit (al) in the cfg_gcr register. setting the al bit in the cfg_gcr register (see section 4.9: activation level control on page 15 ) causes the cpu to return to low power mode after exiting an interrupt service routine without restoring the main execution context when the iret instruction is executed. this saves power by removing both the save/restore context activity and the need for a main software loop execution for power management (in order to return to low power mode). to return to the main loop, the al bit has to be cleared by software. this must be done at least two clock cycles before the iret instruction is executed.
general power management tips AN3404 16/30 doc id 018847 rev 3 5 general power management tips 5.1 choosing the optimal low power mode for your application different low power modes can be selected depending on your application: applications powered by a battery where the mcu is in sleep mode most of the time: ? if the mcu is woken up due to external events, no time tracking is necessary and power consumption has to be as low as po ssible. halt mode is advised to extend battery life as much as possible. ? active-halt mode with awu clocked by the lsi is advised if the application does not only depend on external events, but needs a non accurate periodic wakeup. applications powered by a battery where the mcu is awake most of the time: ? active-halt mode is advised if the mcu has to perform a few periodic actions using no peripheral except the proxsense. ? wait mode is advised if at least one peripheral should be enabled all the time and an interrupt or event can wake up the mcu. applications supplied by mains bu t where consumption is critical: ? run mode, with a clock prescaler adapted to the application requirement, is advised if the mcu has to run all the time and low power modes cannot be used. 5.2 gpio initialization by default, the i/os are configured as floating input. it is important to change the configuration of all i/os that are not connected to defined logic signals so as to obtain one of the following configurations: input configuration with pull-up output configuration with a low (or high) logic level otherwise, an increased consumption is generated by noise, as the internal schmitt triggers detecting this noise are toggling. floating i/os could generate additional consumption in the range of a few 10 a. in 28-pin packages, the unbounded i/os are connected to a defined level by factory option configuration. in 20-pin packages, the following pins pa6, pa7, pd2, pd3 and pd7 must be configured in output push-pull low level by the application code in order to avoid extra consumption on these unbounded pins.
AN3404 general power management tips doc id 018847 rev 3 17/30 5.3 dynamic control of pull-up resistor many applications have buttons which are used as a user interface. these buttons are connected to i/os that are connected to v ss once they are pressed. an internal pull-up is used in order to have a defined logic level on these i/os when the button is off (not pressed). once the button is pressed, the i/o is grounded and it generates an additional current of ~ 40 ? 70 a, drawn from the power supply. this current is negligible if the application is in run mode, but becomes very important for a pplications which run mainly in low power modes. for such low-power applications, the pull-up can be dynamically controlled. once a button is pressed, the related service routine is executed. this routine disables the pull-up and the interrupt, in order to save consumption while the button is being pressed. as the application has to check the button status regularly, the pull-up is enabled again before any checks are made. if the button is continuously pressed, the process is repeated. once the button release is detected, the pull-up remains on. for this task, an i/o can be left floating for a short time frame, given by a check period, generating an extra consumption in the range of ~10 a. therefore, the total current consumption for a button-press operation is lower than without such dynamic control. 5.4 waiting loops/delays in some cases, the application has to wait for an input from the user, communication peripheral, or another external unit. if there is no useful code to execute while waiting for an input, it is recommended to avoid using either a typical delay loop or a polling loop. typical delay loop: (delay = 0; delay < 0xffff; delay++) _asm ("nop"); polling loop: spi_dr = data; // start communication while (!( spi_sr & spi_sr_txe)); // wait for txe bit set a wait mode woken up by an interrupt on the spi transmitter empty (spi_sr_txe flag) is advised by the following sequence: enable txe interrupt: spi_icr |= spi_txie; // enable interrupt for tx empty an event is then generated after each byte is sent. the next data can be loaded in the tx buffer as follows: spi_dr = data; // start communication _asm ("wfi"); //or wfi() if you include stm8tl5x.h file in your project the sequence described above uses wfi mode to wait for tx buffer empty. a delay loop can be replaced by a wait mode woken up by a programmed timer interrupt or better an active- halt with awu if no other peripheral is running. this can also be used for other communication lines. for external sources (like interrupt from an i/o port), halt mode can also be considered.
general power management tips AN3404 18/30 doc id 018847 rev 3 5.5 minimizing power consumption the following recommendations can help the user choose the right configurations to minimize power consumption of the device in the application: switch off all unused peripherals (peripherals are switched off by default) and use the peripheral clock gating (pcg) feature (through the clk_pckenrx registers) to disable the clock provided to the peripherals when not in use (these clocks are disabled by default). all unused pins must be connected to a defined logic level. one option is to configure them as output low level. make sure there are no unused i/o pins configured as a floating input. this needlessl y leads to high consumption. use wait mode if external wakeup capability is needed in low power mode and if some peripherals have to remain active. use the appropriate v dd value for the application. the higher the v dd value, the more power is consumed. thanks to the internal regulator, which supplies internal structures of the mcu, there is no major difference in the mcu consumption but, the difference could be visible at the application level, for example, due to the current flowing through the pull-up resistors out of the mcu. use active-halt and halt modes as much as possible. to achieve this, shorten the time spent in run mode, for example, by using the highest clock speed in run mode. when a low power mode cannot be used, use the minimum possible frequency for the application. select the frequency value that meets requirements. use the dynamic control pull-up configuration if possible (see section 5.3: dynamic control of pull-up resistor on page 17 ).
AN3404 proxsense and low power modes doc id 018847 rev 3 19/30 6 proxsense and low power modes 6.1 possible cpu low power modes combined with proxsense once a proxsense acquisition is launched, the cpu and its clock are not needed to perform the acquisition. wait modes, entered by a wfe or a wfi instruction, can be used as well as active-halt mode by executing a halt instruct ion. if wfe is used, either a pxs interrupt or the pxs event must be enabled but, if wfi or ha lt is used then a pxs interrupt must be enabled. in most cases, the pxs end of completion interrupt is used. in active-halt, it is possible to combine the auto-wakeup with the proxsense. the acquisition can be time limited by conf iguring the maximum counter enable regi ster (pxs_maxenr) and maximum counter value register (pxs_maxr). activation level (al bit set in cfg_gcr register) can be used in the case of successive acquisitions. the al bit should be reset once the last acquisition has been performed in order to return to the main processing and take the appropriate action according to the acquisition results. 6.2 main factor of the proxsense acquisition consumption the best way to reduce consumption of the proxsense acquisition itself is to decrease the acquisition time. this can be done by setting the proxsense in order to get a lower count when the key is not touched. in the stm8tl5x stmtouch library, this is done by reducing the key_target_reference parameter in the touch sensing config uration file. this must be done carefully as reducing this count also reduces the sensitivity of the touchkey. a trade-off must be found between the consumption and the sensitivity. table 3. proxsense compatibility with low power modes low power mode instruction exi t by pxs cpu hsi hsi_pxs synchro (1) 1. ?synchro? indicates compatibility with the synchronization feature. wait wfe yes off off on yes wfi yes off off on yes active-halt halt yes off off on no (2) 2. once in active-halt, the synchronization edge cannot be detected by the proxsense peripheral but, active- halt mode can be entered once the acqui sition is started. to synchronize with an external signal, the acquisition must be launched from an external interrupt routine. halt halt no off off off no
proxsense and low power modes AN3404 20/30 doc id 018847 rev 3 6.3 low power features in the proxsense peripheral power consumption can be reduced in different ways between proxsense acquisitions. the proxsense can be switched off and its clock gated by resetting the pckenr17 bit in the clk_pckenr1. consequently, the proxsens e has the following special low-power features. 6.3.1 low_power bit the most efficient way to reduce power consum ption between two acquisitions is to set the low_power bit in the pxs control register 1 (pxs_cr1). in this case, the proxsense clock (hsi_pxs) and the proxsense regulator are switched off as soon as an acquisition is completed and the results are still available in the pxs counter re gister of receiver channel n (pxs_rx n cntr). by switching off the proxsense regulator, a stab ilization delay is intro duced at the beginning of each new acquisition. this delay time de pends on the number of enabled pxs_rx pins. for a few receivers, a 1.7 ms delay must be selected. for successive acquisitions, it is recommended to reset the low_power bit and to set the proxsense interrupt to a high priority. this saves the stabilization ti me on the one hand and greatly reduces the time between the acquisitions while the proxsense clock and regulator are set. the low_power bit must be set again once the last acquisition has been launched. in this way, the regulator and the clock are switched off as soon as the last acquisition is completed. 6.3.2 stabilization time the stabilization time is needed to ensure t he regulator is fully operat ional at start-up. this delay can be set at different values in t he pxs control register 3 (pxs_cr3). the values are: 1.7 ms (default), 500 s or 120 s. the more the regulator is loaded, the faster the stabilizat ion. in other words, launching an acquisition with many receivers enabled speeds up the regulator stabilization. but, it is the impedance of the receivers that is more important than their number. the best way to check that the stabilization time is long enough, is to perform two successive acquisitions without switching off the regulator between them, in ensuring that the proxsense is off before the first acquisition. if the results of the two acquisitions are similar, this means the regulator is correctly stabilized before the first acquisition. in case of successive acquisitions, in order to select the lowest stabilization time, the acquisition with the maximum number of receivers must be launched first. 6.3.3 bias parameter this is the nominal bias current for the opamp which maintains the pxs_rx n pins at the final (discharged) voltage while the transmit lines are transitioning (back) low. this function is valid only for projected capacitance meas urements. a higher bias is needed when the projected capacitance (the capacitance betw een each rx line and each tx line) is high. this parameter is set in pxs_cr3. the lowe r its value, the less the consumption.
AN3404 proxsense and low power modes doc id 018847 rev 3 21/30 6.3.4 inactive state it is recommended to set the inactive state of the receivers and transmitters to v ss in order to avoid driving noise on these lines this also allows consumption to be reduced through the pxs_rx and pxs_tx pins compared to if th ey were configured in floating state. 6.3.5 receiver disabling between acquisitions, if the proxsense is not switched off by resetting the pxs_en bit in the pxs control register 1 (pxs_cr1) or by setting the low_power bit, there is a static consumption which depends on the number of enabled receivers. to reduce this consumption, it is worth disabling all the re ceivers by resetting the pxs receiver enable register (pxs_rxenr). this is particularly relevant for applications that need a fast response time and which cannot use the low_power bit option du e to the stabilization time.
low power mode management by the stm8tl5x stmtouch library AN3404 22/30 doc id 018847 rev 3 7 low power mode management by the stm8tl5x stmtouch library 7.1 configuration available in the stm8_tsl_conf.h file this section presents the parameters of the library, corresponding to the features presented in section 6: proxsense and low power modes . 7.1.1 acquisition time the acquisition time depends on the: 1. frequency of the acquisition 2. up and pass length 3. average value targeted when there is no touch frequency of the acquisition the frequency of the acquisition is set in the tslprm_pxs_hsi (the high-speed internal clock that is dedicated to the analog proxsense system). the possible frequencies are: 16 mhz (tslprm_pxs_hsi 16000) 8 mhz (tslprm_pxs_hsi 8000) 4 mhz (tslprm_pxs_hsi 4000) 2 mhz (tslprm_pxs_hsi 2000) 1 mhz (tslprm_pxs_hsi 1000) 500 khz (tslprm_pxs_hsi 500) 250 khz (tslprm_pxs_hsi 250) 125 khz (tslprm_pxs_hsi 125) up and pass length up and pass are the two active phases of a pr oxsense acquisition cycle. their length must be selected in order to ensure a correct char ge and discharge of the projected capacitance between each receiver/transmitter pair. if the up and pass lengths are set for a value of less than five by tslprm_pxs_up_length and tslprm_pxs_p ass_length definiti ons, each phase lasts this value (tslprm_pxs_up_leng th/ tslprm_pxs_pass_length) + 0.5 cycles. for a value greater than or equal to five, each up and pass length is 2^(tslprm_pxs_up_length-2)+0.5 cycles and 2^(tslprm_pxs_pass_length- 2)+0.5 cycles. if the tslprm_pxs_up_length and ts lprm_pxs_pass_length are equal, ta bl e 4 gives the correspondence between the up and pass length value and the number of cycles of a complete phase (up + pass + deadtimes).
AN3404 low power mode management by the stm8tl5x stmtouch library doc id 018847 rev 3 23/30 m average value targeted when there is no touch the average value targeted when there is no touch is set in the tslprm_key_target_reference definition. this value defines how long the acquisition lasts. if this value is set to 1 000, the acquisition of a receiver set lasts approximately 1000 times the proxsense cycle length. the lower this value, the lower the consumption but, the lower the key sensitivity. 7.1.2 low_power bit the low_power bit is set if tslprm_pxs_low_power_mode is defined as 1. the firmware library detects if several acquisit ions are launched successively. in this case, the low_power bit is reset until the last acqu isition is launched. this avoids having to wait for the stabilization ti me at each acquisition. 7.1.3 stabilization time the stabilization time is defined by the tslprm_pxs_stab definition. it can be set to: long_stab (default stabilization time) for 1.7 ms medium_stab for 500 s short_stab for 250 s 7.1.4 bias parameter the bias parameter is defined by the tslp rm_pxs_bias definition. it can be set to: high_bias for 10 a (default bias) medium_bias for 7.5 a low_bias for 5 a very_low_bias for 2.5 a table 4. proxsense cycle length tslprm_pxs_up _length and tslprm_pxs_pass_length value proxsense cycle length (in hsi_pxs period) 14 26 38 410 518 634 766
low power mode management by the stm8tl5x stmtouch library AN3404 24/30 doc id 018847 rev 3 7.1.5 receiver config uration when disabled the receivers are configured, when disabled, according to the tslprm_pxs_inactive_rx definit ion. the respective bit is reset in the receive enable register (pxs_rxenr). the tslp rm_pxs_inactive_ rx definition can be defined as 0 to drive the receivers to ground or it can be set to 1 to keep them floating. when the receiver group a is selected, all group b receivers are configured according to the tslprm_pxs_inactive_rx definition. the receiver pxs_rx pins are fully dedicated to proxsense acquisition, i.e. they cannot be used for general purposes and are configured and driven according to the proxsense configuration even if they are not used by any of the acquisition banks. 7.1.6 transmitter configuration when disabled the transmitters, which are defined in an acquisition bank and not enabled in the transmit enable register (pxs_txenr), ar e configured according to the tslprm_pxs_inactive_tx definition. the tslprm_pxs_inactive_tx definition can be defined as 0 to drive the transmitters to ground or it can be set to 1 to keep them floating. the gpios which support the tr ansmitter (pxs_tx) alternate function, but which do not belong to any acquisition bank or acquis ition transmitter definition (example, bank_ x _tx) are not configured by the stm8tl5x stmtouch library. it is the responsibility of the application code developer to configure the gpios which are not used for proxsense acquisition. 7.2 practical code example section 7.2 presents two code examples. both are based on the stm8tl5x stmtouch library. the first example (see section 7.2.1: low power man agement with all acquisition banks ) is a general case using all the acquisition banks as defined by default. the second example (see section 7.2.2: very low power management with proximity detection ) configures the system in a very low power mode using active-halt mode, with the awu and proxsense waiting for a proximity detection. 7.2.1 low power management with all acquisition banks this example shows how to perform all bank acquisitions with minimum code executed by the application and a maximum time spent in wait mode.
AN3404 low power mode management by the stm8tl5x stmtouch library doc id 018847 rev 3 25/30 code example 1 // configure the zone tsl_acq_zoneconfig(&myzone, 0); // set the al bit to exit from wfi mode only on pxs interrupt cfg->gcr |= (uint8_t)cfg_gcr_al; // start bank acquisition tsl_acq_bankstartacq(); wfi(); // process objects tsl_obj_groupprocess(&myobjgroup); // dxs processing tsl_dxs_firstobj(&myobjgroup); with myzone being declared as followed: tsl_zone_t myzone = {mybanksorting, 0, tslprm_total_banks}; and mybanksorting as followed: tsl_tindex_t mybanksorting[tslprm_total_banks] = {0, 1, 2, 3}; mybanksorting is a simple array of index referring to an acquisition bank number. the second element of myzone is the index to an element in mybanksorting used as the first bank to be acquired. the third element of myzone is the number of banks belonging to this zone. in this simple example, all the banks are defi ned in myzone and sorted from the first to the last. user can imagine to declare many zones from a single bank sorting table: tsl_zone_t myzone = {mybanksorting, 0, tslprm_total_banks}; tsl_zone_t myzone1 = {mybanksorting, 1, 3}; tsl_zone_t myzone2 = {mybanksorting, 3, 2}; and mybanksorting as followed: tsl_tindex_t mybanksorting[tslprm_total_banks] = { 0, 1, 2, 3, 6, 5, 4}; with such declaration, the acqu isition on myzone will acquire all acquisition banks, while myzone1 acquires only bank 1, 2, 3 an d myzone2 acquires only bank 3 and 6. 7.2.2 very low power management with proximity detection this example shows how to manage a proximity detection by scanning the key each 512 ms. this is done by alternating active-halt mode with the awu and active-halt mode with proxsense. once a proximity is detected, a scan of the touch keys is performed. this last
low power mode management by the stm8tl5x stmtouch library AN3404 26/30 doc id 018847 rev 3 step is almost identical to the previous example in section 7.2.1: low power management with all acquisition banks . entry into proximity detection mode is conditioned by the value of the ?proxy_mode? variable which is managed in a user function. this mode is exited by checking the state of the power touchkey. the response time depends on the scanning frequency but, also on the debounce value which is defined by the counterdebprox parameter in the touchkey tsl_touchkeyparam_t structure. if needed, this variable can be modified by the user application when entering proximity detection mode and it can be restored when exiting it (this variable is not modified in the example given below). code example 2 // executive low power loop, runs continually till power key detects a proximity awu_init(awu_timebase_512ms); ecs_last_tick = 40; while (proxy_mode) { tsl_user_action_lowpower(); if (mytkeys[power].p_data->stateid == tsl_stateid_deb_prox) { awu_init(awu_timebase_16ms); //reduce the period between acquisition in order to have a faster response time. } else { if (test_prox(power)) { proxy_mode = false; power_led = 1; led_managelighting(); } else { awu_init(awu_timebase_512ms); } } disablepxs(); // prepare awu
AN3404 low power mode management by the stm8tl5x stmtouch library doc id 018847 rev 3 27/30 awu_cmd(enable); halt(); enablepxs(); awu_cmd(disable); } with : /** * @brief execute stmtouch driver main state machine when in low power mode. * @param none * @retval none */ void tsl_user_action_lowpower(void) { // configure bank 2 which the power touchkey belongs to tsl_acq_bankconfig(2); cfg->gcr |= cfg_gcr_al; // start bank acquisition tsl_acq_bankstartacq(); halt(); // process objects of the low power group tsl_obj_groupprocess(&myobjgrouplowpower); // ecs if (--ecs_last_tick == 0) { tsl_ecs_process(&myobjgrouplowpower); ecs_last_tick = 40; } }
conclusion AN3404 28/30 doc id 018847 rev 3 8 conclusion the stm8tl5xxx devices offer many possi bilities for developing low consumption applications. the user can take advantage of various low power modes like wait, active-halt or halt modes. he can also reduce consumption by switching off peripherals when they are not used. another option for reducing consumption is to optimize the ratio between run and halt modes due to the good performance of the cpu itself. the proxsense can be used in wait or active-halt modes where its consumption depends mainly on the acquisition duration and on the number of enabled receivers. the most important principles of low power mode management are described in this application note, including hints on how and when to use it.
AN3404 revision history doc id 018847 rev 3 29/30 9 revision history table 5. document revision history date revision changes 08-jul-2011 1 initial release. 04-nov-2011 2 stm8tl53xx product name update changed references to associated documents updated figure 1: power supply overview on page 6 10-sep-2012 3 stm8tl5xxx product name update replaced all footnotes under figure 1: power supply overview on page 6 updated section 5.2: gpio initialization on page 16 updated section 7: low power mode management by the stm8tl5x stmtouch library on page 22
AN3404 30/30 doc id 018847 rev 3 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of AN3404

	To Download AN3404 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .