cha2066 rohs compliant ref. : dscha20660069 - 10 mar 10 1/8 specifications subject to change without notice united monolithic semiconductors s.a.s. route dpartementale 128 - b.p.46 - 91401 orsay cede x france tel. : +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 33 03 09 10-16ghz low noise amplifier gaas monolithic microwave ic description the cha2066 is a two-stage wide band monolithic low noise amplifier. the circuit is manufactured with a standard phemt process: 0.25m gate length, via holes through the substrate, air bridges and electron beam gate lithography. it is supplied in chip form. main features broad band performance 10-16ghz 2.0db noise figure, 10-16ghz 16db gain, 0.5db gain flatness low dc power consumption, 50ma 20dbm 3rd order intercept point chip size: 1,52 x 1,08 x 0.1mm g1 nc g2 vd rfin rfout a b c d e nc ums 7272 0 2 4 6 8 10 12 14 16 18 20 7 8 9 10 11 12 13 14 15 16 17 18 19 20 frequency ( ghz ) gain ( db ) 0 1 2 3 4 5 noise figure ( db ) on wafer typical measurements. main characteristics tamb = +25c symbol parameter min typ max unit nf noise figure, 10-16ghz 2.0 2.5 db g gain 14 16 db d g gain flatness 0.5 1.0 db esd protections : electrostatic discharge sensitive device observe handling precautions !
cha2066 10-16ghz low noise amplifier ref. : dscha20660069 - 10 mar 10 2/8 specifications subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 electrical characteristics tamb = +25c, vd = +4v symbol parameter min typ max unit fop operating frequency range 10 16 ghz g gain (1) 14 16 db d g gain flatness (1) 0.5 1.0 db nf noise figure (1) 2.0 2.5 db vswrin input vswr (1) 3.0:1 vswrout ouput vswr (1) 3.0:1 ip3 3rd order intercept point 20 dbm p1db output power at 1db gain compression 10 dbm rth thermal resistance 200 c/w id drain bias current (2) 45 ma (1) these values are representative of on-wafer mea surements that are made without bonding wires at the rf ports. when the chip is attached with typ ical 0.3nh input and output bonding wires, the indicated parameter values should be improved. (2) this current is the typical value from the low noise low consumption biasing (b & d grounded). absolute maximum ratings (1) tamb = +25c symbol parameter (1) values unit vd drain bias voltage (3) 4.5 v pin maximum cw input power -1 dbm pin maximum peak input power overdrive (2) +15 dbm top operating temperature range -40 to +85 c tstg storage temperature range -55 to +125 c (1) operation of this device above anyone of these paramaters may cause permanent damage. (2) duration < 1s. (3) for a typical biasing circuit: b & d grounded . see chip biasing option page 7/8.
10-16ghz low noise amplifier cha2066 ref. : dscha20660069 - 10 mar 10 3/8 specifications subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 typical results chip typical response (on wafer sij) tamb = +25c vd = 4.0v; vg1 = vg2 = +1.4volt ; id = 45ma (a,b,c ,d & e not connected) freq ghz ms11 db ps11 ms12 db ps12 ms21 db ps21 ms22 db ps22 1.00 -0.25 -16.1 -82.22 90.1 -46.86 -148.0 -0.07 -7 .1 2.00 -0.54 -31.8 -83.38 37.9 -46.99 -169.6 -0.15 -1 4.8 3.00 -0.88 -48.8 -84.02 17.8 -30.57 -13.6 -0.67 -24 .3 4.00 -1.38 -68.9 -72.90 21.7 -12.70 -58.0 -1.41 -26 .7 5.00 -2.32 -95.1 -62.06 8.4 -1.44 -96.2 -1.47 -33.3 6.00 -4.51 -131.2 -52.22 -25.9 7.98 -145.4 -2.17 -4 1.3 7.00 -8.90 -177.3 -45.23 -71.4 13.83 154.7 -3.17 -4 6.2 8.00 -12.32 122.2 -41.37 -112.2 16.32 100.4 -4.01 - 50.1 9.00 -10.70 61.8 -39.16 -144.4 17.19 56.4 -4.90 -53 .3 10.00 -8.32 24.9 -37.57 -170.5 17.48 20.2 -5.99 -56 .8 11.00 -7.00 -1.8 -36.41 168.3 17.54 -10.5 -7.27 -59 .4 12.00 -6.48 -23.4 -35.43 149.3 17.55 -38.0 -8.87 -6 0.5 13.00 -6.63 -42.1 -34.71 131.5 17.53 -63.6 -10.85 - 57.5 14.00 -7.33 -58.2 -34.27 114.2 17.44 -88.2 -12.73 - 46.1 15.00 -8.51 -71.5 -34.16 98.4 17.23 -112.3 -13.16 - 27.4 16.00 -9.93 -79.7 -34.42 83.4 16.85 -135.9 -11.71 - 13.0 17.00 -11.00 -82.6 -35.18 70.8 16.29 -158.6 -9.84 - 8.5 18.00 -11.11 -83.8 -36.29 61.5 15.59 179.4 -8.29 -9 .4 19.00 -10.35 -88.5 -37.52 58.2 14.75 158.2 -7.17 -1 3.1 20.00 -9.53 -100.1 -38.26 59.5 13.82 137.2 -6.34 -1 8.1 21.00 -8.97 -117.1 -37.98 64.4 12.71 115.9 -5.86 -2 3.7 22.00 -9.04 -137.0 -36.56 64.7 11.36 95.5 -5.47 -29 .3 23.00 -9.70 -161.0 -35.28 56.8 9.72 75.4 -5.35 -34. 7 24.00 -10.97 174.2 -34.49 47.1 7.77 56.6 -5.37 -39. 3 25.00 -12.61 144.5 -34.15 36.2 5.59 39.2 -5.41 -43. 4 26.00 -14.42 110.6 -34.37 24.8 3.10 23.8 -5.70 -46. 2
cha2066 10-16ghz low noise amplifier ref. : dscha20660069 - 10 mar 10 4/8 specifications subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 typical results chip typical response (on wafer sij) tamb = +25c vd = 4.0v; vg1 = vg2 = +1.4volt; id = 45ma (a,b,c, d & e not connected) -20 -15 -10 -5 0 5 10 15 20 2 4 6 8 10 12 14 16 18 20 22 24 26 frequency ( ghz ) gain, rloss ( db ) gain dbs22 dbs11 typical gain and matching measurements on wafer 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 10 11 12 13 14 15 16 17 18 19 20 frequency ( ghz ) gain, nf ( db ) gain nf spec. typical gain and noise figure measurements on wafer
10-16ghz low noise amplifier cha2066 ref. : dscha20660069 - 10 mar 10 5/8 specifications subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 typical test-jig results circuit typical response (test-jig) tamb = +25c vd = 4.0v ; b & e pads grounded ; id = 65ma ( vg1 & vg2 nc ) -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 frequency ( ghz ) gain & nf & rloss ( db ) dbs11 dbs21 dbs22 spec. nf_c typical linear measurements in test-jig -2 0 2 4 6 8 10 12 14 16 18 20 -16 -14 -12 -10 -8 -6 -4 -2 0 pin ( dbm ) at 12ghz pout gain -2 0 2 4 6 8 10 12 14 16 18 20 -16 -14 -12 -10 -8 -6 -4 -2 0 pin ( dbm ) at 16ghz pout gain typical output power measurements in test-jig
cha2066 10-16ghz low noise amplifier ref. : dscha20660069 - 10 mar 10 6/8 specifications subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 chip schematic and pad identification g1 nc g2 vd rfin rfout a b c d e nc 1520m 1080m pad size 100x100m, chip thickness 100m ums 11 23 8 10 15 6 15 2k 1k 20 2k 1k 35 7272 dimensions : 1520 x 1080m 35m 875 1025 115 225 455 605 755 905 1450 35 1010 410 410
10-16ghz low noise amplifier cha2066 ref. : dscha20660069 - 10 mar 10 7/8 specifications subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 typical chip assembly b e vd in c = 100pf out chip biasing options this chip is self-biased, and flexibility is provid ed by the access to number of pads. the internal dc electrical schematic is given in order to use these pads in a safe way. g2 d e 15 15 2k 1k g1 vd a b c 23 8 10 2k 1k 35 20 11 6 the two requirements are: n1 : not exceed vds = 3.5volt ( internal drain to source voltage ). n2 : not biased in such a way that vgs becomes pos itive. ( internal gate to source voltage ) we propose two standard biasing: low noise and low consumption: vd = 4v and b & d grounded. all the other pads non connected (nc). idd = 45ma & pout-1db = +10dbm typical. (equivalent to a,b,c,d,e : nc and vd=4v ; g1=+1.4v ; g2=+1.4v). low noise and high output power: vd = 4v and b & e grounded. all the other pads non connected (nc). idd = 65ma & pout-1db = +13dbm typical. (equivalent to a,b,c,d,e : nc and vd=5v ; g1=+1.4v ; g2=+4.0v). a file is available on request to help the biasing option tuning.
cha2066 10-16ghz low noise amplifier ref. : dscha20660069 - 10 mar 10 8/8 specifications subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 ordering information chip form : cha2066-99f/00 information furnished is believed to be accurate an d reliable. however united monolithic semiconductors s.a.s. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by impli cation or otherwise under any patent or patent rights of united monolithic semiconductors s.a.s. . specifications mentioned in this publication are subject to change without notice. this publication supersedes and re places all information previously supplied. united monolithic semiconductors s.a.s. products are not authorised for use as critical components in life support devices or s ystems without express written approval from united monolithic semiconductors s.a.s.
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