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www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 1 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 key features ? modulation: fsk or ook with frequency ho p- ping spread spectrum capability ? frequency range: 300 to 510 mhz ? high sensitivity: - 112 dbm in circuit ? high data rate: up to 200 kb/s ? low receiver current: 2.7 ma typical ? low s leep current: 0.1 a typical ? up to +13 dbm in - circuit transmit power ? operating supply voltage: 2.1 to 3.6 v ? programmable preamble ? programmable packet start pattern ? integrated rf, pll, if and base - band circuitry ? integrated data & clock recovery ? programmab le rf output power ? pll lock output ? transmit/receive fifo size programmable up to 64 bytes ? continuous, buffered and packet data modes ? packet address recognition ? packet handling features: ? fixed or variable packet length ? packet filtering ? packet formatting ? st andard spi interface ? ttl/cmos compatible i/o pins ? programmable clock output frequency ? low battery detection ? low cost 12.8 mhz crystal reference ? integrated rssi ? integrated crystal oscillator ? host processor interrupt pins ? programmable data rate ? external w ake - up event inputs ? integrated packet crc error detection ? integrated dc - balanced data scrambling ? integrated manchester encoding/decoding ? interrupt signal mapping function ? support for multiple channels ? four power - saving modes ? low external component count ? tq fn - 32 smt package ? standard 13 inch reel, 3k pieces applications ? active rfid tags ? automated meter reading ? home & industrial automation ? security systems ? two - way remote keyless entry ? automobile immobilizers ? sports performance monitoring ? wireless toys ? medic al equipment ? low power two - way telemetry systems ? wireless mesh sensor networks ? wireless modules TRC105 300 - 510 mhz rf transceiver product overview TRC105 is a single c hip, multi - channel, low power uhf transceiver. it is designed for low cost, high volume, two - way short range wireless applic a- tions in the 300 to 510 mhz fre quency range . the TRC105 is fcc & etsi certifiable. all critical rf and base - band functions are int egrated in the TRC105 , min i mizing external component count and simplifying and speeding des ign - ins. a microcontroller, rf saw filter, 12.8 mhz crystal and a few pa s- sive comp o nents are all that is needed to create a complete , robust radio function. the trc1 05 incorporates a set of low - power states to redu ce cu r- rent consumption and extend b attery life. the small size and low power co n- sumption of the TRC105 make it ideal for a wide variety of short range radio applications. the TRC105 c o m plies with directive 2 002/95/ec (rohs) . pb
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 2 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 table of contents 1 .0 pin configuration ................................ ................................ ................................ ................................ ..... 4 1.1 pin description ................................ ................................ ................................ ................................ .. 4 2 .0 functional description ................................ ................................ ................................ ............................. 5 2.1 rf port ................................ ................................ ................................ ................................ .............. 7 2.2 transmitter ................................ ................................ ................................ ................................ ........ 7 2.3 receiver ................................ ................................ ................................ ................................ ............ 8 2.4 crystal oscillator ................................ ................................ ................................ ............................... 9 2.5 frequency synthesizer ................................ ................................ ................................ ................... 10 2.6 pll loop filter ................................ ................................ ................................ ................................ 11 3 .0 operating modes ................................ ................................ ................................ ................................ ... 1 1 3.1 receiving in continuous data mode ................................ ................................ ............................... 12 3.2 continuous mode data and clock recovery ................................ ................................ .................. 14 3.3 continuou s mode start pattern detect ................................ ................................ ........................... 14 3.4 rssi ................................ ................................ ................................ ................................ ................ 15 3.5 receiving in buffered data mode ................................ ................................ ................................ ... 15 3.6 transmitting in continuous or buffered data modes ................................ ................................ ...... 17 3.7 irq 0 and irq1 mapping ................................ ................................ ................................ ................. 18 3.8 buffered clock output ................................ ................................ ................................ ..................... 19 3.9 packet data mode ................................ ................................ ................................ ........................... 1 9 3.9.1 fixed length packet mode ................................ ................................ ................................ .... 19 3.9.2 variable length packet mode ................................ ................................ ............................... 20 3.9.3 extended variable length packet mode ................................ ................................ ............... 20 3.9.4 packet payload processing in transmit and receiv e ................................ ........................... 22 3.9.5 packet filtering ................................ ................................ ................................ ...................... 23 3.9.6 cyclic redundancy check ................................ ................................ ................................ ..... 23 3.9.7 manchester encoding ................................ ................................ ................................ ............ 24 3.9.8 dc - balanced scrambling ................................ ................................ ................................ ...... 25 3.10 spi configuration interface ................................ ................................ ................................ ........... 2 5 3.11 spi data fifo interface ................................ ................................ ................................ ................ 27 4 .0 configuration register memory map ................................ ................................ ................................ ..... 29 4.1 main co nfiguration registers (mcfg) ................................ ................................ ............................ 30 4.2 interrupt configuration registers (irqcfg) ................................ ................................ ................... 33 4.3 receiver configuration registers (rxcfg) ................................ ................................ ................... 35 4.4 start pattern configuration registers (syncfg) ................................ ................................ ........... 38 4.5 transmitter configuration registers (txcfg) ................................ ................................ ............... 3 8 4.6 oscillator c onfiguration register (oscfg) ................................ ................................ .................... 39 4.7 packet handler configuration registers (pktcfg) ................................ ................................ ....... 39 4.8 page configuration register (pgcfg) ................................ ................................ ........................... 40 4.9 low battery configuration registers (lbcfg) ................................ ................................ ............... 41 5 .0 electrical characteristics ................................ ................................ ................................ ....................... 42 5.1 dc electrical characteristics ................................ ................................ ................................ .......... 42 5.2 ac electrical characteristics ................................ ................................ ................................ ........... 43 6 .0 TRC105 design - in steps ................................ ................................ ................................ ....................... 45 6.1 determining frequency specific hardware component values ................................ ..................... 4 5 6.1.1 saw filters and related component values ................................ ................................ ....... 45 6.1.2 voltage controlled oscillator component values ................................ ................................ . 46
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 3 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 6.2 determ ining configuration values for fsk modulation ................................ ................................ .. 46 6.2.1 bit rate related fsk configuration values ................................ ................................ .......... 4 6 6.2.2 determining transmitter power configuration values ................................ .......................... 48 6.3 determining configuration values for ook modulation ................................ ................................ . 49 6.3.1 bit rate related ook con figuration values ................................ ................................ ........ 49 6.3.2 ook demodulator related configuration values ................................ ................................ . 51 6.3.3 ook transmitter related configuration values ................................ ................................ ... 52 6.4 frequency synthesizer channel programming for fsk modulation ................................ .............. 53 6.5 frequency synthesizer channel programming for oo k modulation ................................ ............. 54 6.6 TRC105 data mode selection and configuration ................................ ................................ ........... 55 6.6.1 continuous data mode ................................ ................................ ................................ .......... 55 6.6.2 buffered data mode ................................ ................................ ................................ .............. 5 7 6.6.3 packet data mode ................................ ................................ ................................ ................. 59 6.7 battery power ma nagement configuration values ................................ ................................ ......... 63 7.0 package dimensions and typical pcb foot print - qfn - 32 ................................ ................................ .. 65 8.0 tape and reel dimensions ................................ ................................ ................................ ................... 66 9.0 solder reflow profile ................................ ................................ ................................ ............................. 67
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 4 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 1 .0 pin configuration 1 .1 pin description pin type name description 1 - gnd connect to gnd 2 - gnd connect to gnd 3 o vdd_vco regulated supply for vco 4 i/o tank - vco tank 5 i/o tank+ vco tank 6 i/o pll - pll loop filter output 7 i/o pll+ pll loop filter input 8 - gnd connect to gnd 9 - gnd connect to gnd 10 i /o xtal - crystal connection (oscillator output) 11 i /o xtal + crystal connection (oscillator input) 12 - gnd connect to gnd 13 - nc no connect ion - float pin 14 i nss_config slave select for spi configuration data 15 i nss_data slave select for spi tx/rx data 16 o sdo serial data out 17 i sdi serial data in 18 i sck serial spi clock in 19 o clkout buf fered clock output 20 i/o data transmit/receive data 21 o irq0 interrupt output 22 o irq1/dclk interrupt output/recovered data clock (cont mode) 23 o pll_lock pll locked indicator 24 o nlow_batt low battery detect (leave unconnected if not used) 25 - gnd connect to gnd 26 i vdd main 3.3 v supply voltage 27 o vdd_ana regulated supply for analog circuitry 28 o vdd_dig regulated supply for digital circuitry 29 o vdd_pa regulated supply for rf power amp 30 - gnd connect to gnd 31 i/o rf - rf i/o 3 2 i/o rf+ rf i/o pad - ground ground pad on pkg bottom table 1
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 5 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 2 .0 functional description the TRC105 is a single - chip transceiver that can operate in the 300 - 510 mhz frequency range . the TRC105 supports two modulation schemes - fsk and ook. the TRC105 s highly integrated architecture requires a min i- mum of external components, while maintaining design flexibility. all major rf communication parameters are pr o grammable and most can be dynamically set. the TRC105 is optimized for very l ow p ower consumption (2.7 ma typical in receiver mode). it complies with european etsi , fcc part 15 and canadian rss - 210 regulatory standards. advanced digital features including the tx/rx fifo and the packet handling data mode significantly r e duce the load on the host microc ontroller . figure 1 the receiver is base d on a superheterodyne architecture . it is composed of the following major blocks: ? an lna that pr ovides low noise rf gain followed by an rf band - pass filter . ? a first mixer which down - converts the rf signal to an intermediate frequency equal to 1/9 th of the carrier frequency . ? a variable gain first if pre amplifier followed by two second mixers which down convert the first if signal to i and q signals at a low frequency (zero - if for fsk, low - if for ook).
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 6 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 ? a two - sta ge if filter followed by an amplifier chain for both the i and q channels. limiters at the end of each chain drive the i and q input s to the fsk demodulator function. an rssi signal is also derived from the i and q if amplifiers to drive the ook detector. the second filter stage in each channel can be co n- figured as either a third - order butterworth low - pass filter for fsk operation or an image reject polyphase band - pass filter for ook operation. ? an fsk arctangent type demodulator driven from the i and q lim iter outputs, and an ook demodulator driven by the rssi signal. either detector can drive a data and clock recovery function that provides matched filter enhancement of the demodulated data. the transmitter chain is based on the same doubl e - conversion arc hitecture and uses the same intermediate fr e- quencies as the receiver chain. the main blocks include : ? a digital waveform generator that provides the i and q base - band signals. this block includes digital - to - analog converters and anti - aliasing low - pass filt ers . ? a compound image - rejection mixer to up convert the base - band signal to the first if at 1/9th of the carrier frequency , and a second image - rejection mixer to up - convert the if signal to the rf frequency ? transmitter driver and power amplifier stages t o drive the antenna port the frequency synthesizer is based on an integer - n pll h aving a typical frequency step size of 12.5 khz. two programmable frequency dividers in the feedback loop of the pll and one programmable divider on the reference oscillator allow the lo frequency to be adjusted. the reference frequency is generated by a crystal oscillator ru n- ning at 12.8 mhz. the TRC105 is controlled by a digital block that includes registers to store the configuration settings of the r a dio. these registers are accessed by a host microcontroller through an spi style serial interface. the microco n trollers serial connections to the TRC105s sdi, sdo and sck pins are shown in figure 2 (component values shown are for 418.00 - 434.79 mhz operation; see tables 57 an d 58 for other frequency bands). on - chip regulators provide stable supply voltages to sensi tive blocks and allow the TRC105 to be used with supply voltages from 2.1 to 3.6 v. most blocks are supplied with a vol t age below 1.6 v. figure 2 c17 1.2 pf c16 dnp
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 7 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 2.1 rf port the receiver and the transmitter share t he same rf pins. figure 3 show s the implementation of the common front - end. in transmit mode, the pa and the pa regulator are on; the voltage on vdd_pa pin is the nominal vol t- age of the regulator, about 1.8 v. th e e xternal inductances l1 and l4 are used for the pa. in receive mode, both pa and pa regulator are off, and vdd_pa is tied to ground. the external inductances l1 and l4 are used for b i- asing and matching the lna, which is implemented as a common gate amplifie r. figure 3 2.2 transmitter the TRC105 is set to transmit mode when mcfg00_chip_m ode[7..5] bits are set to 100 . in c ont inuous data mode the transmitted data is sent directly to the modulator. the host microcontroller is provided with a bit rate clock by the TRC105 to clock the data ; using this clock to send the data synchronously is mandatory in fsk co n- figuration and opt ional in ook configuration. in b uffered and packet data mode s the data is first written into the 64 - byte fifo via the spi i n terface; d ata from the fifo is then used by the modulator. at the front end of the transmitter, i and q signals are generated by the base - band circuit which contains a digital waveform generator, two d/a converters and two anti - aliasing low - pass filters. the i and q signals are two qua d- rature sinusoids whose frequency is the selected frequency deviation. in fsk mode, the phase shift between i and q is switched between + 90 and - 90 according to the input data. the modulation is then performed at this stage, since th e information contained in the phase shift will be converted into a frequency shift when the i and q signals are combined in the first mixers. in ook mode, the phase shift is kept constant whatever the data. the combination of the i and q signal s in the fi rst mixers create s a fixed frequency signal at a low intermediate fr e- quency which is equal to the selected frequency deviation. after d/a conversion, both i an d q signals are filtered by anti - aliasing filter s whose bandwidth is programmed with the register txcfg1a_txinterpfilt[7..4] . behind the filters, a set of four mixers combines the i and q signals and converts them into two i and q signals at the second intermediate frequency which is equal to 1/8 of the lo frequency, which in turn is equal to 8/9 of t he rf freque n- cy. these two new i and q signals are then combined and up - converted to the desired rf frequency by two quadrature mixers fed by the lo signals. the signal is then amplified by a driver and power a mplifier stage. mcfg05_pa_r amp[7..6 ] t pa (s) rise/fall (s) 00 3 2.5/2 01 8.5 5/3 10 15 10/6 11 23 20/10 table 2
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 8 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 ook modulation is performed by switching on and off the power amplifier and its regulator. the rise and fall times of the ook signal can be configured in register mcfg05 _ pa_ramp[7. .6 ] , which controls the charge and di s- charge time of the regulator. figure 4 shows the time constants set by mcfg05_pa_r amp[ 7..6 ]. table 2 gives typical values of the rise and fall times as defined in figure 4 when the capacitance connected to the output o f the reg u lator is 0.047 f. figure 4 2.3 receiver the TRC105 is set to receive mode when mcfg00_chip_m ode[7..5] is set to 011. the receiver is based on a double - conversion architecture. the front - end is composed of an lna and a mixer whose gains are c onstant. the mixer down - converts the rf signal to an intermediate frequency which is equal to 1/8 of the lo frequency, which in turn is equal to 8/9 of the rf frequency. behind this first mixer there is a variable gain if amplifier that can be programmed f rom maximum gain to 13.5 db less in 4.5 db steps with the mcfg01_if_gain[1..0] register . after the variable gain if amplifier, the signal is down - converted into two i and q base - band signals by two qua d- rature mixers which are fed by reference signals at 1 /8 the lo frequency. these i and q signals are then filtered and amplified before demodulation. the first filter is a second - order passive r - c filter whose bandwidth can be programmed to 16 values with the register rxcfg10_lp_filt[7..4] . the second filter can be configured as either a third - order butterworth active filter which acts as a low - pass filter for the zero - if fsk configuration , or as a po l- yphase band - pass filter for the low - if ook configura tion. to select butterworth low - pass filter operation , bit rxcfg12_polyfilt_en [ 7 ] is set to 0 . the bandwidth of the butterworth filter can be programmed to 16 values with the register rxcfg10_bw_filt[3..0] . the low - if configuration must be used for ook modulation. this co n- figuration is enabled when the bit rxcfg1 2_polyfilt_en [7 ] is set to 1 . the center frequency of the polyphase fi l ter can be programmed to 16 values with the register rxcfg11_polyfilt[7..4] . the bandwidth of the filter can be programmed with the register rxcfg10_bw_filt[3..0] . in ook mode, the valu e of the low - if is equal to the deviation frequency defined in register mcfg02_freq_dev . in addition to channel filtering, the function of the polyphase filter is to reject the image. figure 5 below shows the t wo configurations of the second if filter. in the butterworth configuration, f cbw is the 3 db cutoff frequency. in the polyphase band - pass configuration f o pp is the center frequency given by rxcfg11_polyfilt[7..4] , and f cpp is the upper 3 db bandw idth of the filter whose of f- set, referenced to f opp , is given by rxcfg10_bw_filt[3..0].
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 9 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 figure 5 after filtering, the i and q signals are each amplified by a chain of 11 amplifiers having 6 db of gain each. the outputs of these amplifiers and their intermediate 3 db nodes are used to evaluate the received signal strength (rssi). limiter s are located behind the 11 amplifiers of the i and q chains and the signals at the output of these limiters are used by the fsk demodulator . t he rssi output is used by the ook demodulator. the global ban d- width of the whole b ase - band chain is given by the bandwidths of the passive filter, the butterworth filter, the a m- plifier chain and the limiter. the maximum achievable global bandwidth when the bandwidths of the first three blocks are programmed at their upper limit is about 350 khz. 2.4 crystal oscillator crystal specifications for the TRC105 reference oscil lator are given in table 3 . rfm recommends the xtl1020 p crystal which is specifically designed for use with the TRC105 . note that crystal frequency error will directly tran s- late to carrier frequency, bit rate and frequency d e viation error. specification min typical max units nominal frequency - 12.8 0000 (fundamental) - mhz load capacitance for fs 13.5 15 16.5 pf motional resistance - - 5 0 motional capacitance 5 - 20 ff shunt capacitance 1 - 7 pf calibration tolerance at 25 c - 10 ppm (1) stability over temperature range ( - 40 c to 85 c) 1 - 15 ppm aging in first 5 years - - 2 ppm/yr table 3
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 10 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 2.5 frequency synthesizer the TRC105 vco operatin g frequency range is covered in six bands. operation in each band requires a sp e cific vco inductor value and configuration paramet er setting, as shown in table 4 below: mcfg00_band[4..2] frequency band mhz 000 300 - 330 001 330 - 365 010 365 - 400 011 400 - 440 100 440 - 470 101 470 - 510 110 to 111 not used table 4 e ach of these band s is divided i nto four subbands to provide a low phase noise vco frequency trimming mech a- nism. subbands are selected as shown in table 5 b e low: mcfg00_subband[1..0] subband 400 - 440 mhz ex a m ple 00 1 st quarter 400 - 410 01 2 nd quarter 410 - 420 10 3 rd quarter 420 - 430 11 4 th quarter 430 - 440 table 5 using the vco as discussed above, t he frequency s ynthesizer generates the local oscillator (lo) si g nal for the receiver and transmitter section s. the core of the synthesizer is implemented with an integer - n pll arch i tecture. the frequency is set by three divider parameters r, p and s. r is the frequency divider ratio in the reference fr e- quency path. p and s set the frequency divider ratio in the feedback loop of the pll. the frequency sy n thesizer includes a crystal oscillator which provides the fr equency reference for the pll. the equations giving the relatio n- ships between the reference crystal frequency, the local oscillator frequency and rf carr ier frequency are given below: f lo = f xtal *(75*(p + 1) + s)/(r + 1), with p and s in the range 0 to 255 , s less than (p + 1) , r in the range 64 to 169 , and f lo and f xtal in mhz. f rf = 1.125*f lo , where f rf and f lo are in mhz f lo is the first local oscil lator (vco) frequency, f xtal is the reference crystal frequency and f rf is the rf channel frequency. f lo is the frequency used for the first down - conversion of the receiver and the second up - conversion of the transmitter. the intermediate frequency used fo r the second down - conversion of the receiver and the first up - conversion of the transmitter is equal to 1/8 of f lo . as an example, with a crystal frequency of 12. 8 mhz and an rf frequency of 434 mhz, f lo is 385.8 mhz and the first if o f the receiver is 48. 2 mhz. there are two sets of divider ratio registers: synthr1[7..0] , synthp1[7..0] , synths1[7..0] , and synthr2[7..0] , synthp2[7..0] , synths2[7..0] . the mcfg05_rf_freq [ 0 ] bit is used to select which set of registers to use as the current frequency setting . for frequency hopping applications, this reduces the programming and synthesizer se t- tling time when changing frequencies. while the data is being transmitted, the next frequency is pr o grammed and ready. when the current transaction is complete, the mcfg0 5_rf_freq [ 0 ] bit is complemented and the freque n- cy shifts to the next freq according to the contents of the divider ratio registers. this process is r e peated for each frequency hop.
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 11 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 2.6 pll loop filter the loop filter for the frequency synthe sizer is sho wn in figure 6 . pll loop filter figure 6 r ecommended component values for the frequency synthesizer loo p filter are provided in table 6 . the loop filter settings are not dependent on the frequency b and, so they can be used on all designs. pll lock status can be provided on pin 23 by setting the irqcfg0e_ pll_lock_en [ 0 ] bit to a 1 . pin 23 goes high w hen the pll is locked . the lock status of the pll can also be checked by reading the irqcfg0e_pll_ lock _st [1 ] bit. t his bit latches high each time the pll locks and must be reset by writing a 1 to it. 3 .0 operating modes the TRC105 has 5 possible chip - level modes. the chip - level mode is set by mcfg00_chip_m ode[7..5] , which is a 3 - bit pattern in the configuration register. tabl e 7 summarizes the chip - level modes: mcfg00_chip_m ode[7..5] chip - level mode enabled functions 0 0 0 sleep none 0 0 1 standby crystal oscill ator 0 1 0 synthesizer crystal and frequency synthesizer 0 1 1 receive crystal, frequency synthesizer and receiver 1 0 0 transmit crystal, frequency synthesizer and transmitter table 7 table 8 giv es the state of the digital pins for the differen t chi p - level modes and settings: pin function sleep mode standby mode synthesizer mode receive mode transmit mode nss_config* i i i i i nss_data * i i i i i irq0 tri o o o o irq1 tri o o o o data tri tri tri o i clk out tri o o o o sdo ** tr i/ o tr i/ o tr i/ o tr i/ o tr i/ o sdi i i i i i sck i i i i i table 8 name value tolerance c8 1000 pf 10% c9 6800 p f 10% r1 6.8 k 5% pll loop filter components table 6 i = input, o = output, tri = high impedance *nss_config has p riority over nss_data **sdo is an output if nss_config = 0 and/or nss_data = 0
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 1 2 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 the TRC105 transmitter and receiver sections support three data handling modes of operatio n : ? continuous mode: each bit transmitted or received is accessed directly at the data input/output pin. ? b uffered mode: a 64 - byte fifo is used to store each data byte transmitted or received. this data is wri t- ten to and read from the fifo through the spi bus. ? packet h a ndling mode: in addition to using the fifo, this data mode builds the complete packet in t ransmit mode and extracts the useful data from the pa cket in receive mode. the p acket includes a pr e- amble, a start pattern (network address) , an optional node address and length byte and the data. packet data mode can also be configured to perform addition al operations like crc error detection and dc - balanced manche s ter encoding or data scrambling. the buffered and packet handling modes allow the host microcontroller overhead to be significantly reduced. the data pin is bidirectional and is used in both tr ansmit and receive modes. in receive mode, data represents the demodulated received data. in transmit mode , input data is applied to this pin. the working length of the fifo can set to 16, 32, 48 or 64 bytes through the mcfg0c_fifo _depth[7..6] regi s- ter . i n the discussions below describing the fifo behavior , the explanations are given with an assumption of 64 bytes, but th e principle is the same for the four possible fifo sizes. the status of the fifo can be monitored via int errupts which are described in s ection 3.7 . in addition to the straightforward nfifoempy and fifofull interrupts, additional configurable interrupts fifo_int_tx and fifo_int_rx are also available. a low - to - high transition occurs on fifo_int_rx when th e number of bytes in the fifo is gr eater than or equal to the threshold set by mcfg0c _fifo_thresh[5..0] (number of byte s fifo_thresh). a low - to - high transition occurs on fifo_int_tx when th e number of bytes in the fifo is less than or equal to the threshold set by mcfg0c _fifo_thresh[5..0 ] (number of byte s fifo_thresh). 3.1 receiving in co ntinuous data mode the receiver operates in c ontinuous data mode when the mcfg01_mode [7..6 ] bit s are set to 00 . in this mode, the receiver has two output signals indicating recovered clock, dclk and r ecovered nrz bit data. dclk is co n- nected to output pin irq1 and data is connected to pin data configured in outpu t mode. the data and clock recovery controls the recovered clock signal, dclk. d ata and clock recovery is enabled by rxcfg12_dclk_ dis [ 6 ] to 0 (default value). t he clock recovered from the incomin g data stream appears at dclk. when data and clock r e covery is disabled, the dclk output is held low and the raw demodulator output appears at data. the fun ction of data and clock recovery is to remove g litches from the data stream and to provide a sy n chronous clock at dclk. the output data is valid at the rising e dge of dclk as shown in figure 8 .
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 13 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 figure 7 as shown in figure 7, t he demodulator section includes the fsk demodulator, the ook demodulator, data and clock recovery and the start p attern detection blocks. if fsk is selected, the demodulation is performed by analyzing the phase between the i and q limited signals at the output of the base - band channels. if ook is selected, the demodulation is performed by c omparing the rssi output value stored in rxcfg14_ rssi[7..0] register to the threshold which can be either a fixed value or a time - variant value depen d ing on the past his tory of the rssi output. table 9 gives the three main possible procedur es, which can be s e lected via the register mcfg01_rx_ook[3..2 ] : mode mcfg01_rx_ook[3..2 ] description fixed thres h old 00 rssi output is compared with a fixed threshold stored in rxcfg13_ook_thresh peak 01 rssi output is compared with a threshold which is at a fixed offset below the maximum rssi. average 10 rssi output is compared with the average of the last rssi va l ues. table 9 if the end - user application requires direct access to the output of the demodulator, then the rxcfg12_dclk_ dis [6 ] bit is se t to 1 disabling the clock recovery. in this case the demodulator output is directly connected to the data pin and the irq1 pin (dclk) is set to low. f or proper operation of the TRC105 demodulator in fsk mode, the modulation index of the input si g nal should meet the following condition: 2*f dev = 2 br where f dev is the frequency deviation in hertz (hz) and br is the data rate in bits per se cond (b/s).
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 14 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 3.2 continuous mode data and clock recovery the raw output signal from the demodulator may contain ji tter and glitches. data and clock recovery converts the data output of the demodulator into a glitch - free bit - stream data and generates a syn chronized clock dclk to be used for samp ling the data output as shown in figure 8 . dclk is available on pin irq1 when the TRC105 ope r- ates in continuous mode. figure 8 to ensure correct operation of the data and clock recovery circuit , the following con ditions have to be satisfied: ? a 1 - 0 - 1 - 0 preamble of at least 24 bits is required for synchronization ? the transmitted bit stream must have at least one transition from 0 to 1 or from 1 to 0 every 8 bits during transmission ? the bit rate accuracy must be better than 2 %. data and clock recovery is enabled by default. it is controlled by rxcfg12_dclk_dis [6 ] . if data and clock r e- covery is disabled , the output of the demodulator is directed to data and the dclk output (irq1 pin in contin u- ous mode) is set to 0. the received bit rate is defined by the value s of the mcfg03 and mcfg04 configuration register s , and is calc u- lated as fo l lows: br = f xtal /(2*(c + 1) *(d + 1) ), with c in the range of 0 to 255, and d = 31 (suitable for most applications) with br the bi t rate in kb/s, f xtal the crystal frequency in khz , c the value in mcfg03 , and d the value in mcfg04 . for e x ample, using a 12.8 mhz crystal (12,800 khz ), the bit rate is 25 kb/s when c = 7 and d = 31 . 3.3 continuous mode start pattern detection start pat tern detection is activated by setting the rxcfg12_recog [5 ] bit to 1. the demodulated signal is co m- pared with a pattern stored in the syncfg registers. the s tart pattern d etect signal (pattern) is driven by the output of this comparator and is synchronized by dclk. it is se t to 1 when a pattern match is detected, othe r w ise set to 0. the pattern detect output is updated at the rising edge of dclk. the number of bytes used for compar i- son is defined in the rxcfg12_pat_sz[4..3] register and the num ber of tolera ted bit errors for pat tern detect ion is defined in the rxcfg12_ptol[2..1] register. figure 9 illustrates the pattern detection pro c ess.
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 15 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 figure 9 note that start pattern detection is enabled only if data and clock recovery is enabled. 3.4 rssi the rec eived signal strength is measured in the amplifier chains behind the second mixers. each amplifier chain is composed of 11 amplifiers each having a gain of 6 db and an intermediate output at 3 db. by monitoring the two outputs of each stage, an estimation of the signal strength with a resolution of 3 db and a dynamic range of 63 db is obtained. this estimation is performed 16 times over a period of the i and q signals and the 16 samples are averaged to obtain a final rssi value with a 0.5 db step. the perio d of the i and q signal is the inverse of the deviation frequency, which is the low - if frequency in ook mode. the rssi effective dynamic range can be i n- creased to 70 db by adjusting mcfg01_if_gain[1..0] for less gain on high si g nal levels . the rssi block can also be used in interrupt mode by setting the bit irqcfg0e_rssi_int [3 ] to 1. when rxcfg14_rssi is equal or greater than a predefined value stored in irqcfg0f_rssi_thld , bit irqcfg0e_ sig_detect [2 ] goes high and an interrupt signal rssi_irq is generated on pin irq0 if irqcfg0d_rx_ irq0[7..6] is set to 01 (see table 10 ). the interrupt is cleared by writing a 1 to bit irqcfg0e_ sig_detect [2 ] . if the bit rssi_irq remains high, the process starts again. figure 10 shows the timing diagram of rssi in inte r- rupt mode. figure 10 3.5 receiving in buffered data mode the receiver works in b uffered data mode when the mcfg01_mode[7..6 ] bit s are set to 01 . in this mode, the ou t put of the data and clock recovery, i.e., the demodulated and resynchronized signal and th e clock signal dclk are not sent directly to the output pins data and irq1 (dclk). these signals are used to store the demodulated data in blocks of 8 bits in a 64 - byte fifo. figure 11 shows the receiver chain in this mode. the fsk and ook demodul a tors, da ta and clock recove ry circuit and start pattern detect block work as described for c ontinuous data mode, but they are used with two additional blocks, the fifo and spi.
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 16 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 figure 11 when the TRC105 is in receive mode and mcfg01_mode [7..6 ] bit s are set t o 0 1, all of the blocks d e scribed above are enabled. in a normal communication frame the data stream is comprised of a 24 - bit pr eamble, a start pattern and data. upon receipt of a matching start pattern the receiver recognizes the start of data, strips off the preamble and start pattern, and stores the data in the fifo for retrieval by the host microcontroller. this automa t- ed data e x traction reduces the loading on the host microcontroller. the irqcfg0e_start_fill [7 ] bit determines how the fifo is filled. i f irqcfg0e_start_fill [7 ] is set to 0 , data onl y fills the fifo when a start pattern is detected. received data bits are shifted into the pattern recognition block which continuously compares the received data with the contents of the syncfg registers. if a match o c- curs, the start pattern detect block output is set for one bit period and the irqcfg0e_start_det [6 ] bit is also set. this i n ternal signal can be mapped to the irq0 output using interrupt signal mapping. once a pattern match has o c curred, the start pattern detect block will remain inactive until the irqcfg0e_start_det [6 ] bit is reset. if irqcfg0e_start_fill [7 ] is set to 1, fifo filling is initiated by asserting irqcfg0e_start_det [6 ] . once 64 bytes have been written to the fifo the irqcfg0d_fifofull [1 ] signal is set. data should then be read out. if no a c tion is taken , the fifo will overflow and subsequent data will be lost. if this occurs the irqcfg0 e _fifo_ ovr [ 4 ] bit is set to 1. the irqcfg0d_fifofull [1 ] signal can be mapped to pin irq1 as an inter rupt for a m i- crocontroller if irqcfg0d_rx_irq1[5..4] is set to 01. to recover from an overflow , a 1 must be written to irqcfg0d_ fifo_ovr [4 ] . this clears the contents of the fifo, resets all fifo status flags a nd re - initiates pa t- tern detection . pat tern det ection can also be re - initiated during a fifo filling sequence by writing a 1 to irqcfg0e_start_det [6 ] . the details of the fifo filling process are shown in figure 12. as the first byte is written into the fifo, signal irqcfg0d_nfifoempy [0 ] is set indicat ing at least one byte is present. the host microcontroller can then read the contents of the fifo through the spi interface. when all data is read from the fifo, irqcfg0d_
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 17 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 nfifoempy [0 ] is reset. when the last bit of the 64 th byte has been written into the fifo, signal irqcfg0d_ fifofull [1 ] is set. data must be read before the next byte is received or it will be overwritten. the irqcfg0d_nfifoempy [0] signal can be used as an interrupt signal for the host microcontroller by ma p- ping to pin irq0 if irqcfg0d_r x_irq0[7..6] is set to 10. alternatively, the write_byte signal may also be used as an interrupt if irqcfg0d_rx_irq0[7..6] is set to 01. demodulation in buffered mode occurs in the sa me way as in continuous mode. received data is directly read from the fi fo and the data and dclk pins are not used. data and clock recovery in buffered mode is automat i- cally enabled. dclk is not externally available. the pattern recognition blo ck is automatically enabled in b uffered data mode. the start pattern d etect (patter n) signal can be mapped to pin irq0 . in b uffered data mode rs si operates the same way as in c o n- tinuous data mode. ho w ever, rssi_irq may be mapped to irq1 instead of to irq0 in c ontinuous data mode. figure 12 3.6 transmitting in continuous or buffered da ta modes the transmitter operates in c ontinuous data mode when the mcfg01_mode [7..6 ] bit s are set to 0 0 . b it clock dclk is available on pin irq1 . bits are clocked into the transmitter on the rising edge of this clock . data must be stable 2 s before the rising edge of dclk and must be held for 2 s following the rising edge of this clock (t sudata ). to meet this requirement, data can be changed on the falling edge of dclk. in fsk mode dclk must be used but is optional in ook mode. the transmitter operates in buffered data mode when the mcfg01_mode [5] bit is set to 1. data to be transmi t- ted is written to the 64 - byte fifo through the spi interface. fifo data is loaded byte - by - byte into a shift register which then transfers the data bit - by - bit to the modulat or. fifo operation in transmit mode is similar to receive mode. transmi s sion can start immediately after the first byte of data is written into the fifo or when the fifo is full, as determined by the irqcfg0e_start_full[4] bit setting. if the transmit fifo is full, the interrupt signal irqcfg0d_ fifofull[2] is asserted on pin irq1. if data is written into the fifo while it is full, the flag irqcfg0d_fifo_ovr[0] will be set to 1 and the previous fifo contents will be overwritten. the irqcfg0d_ fifo_ovr[0] fl ag is cleared by writing a 1 to it. at the same time the contents of the fifo are cleared. once the last data byte in the fifo is loaded into the shift register driving the transmitter modulator, the flag irqcfg0d_ nfifoempy[1] is set to 0 on pin irq0. if new data is not wri t ten to the fifo and the last bit has been transferred to the modulator, the irqcfg0e_tx_ stop[5] bit goes high as the modulator starts to send the last bit. the transmitter must remain on one bit period after tx_stop to transmit the last bit. if the transmitter is switched off (switched to a n other mode), the transmission stops immediately even if there is still data in the shift register. in
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 18 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 transmit mode the two interrupt signals are irq0 and irq1. irq1 is mapped to irqcfg0d_fifofull[2] signal indicating that the transmission fifo is full when irqcfg0d_tx_irq1[3] is set to 0, or to irqcfg0e_tx_ stop[5] when irqcfg0d_ tx_irq1[3] is set to 1. irq0 is mapped to the irqcfg0d_nfifoempy[1] signal. this signal indicates the transmitter fifo is e mpty and must be refilled with data to continue transmi s sion. 3.7 irq0 and irq1 mapping two TRC105 outputs are dedicated to host microcontroller interrupts or signaling. the interrupts are irq0 and irq1 and each have selecta ble sources. t ables 10 , 11, 12 and 13 below summarize the interrupt mapping o p- tions. these interrupts are especially useful in continuous or buffered data mode operation. irqcfg0d_rx_irq0 data mode irq0 irq0 interrupt source 00 continuous output start pattern detect 01 continuous ou tput rssi_irq 10 continuous output start pattern detect 11 continuous output start pattern detect 00 buffered output none (set to 0) 01 buffered output write_byte 10 buffered output nfifoempy 11 buffered output start pattern detect 00 packet output data_rdy 01 packet output write_byte 10 packet output nfifoempy 11 packet output node address match if addrs_cmp is enabled start pattern detect if addrs_cmp is disabled table 10 irqcfg0d_rx_irq1 data mode irq1 irq1 interrupt source 00 continuou s output dclk 01 continuous output dclk 10 continuous output dclk 11 continuous output dclk 00 buffered output none (set to 0) 01 buffered output fifofull 10 buffered output rssi_irq 11 buffered output fifo_int_rx 00 packet output crc_ok 01 packet output fifofull 10 packet output rssi_irq 11 packet output fifo_int_rx table 11 tabl es 12 a nd 13 describe the interrupts available in transmit mode: irqcfg0d_tx_irq0 data mode irq0 irq0 interrupt source 0 continuous output none (set to 0) 1 contin uous output none (set to 0) 0 buffered output fifo_thresh 1 buffered output nfifoemp y 0 packet output fifo_thresh 1 packet output nfifoemp y
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 19 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 table 12 irqcfg0d_tx_irq1 data mode irq1 irq0 interrupt source 0 continuous output dclk 1 continuous output dclk 0 buffered output fi fo full 1 buffered output tx_stop 0 packet output fifo full 1 packet output tx_stop table 13 3.8 buffered clock output the buffered clock output is a signal derived from f xtal . it can be used as a reference clock for the hos t microco n- troller and is output on the clkout pin. the oscfg1b_clkout_en [ 7 ] bit controls the clkout pin. when this bit is set to 1, clkout is enabled, otherwise it is disabled. the output frequency of clkout is defined by the value of the oscfg1b_clk_freq[ 6..2] parameter which gives the frequency divider ratio ap plied to f xtal . refer to ta ble 42 for programming detail s . note: clkout is disabled when the TRC105 is in sleep mode. if sleep mode is used, the host microcontroller must have provisions to run fro m its own clock source. 3.9 packet data mode the TRC105 provides optional on - chip rx and tx packet handling features. these features ease the develo p- ment of packet oriented wireless communication protocols and free the mcu resources for other tasks. the o p- tions include enabling protocols based on fixed and variable packet lengths, data scrambling, crc checksum ca l- culations and received packet filtering. all the programmable parameters of the packet data mode are accessible through the pktcfg configur ation registers of the device. the packet data mode is enabled when the register bit mcfg01_mode [ 7..6 ] is set to 1 0 or 11 . the packet handler supports three types of packet formats: fixed length packets, variable length packets, and e x- tended variable length p ackets. the pktcfg1e_pkt_mode [7] bit selects either the fixed or the variable length packet formats. 3.9 .1 fixed length packet mode the fixed length packet mode is selected by setting the pktcfg1e_pkt_mode [7 ] bit to 0. in this mode the length of the pack et is set by the pktcfg1c_pkt_len[6..0] register up to the size of th e fifo which has been selected. the length stored in this register is the length of the payload which includes the message data bytes and optional a d dress byte. the fixed length pac ket f ormat shown in figure 13 is made up of the following fields: 1. preamble 2. start pattern (network address ) 3. node address byte (optional) 4. data bytes 5. two - byte crc checksum (optional)
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 20 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 figure 13 3.9 .2 variable length packet mode the variable len gth packet mode is selected by setting bit pktcfg1e_pkt_mode [7 ] to 1. the packet format shown in figure 14 is programmable and is made up of the following fields: 1. preamble 2. start pattern (network address ) 3. length byte 4. node address byte (optional ) 5. data bytes 6. two - byte crc checksum (optional) figure 14 in variable length packet mo de, the length of the rest of the payload is given by the first byte written to the fifo. the length b yte itself is not included in this count . the pktcfg1c_pkt_l en[6..0] parameter is used to set the maxi mum received payload length allowed . any received packet having a value in the length byte greater than this maximum is discarded. the variable length packet format a c commodates payloads, including the length byte, up to the length of the fifo. 3.9.3 extended variable length packet mode the extended variable length packet mode is selected by setting bit pktcfg1e_pkt_mode [7] to 1 and setting pktcfg1c_pkt_len[6..0] to a value between 65 and 127. the packet format sh own in figure 15 is programm a- ble and is made up of the fo l lowing fields: 1. preamble 2. start pattern (network address ) 3. length byte 4. node address byte (optional) 5. data bytes 6. two - byte crc checksum (optional)
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 21 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 figure 15 in extended variable len gth packet mo de, the length of the rest of the payload is given by the first byte written to the fifo. the length b yte itself is not included in this count . there are a number of ways to use the extended va r- iable length packet capability. the most common w ay is ou t lined below: 1. set pktcfg1c_pkt_len[6..0] to a value between 65 (0x 41) and 127 (0x7f). this sets the ma ximum allowed payload in extended packet mode. any received packet having a value in the length byte greater than this max i- mum is dis carded. 2. set pktcfg1e_pkt_mode[7 ] to 1 for variable length packet mode operation. set the pktcfg1e_ pr e- amb_len[6..5] bits to 10 or 11 for a 3 or 4 byte preamble. set the pktcfg1e_crc_en[3] bit to 1 to enable crc processing. set the pktcfg1e_pkt_addrs_cmp[2..1] b its as required. clear the pktcfg1e_ crc_stat[0] bit by wri t ing a 1 to it. 3. set mcfg0c _fifo_depth[7..6] bits to 11 for a 64 byte fifo length. 4. set the mcfg0c _fifo_thresh[5..0] to approximately 31(0x1f). this sets the threshold to 32, near the mid poi nt of the fifo. provided the host microcontroller is relatively fast (usual case), this setting can be used for monito r ing the fifo in both transmit and receive. if the host microcontroller is relatively slow, set the threshold to a value lower than 31 for receive, and higher than 31 for transmit. 5. set the irqcfg0d_rx_irq1[5..4] bits to 11. this maps fifo_int_rx interrupt to irq1, which trips when the number of received bytes in the fifo is equal to or greater than the value in mcfg05_fifo_thresh. irq1 w ill then signal received bytes must be retrieved. if received bytes are not retrieved before the fifo completely fills, data will be lost. 6. set the irqcfg0d_tx_irq0[3 ] bit to 0. this causes a transmission to start when the number of transmit bytes in th e fifo is equal to or greater than the value in mcfg0c _fifo_thresh. also, the fifo_int_tx interrupt is mapped to irq0 in transmit mode, and is set when the number of bytes in the fifo is equal to or less than the value in mcfg0c _fifo_thresh. irq0 will then signal more bytes can be added to the fifo. if more message bytes are not added in time, the transmission will cease prematurely and data will be lost. likewise, if more bytes are sent to the fifo than it has room for, data will be lost. 7. when receivin g an extended variable length packet, monitor irq1. when irq1 trips, clock out some of the r e- ceived bytes from the fifo (leave at least one byte in the fifo). repeat the partial packet retrieval each time irq1 triggers. the first byte received is the numbe r of message bytes, and can be used to tell when the last me s- sage byte has been retrieved. when it is dete r mined that the remaining message bytes will not overflow the fifo, the irqcfg0d_rx_irq1[5..4] bits can be set to 00, which maps crc_ok to irq1. after the crc is checked, the final bytes can be read from the fifo and the irqcfg0d_rx_irq1[5..4 ] bits can be reset to 11 to track
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 22 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 fifo_int_rx when the next packet is received. note that crc mapping to irq1 is not r e quired if the crc state is read from the pk tcfg1e_ crc_stat[0] bit prior t o reading the final fifo bytes. 8. when transmitting an extended variable length packet, begin filling the fifo until irq0 trips, indicating the fifo is half full. add up to 32 bytes to the fifo (64 - (mcfg05_ fifo_thresh +1 )) when irq0 resets. repeat the partial packet loading each time irq0 resets until all bytes to be transmitted have been clocked in. the irqcfg0d_tx_irq1[3 ] bit can then be set to 1, which allows the tx_stop event to be mapped to irq1. tx_stop signals the last bit to be transmitted has been transferred the modulator. allow one bit period for this bit to be transmitted before switching out of transmit mode. 3.9 .4 packet payload processing in transmit and receive the TRC105 packet handler constructs transmi t packets usi ng the payload in the fifo . in receive, it processes the packets and extracts the payload to the fifo. packet processing in transmit and receive are detailed below. for transmit, the pa cket handler adds the following fie lds and processing to the payload in the fifo: 1. one automatic preamble byte 2. one to four additional preamble bytes, programmable and usually set to 3 or 4 bytes 3. one to four start pattern bytes, programmable and usually set to at least 2 bytes 4. optional crc checksum c alculated over the fifo payload and appending to the end of the packet 5. optional manchester encoding or dc - balanced scrambling the payload in the fifo may contain one or both of the following optional fields: 1. a length byte if the variable packet len gth mode is selected 2. a node address byte if the fifo is filled while transmit mode is enabled, and if irqcfg0e_start_full[4] is set to 1, the modulator waits until the first byte is written into the fifo, then it starts sending the programmed preamble bytes followed by the start pattern and the user payload. if irqcfg0e_start_full[4 ] is set to 0 in the same conditions, the mod u- l a tor waits until the number of bytes written in the fifo is equal to the number defined in the register mcfg05_ fifo_thresh[5. .0] . note that the transmitter automatically sends preamble bytes in addition the number pr o- grammed while in transmit mode and waiting for the fifo to receive the required number of bytes to start data transmission. data to be transmitted can also be writ ten in to the fifo during standby mode. in this case, the data is automatically transmitted when the transmit mode is e n abled and the transmitter reaches its steady state. if crc is enabled, the crc checksum is calculated over the payload bytes. this 16 - b it checksum is sent after the bytes in the fifo. if crc is enabled, the tx_stop bit is set when the last crc bit is transferred to the tx mod u- lator. if crc is not enabled, the tx_stop bit is set when the last bit from the fifo is transferred to the tx mod u- lator. note that the transmitter must remain on one bit period after the tx_stop bit is set while the last bit is b e- ing transmitted. if the transmitter remains on following the transmission of the last bit after tx_stop is set, the transmitter will send pr eamble bytes. if manchester encoding or scrambling is enabled, all data except the prea m- ble and start pattern is encoded or scrambled before transmission. note that the length byte in the fifo dete r- mines the length of the packet to be sent and the pktcfg1c _pkt_len[6..0] p a rameter is not used in transmit. in receive , the packet handler retrieves the payload by performing the following steps: 1. data and clock recovery synchronization to the preamble 2. start pattern detection 3. optional address byte check 4. error detection through crc
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 23 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 when receive mode is enabled , the demodulator detects the pr eamble followed by the start pattern . if fixed length packet format is enabled , then the number of b ytes received as the payload is given by the pktcfg1c_pkt_ len[ 6..0] parameter. in variable length and extended variable length packet modes, the first byte received after the start pattern is interpreted as the le ngth of the balance of the payload . an internal length counter is initialized to this length. the pktcfg1 c_pkt_len[6..0] register must be set to a value which is equal to or greater than the maximum expected length byte value of the received packet. if the length byte value of a received packet is greater than the value in the pktcfg1c_ pkt_len[6..0] register , the packet is discarded. otherwise the packet payload b e gins loading into the fifo. if address match is enabled, the second byte received in a variable length mode or the first byte in the fixed length mode is interpreted as the node address. if this ad dress matches the byte in pktcfg1d_ node_addrs[7..0] , r e ception of the packet continues, otherwise it is stopped. a crc check is performed if pktcfg1e_ crc_ en[3] is set to 1. if the crc check is successful, a 1 is loaded in the pktcfg1e_ crc_stat[0] bit, and crc_ok and dat_rdy interrupts are simultaneously generated on irq1 and irq0 respectively. this signals that the pa y- load or balance of the payload can be read from the fifo. in receive mode, address match, dat_rdy, and crc_ok interrupts and the crc_stat bi t are reset when the last byte in the fifo is read. note the fifo can be read in standby mode by setting pgcfg1f_ rnw _fifo[6] bit to 1. in standby, reading the last fifo byte does not clear crc_ok and the crc_stat bit. they are reset once the trc103 is put in receive mode again and a start pattern is detected. if the crc check fails, the fifo is cleared and no interrupts are generated. this action can be overridden by se t- ting pgcfg1f_ crcclr_auto[7 ] to 1, which forces a data_rdy interrupt and preserves the pa y load in the fifo even if the crc fails. if address check ing is enabled, the second byte received in a variable length mode or the first byte in the fixed length mode is interpreted as the node address. if this address matches the byte in pktcfg1d_ node _ addrs[7..0] , r e ception of the packet continues, otherwise it is stopped. a crc check is performed if pktcfg1e_ crc_en[3] is set to 1. if the crc check is successful, a 1 is loaded in the pktcfg1e_ crc_stat[0] bit, and crc_ok and dat_rdy interrupts are sim ultaneously generated on irq1 and irq0 respectively, signaling the payload or balance of the payload can be read from the fifo. note the fifo can be read in standby mode by setting pgcfg1f_ rnw _fifo[6] bit to 1 . if the crc check fails, the fifo is cleared and no interrupts are ge n- erated . this action can be overridden by setting pgcfg1f_ crcclr_auto[7 ] to 1, which forces a data_rdy inte r- rupt and preserves the pa y load in the fifo even if the crc fails. 3.9 .5 packet filtering received packets can be filtered based on two criteria: length filtering and address filtering. in variable length or extended variable length packet formats, pktcfg1 c_pkt_len[6 .. 0] stores the maximum packet length permi t ted. if the received packet length is greater than this value, then the packet is discarded. node address filtering is e n- abled by setting p a rameter p ktc fg1 e _ addrs_cmp[ 2..1 ] to any value other than 00, i.e., 01, 10 or 11. these settings enable the following three options: pktcfg1e_ addrs_cmp[2..1] = 01: this configuration activates the address filtering function on the packet handler and the received address byte is compared with the address in the pktcfg1d_ node_a ddrs[7..0] regi s- ter. if both address bytes are the same, the received packet is for the current destination and is stored in fifo . o therwise it is discarded. an interrupt can also be ge n erated on irq0 if the address comparison i s successful. pktcfg1e_ addrs_cmp[2..1] = 10: in this configuration the received address is compared to both the pktcfg1d_ node_a ddrs[7..0] register and constant 0x00. if the r eceived address byte matches either value , the pa cket is accepted. an interrupt can also be ge n erated on irq 0 if the address comparison i s successful. the 0x00 address is useful for sending broadcast pac k ets.
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 24 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 pktcfg1e_ addrs_cmp[2..1] = 11: in this configuration t he packet is accept ed if the received address matches either the pktcfg1d_ node_addrs[7..0] regi ster, 0x00 or 0xff. an interrupt can also be generated on irq 0 if the ad dress comparison i s successful. the 0x00 an d 0xff addresses are useful for sending two types of broa d- cast pac k ets. 3.9 .6 cyclic redundancy check crc check is enabled by setting the pktcfg1e_ crc_en [3 ] bit to 1. a 16 - bit crc checksum is calculated on the p ayload part of the packet and is appended t o the end of the transmitted message. the crc chec k sum is calculated on the received payload and compared to the transmitted crc. the result of the co m parison is stored in the pktcfg1e_ crc_stat [0 ] bit and an interrupt can also be generated on irq1 . the crc is based on the ccitt polynomial as shown in figure 16 . the crc also detects errors due to leading and trailing zeros. figure 16 3.9 .7 manchester encoding manchester encoding is enabled by setting the pktcfg1c_man_en [7 ] bit to 1, and can only be used in p acket data mode . figure 17 illustrates manchester encoding. nrz data is converted to manchester by encoding 1 bits as 10 chip sequences, and 0 bits as 01 chip sequences. manchester encoding guarantees dc - balance and fr e- quent data transitions in the en coded data. note the maximum manchester chip rate corresponds to the maximum b it rate given in the specificati ons in table 52 . figure17 in transmit, manchester encoding is applied only to the payload and crc pa rts of the packet. the receiver d e- codes the payload and crc b efore performing other packet processing tasks .
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 25 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 3.9 .8 dc - balanced scrambling a payload m ay contain long sequences of 1 or 0 bits. these sequence s would introduce dc bias es in the tran s- mitted signal, causing a non - uniform power distribut ion spectrum. these sequences would also degrade the pe r- formance of the demodulation and data and clock recovery functions in the receiver . system p erformance can be enhanced if the payload bits are random ized to reduce dc biases and increase the number o f bit transitions . as discussed above, dc - balanced data can be obtained by using manchester encoding, which ensures that there are no more than two consecutive 1s or 0s in the transmitted data . however , this reduces the effective bit - rate of the system b ecause it doubles the amou nt of data to be transmitted . another technique called scrambling (whitening) is widel y used for randomizing data before radio tr ansmission. the data is scrambled using a random sequence o n the transmit side and then descrambled on the receive side using the same sequence. the TRC105 packet handler provide s a mechanism for scrambling the packet payload. a 9 - bit lfsr is used to generate a random seq uence. the payload and t he 16 - bit crc checksum are xord with this random s e quence as shown in fi gure 18 . the data is descrambled on the receiver side by xoring with the same random s e- quence. the scrambling/descrambling proce ss is enabled by setting the pktcfg1e_scrmb _en [4 ] bit to 1. figure 18 3.10 spi configuration interface the trc 105 contains two spi - compatible interfaces, one to read and write the configuration registers, the other to read and write fifo data. both interfaces are configured in slave mode and share the same pins: sdo (spi slave data out), sdi (spi slave data in), and sck (serial clock). two pins are provided to select the spi co n- nection. the nss_config pin allows access to the configuration registers and the nss_data pin allo ws access to the fifo. figure 19 shows a typical connection between a host microcontroller and the spi interface.
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 26 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 figure 19 a byte transmission can be seen as a rotate operation between the value stor ed in an 8 - bit shift register in the master device ( host microcontroller ) and the value stored in an 8 - b it shift register in the transceiver . th e sck line is used to synchronize both spi bit transfers . data is transfe rred full - duplex from master to slave through the sdi line and from slave to master through the sdo line. the most significant bit is always sent first. in both directions t he rising sck edge is used to sample a bit, and the falling sck edge shifts the bits through the shift register. the nss_config or nss_data signal s are asserted by the master device a nd should remain low during a byte transmission. the transmission is synchronized by these nss_config or nss_data signals. while the nss_config or nss_data is set to 1, the counters controlling transmission are reset. reception starts with the first clock cycle after the falling edge of nss_config or nss_data . i f either signal goes high during a byte transmission the counter s are reset and the byte must be retransmitted. the configuration interface is selected if nss_config is low even if the TRC105 is in buffered mode and nss_data is low ( nss _config has priority). to configure the tran sceiver two bytes are required. t he first byte c ontains a 0 start bit , r/w information (1 = read, 0 = write), 5 bits for the add ress of the register and a 0 stop bit . the second byte contains the data to be sent in write mode or the new address to r ead fro m in read mode. figure 20
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 27 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 figure 20 shows the timing diagram for a single byte write sequence to t he TRC105 through the spi configuration interface. note that nss_config must remain low during the transmission of the two bytes ( address and data). i f it goes high after the first byte, then the next byte will be considered as an address byte. when writing to more than one register successively, nss_config does not need to have a high - to - low transition between two write s e quences. the bytes are alternative ly considered as an address byte followed by a data byte. the read sequence through the spi configuration interface is similar to the write sequence. the host microco n- tro l ler sends the address during the first spi communication and then reads the data dur ing a second spi co m- munication. note that 0 bits can be input to the sdi during the second spi communication for a single byte read. fi g ure 21 shows the timing diagram for a single byte r ead sequence from the TRC105 through the spi. figure 21 figure 2 2 multiple config u ration register reads are also possible by sending a series of register addresses into the spi port , as shown in figure 22 . 3.11 spi data fifo interface when the tran sceiver is used in buffered or p acket data mode, data is written to a nd read from the fifo through the spi interface. two interrupts, irq0 and irq1, are used to manage the transfer procedure. when the transceiver is operating in b uffered or p acket data mode, the fifo interface is selected when nss_data is set to 0 and nss_ config is set to 1. spi o pe rations with the fifo are s imilar to operations with the co nfiguration registers with two important exceptions. first, no addresses are used with the fifo, only data bytes are exchanged . second, nss_data must be toggled high and back low between data bytes when writing to the fifo or reading from the fifo. toggling nss_data indexes the access pointer to each byte in the fifo in lieu of using explicit addressing. figure 23 shows the timing diagram for a multiple - byte write sequence to the TRC105 during transmit , and figure 24 shows the timing for a multi - byte read sequence.
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 28 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 figure 23 figure 24
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 29 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 4 .0 configuration register memory map register names are based on the function name and addr ess location for easy reference. the pag e 0 (default) register mem ory map is shown in table 14 below. the two configuration registers for low battery detection are l o cated in the page 1 register memory map . see t ables 47 and 48 for details of these registers. hex function address name 0x 1f pgcfg1f pktcfg1e pktcfg1d 0x1c pktcfg1c 0x1b osc fg1b 0x1a txcfg1a syncfg19 syncfg18 syncfg17 0x 16 syncfg16 rxcfg15 rxcfg14 rxcfg13 rxcfg12 rxcfg11 0x 10 rxcfg10 irqcfg0f irqcfg0e irqcfg0d 0x0c irq cfg0c mcfg0b mcfg0a mcfg09 mcfg08 mcfg07 mcfg06 mcfg05 mcfg04 mcf g03 mcfg02 mcfg01 0x00 mcfg00 table 14
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 30 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 4.1 main configuration registers (mcfg) power - up default setting s are shown in bold: 0x00 - mcfg00 [default 0x2f ] name bits r/w description chip_mode 7,6,5 r/w transceiver chip mode: 000 sleep 001 standby 010 s ynthesizer 011 receive 100 transmit 101 , 100, 111 not used band 4,3 ,2 r/w frequency band: 00 0 300 - 330 mhz 0 01 330 - 365 mhz 0 10 365 - 400 mhz 0 11 400 - 440 mhz 100 440 - 470 mhz 101 470 - 510 mhz 110, 111 not use d sub b and 1 ,0 r/w frequency subband: 00 1 st (lowest) quarter of selected band 01 2 nd quarter of selected band 10 3 rd quarter of selected band 11 4 th (highest ) quarter of selected band table 15 0x01 - mcfg01 [default 0x24 ] name bits r/w des cription mode 7,6 r/w d ata mode: 00 continuous 01 buffered 10, 11 packet fsk_ook 5,4 r/w tx/rx modulation: 00 reset 01 ook 10 fsk 11 not used rx_ook 3,2 r/w rx ook threshold mode: 00 fixed threshold 01 peak mode 10 avg mode 11 not us ed if_gain 1,0 r/w gain ( agc) on if chain : 00 maximum if gain 01 - 4.5 db below maximum 10 - 9 db below maximum 11 - 13.5 db below maximum table 16
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 31 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 0x02 - mcfg02 [default 0x03 ] name bits r/w description freq_dev 7..0 r/w frequency deviation: f d ev = f xtal /(32 ? (r+1)) where r is the freq_dev register value, f dev and f xtal are in k hz, 0 r 255 freq_dev default = 3, f dev = 100 khz for f xtal = 12,800 khz table 17 0x03 - mcfg03 [default 0x07 ] name bits r/w description bit_r ate _c 7 ..0 r/w b r = f xtal /(2*(c+1) *(d + 1)), where c and d are the bit rate parameters, and bit rate br and f xtal are in k hz , 0 c 255 , d = 31 for standard applications bit_rate _c default = 7, br = 25 kb/s for f xtal = 12,800 khz table 18 0x04 - mcfg04 [default 0x1 f ] name bits r/w description bit_rate_d 7..0 r/w br = f xtal /(2*(c+1)*(d + 1)), where c and d are the bit rate parameters, and bit rate br and f xtal are in khz, 15 d 255 . t he d efault value of 31 is suitable for most applications . bit_rate _d default = 3 1 , br = 25 kb/s for f xtal = 12,800 khz table 19 0x05 - mcfg05 [default 0xc6 ] name bits r/w description pa_r amp 7,6 r/w rise/fall time control of power amplifier in ook mode: 00 3 s 01 8.5 s 10 15 s 11 23 s rx_low_pwr 5 r/w enables receiver low power mode by reducing lna current 0 low power mode off 1 low power mode on (suitable for most applications) reserved 4,3 r/w not used trim 2,1 r/w vco trimming: 00 0 mv 01 60 mv 10 120 mv 11 180 mv rf_freq 0 r/w selection between two rf frequencies as defined by synthrx, synthpx, and synthsx registers: 0 f requency 1 1 f requency 2 table 20 0x06 - mcfg06 [default 0x6b ] name bits r/w description synthr1 7..0 r/w rf f requency 1 , r counter r1 = 0x6b (011 0 10 11) for 434 mhz table 21
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 32 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 0x07 - mcfg07 [default 0x2a ] name bits r/w description synthp1 7..0 r/w rf f requency 1, p counter p1 = 0x2a (00 1010 1 0) for 434 mhz table 22 0x08 - mcfg08 [default 0x1e ] name bits r/w description synths1 7..0 r/w rf f requency 1, s counter s1 = 0 x1e (000 1 11 10) for 434 mhz tabl e 23 0x09 C mcfg09 [default 0x77 ] name bits r/w description synthr2 7..0 r/w rf f requency 2, r counter r2 = 0x77 (01110111 b) for 435 mhz table 24 0x0a - mcfg0a [default 0x2f ] name bits r/w description synthp2 7..0 r /w rf f requency 2, p counter p2 = 0x2f (00 10 1111 b) for 435 mhz table 25 0x0b - mcfg0b [default 0x19 ] name bits r/w description synths2 7..0 r/w rf f requency 2, s counter s2 = 0x19 (000110 0 1 b) for 435 mhz table 26 0x0c - m cfg0c [default 0x0f ] name bits r/w description fifo_depth 7,6 r/w configures the size of the fifo: 00 16 bytes 01 32 bytes 10 48 bytes 11 64 bytes fifo_thresh 5..0 r/w number of bytes to be written in the fifo to activate the fifo_int_tx and fifo_int_rx interrupts. number of bytes = b + 1, where b is the register value. fifo_thresh default = 15, number of bytes = 16 table 27
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 33 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 4.2 interrupt configuration registers (irqcfg) 0x0d - irqcfg0d [default 0x00 ] name bits r/w description rx_irq0 7,6 r/w irq0 source in receive mode: c ontinuous data mode - 00 irq0 mapped to pattern signal 01 irq0 mapped to rssi_irq 10,11 irq0 mapped to start pattern detect b uffered data mode - 00 irq0 set to 0 01 irq0 mapped to write_byte 10 irq0 mapped to nfifoempy (also in standby mode) 11 irq0 mapped to start pattern det ect p acket data mode - 00 irq0 mapped to data_rdy signal 01 irq0 mapped to write_byte 10 irq0 mapped to nfifoempy (also in standby mode) 11 irq0 mapp ed to node address match if addrs_cmp is enabled 11 irq0 mapped to start pattern detect if addrs_cmp is not enabled rx_irq1 5,4 r/w irq1 source in receive mode. c onti nuous data mode - 00 irq1 mapped to dclk signal 01,10,11 irq1 mapped to dclk b uffered data m ode - 00 irq1 set to 0 01 irq1 mapped to fifofull 10 irq1 mapped to rss i_irq 11 i rq1 mapped to fifo_int_rx (also in standby mode) p acket data mode - 00 irq1 mapped to crc_ok 01 irq1 mapped to fifofull (also in standby mode) 10 irq1 mapped to rssi_irq 11 i rq1 mapped to fifo_int_rx (also in standby mode) tx_irq0 3 r/w irq0 source in transmit mode: c ontinuous data mode - 0,1 irq0 set to 0 buffered or p acket data mode s - 0 irq 0 mapped to fifo_thresh (transmission starts when irq0 switches high ) 1 irq0 is mapped to n fifo emp y (transmission starts when irq0 switches high ) tx_irq1 2 r irq1 source in transmit mode. c ontinuous data mode - 0, 1 irq_1 mapped to dclk buffered or p acket data mode s - 0 irq1 mapped to fifo full 1 i rq1 is mapped to tx_stop fifo full 1 r fifo full (irq source) nfifo emp y 0 r low when fifo empty (irq source) . table 28
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 34 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 0x0e - irqcfg0e [default 0x 01 ] name bits r/w description start_fill 7 r/w fifo f ill mode selection: 0 fifo starts filling when st art pattern is recognized 1 fifo fills as long as start_det is 1 start_det 6 r/w /c start of fifo fill: if start_fill = 0, goes high whe n start pattern recognized. write a 1 to reset the start pattern recognition . if start_fill = 1 0 stop filling fifo 1 start filling fifo tx_stop 5 r transmit state: 0 transferring bits to the tx modulator 1 last bit transferred to the tx modulator fifo_o vr 4 r/w /c fifo overflow: in b uffered data mode, writing a 1 to this bit clears the fifo. in p acket data mode, writing a 1 to this bit clears the fifo and allows a new packet to be transmitted or received immediately. rssi_int 3 r/w enable s sig_detect when rssi_thld is tripped: 0 disable interr upt 1 enable interrupt sig_detect 2 r/w/c dete cts a signal above the rssi_thld: 0 signal lower than threshold 1 signal equal or greater than the rssi_thld level this bit latches high and must be cleared by writing a 1 to its location. pll_lock _st 1 r/w/c detects the pll lock status : 0 pll not locked 1 pll locked this bit latches high each time the pll locks and must be cleared by writing a 1 to its location. pll_lock_en 0 r/w enables the pll_lock signal on pin 23 0 pll_lock signal disabled, p in 23 set high 1 pll_lock signal enabled ta ble 29 0x0f - irqcfg0f [default 0x00 ] name bits r/w description rssi_thld(7..0) 7..0 r/w rssi threshold level for interrupt. rssi_thld d efault is 0x00 table 30
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 35 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 4.3 receiver configuration registers (rxcfg) 0x10 - rxcfg10 [default 0xa3 ] name bits r/ w description lp_filt(7..4) 7,6,5,4 r/w bandwidth of the low - pass filter. 0000 65 khz 0001 82 khz 0010 109 khz 0011 137 khz 0100 157 khz 0101 184 khz 0110 211 khz 0111 234 khz 1000 262 khz 1001 321 khz 1010 3 78 khz 1011 414 khz 1100 458 khz 1101 514 khz 1110 676 khz 1111 987 khz bw_filt(3..0) 3,2,1,0 r/w cutoff freque ncy of the receiver fsk butterworth low - pass filter s: f cbw = 200*(f xtal /12800)*((j + 1)/8 ) , where f cbw is the 3 db cutoff frequency of the butterworth filters in khz, and j is the integer value of bw_filt with a ra nge of 0 to 15 . or u pper cutoff frequency of the ook polyphase band - pas s filters: f cpp = f opp + 200*(f xtal /12800)*((j + 1)/8) , where f cpp is the upper cutof f frequency of polyphase filter s in khz , f opp is the center frequency of the ook polyphase filter s in khz (see rxcfg11 below) , f xtal is the crystal frequency in khz, and j is the integer value of bw_filt with the usable range of 0 to 1. bw_filt default = 0011 b , f cbw = 1 00 khz for a 12,800 khz crystal table 31 0x11 - rxcfg11 [default 0x38 ] name bits r/w description polyfilt(7..4) 7,6,5,4 r/w center frequency of the polyphase filter: f opp = 200* (f xtal /12800)* ((l + 1)/8) , whe re f opp is the center frequency of the ook polyphase filter in khz, f xtal is the crystal frequency in khz, and l is the integer value of polyfilt . polyfilt default = 0011 b , f opp = 100 khz for a 12,800 khz crystal pa_reg 3 r/w power amp step regulation mo de: 0 regulation disabled 1 regulation enabled - 2,1,0 n ot used table 32
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 36 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 0x12 - rxcfg12 [default 0x18 ] name bits r/w description polyfilt_en 7 r/w polyphase filter enable: 0 polyphase filter disabled 1 polyphase filter enabled dclk_dis 6 r/w data and clock r ecovery enable: 0 enabled 1 disabled recog 5 r/w start pattern detect ( r ecognition ) enable: 0 disabled 1 enabled pat_sz 4,3 r/w start pattern size: 00 1 byte (syncgf16 byte) 01 2 bytes (syncgf16 and syncgf17 bytes) 10 3 bytes (syncgf16, syncgf17 and syncgf18 bytes) 11 4 bytes (syncgf16, syncgf17, syncgf18, and syncgf19 bytes) ptol 2,1 r/w start p attern bit error tolerance : 00 0 errors 01 1 error 10 2 errors 11 3 errors - 0 - n ot used table 33 0x13 - rx cf g13 [default 0x0c ] name bits r/w description ook_thresh 7..0 r/w ook fixed threshold or minimum threshold in peak mode. default is 6 db. 00000000b 0 db 00000001b 0.5 db 00001100b 6 db 11111111b 127 db table 34 0x14 - rxcfg14 [default 0x00 ] nam e bits r/w description rssi 7..0 r rssi output table 35
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 37 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 0x15 - rxcfg15 [default 0x00 ] name bits r/w description ook_step 7,6,5 r/w reduction of max rssi level in peak mode for ook: 000 0.5 db 001 1.0 db 010 1.5 db 011 2.0 db 100 3.0 db 101 4.0 db 110 5.0 db 111 6.0 db ook_length 4,3,2 r/w ook peak mode update period: 000 once per chip period 001 once per 2 chip periods 010 once per 4 chip periods 011 once per 8 chip periods 100 2x per chip period 101 4x per chip period 11 0 8x per chip period 111 16x per chip period ook_iir_coeff 1,0 r/w ook iir filter coefficients in avg m ode. f cag is the cutoff frequency for the avera g ing filter. 00 f cag = chip rate / 32* 01 f cag = chip rate / 8* 10 f cag = chip rate / 4* 11 f cag = chip rate / 2* table 36
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 38 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 4.4 start pattern configuration registers (syncfg) 0x16 - syncfg16 [default 0x00 ] name bits r/w description sync_pat3 7..0 r/w start pattern most significant b yte. this byte is sent first if one or more start patter n bytes are used. default: 00000000b table 37 0x17 - syncfg17 [default 0x00 ] name bits r/w description sync_pat2 7..0 r/w start pattern byte. this byte is sent second if two or more start pattern bytes are used. default: 00000000b table 38 0x18 - syncfg18 [default 0x00 ] name bits r/w description sync_pat1 7..0 r/w start pattern byte. this byte is sent third if three or more start pattern bytes are used. default: 00000000b table 39 0x19 - syncfg19 [default 0x00 ] name bits r/w description sy nc_pat0 7..0 r/w start pattern least significant b yte. this byte is sent last if four start pattern bytes are used. default: 00000000b table 40 4.5 transmitter configuration registers (txcfg) 0x1a - txcfg1a [default 0x 70h] name bits r/w description txinterpfilt 7,6,5,4 r/w transmitter anti - aliasing filter cutoff frequency: f ctx = 200*(f xtal /12800)*((k + 1)/8), where f ctx is the 3 db bandwidth of the transmitter anti - aliasing filters in khz, f xtal is the crystal frequency in khz, and k is the inte ger value of txinterpfilt , . txinterpfilt default = 0111b, f ctx = 200 khz pout 3,2,1 r/w transmitter output power (approx 3 db steps): 000 13 dbm 001 10 db m 010 7 db m 011 4 db m 100 1 db m 101 - 2 db m 110 - 5 dbm 111 - 8 dbm - 0 not u sed table 41
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 39 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 4.6 oscillator configuration register (oscfg) 0x1b - oscfg1b [default 0xbc ] name bits r/w description clkout_en 7 r/w buffered clock output enable: 0 disabled 1 enabled clk_freq 6..2 r/w buffered clock output f requency on pin clkout : f bc o = f xtal / (2* m), where f bco is the buff ered clock output frequency in k hz, f xtal is the crystal fr equency in k hz and m is the value of clk_freq except if clk_freq is 0, f bco = f xtal clk_freq d efault: 01111 , f bco = 426.67 khz for a 12,800 k hz crystal - 1,0 n ot used table 42 4.7 packet handler configuration registers (pktcfg) 0x1c - pktcfg1c [default 0x00 ] name bits r/w description man_en 7 r/w manchester encoding/d ecoding enable: 0 manchester encoding/d ecoding off 1 manchester encoding/d ecoding on pkt_len 6..0 r/w packet length: the payload size in fixed length mode, the maximum length byte value in var i able length mode, and the maximum length byte value in extended variable le ngth packet mode. pkt_len d efault: 0000000b table 43 0x1d - pktcfg1d [default 0x00 ] name bits r/w description node_addrs 7..0 r/w node address use d in filtering received packets in a network. ta ble 4 4
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 40 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 0x1e - pktcfg1e [default 0x 40 ] name bits r/w description pkt_mode 7 r/w packet m ode: 0 fixed length packet mode 1 variable length packet mode preamb_len 6,5 r/w preamble length: 00 1 byte 01 2 bytes 10 3 bytes 11 4 bytes scrmb _en 4 r/w dc - balanced s crambling enable: 0 scrambling off 1 scrambling on crc_en 3 r/w cyclic redu ndancy check processing enable: 0 crc off 1 crc on addrs_cmp 2,1 r/w node a ddress comparison for received packets: 00 no comparison 01 compare with node_addrs only 10 compare with node_addrs and constant 0x00 11 compare with node_addrs and con stants 0x00 or 0xff crc_stat 0 r calculate crc and check result: 0 crc failed 1 crc successful this bit must be cleared by writing a 1 to its location. table 45 4.8 page configuration register (pgcfg) 0x1f - pgcfg1f [default 0x00 ] name bits r/w d escription crcclr_auto 7 r/w automatically clear fifo if crc fails (receive only): 0 clear fifo if crc fails 1 do not clear fifo rnw_fifo 6 r/w selects read or write fifo while in standby mode: 0 write fifo 1 read fifo - 5,4,3,2 not u sed pa ge 1,0 r/w register p age select (leave set to page 0 unless configuring low battery detect) : 00 page 0 01 page 1 10 not used 11 not used table 46
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 41 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 4.9 low battery configuration registers (lb cfg) page 0x01, 0x05 - lbcfg05 [default 0xb1 ] name bi ts r/w description reserved 7,6,5,4 r/w do not change default bit pattern: 1011 default bit pattern lb_en 3 r/w low battery detection enable : 0 detection off 1 detection on lb_thres 2,1 ,0 r/w low battery detection threshold : 00 0 1.79 v 0 0 1 1. 84 v 010 1.90 v 011 1.97 v 100 2.02 v 101 2.08 v 110 2.14 v 111 2.20 v table 47 page 0x01, 0x06 - lbcfg06 [default 0x96 ] name bits r/w description lb_status 7 r low battery status: 0 battery voltage below threshold 1 battery voltage above threshold lb_ out 6 r/w map low battery detect to pin 24: 0 not mapped 1 mapped reserved 5,4,3, 2,1,0 r/w do not change default bit pattern: 010110 default bit pattern table 48 note: take care to immediately return to configuration regist er memory map p age 0 fo llowing a read or write to the low b a t tery configuration registers in p age 1. page configuration register pgcfg1f is mapped into all pages at the same address of 0x1f. bits 0..1 of this register control page selection. see table 46.
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 42 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 5 .0 electrical characteristics absolute maximum ratings symbol parameter notes min max units v dd supply voltage - 0.3 3.7 v t stg storage temperature - 55 +125 c esd jedec 22 - a114 class rating 1,2 v rf in input level 0 dbm table 49 recommended operating range symbol parameter notes min max units v dd positive supply voltage 2.1 3.6 v top operating temperature - 40 +85 c rfin input level - 0 dbm notes: 1. pins 3,4,5,27,28,29,31 comply with class 1a. 2. all other pins comply with class 2. table 50 5.1 dc electrical characteristics min imum /max imum values are valid over the recommended operating range v dd = 2.1 - 3.6v. typical conditions: t o = 25c; v dd = 3.3 v. the electrical specifications given below are valid for a crystal having the specifica tions given in table 3 . parameter sym notes min typ max units test notes sleep mode current i s 0.1 1 a standby mode current , crystal oscillator running i sb 12.8 mhz crystal 6 5 85 a synthesizer mode current, osc illator and synthesizer ru n ning i fm 300 - 434 mhz 1.3 1.7 ma 440 - 470 mhz 1.4 470 - 510 mhz 1.7 receiver mode current, all receiver blocks running i rx 300 - 434 mhz 2.7 3 .0 ma rx_low_pwr bit = 1 440 - 470 mhz 2.7 470 - 510 mhz 2.7 transmitter mode current i tx pout = +1 0 dbm 25 30 ma pout = +1 dbm 16 21 reset threshold v por 1.37 v digital input low level vil 0.2*v dd v digital input high level vih 0.8*v dd v digital input current low iil - 1 1 a vil = 0 v digital input current high iih - 1 1 a vih = v dd , v dd = 3.3 v digital output low level vol 0.1*v dd v iol = - 1 ma digital output high level voh 0.9*v dd v ioh = +1 ma table 51
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 43 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 5.2 ac electrical characteristics min imum /max imum values are valid over the recommended operating range v dd = 2.1 - 3.6v. typical conditions: t o = 25c; v dd = 3.3 v. the electrical specifications given below are valid for a crystal having the specifications given in table 3 . receiver parameter sym min typ max units test notes rf input impedance 150 ohms d if ferential input rf input p ower 0 dbm above 0 dbm receiver input may be damaged receiver noise figure 8 db ic noise figure fsk receiver b andwidth 50 250 khz butterworth filter mode ook receiver bandwidth 50 400 khz polyphase filter mode fsk s ensitivity, 2 kb/s* 10 - 3 ber, bw = 100 khz f dev = 50 khz - 110 dbm 300 - 330 mhz - 112 - 110 434 mhz - 110 470 - 510 mhz fsk sensitivity, 25 kb/s* 10 - 3 ber, bw = 100 khz f dev = 50 khz - 102 dbm 300 - 330 mhz - 104 - 102 434 mhz - 102 470 - 5 10 mhz ook sensitivity, 2 kb/s* 10 - 3 ber, bw = 50 khz - 108 dbm 300 - 330 mhz - 110 - 108 434 mhz - 108 470 - 510 mhz blocking immunity* 53 dbc signal strength of unmodulated blocking signal relative to desired signal, 1 mhz offset co - channel r ejection* - 12 dbc signal strength of modulated co - channel signal relative to desired signal adjacent channel rejection* 38 42 dbc signal strength of adjacent signal relative to desired signal, 600 khz offset, modulation same as desired signal fsk bi t rate 1.56 2 00 kb/s nrz ook bit rate 1.56 32 kb/s nrz rssi resolution 0.5 db rssi accuracy 3 db rssi dynamic range 63 70 db at maximum if gain at minimum if gain local oscillator (lo) emission - 65 dbm *receiver in - circuit perfor mance with rfm recommended saw filter and crystal. table 52 transmitter parameter sym min typ max units test notes rf output impedance 150 ohms d ifferential output maximum rf outpu t p ower * +13 dbm including saw filter insertion loss rf output p ower range * 21 db p rogrammable spurious * - 46 dbc => 150 khz from carrier , n o modulation , 2 nd & 3 rd harmonic * - 40 dbm no modulation 4 th and higher h armonic s * - 40 dbm no modulation phase n oise - 112 - 105 dbc/hz at 600 khz offset fsk d eviat ion 33 50 200 khz p rogrammable *transmitter in - circuit performance with rfm recommended saw filter and crystal. table 53
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 4 4 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 timing parameter sym min typ max units test condition tx to rx switch t ime 500 1000 s osc & freq s ynth esizer running rx to tx switch t ime 400 1000 s osc & freq s ynth esizer running sleep to rx 5 ms spi command to rx bit sleep to tx 5 ms spi command to tx bit sleep to standby 1.5 5 ms oscillator started standby to synth esizer 500 800 s oscillator running s ynthesizer to rx 500 s osc & freq synthesizer running synthesizer to tx 500 s osc & freq synthesizer running freq hop t ime 180 5 00 s 200 khz hop tx rise/fall t ime 3 s p rogrammable t sudata (continuous mode) 2 - - s setup and hold time f or tx data table 54 pll characteristics parameter sym min typ max units test condition crystal osc illator f req uency 10 12.8 15 mhz pll lock time, 10 khz s ettle 180 s 200 khz step 200 s 1 mhz step 250 s 5 mhz step 280 s 10 mhz step 320 s 20 mhz step freq uency synthesizer s tep 12.5 khz varies depending on freq uency crystal load capacitance 13.5 15 16.5 pf crys tal oscillator start - u p t ime 1.5 5 ms f rom sleep mode synthesizer wake - up time 0.5 0.8 ms crystal runni ng, settling time to 10 khz frequency range 300 330 365 400 440 470 - - - - - - 330 365 400 440 470 510 mhz different external components required for each band table 55 spi timing parameter sym min typ max units description sck for spi_config - - 6 mhz max clock freq sck for spi_data - - 1 mhz max clock freq spi_config t su_sdi 250 - - ns spi_config setup time spi_data t su_sdi 312 - - ns spi_data setup time t sscfg_l 500 - - ns nss_config low to sck rising edge. sck falling edge to nss_config high. t ssdat_l 625 - - ns nss_data low to sck rising edge. sck falling edge to nss_data high. t sscfg_h 500 - - ns nss_config rising to falling edge t ssdat_h 625 - - ns nss_data rising to falling edge table 56
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 45 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 6. 0 TRC105 design - in steps designing a TRC105 into an application consists of seven steps: 1. select th e frequency band for operation from the left column in table 57 below . this allows the fre quency specific hardware components for the TRC105 to be determined. these include the saw filter and its matching components and the vco tank indu c tors. 2. select the modulation type, fsk or ook, and the rf data bit rate. this allows the configuration of the TRC105 on - chip filters, the data and clock recovery circuitry and related p a rameters to be determine d. 3. select the radio regulation under which to operate. this allows the transmitter power level to be dete r- mined. 4. select the frequency channel or channels to be used. this allows the configuration values for the fr e- quency synthesizer to be tabulated. 5. sel ect the operatin g mode to be used: continuous , buffered or packet . for contin u ous mode, determine if the TRC105 internal data and clock recovery feature will be used. this allows the configuration of a nu m- ber of mode - related registers in the TRC105 to be determined. for packet or buffer ed mode, select the data encoding, preamble length, start pattern, fifo length and the mapping of the TRC105 host proce s- sor interrupts. for packet mode, select packet filtering options (address, crc, etc.) . from these dec i- si ons, values for the related configuration registers in the TRC105 can be d e termined. 6. if needed, prepare a battery power management strategy and determine when various system radios may be configured for low power consumption. 7. based on the selections and determinations above, compile the configuration data to be stored in the host microcontroller to support TRC105 operation. the details of each of these steps are discussed below. 6.1 determining frequency specific hardware component values 6.1.1 saw fil ters and related component values rfm offers a low - loss saw rf filter for each of the TRC105 s operating bands listed in table 57 . the part nu m- bers for these saw filters and the values of the related tu ning components are referenced to figur e 2 . the saw f ilters are designed to take advantage of the TRC105 s differential output to achieve low i n sertion loss and high out - of - band rejection. operating band 1 saw fi l ter vco band l1 l2 & l3 c4 l7 l8 c16 c17 303.325 - 307.300 mhz rf3602d 300 - 330 mhz bead 2 68 nh dn p 220 nh short dnp dnp 310.000 - 319.500 mhz rf3603d 300 - 330 mhz bead 2 68 nh dnp 220 nh short dnp dnp 342.000 - 348.000 mhz rf3604d 330 - 365 mhz bead 2 56 nh dnp 220 nh 3.3 nh dnp 15 pf 365 .000 - 380.000 mhz rf3605d 365 - 400 mhz bead 2 47 nh dnp 220 nh 33 nh dnp dnp 382.000 - 398.000 mhz rf3606d 365 - 400 mhz bead 2 47 nh dnp 220 nh 68 nh dnp dnp 402.000 - 407.300 mhz rf3607d 400 - 440 mhz bead 2 39 nh dnp 10 nh 5.6 nh 15 pf 1.2 pf 418.000 - 434.790 mhz rf3608d 400 - 440 mhz bead 2 33 nh dnp 220 nh 5.6 nh dnp 1.2 pf 447.000 - 451.000 mhz rf3609d 440 - 470 mhz bead 2 18 nh dnp 220 nh 56 nh dnp dnp 1. xtl1020 p crystal recommended as frequency reference for all operating bands. 2. bead is fair - rite 2506033017 y0 or equivalent. table 57
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 46 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 6.1.2 voltage controlled oscillator com ponent values the TRC105 vco requires four external components for operation, two tank circuit inductors and two power su p- ply decoupling capacitors. it is important to use high - q chip inductors in the tan k circuit. this assures low phase noise vco operati on and minimum interfe r ence from signals near the TRC105 s operating frequency due to phase noise reciprocal mixing. the two tank circui t inductors have the same value which depends on the vco operating band and t he pcb layout. typical values are given in table 58 (location of l5 & l6 shown in fi g ure 2): band l5 & l6 tolerance 300 - 330 mhz 39 nh 5% 330 - 365 mhz 27 nh 5% 365 - 400 mhz 27 nh 5% 400 - 440 mhz 22 nh 5% 440 - 470 mhz 15 nh 5% 470 - 510 mhz tbd 5% table 58 the tank circuit inductors should be mounted close to their ic pads with the long axis of the coil at right angles to the edge of the ic where the pads are located. the decoupling capacitors should be positioned on each side of the tank circuit inductors. other rf chokes and coils should be spaced somewhat away from the tank inductors and pos i tioned at right angles to minimize coupling. vco frequency centering is checked by looking at the voltage between pads 6 and 7. the voltage should be 150 50 mv when the TRC105 is in transmit mode at a frequency near the center of the operating band and subband . vco fr e quency centering can be adjusted by changing the value of the tuning inductors and/or adjusting the vco trim bits 1 and 2 in configuration register mcfg05 . the trim bits adjust the tuni ng voltage in increments of about 60 mv. increasing the value of the tuning inductors increases the tuning voltage b e tween pads 6 and 7. 6.2 determining configuration values for fsk modulation 6.2.1 bit rate related fsk configuration values the TRC105 s upports rf bit rat es (data rates) from 1.5625 to 2 00 kb/s for fsk modulation. there are several considerations in choosing a bit rate. the sensitivity of the TRC105 decreases with increasing data rate. a bit rate should be chosen that is adequate but not h igher than the application requires. the exception to this rule is when the TRC105 is operated as a frequency hopping spread spectrum transceiver in a noisy or crowded band. ru n- ning at a higher bit rate will allow a higher channel hopping rate, which provi des more robust operation in a crowded band in tradeoff for less range under quiet band conditions. the TRC105 rf bit rate is set by the value of the byte s loaded in mcfg03 and mcfg04 . for the standard cry s- tal frequency of 12.8 mhz: br = 12800/(2*(c+1) *( d + 1)), with c in th e range of 0 to 255, and d = 31 (default value) where br is the bit rate in kb/s, f xtal the crystal frequency in khz, c the value in mcfg03 , and d is the value in mcfg04 . this bit rate value supports both the data and clock recovery c ircuit in the receiver and the bit rate clockin g in the transmitter modulator. us ing the default value of d and solving the equ a tion above for c : c = (12800 - 64*br)/64*br
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 47 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 c must be an intege r value, so br is limited to 256 di screte values. if the value of c given in the above equation is not an integer for your desire d bit rate, round the value of c down to the nearest integer. you can then calculate the nearest available bit rate equal to or grea ter than your desired bit rate. selection of the rf data rate allows a suitable fsk deviation to be determined. this, in turn, allows the configur a- tion value for the anti - aliasing filters in the transmitter and the configuration values for the r - c and butterworth low - pass filters in the receiver to be determined . the minimum required deviation for good TRC105 fsk performance is: f dev = br where f dev is the deviation in khz and br is the bit rate in kb/s. specific to the TRC105 , the minimum reco m- mended deviation is 33 khz, even at low data rates. f dev is confi gured with an integer r stored in mcfg02 . for the standard crystal frequency of 12.8 mhz: f dev = 12800/(32*(r + 1)), with the useable range of r 1 to 11 where f dev is the deviation in khz. solving the equation above for r: r = (12800 - 32*f dev )/32*f dev r must be an integer value, so f dev is limited to 11 discrete values. if the value of r given in the above equation is not an integer for your desired deviation, round the value of r down to the nearest integer and use this value to meet or exceed the min imum required deviation for the bit rate you are using. once br and f dev have been determined, the bandwidths and related configuration values for the TRC105 filters can be determined. the recommended 3 db bandwidth (cutoff frequency) for the transmitter anti - aliasing filters is: f ctx = 3*f dev + 1.5*br where f ctx is the 3 db bandwidth of the transmitter anti - aliasing filters in khz, f dev is the frequency deviation in khz and br is the bit rate in kb/s. f ctx is configured with bits 7..4 in txcfg1a . for th e standard crystal freque n- cy of 12.8 mhz: f ctx = 200*(k + 1)/8 , with k in the range of 0 to 15 where f ctx is the 3 db bandwidth of the transmitter anti - alias ing filters in khz and k is the integer value of the bit pa t tern in txcfg1a bits 7..4. solving th e equation above for k: k = (f ctx - 25)/25 k must be an integer value, so f ctx is limited to 16 discrete values. if the value of k given in the above equation is not an integer for your desired deviation, round the value of k down to the nearest integer and use this value to set the bandwidth of the transmitter anti - aliasing filters. for operation at 90 kb/s and above, use a value of 15 for k. the recommended 3 db bandwidth for the receiver butterworth filters is: f cbw = 2*f dev + br where f cbw is the 3 db bandwidth of the butterworth filters in khz, f dev is the frequency deviation in khz and br is the bit rate in kb/s. this equation assumes use of the high accuracy, low drift xtl1020 p crystal. if an altern a- tive crystal is used, add ? the expected drift due to temperature and aging to the equation above. f cbw is confi g- ured with bits 3..0 in rxcfg10 . for the standard crystal frequency of 12.8 mhz: f cbw = 200*(j + 1)/8 , with j in the range of 0 to 15
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 48 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 where f cbw is the 3 db bandwidth of the recei ver butte rworth filters in khz and j is the integer value of the bit pa t tern in rxcfg10 bits 3..0 . using a standard 12.8 mhz crystal, t he equation for determining j is: j = (f cbw - 25)/25 j must be an integer value, so f cbw is limited to 16 discrete values. if t he value of j given in the above equation is not an integer for your deviation and bit rate , round the value of j down to the nearest integer and use this value to set the bandwidth of the receiver butterworth filters for the bit rate you are using. for op eration at 133 kb/s and above, use a value of 15 for j. the recommended 3 db bandwidth for the receiver r - c filters is: f crc = 3.25*f cbw where f crc and f cbw are i n khz. the bandwidth of f crc is set by bits 7..4 in rxcfg10 . the relationship of the r - c fi lter bandwidth to the integer value in rxcfg10 bits 7..4 is given in t able 59 . where the calculated value for f crc falls between table values, use the higher table value. for operation at 100 kb/s and above, use the 987 khz r - c filter ban d width. pattern o f bits 7..4 r - c filter bandwidth 0000 65 khz 0001 82 khz 0010 109 khz 0011 137 khz 0100 157 khz 0101 184 khz 0110 211 khz 0111 234 khz 1000 262 khz 1001 321 khz 1010 378 khz 1011 414 khz 1100 458 khz 1101 514 khz 1110 676 khz 1111 987 khz table 59 6.2.2 determining transmitter power configuration values european etsi en 300 220 - 1 regulates un licensed radio operation in the 433.05 to 434.97 mhz band. a transmi t ter power level up to 10 dbm can be used in this band, subject to certain restr ictions. see en 300 220 - 1 for d e tails. fcc part 15 and canadian rss - 210 regulate unlicensed rad io operation in several band s covered by the TRC105. the allowed transmitter power level (field strength) depends on the operating frequency and applic a tion. se e these doc u ments for details. the use of the TRC105 is supported by various radio regulations in almost eve ry geographic location in the world. please contact rfms local field application engineer for additional information. the relationship of the tra nsmitter power level to the integer value of txcfg1a bits 3..1 is given in t able 60 . there are eight available power settings (approximate) :
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 49 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 pattern of bits 3..1 transmi t ter power 000 13 dbm 001 10 dbm 010 7 dbm 011 4 dbm 100 1 dbm 101 - 2 dbm 110 - 5 dbm 111 - 8 dbm table 60 the highest power setting allowed under the governing radio regulations is usually chosen unless the application operates at short range and min i mum dc power consumption is critical. 6.3 determining configuration values for ook modulation 6.3.1 bit rate related ook configuration values the TRC105 supports rf bit rates (data rates) from 1.5625 to 33.33 kb/s for ook modulation. as with fsk mo d- ulation, there are several considerations in choosing an ook data rate. the sensiti vity of the TRC105 d e creases with increasing bit rate. a bit rate should be chosen that is adequate but not higher than the application requires. the exception to this rule is when the TRC105 is operated as a frequency hopping spread spectrum transceiver i n a noisy or crowded band. running at a higher bit rate will allow a higher channel hopping rate, which provides more robust operation in a crowded band in tradeoff for less range under quiet band conditions. the TRC105 rf bit rate is set by the value of the bytes loaded in mcfg03 and mcfg04 . for the standard cry s- tal frequency of 12.8 mhz: br = 12800/(2*(c+1)*(d + 1)), with c in the range of 0 to 255, and d = 31 (default value) where br is the bit rate in kb/s, f xtal the crystal frequency in khz, c the v alue in mcfg03 , and d is the value in mcfg04 . this bit rate value supports both the data and clock recovery circuit in the receiver and the bit rate clocking in the transmitter modulator. us ing the default value of d and solving the equ a tion above for c: c = (12800 - 64*br)/64*br c must be an integer value, so br is limited to 256 discrete values. if the value of c given in the above equation is not an integer for your desired bit rate, round the value of c down to the nearest integer. you can then calcul ate the nearest available bit rate equal to or greater than your desired bit rate. in ook mode, the second if frequency f if2 is normally set to 100 khz. the discussion in the rest of this section assumes f if2 is 100 khz. once br and f if2 has been determi ned, the bandwidths and related configuration values for the TRC105 filters can be determined. the recommended 3 db bandwidth for the transmitter anti - aliasing filters is: f ctx = 3*f if2 = 300 khz f ctx is configured with bits 7..4 in txcfg1a . for the stan dard crystal frequency of 12.8 mhz: f ctx = 200*(k + 1)/8 , with k in the range of 0 to 15 where f ctx is the 3 db bandwidth of the transmitter anti - aliasing filters in khz and k is the integer value of the bit pa t tern in txcfg1a bits 7..4 . t he equation for determining k is:
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 50 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 k = (f ctx - 25)/25 = 11 for f ctx = 300 khz for ook operation, the receiver filters are configured as polyphase band - pass filters by setting rxcfg12 bit 7 to 1. the center frequency of the polyphase filters is set to 100 khz to match th e second if frequency. the center frequency, f opp , is configured with bits 7..4 in rxcfg11 . for the standard crystal fr e quency of 12.8 mhz: f opp = 200*(l + 1)/8 , with l in the range of 0 to 15 where f opp is the center frequency of the ook polyphase filt er in khz, l is the integer value of the bit pattern in rxcfg11 bits 7..4 . t he equation for determining l is: l = (f opp - 25)/25 = 3 for f opp = 100 khz the recommended upper cutoff frequency for the receiver polyphase band - pass filters is: f cpp = f opp + br where f cpp is the upper cutoff frequency of the polyphase filters in khz and br is the bit rate in kb/s. this equ a- tion assumes use of the high accuracy, low drift xtl1020 p crystal. if an alternative crystal is used, add ? the e x- pected drift due to tem perature and aging to the equation above. f cpp is configured with bits 3..0 in rxcfg10 . for the standard crystal frequency of 12.8 mhz: f cpp = 100 + 200*(j + 1)/8 , with the usable range of j 0 to 1 where f cpp is the upper cutoff frequency of the receiver ook polyphase f ilter in khz and j is the integer value of the bit pattern in rxcfg10 bits 3..0. t he equation for determining j is: j = (f cpp - 125)/25 j must be an integer value, so f cpp is limited to 2 discrete values: 125 khz and 150 khz. choose the value of j that provides the f ccp value that is nearest to the value calculated for the bit rate you are using. the recommen d- ed 3 db bandwidth for the receiver r - c filters is: f crc = 3.25*f cpp where f crc and f cpp are in khz. the bandwidth of f crc is set by bits 7..4 in rxcfg10 . the relationship of the r - c filter bandwidth to the integer value in rxcfg10 bits 7..4 is given in t able 61 . the matching values for the 125 and 150 khz f ccp values are shown in bold : pattern of bits 7..4 r - c filter bandwidth 0 000 65 khz 0001 82 khz 0010 109 khz 0011 137 khz 0100 157 khz 0101 184 khz 0110 211 khz 0111 234 khz 1000 262 khz 1001 321 khz 1010 378 khz 1011 414 khz 1100 458 khz 1101 514 khz 1110 676 khz 1111 987 khz table 61
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 51 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 6.3 .2 ook demodulator re lated configuration values ook demodulation in the TRC105 is accomplished by comparing the rssi to a threshold value. an rssi value greater than the threshold is sliced to a logic 1, and an rssi value equal or less than the rssi value is sliced to a log ic 0. the TRC105 provides three threshold options - fixed threshold, average - referenced threshold, and peak - ref erenced threshold. mcfg01 bits 3..2 select the ook threshold as shown in table 62 : pattern of bits 3..2 threshold 00 fixed 01 peak referenced 10 average referenced 11 not used table 62 the configuration settings for each of these threshold options depend directly or indirectly on the bit rate. the fixed - threshold value is configured in mcfg 13 . the fixed threshold can be adjusted in 0.5 db i ncr e ments over a range of 128 db. also, the gain of the if can be adjusted over a range of 13.5 db to reduce the rssi value under no signal conditions. mcfg01 bits 1..0 sele ct the if gain as shown in t able 63 : pattern of bits 1..0 if gain 00 maximum 01 - 4.5 db 10 - 9.0 db 11 - 13.5 db table 63 the useable threshold setting depends on the rf operating band, the bandwidths of the receiver filters, the rf noise generated by host circuitry, the rf noise generated in the application environment, and the an tenna eff i- ciency. the fixed threshold is adjusted heuristically by incrementing the threshold while monitoring the data output pin with an oscilloscope. the threshold is adjusted upward under no signal conditions until noise spikes on the d a ta output are r educed to an average of one spike every five or more seconds. because the fixed threshold has no automatic adjustment capability, it should only be used in applications where incidental rf noise generators such as pcs, switchgear, etc., are not present. t he average - referenced threshold is generated by passing the rssi signa l through a low - pass filter. four cutoff fre quencies can be configured for this filt er with rxcfg15 bits 1..0 , as shown in table 64 b e low: pattern of bits 1..0 cutoff frequency 00 chip rate/ 32* 01 chip rate/ 8* 10 chip rate/ 4* 11 chip rate/ 2* table 64 the chip rate is equal to the bit rate except when manchester encoding is used. for manchester enco d ing, the chip rate is equal to twice the bit rate. an adequately long 1 - 0 - 1 - 0 preamble must be transmitted to center the average - referenced threshold . a preamble of at least 24 bits is recommended . the average - referenced thres h old should be used in conjunction with a mech a nism to avoid transmitting a long sequence of bits of the sam e value,
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 52 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 such as the TRC105 s data scrambling or manchester encoding options. the average - referenced threshold ru n- ning with a chip rate/ 2* cutoff frequency is a good choice for the majority of ook a p plications . the peak - referenced threshold is generated from the rssi signal using a fast attack, slow decay peak detector emulation. the slicer threshold is immediately set to 6 db below the peak value of the rssi signal anytime the rssi value exceeds the threshold by 6 db. the threshold then decays by a configurable db step when a config u- rable interval passes without the rssi signal peaking 6 db above the threshold. the decay step is configur ed with rxcfg15 bits 7..5 as shown in t able 65 : pattern of bits 7..5 decay step 000 0.5 db 001 1.0 db 010 1.5 db 011 2.0 db 100 3.0 db 101 4.0 db 110 5.0 db 111 6.0 db table 65 the decay interval is configured with rxcfg15 bits 4..2 as shown in t able 66 : pattern of bits 4..2 decay interval 000 once per chip 001 once per 2 chips 010 once per 4 chips 011 once per 8 chips 100 twice per chip 101 four times per chip 110 8 times per chip 111 16 times per chip table 66 the chip period t cp i s equal to the bit period except when manchester encoding is used. for manchester enco d- ing, the chip period is equal to ? the bit period: t cp = 1/br without manchester encoding, t cp = 1/(2*br) with manchester encoding where t cp is in ms and br is in kb/s . the default values of 0.5 db per decay step and 1 decay interval per chip provide a good starting point for most applications. for application environments that contain pulse noise, such as operation in a band where other fhss systems are operating, usin g manchester encoding and decreasing the decay interval to twice or four times per chip and/or increasing the decay step to 1 db will reduce the blinding effect of pulse noise. multipath flutter tolerance is also improved by using manchester encoding and decreasing the decay interval and/or increasing the decay step size. 6.3.3 ook transmitter related configuration values mcfg0 5 bits 7..6 allow the rise and fall time of the power amplifier regulator to be adjusted. using the default component values fo r r6 and c5 as shown in figure 2 , the rise and fall times for the power amplifier regulator and the o ok modulation are given in table 67 :
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 53 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 pattern of bits 4..3 regulator rise/fall times ook rise/fall time 00 3/3 s 2.5/2 s 01 8.5/8.5 s 5/3 s 10 15/1 5 s 10/6 s 11 23/23 s 20/10 s table 67 it is generally a good practice to set the ook rise and fall time to about 5% of a bit period to avoid excessive modulation bandwidth: t ook = 50/br where t ook is the nominal 5% ook rise/fall time in s and b r is the bit rate in kb/s. at low ook data rates the 20/10 s rise/fall times given in the table above are satisfactory. when operating in the 434 mhz band under etsi en300 220 - 1 regulations, check the modulation bandwidth carefully at bit rates above 8 kb /s to confirm compl i- ance. fo r operation in certain parts of the 434 mhz band , the required rise and fall time may be greater than 5%. 6.4 frequency synthesizer channel programming for fsk modulation when using a standard 12.8 mhz reference crystal, the f sk rf channel frequency is: f rf = 14.4*(75*(p + 1) + s)/(r + 1), with p and s in the r ange 0 to 255, r in the range 64 to 169 where f rf is in mhz, and p, s, and r are divi der integers with s less than ( p + 1) . there are two sets of three registers that h old the values of p, s and r: register divider parameter mcfg06 r1 mcfg07 p1 mcfg08 s1 mcfg09 r2 mcfg0a p2 mcfg0b s2 t able 68 mcfg05 bit 0 sel ects the register set to use with the frequency synthesizer. a 0 value selects register set mcfg06 - mcfg0 8 and a 1 value selects register set mcfg09 - mcfg0b . in addition, mcfg00 bits 4..2 select the vco o p erating band as follows: mcf g00 bits 4..2 band , mhz 000 300 - 330 00 1 330 - 365 01 0 365 - 400 011 400 - 440 100 440 - 470 101 470 - 510 table 69 the dual regis ter set allows a new frequency to be completely entered in one register set while operating on the other register set. it is important to load all three divider parameters into a register set before switching control to it. otherwise, a transient out - of - ba nd frequency shift can occur. the dual register set facilitates fhss operation, as the operating frequency for the next hop can be loaded anytime during the current hop interval, making this
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 54 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 programming task less time critical. the value s of p, s and r fo r fsk operation on several common frequenc ies are given in table 70 . software for determining p, s and r values for any in - band frequency is provided with the TRC105 development kit. configuration 315 mhz 434 mhz 447 mhz mcfg00 bits 4..2 000 01 1 100 p 34 42 58 s 0 30 45 r 119 107 143 table 70 6.5 frequency synthesizer channel programming for ook modulation when using a standard 12.8 mhz reference crystal the rf channel frequency for ook receive is: f txrf = (14.4*(75*(p + 1) + s)/(r + 1)) - f dev , with p, s in the rang e 0 to 255, r in the range of 64 to 169 where f txrf and transmitter deviation frequency f dev are in mhz, and p, s, and r are divider integ ers where s must be less than ( p +1) . an f dev value of 0.1 mhz is normally used, which must matc h the receiver low if fr e- quency f if2 . there are two sets of three registers that hold the values of p, s and r: register divider parameter mcfg06 r1 mcfg07 p1 mcfg08 s1 mcfg09 r2 mcfg0a p2 mcfg0b s2 t able 71 mcfg05 bit 0 selects the register set to use with the frequency synthesizer. a 0 value selects register set mcfg06 - mcfg08 and a 1 value selects register set mcfg09 - mcfg0b . in addition, mcfg00 bits 4..2 select the vco o p erating band as follows: mcfg00 bits 4..2 band, mhz 000 300 - 330 001 330 - 365 010 365 - 400 011 400 - 440 100 440 - 470 101 470 - 510 table 72 the dual register set allows a new frequency to be completely entered in one register set while operating on the other register set. it is important to load all three divider parameters in to a register set before switching control to it. otherwise, a transient out - of - band frequency shift can occur. the dual register set facilitates fhss operation, as the operating frequency for the next hop can be loaded anytime during the current hop inter val, making this progra mming task less time critical. the value s of p, s and r for ook receive operation on several common f r e- quencies are given in table 73 for a 0.1 mhz f if 2 . software for determining p, s and r values for any in - band fr e quency is provide d with the TRC105 development kit .
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 55 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 configuration 315 mhz 434 mhz 447 mhz mcfg00 bits 4..2 000 011 100 p 41 76 58 s 1 13 46 r 143 191 143 table 73 the rf channel frequency for ook transmit is: f rxrf = (14.4*(75*(p + 1) + s)/(r + 1)) - f if2 , with p, s in the range 0 to 255, r in the range of 64 to 169 where f rxrf and the ook 2 nd if frequency f if 2 are in mhz, and p, s, and r are divider integ ers where s must be less than ( p +1) , and r has a value in t he range of 64 to 169 . an f if 2 value of 0.1 mhz is normally used. the va l- ue s of p, s and r for ook transmit operation on several commo n f requencies are given in tab le 74 for a 0.1 mhz f if 2 . software for determining p, s and r values is provided with the TRC105 development kit. configuration 315 mhz 43 4 mhz 447 mhz mcfg00 bits 4..2 000 011 100 p 41 76 58 s 1 13 46 r 143 191 143 table 74 6.6 TRC105 data mode selection and configuration t he TRC105 suppo rts three data modes: continuous, buffered and p acket. continuous data mode provides the most formatting flexibility, but places the heaviest demand on host microcontroller resources and requires the most custom firmware development. in contrast, the p acket data mode unloads the host processor and the appl i- cation firmware from handing tasks such as dc - balanced data encoding, packet frame assembly and disasse m- bly, error detection, packet filtering and fifo buf fering. the trade - off for p acket data mode is limited flexibility i n data formatting parameters such as packet frame design. buffered data mode falls between packet and c ontin u- ous data mode capabilities, providing fifo buffering, but allowing conside rable flexibility in the design of the packet frame. packet data mode is generally preferred as it supports the fastest application development time and requires the smallest and least expensive host microcontroller. buffered data mode covers applications that require a specific packet frame design to support features such as multi - hop routing. continuous data mode is reserved for specia l- ized requirem ents, such as compatibility with a legacy product. mcfg01 bit s 7..6 select the data mode. a 00 bit pattern selects continuous data mode. a 01 bit pattern selects buffered da ta mode. bit patterns 10 or 11 s elect packet data mode. the TRC105 configuration d etails for each data mode are di s cussed below. 6.6.1 continuous data mode in c ontinuous data mode operation, transmitted data streams ar e applied to data pin 20, and received data streams are output on pin 20. irq1 pin 22 is usually configured to supply a clock signal to the host micro - contro l ler to pace the transmitted and received data steams. the clock signal is generated at the configured bit rate. when transmitting, bits are clocked into pin 20 on the low - to - hi gh clock transitions at pin 22.
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 56 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 receiv ed bits are valid (clocked out) on pin 20 on low - to - high clock transitions on pin 22. the clock signal is co n- trolled by rxcfg12 bit 6. setting this bit to 0 enables bit clocking and setting this bit to 1 disables bit clocking. clocking must be used for fsk transmissions. it is optional for ook transmissions. while clocking is optional for fsk and ook reception, enabling clocking provides additional bit stream filtering and regeneration, even if the clock signal is not used by the microcontroller. to effect ively use the data and clock recovery feature, data must be transmitted with a bit rate accuracy of better than 2%, and a 1 - 0 - 1 - 0 training preamble of at least 24 bits must be sent at the beginning of a transmission. when clocking is enabled, contin u- ous mode will optionally support the detection of a start - of - packet (start) pattern when receiving. the start pattern must be generated by the host microcontroller when transmitting. start pattern detection is enabled by setting rxcfg12 bit 5 to 1. the length of the start pattern is set by rxcfg12 bits 4..3 as follows: rxcfg12 bits 4..3 pattern length 00 8 bits 01 16 bits 10 24 bits 11 32 bits table 75 the number of allowed bit errors in the start pattern is configured by rxcfg12 bits 2..1 as follows: rxcfg12 bits 2..1 error tolerance 00 none 01 1 bit 10 2 bits 11 3 bits table 76 for most applications, a start pattern length of 24 to 32 bits is recommended with the error tolerance set to none. the start pattern is stored in registers syncfg16 thr ough syncfg19 . received bits flow through a shift register for pattern comparison with the most significant bit of syncfg16 compared to the earliest received bit and the least significant bit of the last register (selected by the pattern length) compared t o the last received bit. pattern detection is usually output on irq0, as discussed below. refer to figure 9 for pattern detection output timing. a well designed pattern should contain approximately the same number of 1 and 0 bits to achieve dc - balance, it should include frequent bit transitions, and it should be a pattern that is unlikely to occur in the encoded data fo l- lowing it. as shown in figure 19 , two interrupt (control) outputs, irq0 and irq1, are provided by the TRC105 to coordinate data flow to an d fro m the host microcontroller. in c ontinuous data mode, one of two signals can be mapped to irq0. this mapping is configured in register irqcfg0d . bits 7..6 select the signal for irq0 in the receive mode. the mapping options for c ontinuous data mode a re s ummarized in table 77 , where x denotes a dont care bit value. note th at irq1 always outputs dclk in c ontinuous data mode when clocking is enabled.
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 57 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 irqcfg0d bits cfg state irq source 7..6 00, 1x rx 0 start pattern detect 7..6 01 rx 0 rssi 3 x tx 0 n o signal (0) 5..4 xx rx 1 dclk 2 x tx 1 dclk table 77 the motivation for disab ling clocking when transmitting or receiving ook is that non - standard bit rates can be used. however, the host microcontroller must handle the dat a and clock recovery functi ons. when using contin u- ous mode with or without clocking enabled, data should be encoded to provide dc - balance (same number of 1 and 0 bits) and limited run lengths of the same bit value. manchester encoding, 8 - to - 12 bit symbolizing or scra m- bling must be a pplied to the data before transmitting and removed after receiving to achieve good rf transmi s- sion performance. the preamble, start pattern and error checking bits must also be generated by the host micr o- controller to establish robust data communications. 6.6.2 buffered data mode in b uffered data mode operation, the transmitted and received data bits pass thro ugh the spi port in groups of 8 bits to the internal TRC105 fifo. bits flow from the fifo to the modulator for transmission and are loaded into the fifo as data is received. as discussed in section s 3.10 and 3. 11 , the spi p ort can address the data fifo or the configuration registers. asserting a logic low on the nss_data input addresses the fifo, and asserting a logic low on the nss_config addresses t he configuration registers. if both of these input s are asserted, nss_config will override nss_data. the TRC105 acts as an spi slave and receives clocking from its host microcontroller. spi read/write details are provided in section s 3.10 and 3.11 . as show n in figure 19 , two inte r- rupt (control) outputs, irq0 and irq1, are provided by the TRC105 to coordinate spi data flow to and from the host microcontroller. on e to four signals can be selected or mapped to each interrupt output. this mapping is co n- figured in register irqcfg0d . bits 7..6 select the signal for irq0 in the receive mode , and bit 3 selects the irq0 signal in transmit mode. bits 5..4 select the signal for irq1 in the receive mode , and bit 2 selects the irq1 si g nal in transmit mode. the mapping op tions for b uffered d ata mode are summarized in table 78 : irqcfg0d bits cfg state irq source 7..6 00 rx 0 no signal (0) 7..6 01 rx 0 write_byte (high pulse when received byte written to fifo) 7..6 10 rx 0 nfifoempty 7..6 11 rx 0 start p attern detect 3 1 tx 0 fifo_int_tx 3 0 tx 0 nfifoempty 5..4 00 rx 1 no signal (0) 5..4 01 rx 1 fifofull 5..4 10 rx 1 rssi_irq 5..4 11 rx 1 fifo_int_rx 2 0 tx 1 fifofull 2 1 tx 1 tx_stop table 78
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 58 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 in addition, irqcfg0e allows several internal interrupts to be co nfigure d. see t able 79 b e low: irqcfg0e bits cfg internal interrupt control 7 0 start fifo fill when start pattern detected 7 1 control fifo with bit 6 6 0 stop filling fifo (if bit 7 is 0, this is start pattern detect) 6 1 start filling fifo 5 0 tran smitting all pending bits in fifo 5 1 all bits in fifo transmitted 4 0 fifo ok 4 1 fifo overflow (write 1 to reset fifo) 3 0 disable rssi interrupt (bit 2) 3 1 enable rssi interrupt (bit 2) 2 1 rf signal rssi threshold 2 0 rf signal < rssi threshold 1 1 pll not locked 1 0 pll locked 0 1 pll_lock signal disabled (bit 1 above), pin 23 set high 0 0 pll_ lock signal enabled table 79 mcfg0 c bits 7..6 set the length of the fifo as shown in table 8 0 : mc fg0c bits 7..6 fifo length 00 16 bytes 01 32 bytes 10 48 bytes 11 64 bytes table 8 0 the integer value of mcfg0 c bits 5..0 plus 1 sets the fifo interrupt threshold. when receiving in b uffered data mode, fifo_int_rx is triggered when the number of byt es in the fifo is equal to or greater than the threshold. the fifo threshold facilitates sending and receiving messages longer than the chosen fifo length, by signaling when additional bytes should be added to the fifo during a packet transmission and retr ieved from the fifo du r- ing a packet reception. two additional interrupts, nfifoemp y and fifofull provide signaling that a packet transmission is complete or a full packet has been received respectively. the following is a typical b uffered data mode operat ing scenario. there are many other ways to configure this very flexible data mode. 1. switch to standby mode by setting mcfg00 bits 7..5 to 001. 2. set the fifo to a suitable size for the application in mcfg0 c bits 7..6. 3. set the start pattern length in rxcfg1 2 bits 4..3. 4. load the start pattern in registers syncfg16 up through syncfg19 as required. 5. set irqcfg0e bit 7 to 0. in receive, the fifo will start filling when a start pattern is detected. 6. set irqcfg0d bit 7..6 to 01. in receive, irq0 will flag each ti me a byte is ready to be retrieved. 7. set irqcfg0d bit 5..4 to 00. irq1 signaling will not be required in receive mode.
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 59 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 8. in transmit mode, irq0 wi ll flag when the fifo is empty. 9. set irqcfg0d bit 3 to 1. irq1 will flag when the last bit starts to be transm itted . 10. load the operating frequency into register set mcfg06 - mcfg08 or mcfg09 - mcfg0b. 11. select the register set to use by setting mcfg0 5 bit 0. a 0 value selects register set mcfg06 - mcfg08 and a 1 value selects register set mcfg09 - mcfg0b . 12. when ready to tr ansmit, place the TRC105 in synthesizer mode by setting mcfg00 bits 7..5 to 010. mo n- itor the TRC105 pin 23 to confirm pll lock. 13. place TRC105 in transmit mode by setting mcfg00 bits 7..5 set to 100. 14. load the message in the fifo through the spi port. in b u ffered data mode, the transmitted message must include the 1 - 0 - 1 - 0 training preamble, the start pattern and the data. a length byte at the begi n- ning of the data or a designated end - of - message character is normally used to indicate message length. 15. monitor irq1. it sets when the when the last bit starts to be transmitted. allow one bit period for the last bit to be transmitted and then switch to standby mode by setting mcfg00 bits 7..5 to 001. 16. to prepare for receive mode, write a 1 to irqcfg0e bit 6. this arms the start pattern detection. 17. switch the TRC105 from standby mode to synthesizer mode by setting mcfg00 bits 7..5 set to 010. mo n itor the TRC105 pin 23 to confirm pll lock. 18. switch from synthesizer mode to receive mode by setting mcfg00 bits 7..5 to 0 11. 19. following a start pattern detection, the fifo will start filling. note that the preamble and start pattern are not loaded in the receive fifo. 20. as each data byte is loaded into the fifo, irq0 will pulse to alert the host microcont roller to retrieve th e byte. 21. the host microcontroller can use a countdown on the length byte or detection of the end - of - message byte to determine when all of the m essage data has been retrieved. 22. as soon as all the message has been retrieved, switch the TRC105 to standby mode by setting mcfg00 bits 7..5 to 001. 23. from standby mode, enter another transmit cycle as outlined in steps 12 through 15, or enter another r e- ceive cycle as outlined in steps 16 through 23 . it is possible to transmit messages longer than th e fifo in b uffer ed data mode by monitoring the nfifoemp y flag and immediately loading additional data bytes. however, messages sent by low power radios s uch as the tr103 are normally 127 bytes or less to reduce the chances of corruption due to noise, fading or interferenc e. 6.6.3 packet data mode the p acket da ta mode is built on top of the b uffered data mode, and adds a number of standard and optional fe a- tures: ? fixed or variable length packet options ? generation of preamble and start pattern (network id) in transmit mod e ? dc - balancing of data by scrambling (whitening) or manchester encoding ? generation of a 16 - bit error detection crc ? optional 1 - byte node address and/or 1 - byte length address
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 60 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 ? recognition of start pattern in receive mode ? automatic removal of preamble and start pattern in receive mode (payload only in fifo) ? flagging of received packets with errors or flagging and discard of packets with errors ? filtering of received packets based on address byte - address match only, address byte plus 0x00 broa d- cast addres s or address byte plus 0x00 and 0xff broadcast addresses ? new irq0 and irq1 mapping options the spi interface is used with packet data mode as with b uffered data mode. irq0 and irq1 mapping is confi g- ured in register irqcfg0d . bits 7..6 select the signal f or irq0 in the receive mode. in transmit mode, irq0 mapping is set by irqcfg0 d bit 3 . irqcfg0d bits 5..4 select the signal for irq1 in the receive mode. bit 3 s e- lects the irq1 signal in transmit mode. the mapping options for p acket data mode are summarized in t able 81 b e low : irqcfg0d bits cfg state irq source 7..6 00 rx 0 data_rdy (crc ok) 7..6 01 rx 0 write_byte (high pulse when received byte written to fifo) 7..6 10 rx 0 nfifoemp y (low when fifo is empty) 7..6 11 rx 0 start p attern detect or node a dd ress m atch 3 1 tx 0 fifo_int_tx 3 0 tx 0 nfifoemp y 5..4 00 rx 1 crc_ok 5..4 01 rx 1 fifofull 5..4 10 rx 1 rssi_irq 5..4 11 rx 1 fifo_int_rx 3 0 tx 1 fifofull 3 1 tx 1 tx_stop table 81 in addition, irqcfg0e allows several internal interrupts to b e configure d. see t able 82 b e low: irqcfg0e bits cfg internal interrupt control 7 0 start fifo fill when start pattern detected 7 1 control fifo with bit 6 6 0 stop filling fifo (if bit 7 is 0, this is start pattern detect) 6 1 start filling fifo 5 0 transmitting all pending bits in fifo 5 1 all bits in fifo transmitted 4 0 fifo ok 4 1 fifo overflow (write 1 to reset fifo) 3 0 disable rssi interrupt (bit 2) 3 1 enable rssi interrupt (bit 2) 2 1 rf signal rssi threshold 2 0 rf signal < rssi threshold 1 1 pll not locked 1 0 pll locked 0 1 pll_lock signal disabled (bit 1 above), pin 23 set high 0 0 pll_lock signal enabled table 82
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 61 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 mcfg0 c bits 7..6 set the leng th of the fifo as shown in t able 83 . the length of the fifo must be equal to or greater tha n the maximum payload length set in pktcfg1c , as discussed below. mcfg0c bits 7..6 fifo length 00 16 bytes 01 32 bytes 10 48 bytes 11 64 bytes table 8 3 the integer value of mcfg0 c bits 5..0 + 1 sets the fifo interrupt threshold. when receivi ng in p acket data mode, fifo_int_rx is triggered when the number of bytes in the fifo is equal to or greater than the threshold. fifo_int_tx is triggered when the number of bytes in the fifo is equal to or less th an the threshold value. two additional i nterrupts, nfifoemp y and fifofull provide signaling that a packet transmission is complete or a full packet has been received respectively. packet data mode formats are discussed in section 3.9. packet data mode opt ions are configured in re g isters pktcfg1c through pktcfg1f. setting pktcfg1c bit 7 to 1 selects manchester encoding/decoding. ma n- che s ter encoding provides excellent dc - balance and other characteristics that support robust communications, but effectively do ubles the number of bits needed to transmit the packet pa y load. scrambling provides adequate dc - balance in many applications without doubling the number of bits in the payload. it is not necessary to enable both manchester encoding and scrambling. pktcfg1c bits 6..0 configure the payload size (not including the preamble and start pattern) in fixed format and maximum allowed length byte value in variable length and exten d- ed var i able length formats. in a variable length format, a received packet with a length byte value greater than the maximum allowed is discarded. pktcfg1d bits 7..0 hold the node address byte used to identify a specific radio in a ne t work. pktcfg1d bits 7..0 hold the node address byte used to identify a specific radio in a network. pktcfg1 e bit 7 configures the basic pack et format. setting this bit to 0 selects the fixed - length f ormat, and setting this bit to 1 s e- lects the variable length format. pktcfg1e bits 6..5 set the preamble length: pktcfg1e bits 6..5 preamble length 00 1 byte 01 2 bytes 10 3 bytes 11 4 bytes table 84 for most applications a preamble length of three or four bytes is recommended. pktcfg1e bit 4 controls dc - balanced scrambling. setting this bit to 1 enables scrambling. pktcfg1e bit 3 con trols crc calculations. s etting his bit to 1 enables crc calculations. pktcfg1e bits 2..1 configure node address filtering: pktcfg1e bits 2..1 node address filtering 00 no filtering 01 only node address accepted 10 node address and 0x00 accepted 11 node address, 0x00 and 0xff accepted table 85
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 62 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 pktcfg1e bit 0 is the result of the last crc calculation. this bit is 1 when the crc ind icates no er rors. pktcfg1f bit 7 controls crc packet filtering. if this bit is set to 0, the fifo is cleared automatically if the crc calculation on a received packet indicates an error. if set to 1, the fifo data is preserved when the crc calcul a- tion shows an error. pktcfg1f bit 6 allows the fifo to be written to or read when the TRC105 is in standby mode. setting this bit to 0 allows the fifo to b e written and setting this bit to 1 allows it to be read. the following is a typical p acket data mode operating scenario. there are many other ways to configure this flex i- ble data mode. 1. switch to standby mode by setting mcfg00 bits 7..5 to 001. 2. set the fifo to a suitable size for the application in mcfg0 c bits 7..6. 3. in pktcfg1c set bit 7 to 0 to disable manchester encoding and set the value in bits 6..0 to match the fifo size - 1 . 4. load the chosen node address into pktcfg1d . 5. in pktcfg1e set bit 7 to 1 to for variable length packets. 6. set the preamble length in pktcfg1e bits 6..5. 7. set bit 4 in pktcfg1e to 1 to enable dc - balanced scrambling. 8. set bit s 2..1 in pktcfg1e to 10 to accept packets to this node address and 0x00 broadcasts. 9. set bit 3 in pktcfg1 e to 1 to enable crc calculations. 10. in pktcfg1f set bit 7 to 0 to enable fifo clear on crc error. 11. set the start pattern length in rxcfg12 bits 4..3. 12. load the start pattern in registers syncfg16 up through syncfg19 as required. 13. set irqcfg0e bit 7 to 0. i n receive, the fifo will start filling when a start pattern is detected. 14. set irqcfg0d bit 7..6 to 00. in receive, irq0 will flag that a packet has been received with a good crc calculation and is ready to retrieve. 15. set irqcfg0 d bit 3 to 1. in tra nsmit, i rq0 will clear to 0 when the fifo is empty (optional) . 16. set irqcfg0d bit 5..4 to 00. in receive, irq1 will signal the crc is ok (optional). 17. set irqcfg0d bit 3 to 1. irq1 will flag when the last bit starts to be transmitted . 18. load the operating frequency i nto register set mcfg06 - mcfg08 or mcfg09 - mcfg0b. 19. select the register set to use by setting mcfg0 5 bit 0. a 0 value selects register set mcfg06 - mcfg08 and a 1 value selects register set mcfg09 - mcfg0b . 20. when ready to transmit, set bit 6 to 0 in pktcfg1f to enable fifo write in standby mode. 21. load the fifo with the packet to be transmitted through the spi port. 22. place the TRC105 in synthesizer mode by setting mcfg00 bits 7..5 set to 010. monitor the TRC105 pin 23 to confirm pll lock. 23. place trc103 in transmit mode by setting mcfg00 bits 7..5 set to 100. monitor irq1. it sets when the when the last bit starts to be transmitted. allow one bit period for the last bit to be transmitted and then switch to standby mode by setting mcfg00 bits 7..5 to 001.
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 63 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 24. when ready to receive, place the TRC105 in synthesizer mode by setting mcfg00 bits 7..5 set to 010. monitor the TRC105 pin 23 to confirm pll lock. 25. switch from synthesizer mode to receive mode by setting mcfg00 bits 7..5 to 011. 26. monitor irq0. when an error free pac ket is received addressed to this node, irq0 will set. 27. switch the TRC105 to standby mode by setting mcfg00 bits 7..5 to 001. 28. set bit 6 to 1 in pktcfg1f to enable fifo read in standby mode. 29. retrieve the received data from the fifo through the spi port. 30. from standby mode, enter another transmit cycle as outlined in steps 20 through 23 , or enter another r e cei ve cycle as outlined in steps 24 through 30. 6.7 battery power management configuration values battery life can be greatly extended in TRC105 applic ations where transmissions from field nodes are infrequent, or network communications can be concentrated in to periodic time slots. for example, field nodes in many wir e- less alarm systems report operational status a few times a day, and can otherwise sleep unless an alarm cond i- tion occurs. sensor networks that monitor parameters that change relatively slowly, such as air and soil temper a- ture in agricultural settings, only need to transmit updates a few times an hour. at room temperature the TRC105 draws a maximum of 1 a in sleep mode, with a typical value of 100 na. to achieve min i mum sleep mode current, nss_config (pin 14), sdi (pin 17) and sck (pin 18) must be held logic low, while nss_data (pin 15) must be held logic high. also, the external connection to sdo (pin 16) must be configured as high impedance (tri - state or input). the TRC105 can go from sleep mode through standby mode and synthesizer mode to transmit (or receive) mode in less than 6 ms. at a data rate of 33.33 kb/s, a 32 byte packet with a 4 byte preamble and a 4 byte start pattern takes about 10 ms to transmit. assume that the TRC105 then switches to r e ceive mode for 1 second to listen for a response and returns to sleep. on the basis of reporting every six hours, the on to sleep duty cycle i s about 1:21,259, greatly extending battery life over continuous transmit - receive or even standby operation. rfm provides an excel spreadsheet, battery_ life_ calcul a tor.xls, in the application notes section of www.rfm.co m to support battery life for various o p erating scenarios. the required timing accuracy for the microcontrollers in a sleep - cycled application depends on several things: ? the required time - stamp accuracy of data reported by sleeping field nodes. r - c sl eep mode timers built into many microcontrollers have a tolerance of 20% or more. where more accurate time stamping is r e- quired, many microcontrollers can run on a watch crystal during sleep and achieve time stamp accuracies better than 1 second per 24 ho urs. ? if the base station and any routing nodes present in a network must sleep cycle in addition to the field nodes, watch crystal control will us ually be needed to keep all nodes accurately synchronized to the a c- tive time slots. ? if the base station and any routing nodes present in a network can operate continuously (ac powered, s o lar charged batteries, etc.) and a loose time stamp accuracy is ok, the microcontrollers in sleeping field nodes can usually operated from internal low - accuracy r - c timers. not e: the host microcontroller usually cannot be operated from the TRC105 buffered clock output if sleep c y- cling is planned. in sleep mode, the TRC105 buffered clock output is disabled, which will disable the microcontro l- ler unless it is capable of automatic ally switching to an internal clock source w hen external clocking is lost. TRC105 sleep related mode switching is configured in mcfg00 bits 7..5 as follows:
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 64 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 mcfg bits 7..5 operating mode 000 sleep mode - all oscillators off 001 standby - crystal oscil lator only on 010 synthesizer - crystal and pll on 011 receive mode 100 transmit mode table 86 when switching from sleep mode to standby, the crystal oscillator will be active in no more than 5 ms. switching from standby to synthesizer mode, the pll will lock in less than 0.5 ms. pll lock can be monitored on pin 23 of the TRC105 . the radio can then be switched to e ither transmit or receive mode. when switching from any other mode back to sleep, the TRC105 will drop to its sleep mode current in less th an 1 ms.
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 65 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 7.0 package dimensions and typical pcb footprint - qfn - 32 figure 25 dimension millimeters inches minimum nominal maximum minimum nominal maximum a 4.95 5.00 5.05 0.195 0.197 0.199 b 4.95 5.00 5.05 0.195 0.197 0.199 c 0.00 0.03 0.05 0. 000 0.001 0.002 d 0.70 0.75 0.80 0.028 0.030 0.031 e 3.50 0.138 f 0.50 0.020 g 0.20 0.25 0.30 0.008 0.010 0.012 h 3.50 0.138 i 0.30 0.40 0.50 0.012 0.016 0.020 j 3.00 3.10 3.20 0.118 0.122 0.126 k 3.00 3.10 3.20 0.118 0.122 0.126 l 5. 90 0.232 m 0.90 0.035 n 4.10 0.161 o 4.10 0.161 p 5.90 0.232 q 0.30 0.012 r 0.50 0.020 s 3.30 0.130 t 3.30 0.130 u 0.90 0.035 v 0.90 0.035 table 82
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 66 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 8.0 tape and reel dimensions figure 26 di mension mm inches minimum nominal maximum minimum nominal maximum a o 5.05 5.25 5.45 0.199 0.207 0.215 b o 5.05 5.25 5.45 0.199 0.207 0.215 d - 330.2 - - 13.0 - k o 1.0 1.1 1.2 0.039 0.043 0.047 p 7.9 8.0 8.1 0.311 0.315 0.319 t - 12.4 - - 0.488 - w 11.7 12.0 12.3 0.461 0.472 0.484 table 83 pin 1
www.rfm.com e - mail: info@rfm.com technical support +1.800.704.6079 page 67 of 67 ? 2009 - 201 3 by rf m onolithics, inc. TRC105 - 05 /29 /1 3 9.0 solder reflow profile TRC105 lead free ir reflow profile (mlp/tqfn package) figure 27 ventilator: off speed: 17 cm/min zones upper lower #1 #2 #3 #4 380 240 320 380 380 240 320 380 table 84 name - probe # max. temp. reached, t = 0 s to 449 s temp reached at time above 200 oc reached at , dur a tion time above 217 oc reached at , dur a tion time above 260 oc reached at , dur a tion max slope, t < 200 oc slope, reached at , dur a tion max slope, t < 200 oc slope, reached at , dur a tion 2749 - 3 - 1 curve 1 258 356.83 276.41 111.99 314.53 69.70 -- -- 5.00 3 8 1 - 11.00 409 1 max. slope, t = 200 o c t o 217 o c max. slope, t = 217 o c to 260 o c max. slope, t > 260 o c slope, reached at , dur a tion slope, reached at , dur a tion slope, reached at , dur a tion slope, reached at , dur a tion slope, reached at , dur a tion slope, reached at , dur a tion 1.50 315 2 - 5.00 387 1 1.50 315 2 - 5.00 379 1 -- -- -- - - -- -- table 85

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