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? semiconductor components industries, llc, 2015 may, 2015 ? rev. 1 1 publication order number: NCV4274C/d NCV4274C 400 ma low dropout voltage regulator description the NCV4274C is a precision micro?power voltage regulator with an output current capability of 400 ma available in the dpak and d2pak packages. the output voltage is accurate within 2.0% with a maximum dropout voltage of 0.5 v with an input up to 40 v. low quiescent current is a feature drawing only 125 a with a 1 ma load. this part is ideal for automotive and all battery operated microprocessor equipment. the regulator is protected against reverse battery, short circuit, and thermal overload conditions. the device can withstand load dump transients making it suitable for use in automotive environments. features ? 3.3 v, 5.0 v, 2.0% output options ? low 125 a quiescent current at 1 ma load current ? 400 ma output current capability ? fault protection ? +60 v peak transient voltage with respect to gnd ?42 v reverse voltage short circuit thermal overload ? very low dropout voltage ? aec?q100 grade 1 qualified and ppap capable ? these are pb?free devices marking diagrams dpak dt suffix case 369c see detailed ordering and shipping information on page 11 o f this data sheet. ordering information www. onsemi.com 74c?xxg alyww x xx = 33 (3.3 v) = 50 (5.0 v) a = assembly location l, wl = wafer lot y = year ww = work week g = pb?free package 4 1 2 3 1 input 2, 4 ground 3 output d2pak ds suffix case 418af nc v4274c?xx awlyywwg 1 input 2, 4 ground 3 output
NCV4274C www. onsemi.com 2 figure 1. block diagram ? + bandgap refernece thermal shutdown current limit and saturation sense gnd q i pin definitions and functions pin no. symbol function 1 i input; bypass directly at the ic a ceramic capacitor to gnd. 2,4 gnd ground 3 q output; bypass with a capacitor to gnd. absolute maximum ratings pin symbol, parameter symbol condition min max unit i , input?to?regulator voltage v i ?42 45 v current i i internally limited internally limited i , input peak transient voltage to regulator with respect to gnd (note 1) v i 60 v q, regulated output voltage v q v q = v i ?1.0 40 v current i q internally limited internally limited gnd, ground current i gnd ? 100 ma junction temperature storage temperature t j t stg ?40 ?50 150 150 c c esd capability, human body model (note 2) esd hb 4 kv esd capability, machine model (note 2) esd mm 200 v esd capability, charged device model (note 2) esd cdm 1 kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. load dump test b (with centralized load dump suppression) according to iso16750-2 standard. guaranteed by design. not tested in production. passed class c. 2. this device series incorporates esd protection and is tested by the following methods: esd hbm tested per aec?q100?002 (eia/jesd22?a114) esd mm tested per aec?q100?003 (eia/jesd22?a115) esd cdm tested per eia/jes d22/c101, field induced charge model
NCV4274C www. onsemi.com 3 operating range parameter symbol condition min max unit input voltage (5.0 v version) v i 5.5 40 v input voltage (3.3 v version) v i 4.5 40 v junction temperature t j ?40 150 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. thermal resistance parameter symbol condition min max unit junction?to?ambient dpak r thja ? 112.3 (note 3) c/w junction?to?ambient d2pak r thja ? 89.7 (note 3) c/w junction?to?case dpak r thjc ? 5.8 c/w junction?to?case d2pak r thjc ? 5.8 c/w 3. 1 oz copper, 100 mm 2 copper area, single?sided fr4 pcb. pb?free soldering tempera ture and msl parameter symbol condition min max unit pb?free soldering, (note 4) reflow (smd styles only), pb?free t sld 60s ? 150s above 217s 40s max at peak ? 265 pk c moisture sensitivity level msl dpak and d2pak 1 ? 4. per ipc/jedec j?std?020c
NCV4274C www. onsemi.com 4 electrical characteristics ?40 c < t j < 150 c; v i = 13.5 v unless otherwise noted. parameter symbol test conditions min typ max unit regulator output voltage (5.0 v version) v q 5 ma < i q < 400 ma 6 v < v i < 28 v 4.9 5.0 5.1 v output voltage (5.0 v version) v q 5 ma < i q < 200 ma 6 v < v i < 40 v 4.9 5.0 5.1 v output voltage (3.3 v version) v q 5 ma < i q < 400 ma 4.5 v < v i < 28 v 3.23 3.3 3.37 v output voltage (3.3 v version) v q 5 ma < i q < 200 ma 4.5 v < v i < 40 v 3.23 3.3 3.37 v current limit (all versions) i q v q = 90% v qtyp 400 600 ? ma quiescent current i q i q = 1 ma v q = 5.0 v v q = 3.3 v i q = 250 ma v q = 5.0 v v q = 3.3 v i q = 400 ma v q = 5.0 v v q = 3.3 v ? ? ? ? ? ? 125 125 5 5 10 10 250 250 15 15 35 35 a a ma ma ma ma dropout voltage 5.0 v version v dr i q = 250 ma, v dr = v i ? v q v i = 5.0 v ? 250 500 mv load regulation (3.3 v and 5 v versions) v q i q = 5 ma to 400 ma ? 3 20 mv line regulation (3.3 v and 5 v versions) v q v i = 12 v to 32 v i q = 5 ma ? 4 25 mv power supply ripple rejection p srr ?r = 100 hz, v r = 0.5 v pp ? 60 ? db thermal shutdown temperature* t sd i q = 5 ma 150 ? 210 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. *guaranteed by design, not tested in production figure 2. measuring circuit NCV4274C r load v q c q 10 f or 22 f c 12 100 nf c 11 1.0 f v q i q q i i i v i v i i gnd gnd 13 2,4 figure 3. application circuit output c q * c i 100 nf gnd NCV4274C 13 2,4 input v q v i *c q = 10 f for v q 3.3 v c q = 22 f for v q 5 v
NCV4274C www. onsemi.com 5 typical characteristic curves ? 5 v version i q , output current (ma) v i , input voltage (v) 400 300 200 100 0 100 50 30 10 ?10 ?30 ?50 1.6 esr ) c q = 22 f i i , input current (ma) r l = 6.8 k t j = 25 c v i , input voltage (v) 10 0 6 v q , output voltage (v) t j = 25 c r l = 20 figure 4. output stability with output capacitor esr t j , junction temperature ( c) i q , output current (ma) 160 120 80 40 0 ?40 5.1 400 350 300 100 50 0 400 v q , output voltage (v) v i = 13.5 v r l = 1 k v dr , dropout voltage (mv) v i , input voltage (v) 45 35 30 20 5 0 700 i q , output current (ma) t j = 25 c v q = 0 v figure 5. output voltage vs. junction temperature figure 6. output voltage vs. input voltage figure 7. dropout voltage vs. output current 40 figure 8. input current vs. input voltage figure 9. maximum output current vs. input voltage 10 1 0.1 0.01 unstable region stable region 5.05 5 4.95 4.9 8 6 4 2 5 4 3 2 1 0 t j = 125 c t j = 25 c 150 250 100 350 300 250 200 150 100 50 0 1.2 0.8 0.4 0 ?0.4 ?0.8 ?1.2 600 500 400 300 200 100 0 25 10 15
NCV4274C www. onsemi.com 6 typical characteristic curves ? 5 v version i q , output current (ma) 400 300 200 100 0 11 i q , output current (ma) 60 50 40 30 20 10 0 0.7 i q , quiescent current (ma) v i = 13.5 v t j = 25 c i q , quiescent current (ma) figure 10. quiescent current vs. output current (high load) figure 11. quiescent current vs. output current (low load) v i = 13.5 v t j = 25 c 10 9 8 7 6 5 4 3 2 1 0 450 350 250 150 50 0.6 0.5 0.4 0.3 0.2 0.1 0 v i , input voltage (v) 45 40 30 20 10 0 10 i q , quiescent current (ma) figure 12. quiescent current vs. input voltage t j = 25 c r l = 20 9 8 7 6 5 4 3 2 1 0 35 25 515
NCV4274C www. onsemi.com 7 typical characteristic curves ? 3.3 v version i q , output current (ma) v i , input voltage (v) 400 300 200 100 0 100 700 esr ) c q = 10 f i q , output current (ma) v i , input voltage (v) 10 0 v q , output voltage (v) t j = 25 c r l = 20 figure 13. output stability with output capacitor esr t j , junction temperature ( c) v i , input voltage (v) 160 120 80 40 0 ?40 3.36 1.4 v q , output voltage (v) v i = 13.5 v r l = 660 i i , input current (ma) v i , input voltage (v) 45 35 30 20 5 0 4 i q , quiescent current (ma) t j = 25 c v q = 0 v figure 14. output voltage vs. junction temperature figure 15. output voltage vs. input voltage figure 16. input current vs. input voltage 40 figure 17. maximum output current vs. input voltage figure 18. quiescent current vs. input voltage 10 1 0.1 0.01 unstable region stable region 8 6 4 2 4 3 2 1 0 25 10 15 3.34 3.32 3.3 3.28 3.26 3.24 50 30 10 ?10 ?30 ?50 1.2 1 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1 t j = 25 c r l = 3.3 k 45 35 30 20 5 040 25 10 15 600 500 400 300 200 100 0 t j = 25 c r l = 20 3.5 3 2.5 2 1.5 1 0.5 0
NCV4274C www. onsemi.com 8 typical characteristic curves ? 3.3 v version i q , output current (ma) 400 300 200 100 0 11 i q , output current (ma) 60 50 40 30 20 10 0 0.7 i q , quiescent current (ma) v i = 13.5 v t j = 25 c i q , quiescent current (ma) figure 19. quiescent current vs. output current (high load) figure 20. quiescent current vs. output current (low load) v i = 13.5 v t j = 25 c 10 9 8 7 6 5 4 3 2 1 0 450 350 250 150 50 0.6 0.5 0.4 0.3 0.2 0.1 0
NCV4274C www. onsemi.com 9 application description output regulator the output is controlled by a precision trimmed reference and error amplifier. the pnp output has saturation control for regulation while the input voltage is low , preventing over saturation. current limit and voltage monitors complement the regulator design to give safe operating signals to the processor and control circuits. stability considerations the input capacitor c i1 in figure 2 is necessary for compensating input line reactance. possible oscillations caused by input inductance and input capacitance can be damped by using a resistor of approximately 1 in series with c i2. the output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (?25 c to ?40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturer?s data sheet usually provides this information. the value for the output capacitor c q shown in figure 2 should work for most applications; however, it is not necessarily the optimized solution. actual stability regions are shown in a graphs in the typical performance characteristics section. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 3) is: p d(max) [v i(max) v q(min) ]i q(max) v i(max) i q (eq. 1) where: v i(max) is the maximum input voltage, v q(min) is the minimum output voltage, i q(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i q(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: p ja 150 c t a p d (eq. 2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heat sink will be required. the current flow and voltages are shown in the measurement circuit diagram. heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (eq. 3) where: r jc = the junction?to?case thermal resistance, r cs = the case?to?heat sink thermal resistance, and r sa = the heat sink?to?ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heat sink and the interface between them. these values appear in data sheets of heat sink manufacturers. thermal, mounting, and heat sinking are discussed in the on semiconductor application note an1040/d, available on the on semiconductor website .
NCV4274C www. onsemi.com 10 copper spreader area (mm 2 ) 700 300 200 0 180 r ja , thermal resistance ( c/w) figure 21. r ja vs. copper spreader area, dpak 3?lead 800 100 1 oz 2 oz 400 500 600 160 140 120 100 80 60 40 copper spreader area (mm 2 ) 700 300 200 0 130 r ja , thermal resistance ( c/w) figure 22. r ja vs. copper spreader area, d 2 pak 3?lead 800 100 1 oz 2 oz 400 500 600 120 100 90 70 80 60 30 110 50 40 0.1 1 10 100 1000 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 figure 23. single?pulse heating curves, dpak 3?lead pulse time (s) r(t) ( c/w) 1 oz cu area 100 mm 2 1 oz cu area 645 mm 2 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 figure 24. single?pulse heating curves, d 2 pak 3?lead pulse time (s) r(t) ( c/w) 1 oz cu area 100 mm 2 1 oz cu area 645 mm 2
NCV4274C www. onsemi.com 11 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 figure 25. duty cycle for 1 inch 2 (645 mm 2 ) spreader board, dpak 3?lead pulse time (s) r(t) ( c/w) 50% duty cycle 20% 10% 5% 2% single pulse 1% non?normalized response 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 figure 26. duty cycle for 1 inch 2 (645 mm 2 ) spreader board, d 2 pak 3?lead pulse time (s) r(t) ( c/w) 50% duty cycle 20% 10% 5% 2% single pulse 1% non?normalized response ordering information device output voltage accuracy output voltage package shipping ? NCV4274Cdt33rkg 2% 3.3 v dpak (pb?free) 2500 / tape & reel NCV4274Cds33r4g 2% 3.3 v d2pak (pb?free) 800 / tape & reel NCV4274Cdt50rkg 2% 5.0 v dpak (pb?free) 2500 / tape & reel NCV4274Cds50r4g 2% 5.0 v d2pak (pb?free) 800 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCV4274C www. onsemi.com 12 package dimensions d2pak case 418af issue d 5 ref 5 ref v u terminal 4 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inches. 3. tab contour optional within dimensions a and k. 4. dimensions u and v establish a minimum mounting surface for terminal 4. 5. dimensions a and b do not include mold flash or gate protrusions. mold flash and gate protrusions not to exceed 0.025 (0.635) maximum. 6. single gauge design will be shipped af- ter fpcn expiration in october 2011. dim a min max min max millimeters 0.386 0.403 9.804 10.236 inches b 0.356 0.368 9.042 9.347 c 0.170 0.180 4.318 4.572 d 0.026 0.036 0.660 0.914 e 0.045 0.055 1.143 1.397 f 0.051 ref 1.295 ref g 0.100 bsc 2.540 bsc h 0.539 0.579 13.691 14.707 j 0.125 max 3.175 max k 0.050 ref 1.270 ref l 0.000 0.010 0.000 0.254 m 0.088 0.102 2.235 2.591 n 0.018 0.026 0.457 0.660 p 0.058 0.078 1.473 1.981 r s 0.116 ref 2.946 ref u 0.200 min 5.080 min v 0.250 min 6.350 min a 12 3 k f b j s h d m 0.010 (0.254) t e optional chamfer bottom view optional constructions top view side view dual gauge bottom view l t p r detail c seating plane 3x g n m construction d c detail c e optional chamfer side view single gauge construction s c detail c t t d e 0.018 0.026 0.457 0.660 s *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 8.380 2.540 dimensions: millimeters pitch 3x 16.155 1.016 3x 10.490 3.504
NCV4274C www. onsemi.com 13 package dimensions dpak (single gauge) case 369c issue e b d e b3 l3 l4 b2 m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.028 0.045 0.72 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 7. optional mold feature. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.114 ref 2.90 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw e bottom view z bottom view side view top view alternate construction note 7 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCV4274C/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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