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56f8000 16-bit digital signal controllers freescale.com 56f8014 data sheet technical data mc56f8014 rev. 11 05/2008
56f8014 technical data, rev. 11 2 freescale semiconductor document revision history version history description of change rev 0 initial release rev 1 updates to part 10, specifications, table 10-1 , added maximum clamp current, per pin table 10-11 , clarified variation over temperature table and graph table 10-15 , added lin slave timing rev 2 added alternate pins to figure 11-1 and table 11-1 . rev 3 corrected bit selects in timer channel 3 input (tc3_inp) bit 9, section 6.3.1.7 , clarified section 1.4.1 , and simplified notes in table 10-9 , rev 4 added clarification on sync inputs in section 1.4.1 , added voltage difference specification to table 10-1 and table 10-4 , deleted formula for ambient operating temperature in table 10-4 , and a note for pin group 3, corrected table 8-1 , error in port c peripheral function configuration, updated notes in table 10-9 . added rohs and ?pb-free? language to back cover. rev 5 updates to section 10 table 10-5 , corrected max values for adc input current high and low; corrected typ value for pull-up disabled digital input current low (a) table 10-6 , corrected typ and added max values for standby > stop and powerdown modes table 10-7 , corrected min value for low-voltage interrupt for 3.3v table 10-11 , corrected typ and max values and units for pll lock time table 10-12 , corrected typ values for relaxation osci llator output frequency and variation over temperature (also increased temp range to 150 degreesc) and added variation over temperature from 0?105 degreesc updated figure 10-5 table 10-19 , updated max values for integral non-lin earity full input signal range, negative differential non-linearity, adc internal clock, offs et voltage internal ref, gain error and offset voltage external ref; updated typ values for negati ve differential non-linearity, offset voltage internal ref, gain error and offset voltage external ref; added new min values and corrected typ values for signal-to-noise ratio, total ha rmonic distortion, spurious free dynamic range, signal-to-noise plus distorti on, effective number of bits rev 6 added details to section 1. clarified language in state during reset column in table 2-3 ; corrected flash data retention temperature in table 10-4 ; moved input current high/low to table 10-19 and location of footnotes in table 10-5 ; reorganized table 10-19 ; clarified title of figure 10-1 . rev. 7 ? in table 10-4 , added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years). ?in table 10-6 , changed the device clock speed in stop mode from 8mhz to 4mhz. ?in table 10-12 , changed the typical relaxation oscill ator output frequency in standby mode from 400khz to 200khz. rev. 8 in table 10-19 , changed the maximum adc internal clock frequency from 8mhz to 5.33mhz.
56f8014 technical data, rev. 11 freescale semiconductor 3 rev. 9 added the following note to the description of the tms signal in table 2-3 : note: always tie the tms pin to v dd through a 2.2k resistor. rev. 10 ? in table 2-3 , changed v cap value from 4.7 f to 2.2 f. ?in table 2-3 , changed the input type for fault3 (was ?output?, is ?input?). ?in table 2-3 , changed the input type for fault2 (was ?input/output ?, is ?input?). ? revised section 7, security features . ? added mc56f8014mfae to section 13, ordering information . ? fixed miscellaneous errors. rev.11 ? updated temperat ure information in table 10-1 and table 10-4 . document revision history (continued) version history description of change please see http://www.freescale.com for the most current data sheet revision.
56f8014 technical data, rev. 11 4 freescale semiconductor 56f8014 block diagram program controller and hardware looping unit data alu 16 x 16 + 36 -> 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit 16-bit 56800e core interrupt controller 4 unified data / program ram 4kb pdb pdb xab1 xab2 xdb2 cdbr spi or i 2 c or timer or gpiob ipbus bridge (ipbb) system bus control r/w control memory pab pab cdbw cdbr cdbw jtag/eonce port or gpiod digital reg analog reg low-voltage supervisor v cap v dd v ss_io v dda v ssa 4 reset 5 timer or gpiob ad0 2 4 clock generator* system integration module p o r o s c pwm outputs pwm or timer port or gpioa *includes on-chip relaxation oscillator cop/ watchdog ad1 4 program memory 8k x 16 flash adc or gpioc sci or i 2 c or gpiob 2 2 ? up to 32 mips at 32mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? 16kb program flash ? 4kb unified data/program ram ? one 5-channel pwm module ? two 4-channel 12-bit adcs ? one serial communicatio n interface (sci) with lin slave functionality ? one serial peripheral interface (spi) ? one 16-bit quad timer ? one inter-integrated circuit (i 2 c) port ? computer operating properly (cop)/watchdog ? on-chip relaxation oscillator ? integrated power-on reset and low-voltag e interrupt module ? jtag/enhanced on-chip emulation (once?) for unobtrusive, real-time debugging ? up to 26 gpio lines ? 32-pin lqfp package 56f8014 general description
56f8014 technical data, rev. 11 freescale semiconductor 5 part 1: overview . . . . . . . . . . . . . . . . . . . . . . . 6 1.1. 56f8014 features . . . . . . . . . . . . . . . . . . . . 6 1.2. 56f8014 description. . . . . . . . . . . . . . . . . . . 8 1.3. award-winning development environment . 8 1.4. architecture block diagram . . . . . . . . . . . . . 9 1.5. synchronize adc with pwm . . . . . . . . . . . . 9 1.6. multiple frequency pwm output . . . . . . . . . 9 1.7. product documentation . . . . . . . . . . . . . . . 13 1.8. data sheet conventions. . . . . . . . . . . . . . . 13 part 2: signal/connection descriptions . . . 14 2.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2. 56f8014 signal pins . . . . . . . . . . . . . . . . . 18 part 3: occs . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1. overview. . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3. operating modes . . . . . . . . . . . . . . . . . . . . 26 3.4. block diagram . . . . . . . . . . . . . . . . . . . . . . 28 3.5. pin descriptions . . . . . . . . . . . . . . . . . . . . . 29 part 4: memory map . . . . . . . . . . . . . . . . . . . 29 4.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2. interrupt vector table . . . . . . . . . . . . . . . . . 29 4.3. program map . . . . . . . . . . . . . . . . . . . . . . . 31 4.4. data map . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.5. eonce memory map . . . . . . . . . . . . . . . . . 32 4.6. peripheral memory mapped registers . . . . 33 part 5: interrupt controller (itcn) . . . . . . . . 43 5.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3. functional description . . . . . . . . . . . . . . . . 43 5.4. block diagram . . . . . . . . . . . . . . . . . . . . . . 45 5.5. register descriptions . . . . . . . . . . . . . . . . . 45 5.6. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 part 6: system integration module (sim) . . 62 6.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3. register descriptions . . . . . . . . . . . . . . . . . 64 6.4. clock generation overview . . . . . . . . . . . . 77 6.5. power-down modes . . . . . . . . . . . . . . . . . . 77 6.6. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.7. clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.8. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 82 part 7: security features . . . . . . . . . . . . . . .82 7.1. operation with security enabled . . . . . . . . . 82 7.2. flash access lock and unlock mechanisms 83 7.3. product analysis. . . . . . . . . . . . . . . . . . . . . . 84 part 8: general purpose input/output (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 8.1. introduction. . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.2. configuration . . . . . . . . . . . . . . . . . . . . . . . . 84 8.3. reset values . . . . . . . . . . . . . . . . . . . . . . . . 86 part 9: joint test action group (jtag) . . .91 9.1. 56f8014 information . . . . . . . . . . . . . . . . . . 91 part 10: specifications . . . . . . . . . . . . . . . . .91 10.1. general characteristics . . . . . . . . . . . . . . . 91 10.2. dc electrical characteristics . . . . . . . . . . . 95 10.3. ac electrical characteristics . . . . . . . . . . . 97 10.4. flash memory characteristics . . . . . . . . . . 98 10.5. external clock operation timing . . . . . . . . 99 10.6. phase locked loop timing . . . . . . . . . . . . 99 10.7. relaxation oscillator timing. . . . . . . . . . . 100 10.8. reset, stop, wait, mode select, and interrupt timing . . . . . . . . . . . . . . 101 10.9. serial peripheral interface (spi) timing . . 102 10.10. quad timer timing. . . . . . . . . . . . . . . . . 105 10.11. serial communic ation interface (sci) timing . . . . . . . . . . . . . . . . . . . . . 107 10.12. inter-integrated circuit interface (i2c) timing . . . . . . . . . . . . . . . . . . . . . 108 10.13. jtag timing. . . . . . . . . . . . . . . . . . . . . . 109 10.14. analog-to-digital converter (adc) parameters . . . . . . . . . . . . . . . . . 111 10.15. equivalent circuit for adc inputs . . . . . . 112 10.16. power consumption . . . . . . . . . . . . . . . . 112 part 11: packaging . . . . . . . . . . . . . . . . . . .115 11.1. 56f8014 package and pin-out information . . . . . . . . . . . . . . . . . . 115 part 12: design considerations . . . . . . . . .118 12.1. thermal design considerations . . . . . . . . 118 12.2. electrical design considerations . . . . . . . 119 part 13: ordering information . . . . . . . . . .121 part 14: appendix . . . . . . . . . . . . . . . . . . . .122 56f8014 data sheet table of contents
56f8014 technical data, rev. 11 6 freescale semiconductor part 1 overview 1.1 56f8014 features 1.1.1 digital signal controller core ? efficient 16-bit 56800e family digital signal cont roller (dsc) engine with dual harvard architecture ? as many as 32 million instructions pe r second (mips) at 32mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? four 36-bit accumulators, including extension bits ? 32-bit arithmetic and logic multi-bit shifter ? parallel instruction set with unique dsp addressing modes ? hardware do and rep loops ? three internal address buses ? four internal data buses ? instruction set supports both dsp and controller functions ? controller-style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stac k with depth limited only by memory ? jtag/enhanced on-chip emulation (once) for unobtrusive, processor speed-independent, real-time debugging 1.1.2 memory ? dual harvard architecture permits as many as thre e simultaneous accesses to program and data memory ? flash security and protection that prevent unauthorized users from ga ining access to the internal flash ?on-chip memory ? 16kb of program flash ? 4kb of unified data/program ram ? eeprom emulation capability using flash 1.1.3 peripheral circuits for 56f8014 ? one multi-function five-output pu lse width modulator (pwm) module ? up to 96mhz pwm operating clock ? 15 bits of resolution ? center-aligned and edge-aligned pwm signal mode ? three programmable fault inputs wi th programmable digital filter ? double-buffered pwm registers
56f8014 features 56f8014 technical data, rev. 11 freescale semiconductor 7 ? each complementary pwm signal pair can output a different sw itching frequenc y by selecting pwm generation sources from: ? pwm generator ? external gpio ? internal timers ? adc conversion result of over/under limits: when conversion result is greater th an high limit, deactivate pwm signal when conversion result is less than low limit, activate pwm signal ? two independent 12-bit analog- to-digital converters (adcs) ? 2 x 4 channel inputs ? supports both simultaneous and sequential conversions ? adc conversions can be synchr onized by both pwm and timer modules ? sampling rate up to 2.67msps ? 8-word result buffer registers ? adc smart power management (auto-standby, auto-powerdown) ? one 16-bit multi-purpose quad timer module (tmr) ? up to 96mhz operating clock ? four independent 16-bit counter/t imers with cascading capability ? each timer has capture and compare capability ? up to 12 operating modes ? one serial communication interface (sci) with lin slave functionality ? full-duplex or single-wire operation ? two receiver wake-up methods: ? idle line ? address mark ? one serial peripheral interface (spi) ? full-duplex operation ? master and slave modes ? programmable length transacti ons (two to sixteen bits) ? one inter-integrated circuit (i 2 c) port ? operates up to 400 kbps ? supports both master and slave operation ? computer operating properly (cop )/watchdog timer capable of sel ecting different clock sources ? up to 26 general-purpose i/o (g pio) pins with 5v tolerance ? integrated power-on reset a nd low-voltage interrupt module ? phase lock loop (pll) provides a high-sp eed clock to the core and peripherals ? clock sources: ? on-chip relaxation oscillator
56f8014 technical data, rev. 11 8 freescale semiconductor ? external clock source ? on-chip regulators for digital and analog circuitry to lower cost and reduce noise ? jtag/eonce debug programming in terface for real-time debugging 1.1.4 energy information ? fabricated in high-density cmos with 5v -tolerant, ttl-compa tible digital inputs ? on-chip regulators for digital and analog circuitry to lower cost and reduce noise ? wait and stop modes available ? adc smart power management ? each peripheral can be indivi dually disabled to save power 1.2 56f8014 description the 56f8014 is a member of the 56800e core-based family of digital signal cont rollers (dscs). it combines, on a single chip, the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost, configuration flexibility, and comp act program code, the 56f8014 is we ll-suited for many applications. the 56f8014 includes many peripherals that are especially useful for industrial control, motion control, home appliances, general purpose inve rters, smart sensors, fire and security systems, switched-mode power supplies, power management, a nd medical monitori ng applications. the 56800e core is based on a dual harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per inst ruction cycle. the mcu-style programming model and optimized instru ction set allow straightforward ge neration of efficient, compact dsp and control code. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. the 56f8014 supports program executio n from internal memories. two data operands can be accessed from the on-chip data ram per in struction cycle. the 56f8014 also offers up to 26 general purpose input/output (gpio) lines, depe nding on peripheral configuration. the 56f8014 digital signal controll er includes 16kb of progra m flash and 4kb of unified data/program ram. program flash memory can be independently bulk erased or erased in pages. program flash page erase size is 512 bytes/256 words. a full set of programmable peri pherals?pwm, adcs, sci, spi, i 2 c, quad timer?support various applications. each pe ripheral can be independently shut down to save power. any pin in these peripherals can also be used as a genera l purpose input/outputs (gpio). 1.3 award-winning development environment processor expert tm (pe) provides a rapid application design (rad) tool that combines easy-to-use component-based software application cr eation with an expert knowledge system. the codewarrior integrated devel opment environment is a sophisti cated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms) , demonstration board kit and development system cards will s upport concurrent engin eering. together, pe, codewarrior and evms
architecture block diagram 56f8014 technical data, rev. 11 freescale semiconductor 9 create a complete, scalable tools solution for easy, fast, and efficient development. 1.4 architecture block diagram the 56f8014?s architecture is shown in figure 1-1 , figure 1-2 , and figure 1-3 . figure 1-1 illustrates how the 56800e system buses communi cate with internal me mories and the ipbus bridge, as well as showing the internal connections be tween each unit of the 56800e core. figure 1-2 shows the peripherals and control blocks connect ed to the ipbus bridge. figure 1-3 details how the device? s i/o pins are muxed. the figures do not show the on-board regulator and power a nd ground signals. they also do not show the multiplexing between peripherals or the dedicated gpios. please see part 2 signal/connection descriptions to see which signals are multiplexe d with those of other peripherals. 1.5 synchronize adc with pwm adc conversion can be synchronized with the pwm module via quad ti mer channel 2 and 3 if needed. internally, the pwm synch signal ? which is generate d at every pwm reload ?can be connected to the timer channel 3 input, and the time r channel 2 and channel 3 outputs are connected to the adc sync inputs. timer channel 3 output is connected to sync0 and timer channel 2 is connected to sync1. the setting is controlled by the tc3_inp bit in the sim control register; see section 6.3.1 . sync0 is the master adc sync i nput, used to trigger both adca and adcb in seque nce and parallel mode. sync1 is used to trigger ad cb in parallel independent mode, while sync0 is used to trigger adca. see mc56f8000rm , the 56f801x peripheral reference manual, for additional information. 1.6 multiple frequency pwm output when both pwm channels of a comple mentary pair in software contro l mode and software control bits are set to 1, each complementary pwm signal pair ? pwm 0 and 1; pwm 2 and 3; and pwm 4 and 5 ? can select a pwm source fr om one of the following sources. this will enable each pwm pair and pwm2 to output pwm signals at different frequencies. ? external gpio input: ? gpiob2 input can be used to drive pwm 0 and 1 ? gpiob3 input can be used to drive pwm 2 ? gpiob4 input can be used to drive pwm 4 and 5 ? quad timer output: ? timer0 output can be used to drive pwm 0 and 1 ? timer2 output can be used to drive pwm 2 ? timer3 output can be used to drive pwm 4 and 5 ? adc conversion result: ? signal of over/under limit of adc sample 0 can be used to drive pwm 0 and 1 ? signal of over/under limit of adc samp le 1 can be used to drive pwm 2
56f8014 technical data, rev. 11 10 freescale semiconductor ? signal of over/under limit of adc sample 2 can be used to drive pwm 4 and 5 figure 1-1 56800e core block diagram data dsp56800e core arithmetic logic unit (alu) xab2 pab pdb cdbw cdbr xdb2 program memory data / ipbus interface bit- manipulation unit n3 m01 address xab1 generation unit (agu) pc la la2 hws0 hws1 fira omr sr fisr lc lc2 instruction decoder interrupt unit looping unit program control unit alu1 alu2 mac and alu a1 a2 a0 b1 b2 b0 c1 c2 c0 d1 d2 d0 y1 y0 x0 enhanced jtag tap r2 r3 r4 r5 sp r0 r1 n y multi-bit shifter once? program ram
multiple frequency pwm output 56f8014 technical data, rev. 11 freescale semiconductor 11 figure 1-2 peripheral subsystem ipbus gpio a interrupt controller to/from ipbus bridge gpio b gpio c clkgen (rosc / pll / clkin) por & lvi sim gpio d low-voltage interrupt system por cop reset reset / gpioa7 cop gpioa n gpiob n gpioc n gpiod n (continues on figure 1-3 ) 8 8 6 4
56f8014 technical data, rev. 11 12 freescale semiconductor figure 1-3 56f8014 peripheral i/o pin-out to/from ipbus bridge 3 to pwm sync0, sync1 over/under limits adc ana0, 1, 3 ana2 v refh , v refl anb2 anb0, 1, 3 ipbus 3 2 v refh , v refl ana2 anb2 ana0, 1, 3 3 spi i 2 c sci 2 t2o, t3o t3i t2/3 t1 t0 timer pwm pwm0 - 3 fault3 fault0 fault1, 2 pwm4, 5 pwm4, 5 pwm0 - 3 fault1, 2 fault0 fault3 t2, 3 2 3 from adc i 2 c is muxed with both spi and sci. t2 and t3 are muxed with spi and pwm. t1 t0 clko txd, rxd 2 2 2 2 t2, 3 anb0, 1, 3 gpioa0 - 3 gpioa4 - 5 gpioa6 gpiob5 gpiob4 gpiob6 - 7 gpiob0 - 1 gpiob2 - 3 gpioc0, 1, 3 gpioc2, 6 gpioc4, 5, 7 sda, scl sclk, ss miso, mosi 4 2 2 output controls 2 2 2 (continued from figure 1-2 ) reload pulse
product documentation 56f8014 technical data, rev. 11 freescale semiconductor 13 1.7 product documentation the documents listed in table 1-1 are required for a complete description and proper design with the 56f8014. documentation is available from local freescale distributors, freescale se miconductor sales offices, freescale literature distribut ion centers, or online at: http://www.freescale.com table 1-1 56f8014 chip documentation 1.8 data sheet conventions this data sheet uses the following conventions: topic description order number dsp56800e reference manual detailed description of the 56800e family architecture, 16-bit digital signal controller core processor, and the instruction set dsp56800erm 56f801x peripheral reference manual detailed description of peripherals of the 56f801x family of devices mc56f8000rm 56f801x serial bootloader user guide detailed description of the serial bootloader in the 56f801x family of devices 56f801xblug 56f8014 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) mc56f8014 56f8014 errata details any chip issues that might be present MC56F8014E overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. ?asserted? a high true (active high) signal is hi gh or a low true (active low) signal is low. ?deasserted? a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for v il , v ol , v ih , and v oh are defined by individual product specifications. pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
56f8014 technical data, rev. 11 14 freescale semiconductor part 2 signal/connection descriptions 2.1 introduction the input and output signals of the 56f8014 are orga nized into functional groups, as detailed in table 2-1 . table 2-2 summarizes all device pins. in table 2-2 , each table row describes the signal or signals present on a pin, sorted by pin number. table 2-1 functional gr oup pin allocations functional group number of pins power (v dd or v dda )2 ground (v ss or v ssa )3 supply capacitors 1 reset 1 pulse width modulator (pwm) ports 1 1. pins in this section can function as tmr and gpio. 5 serial peripheral interface (spi) ports 2 2. pins in this section can function as tmr, i 2 c, and gpio. 4 analog-to-digital converter (adc) ports 8 timer module ports 3 3. pins can function as pwm and gpio. 2 serial communications interface (sci) ports 4 4. pins in this section can function as i 2 c and gpio. 2 jtag/enhanced on-chip emulation (eonce) 4
introduction 56f8014 technical data, rev. 11 freescale semiconductor 15 table 2-2 56f8014 pins peripherals: lqfp pin # pin name signal name gpio i2c sci spi adc pwm quad timer power & ground jtag misc. 1 gpiob1 gpiob1, ss , sda b1 sda ss 2 gpiob7 gpiob7, txd, scl b7 scl txd 3 gpiob5 gpiob5, t1, fault3 b5 fault3 t1 4 anb0 anb0, gpioc4 c4 anb0 5 anb1 anb1, gpioc5 c5 anb1 6 anb2 anb2, v refl , gpioc6 c6 anb2, v refl 7 anb3 anb3, gpioc7 c7 anb3 8 vdda v dda v dda 9 vssa v ssa v ssa 10 ana3 ana3, gpioc3 c3 ana3 11 ana2 ana2, v refh , gpioc2 c2 ana2, v refh 12 ana1 ana1, gpioc1 c1 ana1 13 ana0 ana0, gpioc0 c0 ana0 14 vss_io v ss_io v ss_io 15 tck tck, gpiod2 d2 tck 16 reset reset , gpioa7 a7 reset 17 gpiob3 gpiob3, mosi, t3 b3 mosi t3 18 gpiob2 gpiob2, miso, t2 b2 miso t2 19 gpiob4 gpiob4, t0, clko b4 t0 clko 20 gpioa5 gpioa5, pwm5, fault2, t3 a5 pwm5, fault2 t3 21 gpiob0 gpiob0, sclk, scl b0 scl sclk 22 gpioa4 gpioa4, pwm4, fault1, t2 a4 pwm4, fault1 t2 23 gpioa2 gpioa2, pwm2 a2 pwm2 24 vcap v cap v cap
56f8014 technical data, rev. 11 16 freescale semiconductor 25 vdd_io v dd_io v dd_io 26 vss_io v ss_io v ss_io 27 gpioa1 gpioa1, pwm1 a1 pwm1 28 gpioa0 gpioa0, pwm0 a0 pwm0 29 tdi tdi, gpiod0 d0 tdi 30 tms tms, gpiod3 d3 tms 31 tdo tdo, gpiod1 d1 tdo 32 gpiob6 gpiob6, rxd, sda, clkin b6 sda rxd clkin table 2-2 56f8014 pins (continued) peripherals: lqfp pin # pin name signal name gpio i2c sci spi adc pwm quad timer power & ground jtag misc.
introduction 56f8014 technical data, rev. 11 freescale semiconductor 17 figure 2-1 56f8014 signals identified by functiona l group (32-pin lqfp) v dd_io v dda v ssa gpiob6 (rxd, sda, clkin) gpiob7 (txd, scl) other supply ports sci port or i 2 c port or gpio jtag/ eonce port or gpio 1 1 2 v cap 1 1 1 tck (gpiod2) tms (gpiod3) gpioa4 (pwm4, fault1, t2) ana0 - 1 (gpioc0 - 1) 1 1 1 2 1 56f8014 1 tdi (gpiod0) tdo (gpiod1) gpiob0 (sclk, scl) gpiob1 (ss , sda) gpiob2 (miso, t2) gpiob3 (mosi, t3) anb0 - 1 (gpioc4 - 5) anb2 (v refl , gpioc6) 1 1 1 1 1 1 1 2 ana2 (v refh , gpioc2) 1 v ss_io power ground power ground gpioa0 - 2 (pwm0 - 2) 3 gpioa5 (pwm5, fault2, t3) 1 reset reset (gpioa7) 1 gpiob4 (t0, clko) gpiob5 (t1, fault3) timer port or gpio 1 1 adc port or gpio spi port or i 2 c port or timer port or gpio pwm port or timer port or gpio ana3 (gpioc3) 1 anb3 (gpioc7) 1
56f8014 technical data, rev. 11 18 freescale semiconductor 2.2 56f8014 signal pins after reset, each pin is configured for its primary function (listed first). any alternate functionality must be programmed. table 2-3 56f8014 signal and package information for the 32-pin lqfp signal name lqfp pin no. type state during reset signal description v dd_io 25 supply supply i/o power ? this pin supplies 3.3v power to the chip i/o interface. v ss_io 14 supply supply v ss ? these pins provide ground fo r chip logic and i/o drivers. v ss_io 26 v dda 8 supply supply adc power ? this pin supplies 3.3v power to the adc modules. it must be connected to a clean analog power supply. v ssa 9 supply supply adc analog ground ? this pin supplies an analog ground to the adc modules. v cap 24 supply supply v cap ? connect a 2.2 f or greater bypass capacitor between this pin and vss_io, which is required by the internal voltage regulator for proper chip operation. see section 10.2.1 . gpiob6 (rxd) (sda 1 ) (clkin) 32 input/ output input input/ output input input with internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. receive data ? sci receive data input. serial data ? this pin serves as the i 2 c serial data line. clock input ? this pin serves as an optional external clock input. after reset, the default state is gpiob6. the alternative peripheral functionality is controlled via the sim (see section 6.3.8 ) and the clkmode bit of the occs o scillator control register. 1. this signal is also brought out on the gpiob1 pin. return to table 2-2
56f8014 signal pins 56f8014 technical data, rev. 11 freescale semiconductor 19 gpiob7 (txd) (scl 2 ) 2 input/ output input/ output input/ output input with internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. transmit data ? sci transmit data output or transmit / receive in single wire opeation. serial clock ? this pin serves as the i 2 c serial clock. after reset, the default state is gpiob7. the alternative peripheral functionality is controlled via the sim. see section 6.3.8 . 2. this signal is also brought out on the gpiob0 pin. reset (gpioa7) 16 input input/open drain output input with internal pull-up enabled reset ? this input is a direct hardware reset on the processor. when reset is asserted low, the chip is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. the internal reset signal will be deasserted synchronous with the internal clocks after a fixed numbe r of internal clocks. port a gpio ? this gpio pin can be individually programmed as an input or open dr ain output pin. note that reset functionality is disabled in this mode and the chip can only be reset via por, cop reset, or software reset. after reset, the default state is reset . gpiob4 (t0) (clko) 19 input/ output input/ output output input with internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. t0 ? timer, channel 0 clock output ? this is a buffered clock signal. using the sim_clko select register (sim_clkosr), this pin can be programmed as any of the following: disabled (logic 0), clk_mstr (system clock), ipbus clock, or oscillator output. see section 6.3.7 . after reset, the default state is gpiob4. the alternative peripheral functionality is controlled via the sim. see section 6.3.8 . return to table 2-2 table 2-3 56f8014 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8014 technical data, rev. 11 20 freescale semiconductor gpiob5 (t1) (fault3) 3 input/ output input/ output input input with internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. t1 ? timer, channel 1 fault3 ? this fault input pin is used for disabling selected pwm outputs in cases where fault conditions originate off-chip. after reset, the default state is gpiob5. the alternative peripheral functionality is controlled via the sim. see section 6.3.8 . tck (gpiod2) 15 input input/ output input with internal pull-up enabled test clock input ? this input pin provides a gated clock to synchronize the test logic and shift serial data to the jtag/eonce port. the pin is connected internally to a pull-up resistor. a schmitt trigger input is used for noise immunity. port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tck. tms (gpiod3) 30 input input/ output input with internal pull-up enabled test mode select input ? this input pin is used to sequence the jtag tap controller?s state machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tms. note: always tie the tms pin to v dd through a 2.2k resistor if this pin is configured as tms. tdi (gpiod0) 29 input input/ output input with internal pull-up enabled test data input ? this input pin provides a serial input data stream to the jtag/eonce port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tdi. return to table 2-2 table 2-3 56f8014 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8014 signal pins 56f8014 technical data, rev. 11 freescale semiconductor 21 tdo (gpiod1) 31 output input/ output output test data output ? this tri-stateable output pin provides a serial output data stream from the jtag/eonce port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tdo. gpiob0 (sclk) (scl 3 ) 21 input/ output input/ output input/ output input with internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. spi serial clock ? in the master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. a schmitt trigger input is used for noise immunity. serial data ? this pin serves as the i 2 c serial clock. after reset, the default state is gpiob0. the alternative peripheral functionality is controlled via the sim. see section 6.3.8 . 3. this signal is also brought out on the gpiob7 pin. gpiob1 (ss ) (sda 4 ) 1 input/ output input input/ output input with internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. spi slave select ? ss is used in slave mode to indicate to the spi module that the current transfer is to be received. serial clock ? this pin serves as the i 2 c serial data line. after reset, the default state is gpiob1. the alternative peripheral functionality is controlled via the sim. see section 6.3.8 . 4. this signal is also brought out on the gpiob6 pin. return to table 2-2 table 2-3 56f8014 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8014 technical data, rev. 11 22 freescale semiconductor gpiob2 (miso) (t2 5 ) 18 input/ output input/ output input/ output input with internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. spi master in/slave out ? this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high-im pedance state if the slave device is not selected. the slave device places data on the miso line a half-cycle before the cloc k edge the master device uses to latch the data. t2 ? timer, channel 2 after reset, the default state is gpiob2. the alternative peripheral functionality is controlled via the sim. see section 6.3.8 . 5. this signal is also brought out on the gpioa4 pin. gpiob3 (mosi) (t3 6 ) 17 input/ output input/ output input/ output input with internal pull-up enabled port b gpio ? this gpio pin can be individually programmed as an input or output pin. spi master out/slave in ? this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before t he clock edge the slave device uses to latch the data. t3 ? timer, channel 3 after reset, the default state is gpiob3. the alternative peripheral functionality is controlled via the sim. see section 6.3.8 . 6. this signal is also brought out on the gpioa5 pin. gpioa0 (pwm0) 28 input/ output output input with internal pull-up enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm0 ? this is one of the six pwm output pins. after reset, the default state is gpioa0. return to table 2-2 table 2-3 56f8014 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8014 signal pins 56f8014 technical data, rev. 11 freescale semiconductor 23 gpioa1 (pwm1) 27 input/ output output input with internal pull-up enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm1 ? this is one of the six pwm output pins. after reset, the default state is gpioa1. gpioa2 (pwm2) 23 input/ output output input with internal pull-up enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm2 ? this is one of the six pwm output pins. after reset, the default state is gpioa2. gpioa4 (pwm4) (fault1) (t2 7 ) 22 input/ output output input input/ output input with internal pull-up enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm4 ? this is one of the six pwm output pins. fault1 ? this fault input pin is used for disabling selected pwm outputs in cases where fault conditions originate off-chip. t2 ? timer, channel 2 after reset, the default state is gpioa4. the alternative peripheral functionality is controlled via the sim. see section 6.3.8 . 7. this signal is also brought out on the gpiob2 pin. gpioa5 (pwm5) (fault2) (t3 8 ) 20 input/ output output input input/ output input with internal pull-up enabled port a gpio ? this gpio pin can be individually programmed as an input or output pin. pwm5 ? this is one of the six pwm output pins. fault2 ? this fault input pin is used for disabling selected pwm outputs in cases where fault conditions originate off-chip. t3 ? timer, channel 3 after reset, the default state is gpioa5. the alternative peripheral functionality is controlled via the sim. see section 6.3.8 . 8. this signal is also brought out on the gpiob3 pin. return to table 2-2 table 2-3 56f8014 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8014 technical data, rev. 11 24 freescale semiconductor ana0 (gpioc0) 13 input input/ output analog input ana0 ? analog input to adc a, channel 0 port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is ana0. ana1 (gpioc1) 12 input input/ output analog input ana1 ? analog input to adc a, channel 1 port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is ana1. ana2 (v refh ) (gpioc2) 11 input input input/ output analog input ana2 ? analog input to adc a, channel 2 v refh ? analog reference voltage high port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is ana2. ana3 (gpioc3) 10 input input/ output analog input ana3 ? analog input to adc a, channel 3 port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is ana3. anb0 (gpioc4) 4 input input/ output analog input anb0 ? analog input to adc b, channel 0 port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is anb0. return to table 2-2 table 2-3 56f8014 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8014 signal pins 56f8014 technical data, rev. 11 freescale semiconductor 25 anb1 (gpioc5) 5 input input/ output analog input anb1 ? analog input to adc b, channel 1 port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is anb1. anb2 (v refl ) (gpioc6) 6 input input input/ output analog input anb2 ? analog input to adc b, channel 2 v refl ? analog reference voltage low. this should normally be connected to a low-noise v ss . port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is anb2. anb3 (gpioc7) 7 input input/ output analog input anb3 ? analog input to adc b, channel 3 port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is anb3. return to table 2-2 table 2-3 56f8014 signal and package information for th e 32-pin lqfp (continued) signal name lqfp pin no. type state during reset signal description
56f8014 technical data, rev. 11 26 freescale semiconductor part 3 occs 3.1 overview this module provides the system clock, which uses it to generate the va rious chip clocks. this module also produces the oscillator clock signals, plus the adc clock and high-speed peripheral clock. the on-chip clock synthesis module al lows product design using an intern al relaxation oscillator to run 56f801x family parts at user-sel ectable frequencies up to 32mhz. 3.2 features the on-chip clock synthesis (occs) module interfaces to the oscill ator and pll. the occs module features: ? internal relaxation oscillator ? ability to power down the in ternal relaxation oscillator ? ability to put the internal relaxa tion oscillator into a standby mode ? 3-bit postscaler provides control for the pll output ? ability to power down the internal pll ? provides 2x system clock frequency, which operates at twice the system clock, to the system integration module (sim) that is used to generate the various device clocks ? provides 3x system clock, which operates at three times the system clock, to pwm and timer ? safety shutdown feature is available in th e event that the pll reference clock disappears ? can be driven from an external clock source the clock generation module provides the programming in terface for both the pll and internal relaxation oscillator. 3.3 operating modes in 56f801x family parts, ei ther an internal oscillator or an ex ternal frequency sour ce can be used to provide a reference clock to the sim. the 2x system clock source output from the occs ca n be described by one of the following equations: 2x system frequency = oscillator frequency 2x system frequency = (oscillato r frequency x 8) / (postscaler) where: postscaler = 1, 2, 4, 8, 16, or 32 pll output divider the sim is responsible for further dividing these frequencies by two, wh ich will insure a 50% duty cycle in the system clock output.
operating modes 56f8014 technical data, rev. 11 freescale semiconductor 27 the 56f801x family parts? on-chip clock s ynthesis module has the following registers: ? control register (occs_cr) ? divide-by register (occs_db) ? status register (occs_sr) ? shutdown register (occs_shutdn) ? oscillator control register (occs_octrl) for more information on these registers, please refer to the 56f801x peripheral reference manual. 3.3.1 external clock source the recommended method of connecting an external cl ock is illustrated in figure 3-1 . the external clock source is connected to gpiob6 / rxd / sda / clkin. figure 3-1 connecting an exte rnal clock signal using gp iob6 / rxd / sda / clkin 56f8014 gpiob6/rxd/sda/clkin external clock
56f8014 technical data, rev. 11 28 freescale semiconductor 3.4 block diagram figure 3-2 provides a block diagram which shows how the 56f8014 creates it s internal clock, using the relaxation oscillator as an 8m hz clock reference for the pll. figure 3-2 occs block diagra m with relaxat ion oscillator trim[9:0] rosb ropd relaxation osc bus interface and control bus interface gpiob6 / rxd precs mux mux mux mstr_osc sys_clk_x2 source to the sim (64mhz max) zsrc hs perf clk (96mhz max) postscaler ( 1, 2, 4, 8, 16, 32) postscaler ( 1, 2, 4, 8, 16, 32) 3 2 pll x 24 lock detector loss of reference clock detector loss of referenc e clock interrupt lck f out /2 feedback pllcod fout
pin descriptions 56f8014 technical data, rev. 11 freescale semiconductor 29 3.5 pin descriptions 3.5.1 external reference (g piob6 / rxd / sda / clkin) after reset, the internal re laxation oscillator is select ed as the clock source for the chip. the user then has the option of switching to an external clock reference by enabling the precs bit in the occs oscillator control register, if desired. part 4 memory map 4.1 introduction the 56f8014 device is a 16-bit motor-control chip ba sed on the 56800e core. it uses a harvard-style architecture with two independent memory spaces for data and program. on-chip ram is used in both spaces and flash memory is used only in program space. this section provides memory maps for: ? program address space, including the interrupt vector table ? data address space, including the eonce memory and peripheral memory maps on-chip memory sizes for the device are summarized in table 4-1 . flash memories? restrictions are identified in the ?use restrictions? column of table 4-1 . 4.2 interrupt vector table table 4-2 provides the 56f8014?s reset and inte rrupt priority structure, in cluding on-chip peripherals. the table is organized with hi gher-priority vectors at the top and lowe r-priority interrupts lower in the table. as indicated, the priority of an in terrupt can be assigned to different levels, allo wing some control over interrupt priorities. all le vel 3 interrupts will be serviced before level 2, and so on. for a selected priority level, the lowest vector num ber has the highest priority. the location of the vector table is determined by the vector base addr ess (vba). please see section 5.5.6 for the reset value of the vba. by default, the chip reset address and cop reset address wi ll correspond to vector 0 and 1 of the interrupt vector table. in these instances, the first two locati ons in the vector table must contain branch or jmp instructions. all other entries must contain jsr instructions. table 4-1 chip memo ry configurations on-chip memory 56f8014 use restrictions program flash (pflash) 8k x 16 erase / program via flash interface unit and word writes to cdbw unified ram (ram) 2k x 16 usable by both the program and data memory spaces
56f8014 technical data, rev. 11 30 freescale semiconductor table 4-2 interrupt v ector table contents 1 peripheral vector number priority level vector base address + interrupt function core p:$00 reserved for reset overlay 2 core p:$02 reserved for cop reset overlay core 2 3 p:$04 illegal instruction core 3 3 p:$06 sw interrupt 3 core 4 3 p:$08 hw stack overflow core 5 3 p:$0a misaligned long word access core 6 1-3 p:$0c eonce step counter core 7 1-3 p:$0e eonce breakpoint unit 0 core 8 1-3 p:$10 eonce trace buffer core 9 1-3 p:$12 eonce transmit register empty core 10 1-3 p:$14 eonce receive register full core 11 2 p:$16 sw interrupt 2 core 12 1 p:$18 sw interrupt 1 core 13 0 p:$1a sw interrupt 0 14 reserved 15 reserved ps 16 0-2 p:$20 power sense occs 17 0-2 p:$22 pll lock, loss of clock reference interrupt fm 18 0-2 p:$24 fm access error interrupt fm 19 0-2 p:$26 fm command complete fm 20 0-2 p:$28 fm command, data and address buffers empty 21 reserved gpiod 22 0-2 p:$2c gpiod gpioc 23 0-2 p:$2e gpioc gpiob 24 0-2 p:$30 gpiob gpioa 25 0-2 p:$32 gpioa spi 26 0-2 p:$34 spi receiver full / error spi 27 0-2 p:$36 spi transmitter empty sci 28 0-2 p:$38 sci transmitter empty sci 29 0-2 p:$3a sci transmitter idle sci 30 0-2 p:$3c sci reserved sci 31 0-2 p:$3e sci receiver error sci 32 0-2 p:$40 sci receiver full 33, 34 reserved i 2 c 35 0-2 p:$46 i 2 c timer 36 0-2 p:$48 timer channel 0 timer 37 0-2 p:$4a timer channel 1 (continues next page)
program map 56f8014 technical data, rev. 11 freescale semiconductor 31 4.3 program map the program memory map is shown in table 4-3 . timer 38 0-2 p:$4c timer channel 2 timer 39 0-2 p:$4e timer channel 3 adc 40 0-2 p:$50 adca conversion complete adc 41 0-2 p:$52 adcb conversion complete adc 42 0-2 p:$54 adc zero crossing or limit error pwm 43 0-2 p:$56 reload pwm pwm 44 0-2 p:$58 pwm fault swilp 45 -1 p:$5a sw interrupt low priority 1. two words are allocated for each entry in the vector table. this does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2. if the vba is set to the reset value, the first two locations of the vector table will overlay the chip reset addresses. table 4-3 program memory map 1 1. all addresses are 16-bit word addresses. begin/end address memory allocation p: $ff ffff p: $00 8800 reserved p: $00 87ff p: $00 8000 on-chip ram 2 4kb 2. this ram is shared with data space starting at address x: $00 0000; see figure 4-1 . p: $00 7fff p: $00 2000 reserved p: $00 1fff p: $00 0000 internal program flash 16kb cop reset address = $00 0002 boot location = $00 0000 table 4-2 interrupt vector table contents 1 (continued) peripheral vector number priority level vector base address + interrupt function
56f8014 technical data, rev. 11 32 freescale semiconductor 4.4 data map figure 4-1 dual port ram 4.5 eonce memory map figure 4-5 lists all eonce registers necessary to access or control the eonce. table 4-4 data memory map 1 1. all addresses are 16-bit word addresses. begin/end address memory allocation x:$ff ffff x:$ff ff00 eonce 256 locations allocated x:$ff feff x:$01 0000 reserved x:$00 ffff x:$00 f000 on-chip peripherals 4096 locations allocated x:$00 efff x:$00 8800 reserved x:$00 efff x:$00 0800 reserved x:$00 7fff x:$00 0040 reserved x:$00 07ff x:$00 0000 on-chip data ram 2 4kb 2. this ram is shared with program space starting at p: $00 8000; see figure 4-1 . reserved ram reserved flash reserved eonce peripherals reserved ram dual port ram program data
peripheral memory mapped registers 56f8014 technical data, rev. 11 freescale semiconductor 33 4.6 peripheral memory mapped registers on-chip peripheral registers are pa rt of the data memory map on th e 56800e series. these locations may be accessed with the same addressing modes used for ordinary data memory, except all peripheral registers should be read/writt en using word accesses only. table 4-6 summarizes base addresses for the set of pe ripherals on the 56f8014 de vice. peripherals are listed in order of the base address. table 4-5 eonce memory map address register acronym register name x:$ff ffff otx1 / orx1 transmit register upper word receive register upper word x:$ff fffe otx / orx (32 bits) transmit register receive register x:$ff fffd otxrxsr transmit and receive status and control register x:$ff fffc oclsr core lock / unlock status register x:$ff fffb - x:$ff ffa1 reserved x:$ff ffa0 ocr control register x:$ff ff9f instruction step counter x:$ff ff9e oscntr (24 bits) instruction step counter x:$ff ff9d osr status register x:$ff ff9c obase peripheral base address register x:$ff ff9b otbcr trace buffer control register x:$ff ff9a otbpr trace bu ffer pointer register x:$ff ff99 trace buffer register stages x:$ff ff98 otb (21 - 24 bits/stage) trace buffer register stages x:$ff ff97 breakpoint unit control register x:$ff ff96 obcr (24 bits) breakpoint unit control register x:$ff ff95 breakpoint unit address register 1 x:$ff ff94 obar1 (24 bits) breakpoint unit address register 1 x:$ff ff93 breakpoint unit address register 2 x:$ff ff92 obar2 (32 bits) breakpoint unit address register 2 x:$ff ff91 breakpoint unit mask register 2 x:$ff ff90 obmsk (32 bits) breakpoint unit mask register 2 x:$ff ff8f reserved x:$ff ff8e obcntr eonce breakpoint unit counter x:$ff ff8d reserved x:$ff ff8c reserved x:$ff ff8b reserved x:$ff ff8a oescr external signal control register x:$ff ff89 - x:$ff ff00 reserved
56f8014 technical data, rev. 11 34 freescale semiconductor the following tables list all of the peripheral registers requi red to control or access the peripherals. table 4-6 data memory periph eral base address map summary peripheral prefix base address table number timer tmr n x:$00 f000 4-7 pwm pwm x:$00 f040 4-8 itcn itcn x:$00 f060 4-9 adc adc x:$00 f080 4-10 sci sci x:$00 f0b0 4-11 spi spi x:$00 f0c0 4-12 i 2 c i2c x:$00 f0d0 4-13 cop cop x:$00 f0e0 4-14 clk, pll, osc, test occs x:$00 f0f0 4-15 gpio port a gpioa x:$00 f100 4-16 gpio port b gpiob x:$00 f110 4-17 gpio port c gpioc x:$00 f120 4-18 gpio port d gpiod x:$00 f130 4-19 sim sim x:$00 f140 4-20 power supervisor ps x:$00 f160 4-21 fm fm x:$00 f400 4-22 table 4-7 quad timer registers address map (tmr_base = $00 f000) register acronym address offset register description tmr0_comp1 $0 compare register 1 tmr0_comp2 $1 compare register 2 tmr0_capt $2 capture register tmr0_load $3 load register tmr0_hold $4 hold register tmr0_cntr $5 counter register tmr0_ctrl $6 control register tmr0_sctrl $7 status and control register tmr0_cmpld1 $8 comparator load register 1 tmr0_cmpld2 $9 comparator load register 2 tmr0_csctrl $a comparator status and control register reserved tmr1_comp1 $10 compare register 1 tmr1_comp2 $11 compare register 2
peripheral memory mapped registers 56f8014 technical data, rev. 11 freescale semiconductor 35 tmr1_capt $12 capture register tmr1_load $13 load register tmr1_hold $14 hold register tmr1_cntr $15 counter register tmr1_ctrl $16 control register tmr1_sctrl $17 status and control register tmr1_cmpld1 $18 comparator load register 1 tmr1_cmpld2 $19 comparator load register 2 tmr1_csctrl $1a comparator status and control register reserved tmr2_comp1 $20 compare register 1 tmr2_comp2 $21 compare register 2 tmr2_capt $22 capture register tmr2_load $23 load register tmr2_hold $24 hold register tmr2_cntr $25 counter register tmr2_ctrl $26 control register tmr2_sctrl $27 status and control register tmr2_cmpld1 $28 comparator load register 1 tmr2_cmpld2 $29 comparator load register 2 tmr2_csctrl $2a comparator status and control register reserved tmr3_comp1 $30 compare register 1 tmr3_comp2 $31 compare register 2 tmr3_capt $32 capture register tmr3_load $33 load register tmr3_hold $34 hold register tmr3_cntr $35 counter register tmr3_ctrl $36 control register tmr3_sctrl $37 status and control register tmr3_cmpld1 $38 comparator load register 1 tmr3_cmpld2 $39 comparator load register 2 tmr3_csctrl $3a comparator status and control register table 4-7 quad timer regi sters address map (continued) (tmr_base = $00 f000) register acronym address offset register description
56f8014 technical data, rev. 11 36 freescale semiconductor table 4-8 pulse width modulat or registers address map (pwm_base = $00 f040) register acronym address offset register description pwm_ctrl $0 control register pwm_fctrl $1 fault control register pwm_fltack $2 fault status acknowledge register pwm_out $3 output control register pwm_cntr $4 counter register pwm_cmod $5 counter modulo register pwm_val0 $6 value register 0 pwm_val1 $7 value register 1 pwm_val2 $8 value register 2 pwm_val3 $9 value register 3 pwm_val4 $a value register 4 pwm_val5 $b value register 5 pwm_dtim0 $c dead time register 0 pwm_dtim1 $d dead time register 1 pwm_dmap1 $e disable mapping register 1 pwm_dmap2 $f disable mapping register 2 pwm_cnfg $10 configure register pwm_cctrl $11 channel control register pwm_port $12 port register pwm_icctrl $13 internal correction control register pwm_sctrl $14 source control register table 4-9 interrupt cont rol registers address map (itcn_base = $00 f060) register acronym address offset register description itcn_ipr0 $0 interrupt priority register 0 itcn_ipr1 $1 interrupt priority register 1 itcn_ipr2 $2 interrupt priority register 2 itcn_ipr3 $3 interrupt priority register 3 itcn_ipr4 $4 interrupt priority register 4 itcn_vba $5 vector base address register itcn_fim0 $6 fast interrupt match 0 register itcn_fival0 $7 fast interrupt ve ctor address low 0 register itcn_fivah0 $8 fast interrupt vector address high 0 register
peripheral memory mapped registers 56f8014 technical data, rev. 11 freescale semiconductor 37 itcn_fim1 $9 fast interrupt match 1 register itcn_fival1 $a fast interrupt ve ctor address low 1 register itcn_fivah1 $b fast interrupt vector address high 1 register itcn_irqp 0 $c irq pending register 0 itcn_irqp 1 $d irq pending register 1 itcn_irqp 2 $e irq pending register 2 reserved itcn_ictrl $12 interrupt control register reserved table 4-10 analog-to-digital c onverter registers address map (adc_base = $00 f080) register acronym address offset register description adc_ctrl1 $0 control register 1 adc_ctrl2 $1 control register 2 adc_zxctrl $2 zero crossing control register adc_clist 1 $3 channel list register 1 adc_clist 2 $4 channel list register 2 adc_sdis $5 sample disable register adc_stat $6 status register adc_limstat $7 limit status register adc_zxstat $8 zero crossing status register adc_rslt0 $9 result register 0 adc_rslt1 $a result register 1 adc_rslt2 $b result register 2 adc_rslt3 $c result register 3 adc_rslt4 $d result register 4 adc_rslt5 $e result register 5 adc_rslt6 $f result register 6 adc_rslt7 $10 result register 7 adc_lolim0 $11 low limit register 0 adc_lolim1 $12 low limit register 1 adc_lolim2 $13 low limit register 2 adc_lolim3 $14 low limit register 3 adc_lolim4 $15 low limit register 4 adc_lolim5 $16 low limit register 5 table 4-9 interrupt control re gisters address map (continued) (itcn_base = $00 f060) register acronym address offset register description
56f8014 technical data, rev. 11 38 freescale semiconductor adc_lolim6 $17 low limit register 6 adc_lolim7 $18 low limit register 7 adc_hilim0 $19 high limit register 0 adc_hilim1 $1a high limit register 1 adc_hilim2 $1b high limit register 2 adc_hilim3 $1c high limit register 3 adc_hilim4 $1d high limit register 4 adc_hilim5 $1e high limit register 5 adc_hilim6 $1f high limit register 6 adc_hilim7 $20 high limit register 7 adc_offst0 $21 offset register 0 adc_offst1 $22 offset register 1 adc_offst2 $23 offset register 2 adc_offst3 $24 offset register 3 adc_offst4 $25 offset register 4 adc_offst5 $26 offset register 5 adc_offst6 $27 offset register 6 adc_offst7 $28 offset register 7 adc_pwr $29 power control register adc_vref $2a voltage reference register reserved table 4-11 serial communication interface registers address map (sci_base = $00 f0b0) register acronym address o ffset register description sci_rate $0 baud rate register sci_ctrl1 $1 control register 1 sci_ctrl2 $2 control register 2 sci_stat $3 status register sci_data $4 data register table 4-10 analog-to-digit al converter register s address map (continued) (adc_base = $00 f080) register acronym address offset register description
peripheral memory mapped registers 56f8014 technical data, rev. 11 freescale semiconductor 39 table 4-12 serial peripheral interface registers address map (spi_base = $00 f0c0) register acronym address offset register description spi_sctrl $0 status and control register spi_dsctrl $1 data size and control register spi_drcv $2 data receive register spi_dxmit $3 data transmit register table 4-13 i 2 c registers address map (i2c_base = $00 f0d0) register acronym address offset register description i2c_addr $0 address register i2c_fdiv $1 frequency divider register i2c_ctrl $2 control register i2c_stat $3 status register i2c_data $4 data register i2c_nfilt $5 noise filter register table 4-14 computer operating properly registers address map (cop_base = $00 f0e0) register acronym address offset register description cop_ctrl $0 control register cop_tout $1 time-out register cop_cntr $2 counter register table 4-15 clock generation module registers address map (occs_base = $00 f0f0) register acronym address offset register description occs_ctrl $0 control register occs_divby $1 divide-by register occs_stat $2 status register reserved occs_shutdn $4 shutdown register occs_octrl $5 oscillator control register
56f8014 technical data, rev. 11 40 freescale semiconductor table 4-16 gpioa re gisters address map (gpioa_base = $00 f100) register acronym address offset register description gpioa_pupen $0 pull-up enable register gpioa_data $1 data register gpioa_ddir $2 data direction register gpioa_peren $3 peripheral enable register gpioa_iassrt $4 interrupt assert register gpioa_ien $5 interrupt enable register gpioa_iepol $6 interrupt edge polarity register gpioa_ipend $7 interrupt pending register gpioa_iedge $8 interrupt edge-sensitive register gpioa_ppoutm $9 push-pull output mode control register gpioa_rdata $a raw data register gpioa_drive $b drive strength control register table 4-17 gpiob re gisters address map (gpiob_base = $00 f110) register acronym address offset register description gpiob_pupen $0 pull-up enable register gpiob_data $1 data register gpiob_ddir $2 data direction register gpiob_peren $3 peripheral enable register gpiob_iassrt $4 interrupt assert register gpiob_ien $5 interrupt enable register gpiob_iepol $6 interrupt edge polarity register gpiob_ipend $7 interrupt pending register gpiob_iedge $8 interrupt edge-sensitive register gpiob_ppoutm $9 push-pull output mode control register gpiob_rdata $a raw data register gpiob_drive $b drive strength control register
peripheral memory mapped registers 56f8014 technical data, rev. 11 freescale semiconductor 41 table 4-18 gpioc re gisters address map (gpioc_base = $00 f120) register acronym address offset register description gpioc_pupen $0 pull-up enable register gpioc_data $1 data register gpioc_ddir $2 data direction register gpioc_peren $3 peripheral enable register gpioc_iassrt $4 interrupt assert register gpioc_ien $5 interrupt enable register gpioc_iepol $6 interrupt edge polarity register gpioc_ipend $7 interrupt pending register gpioc_iedge $8 interrupt edge-sensitive register gpioc_ppoutm $9 push-pull output mode control register gpioc_rdata $a raw data register gpioc_drive $b drive strength control register table 4-19 gpiod re gisters address map (gpiod_base = $00 f130) register acronym address offset register description gpiod_pupen $0 pull-up enable register gpiod_data $1 data register gpiod_ddir $2 data direction register gpiod_peren $3 peripheral enable register gpiod_iassrt $4 interr upt assert register gpiod_ien $5 interrupt enable register gpiod_iepol $6 interrupt edge polarity register gpiod_ipend $7 interrupt pending register gpiod_iedge $8 interrupt edge-sensitive register gpiod_ppoutm $9 push-pull output mode control register gpiod_rdata $a raw data register gpiod_drive $b drive strength control register
56f8014 technical data, rev. 11 42 freescale semiconductor table 4-20 system integration module registers address map (sim_base = $00 f140) register acronym address o ffset register description sim_ctrl $0 control register sim_rstat $1 reset status register sim_swc0 $2 software control register 0 sim_swc1 $3 software control register 1 sim_swc2 $4 software control register 2 sim_swc3 $5 software control register 3 sim_mshid $6 most significant half jtag id sim_lshid $7 least signi ficant half jtag id sim_pwr $8 power control register reserved sim_clkout $a clock out select register sim_gps $b gpio peripheral select register sim_pce $c peripheral clock enable register sim_iosahi $d i/o short address location high register sim_iosalo $e i/o short address location low register table 4-21 power supervisor registers address map (ps_base = $00 f160) register acronym address offset register description ps_ctrl $0 control register ps_stat $1 status register table 4-22 flash module registers address map (fm_base = $00 f400) register acronym address o ffset register description fm_clkdiv $0 clock divider register fm_cnfg $1 configuration register $2 reserved fm_sechi $3 security high half register fm_seclo $4 security low half register $5 - $9 reserved fm_prot $10 protection register $11 - $12 reserved
introduction 56f8014 technical data, rev. 11 freescale semiconductor 43 part 5 interrupt controller (itcn) 5.1 introduction the interrupt controller (itcn) m odule is used to arbitr ate between various inte rrupt requests (irqs), to signal to the 56800e core when an inte rrupt of sufficient priority exists , and to what address to jump in order to service this interrupt. 5.2 features the itcn module design includes these distinctive features: ? programmable priority levels for each irq ? two programmable fast interrupts ? notification to sim module to restar t clocks out of wait and stop modes ? ability to drive initial address on the address bus after reset for further information, see table 4-2 , interrupt vector table contents. 5.3 functional description the interrupt controller contains re gisters that allow each of the 46 in terrupt sources to be set to one of three priority levels (exc luding certain interrupts that are of fixed priority). next, all of the interrupt requests of a given level are priori ty encoded to determine the lowe st numerical value of the active interrupt requests for that level. wi thin a given priority level, number 0 is the highest priority and number 45 is the lowest. during wait and stop modes, the system clocks and the 56800e core are turned off. the itcn can wake the core and restart system clocks by signaling a pe nding irq to the system integration module (sim) to fm_ustat $13 user status register fm_cmd $14 command register $15 reserved $16 reserved $17 reserved fm_data $18 data buffer register $19 reserved $1a reserved fm_opt1 $1b optional data 1 register reserved fm_tstsig $1d test array signature register table 4-22 flash module regi sters address map (continued) (fm_base = $00 f400) register acronym address o ffset register description
56f8014 technical data, rev. 11 44 freescale semiconductor restart the clocks and service the irq. an irq can only wake the core if the irq is enabled prior to entering wait or stop mode. 5.3.1 normal interrupt handling once the intc has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vect or address is generated. no rmal interrupt handling con catenates the vector base address (vba) and the vector number to determine the vector address, generating an offset into the vector table for each interrupt. 5.3.2 interrupt nesting interrupt exceptions may be nested to allow an irq of higher priori ty than the current exception to be serviced. the following table defines the nesting requirements for each priority level. 5.3.3 fast interrupt handling fast interrupts are described in the dsp56800e reference manual . the interrupt c ontroller recognizes fast interrupts before the core does. a fast interrupt is de fined (to the itcn) by: 1. setting the priority of the interrupt as level 2, with the appropriate field in the ipr registers 2. setting the fim n register to the appropriate vector number 3. setting the fival n and fivah n registers with the address of the code for the fast interrupt when an interrupt occurs, its vector number is compar ed with the fim0 and fim1 register values. if a match occurs, and it is a level 2 inte rrupt, the itcn handles it as a fast interrupt. the itcn takes the vector address from the appropriate fival n and fivah n registers, instead of gene rating an addres s that is an offset from the vba. the core then fetches the instruction from the indicated vector adddress and if it is not a js r, the core starts its fast interrupt handling. table 5-1 interrupt mask bit definition sr[9] sr[8] exceptions permitted exceptions masked 0 0 priorities 0, 1, 2, 3 none 0 1 priorities 1, 2, 3 priority 0 1 0 priorities 2, 3 priorities 0, 1 1 1 priority 3 priorities 0, 1, 2
block diagram 56f8014 technical data, rev. 11 freescale semiconductor 45 5.4 block diagram figure 5-1 interrupt controller block diagram 5.5 register descriptions a register address is the sum of a base address and an addr ess offset. the base addr ess is defined at the system level and the addres s offset is defined at the module leve l. the itcn module has 16 registers. table 5-2 itcn register summary (itcn_base = $00 f060) register acronym base address + register name section location ipr0 $0 interrupt priority register 0 5.5.1 ipr1 $1 interrupt priority register 1 5.5.2 ipr2 $2 interrupt priority register 2 5.5.3 priority level 2 -> 4 decode int0 priority level 2 -> 4 decode int45 level 0 46 -> 6 priority encoder any0 level 3 46 -> 6 priority encoder any3 int vab ipic control 6 6 pic_en iack sr[9:8]
56f8014 technical data, rev. 11 46 freescale semiconductor ipr3 $3 interrupt priority register 3 5.5.4 ipr4 $4 interrupt priority register 4 5.5.5 vba $5 vector base address register 5.5.6 fim0 $6 fast interrupt match 0 register 5.5.7 fival0 $7 fast interrupt 0 vector address low register 5.5.8 fivah0 $8 fast interrupt 0 vector address high register 5.5.9 fim1 $9 fast interrupt match 1 register 5.5.10 fival1 $a fast interrupt 1 vector address low register 5.5.11 fivah1 $b fast interrupt 1 vector address high register 5.5.12 irqp0 $c irq pending register 0 5.5.13 irqp1 $d irq pending register 1 5.5.14 irqp2 $e irq pending register 2 5.5.15 reserved ictrl $12 interrupt control register 5.5.16 reserved table 5-2 itcn regist er summary (continued) (itcn_base = $00 f060) register acronym base address + register name section location
register descriptions 56f8014 technical data, rev. 11 freescale semiconductor 47 figure 5-2 itcn register map summary 5.5.1 interrupt priority register 0 (ipr0) figure 5-3 interrupt prio rity register 0 (ipr0) add. offset register name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 ipr0 r lvi ipl 0 0 0 0 rx_reg ipl tx_reg ipl trbuf ipl bkpt_u ipl stpcnt ipl w $1 ipr1 r gpiob ipl gpioc ipl gpiod ipl 0 0 fm_cbe ipl fm_cc ipl fm_err ipl pll ipl w $2 ipr2 r sci_rcv ipl sci_rerr ipl 0 0 sci_tidl ipl sci_xmit ipl spi_xmit ipl spi_rcv ipl gpioa ipl w $3 ipr3 r adca_cc ipl tmr_3 ipl tmr_2 ipl tmr_1 ipl tmr_0 ipl i2c_addr ipl 0 0 0 0 w $4 ipr4 r 0 0 0 0 0 0 0 0 pwm_f ipl pwm_rl ipl adc_zc_le ipl adcb_cc ipl w $5 vba r 0 0 vector_base_address w $6 fim0 r 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 w $7 fival0 r fast interrupt 0 vector address low w $8 fivah0 r 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 vector address high w $9 fim1 r 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 w $a fival1 r fast interrupt 1 vector address low w $b fivah1 r 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 vector address high w $c irqp0 r pending[16:2] 1 w $d irqp1 r pending[32:17] w $e irqp2 r 1 1 1 pending[45:33] w reserved $12 ictrl r int ipic vab int_ dis 1 1 1 0 0 w reserved = reserved base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read lvi ipl 0 0 0 0 rx_reg ipl tx_reg ipl trbuf ipl bkpt_u ipl stpcnt ipl write reset 0 0 0 0 0 0 0 000000000
56f8014 technical data, rev. 11 48 freescale semiconductor 5.5.1.1 lvi ipl?bits 15?14 this field is used to set the interr upt priority levels for a peripheral ir q. this irq is limited to priorities 0 through 2 and is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.1.2 reserved?bits 13?10 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.5.1.3 eonce receive register full interrupt priority level (rx_reg ipl)? bits 9?8 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.5.1.4 eonce transmit regist er empty interrupt priority level (tx_reg ipl)? bits 7?6 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.5.1.5 eonce trace buffer interrupt priority level (trbuf ipl)? bits 5?4 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3
register descriptions 56f8014 technical data, rev. 11 freescale semiconductor 49 5.5.1.6 eonce breakpoint un it interrupt priority level (bkpt_u ipl)? bits 3?2 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.5.1.7 eonce step counte r interrupt priority level (stpcnt ipl)? bits 1?0 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.5.2 interrupt priority register 1 (ipr1) figure 5-4 interrupt prio rity register 1 (ipr1) 5.5.2.1 gpiob interrupt priorit y level (gpiob ipl)?bits 15?14 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.2.2 gpioc interrupt priorit y level (gpioc ipl)?bits 13?12 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read gpiob ipl gpioc ipl gpiod ipl 0 0 fm_cbe ipl fm_cc ipl fm_err ipl pll ipl write reset 0 0 0 0 0 0 0 000000000
56f8014 technical data, rev. 11 50 freescale semiconductor 5.5.2.3 gpiod interrupt priorit y level (gpiod ipl)?bits 11?10 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.2.4 reserved?bits 9?8 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.5.2.5 fm command, data, address buffers empty interrupt priority level (fm_cbe ipl)?bits 7?6 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.2.6 fm command complete priority level (fm_cc ipl)?bits 5?4 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.2.7 fm error interrupt prio rity level (fm_e rr ipl)?bits 3?2 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8014 technical data, rev. 11 freescale semiconductor 51 5.5.2.8 pll loss of referenc e or change in lock sta tus interrupt priority level (pll ipl)?bits 1?0 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.3 interrupt priority register 2 (ipr2) figure 5-5 interrupt prio rity register 2 (ipr2) 5.5.3.1 sci receiver full interr upt priority level (sci_rcv ipl)? bits 15?14 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.3.2 sci receiver error interrupt priority level (sci_rerr ipl)? bits 13?12 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.3.3 reserved?bits 11?10 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read sci_rcv ipl sci_rerr ipl 0 0 sci_tidl ipl sci_xmit ipl spi_xmit ipl spi_rcv ipl gpioa ipl write reset 0000000000000000
56f8014 technical data, rev. 11 52 freescale semiconductor 5.5.3.4 sci transmitter idle inte rrupt priority level (sci_tidl ipl)? bits 9?8 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.3.5 sci transmitter empty inte rrupt priority level (sci_xmit ipl)? bits 7?6 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.3.6 spi transmitter empty inte rrupt priority level (spi_xmit ipl)? bits 5?4 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.3.7 spi receiver full interr upt priority level (spi_rcv ipl)? bits 3?2 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8014 technical data, rev. 11 freescale semiconductor 53 5.5.3.8 gpioa interrupt priority level (gpioa ipl)?bits 1?0 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.4 interrupt priority register 3 (ipr3) figure 5-6 interrupt prio rity register 3 (ipr3) 5.5.4.1 adca conversion comp lete interrupt pr iority level (adca_cc ipl)?bits 15?14 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.4.2 timer channel 3 interrupt priority level (tmr_3 ipl)?bits 13?12 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.4.3 timer channel 2 interrupt priority level (tmr_2 ipl)?bits 11?10 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read adca_cc ipl tmr_3 ipl tmr_2 ipl tmr_1 ipl tmr_0 ipl i2c_addr ipl 0 0 0 0 write reset 0 000000000000000
56f8014 technical data, rev. 11 54 freescale semiconductor 5.5.4.4 timer channel 1 interrupt priority level (tmr_1 ipl)?bits 9?8 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.4.5 timer channel 0 interrupt priority level (tmr_0 ipl)?bits 7?6 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.4.6 i 2 c address detect i nterrupt priority level (i2c_addr ipl)?bits 5?4 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.4.7 reserved?bits 3?0 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.5.5 interrupt priority register 4 (ipr4) figure 5-7 interrupt prio rity register 4 (ipr4) 5.5.5.1 reserved?bits 15?8 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. base + $4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 pwm_f ipl pwm_rl ipl adc_zc_le ipl adcb_cc ipl write reset 0000000000000000
register descriptions 56f8014 technical data, rev. 11 freescale semiconductor 55 5.5.5.2 pwm fault interrupt priority level (pwm_f ipl)? bits 7?6 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.5.3 reload pwm interrupt priority level (pwm_rl ipl)? bits 5?4 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.5.4 adc zero crossing or li mit error interrupt priority level (adc_zc_le ipl)? bits 3?2 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.5.5.5 adcb conversion comp lete interrupt pr iority level (adcb_cc ipl)?bits 1?0 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
56f8014 technical data, rev. 11 56 freescale semiconductor 5.5.6 vector base address register (vba) figure 5-8 vector base address register (vba) 5.5.6.1 reserved?bits15?14 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.5.6.2 vector address bus (vab)?bits 13?0 the value in this register is used as the upper 14 bits of the interrupt vector vab[20:0]. the lower 7 bits are determined based on the highest priority interrupt and are then a ppended onto vba be fore presenting the full vab to the core. 5.5.7 fast interrupt match 0 register (fim0) figure 5-9 fast interrupt match 0 register (fim0) 5.5.7.1 reserved?bits 15?6 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.5.7.2 fast interrupt 0 vector number (fast inte rrupt 0)?bits 5?0 these values determine which irq will be fast interrupt 0. fast interrupts vector directly to a service routine based on values in the fast interrupt vector address registers without having to go to a jump table first. irqs used as fast interrupts must be set to priority level 2. unexp ected results will occur if a fast interrupt vector is set to any othe r priority. a fast interrupt automa tically becomes the highest-priority level 2 interrupt regardless of its location in the interru pt table prior to being de clared as fast interrupt. fast interrupt 0 has priority over fa st interrupt 1. to determine the vect or number of each irq, refer to the vector table. base + $5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 vector_base_address write reset 1 1. the 56f8014 resets to a value of 0x0000. this corresponds to reset addresses of 0x00 0000. 000000 0 0 00000000 base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 write reset 0000000000000000
register descriptions 56f8014 technical data, rev. 11 freescale semiconductor 57 5.5.8 fast interrupt 0 vector address low register (fival0) figure 5-10 fast interrupt 0 vect or address low register (fival0) 5.5.8.1 fast interrupt 0 vector address low (fi val0)?bits 15?0 the lower 16 bits of the vector addr ess used for fast interrupt 0. this register is combined with fivah0 to form the 21-bit vector address for fast interrupt 0 defined in the fim0 register. 5.5.9 fast interrupt 0 vector address high register (fivah0) figure 5-11 fast interr upt 0 vector address high register (fivah0) 5.5.9.1 reserved?bits 15?5 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.5.9.2 fast interrupt 0 vector address high (fi vah0)?bits 4?0 the upper five bits of the vector a ddress used for fast inte rrupt 0. this register is combined with fival0 to form the 21-bit vector address for fast interrupt 0 defined in the fim0 register. 5.5.10 fast interrupt 1 match register (fim1) figure 5-12 fast interrupt 1 match register (fim1) 5.5.10.1 reserved?bits 15?6 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.5.10.2 fast interrupt 1 vector number (fast inte rrupt 1)?bits 5?0 these values determine which irq will be fast interrupt 1. fast interrupts vector directly to a service routine based on values in the fast interrupt vector address registers without having to go to a jump table first. irqs used as fast interrupts must be set to priority level 2. unexp ected results will occur if a fast base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fast interrupt 0 vector address low write reset 0000000000000000 base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 vector address high write reset 0000000000000000 base + $9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 write reset 0000000000000000
56f8014 technical data, rev. 11 58 freescale semiconductor interrupt vector is set to any othe r priority. a fast interrupt automa tically becomes the highest-priority level 2 interrupt regardless of its location in the interru pt table prior to being de clared as fast interrupt. fast interrupt 0 has priority over fast interrupt 1. to determine the vector numbe r of each irq, refer to the vector table. 5.5.11 fast interrupt 1 vector address low register (fival1) figure 5-13 fast interrupt 1 vect or address low register (fival1) 5.5.11.1 fast interrupt 1 vector address low (fi val1)?bits 15?0 the lower 16 bits of the vector addr ess used for fast interrupt 1. this register is combined with fivah1 to form the 21-bit vector address for fast interrupt 1 defined in the fim1 register. 5.5.12 fast interrupt 1 vector address high register (fivah1) figure 5-14 fast interr upt 1 vector address high register (fivah1) 5.5.12.1 reserved?bits 15?5 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.5.12.2 fast interrupt 1 vector address high (fi vah1)?bits 4?0 the upper five bits of the vector a ddress are used for fast interrupt 1. this regi ster is combined with fival1 to form the 21-bit vector address for fast interrupt 1 defined in the fim1 register. 5.5.13 irq pending register 0 (irqp0) figure 5-15 irq pending register 0 (irqp0) 5.5.13.1 irq pending (pending)?bits 15?1 this register combines with irqp1 and irqp2 to re present the pending irqs for interrupt vector numbers 2 through 45. base + $a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fast interrupt 1 vector address low write reset 0000000000000000 base + $b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 vector address high write reset 0000000000000000 base + $c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending[16:2] 1 write reset 1111111111111111
register descriptions 56f8014 technical data, rev. 11 freescale semiconductor 59 ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.5.13.2 reserved?bit 0 this bit is reserved or not implemented. it is read as 1 and cannot be modified by writing. 5.5.14 irq pending register 1 (irqp1) figure 5-16 irq pending register 1 (irqp1) 5.5.14.1 irq pending (pending)?bits 32?17 this register combines with irqp0 and irqp2 to re present the pending irqs for interrupt vector numbers 2 through 45. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.5.15 irq pending register 2 (irqp2) figure 5-17 irq pending register 2 (irqp2) 5.5.15.1 irq pending (pending)?bits 45?33 this register combines with irqp0 and irqp1 to re present the pending irqs for interrupt vector numbers 2 through 45. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.5.16 interrupt contro l register (ictrl) figure 5-18 interrupt cont rol register (ictrl) base + $d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending[32:17] write reset 1111111111111111 base + $e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 pending[45:33] write reset 1111111111111111 $base + $12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read int ipic vab int_ dis 1 1 1 0 0 write reset 0000000000011100
56f8014 technical data, rev. 11 60 freescale semiconductor 5.5.16.1 interrupt (int)?bit 15 this read-only bit reflects the state of th e interrupt to the 56800e core. ? 0 = no interrupt is be ing sent to the 56800e core ? 1 = an interrupt is be ing sent to the 56800e core 5.5.16.2 interrupt priority level (ipic)?bits 14?13 these read-only bits reflect the state of the new interrupt priority level bits be ing presented to the 56800e core. these bits indicate the priority level needed fo r a new irq to interrupt the current interrupt being sent to the 56800e core. this field is only updated wh en the 56800e core jumps to a new interrupt service routine. note: nested interrupts may cause this field to be update d before the original inte rrupt service routine can read it. ? 00 = required nested exception prio rity levels are 0, 1, 2, or 3 ? 01 = required nested exception pr iority levels are 1, 2, or 3 ? 10 = required nested exceptio n priority levels are 2 or 3 ? 11 = required nested exception priority level is 3 5.5.16.3 vector number - vec tor address bus (vab)?bits 12?6 this read-only field shows the vector number (vab[6:0]) used at the time the last irq was taken. in the case of a fast interrupt, it shows the lower address bits of the jump address. th is field is only updated when the 56800e core jumps to a new interrupt service routine. note: nested interrupts may cause this field to be update d before the original inte rrupt service routine can read it. 5.5.16.4 interrupt disable (int_dis)?bit 5 this bit allows all interrupts to be disabled. ? 0 = normal operation (default) ? 1 = all interrupts disabled table 5-3 interrupt priority encoding ipic_value[1:0] current interrupt priority level required nested exception priority 00 no interrupt or swilp priorities 0, 1, 2, 3 01 priority 0 priorities 1, 2, 3 10 priority 1 priorities 2, 3 11 priority 2 or 3 priority 3
resets 56f8014 technical data, rev. 11 freescale semiconductor 61 5.5.16.5 reserved?bits 4?2 this bit field is reserved or not implemented. it is read as 1 a nd cannot be modified by writing. 5.5.16.6 reserved?bits 1?0 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6 resets 5.6.1 general 5.6.2 description of reset operation 5.6.2.1 reset handshake timing the itcn provides the 56800e core with a reset vector address on the vab pins whenever reset is asserted from the sim. th e reset vector will be pr esented until the second risi ng clock edge after reset is released. the genera l timing is shown in figure 5-19 . figure 5-19 reset interface 5.6.3 itcn after reset after reset, all of the itcn regist ers are in their default states. this means all interrupts are disabled, except the core irqs wi th fixed priorities: ? illegal instruction ? sw interrupt 3 ? hw stack overflow ? misaligned long word access ? sw interrupt 2 ? sw interrupt 1 table 5-4 reset summary reset priority source characteristics core reset rst core reset from the sim res clk vab pab reset_vector_adr read_adr
56f8014 technical data, rev. 11 62 freescale semiconductor ? sw interrupt 0 ? sw interrupt lp these interrupts are enabled at their fixed priority levels. part 6 system integration module (sim) 6.1 introduction the sim module is a system catchall for the glue logic that ties together the system-on-chip. it controls distribution of resets and clocks and provides a number of control features. the system integration module is responsible for the following functions: ? reset sequencing ? clock control & distribution ? stop/wait control ? system status registers ? registers for software access to the jtag id of the chip ? test registers ? power control ? i/o pad multiplexing these are discussed in more detail in the sections that follow. 6.2 features the sim has the following features: ? reset sequencing ? core and peripheral clock control & distribution ? stop/wait mode control ? system status ? power control ? control i/o multiplexing ? system bus clocks with pipeline hold-off support ? system clocks for non-pipelined interfaces ? peripheral clocks for quad timer and pwm with high-speed (3x) option ? power-saving clock gating for peripherals ? three power modes (run, wait, st op) to control power utilization ? stop mode shuts down the 56800e core, system clock, and peripheral clock ? wait mode shuts down the 56800e core and unnecessary system clock operation ? run mode supports full part operation ? controls, with write protection, the enable/disab le of 56800e core wait and stop instructions
features 56f8014 technical data, rev. 11 freescale semiconductor 63 ? controls, with write protection, the enab le/disable of large regulator standby mode ? controls to route functional signals to selected peripherals and i/o pads ? controls deassertion sequence of internal resets ? software-initiated reset ? four 16-bit registers reset only by a power-on r eset usable for general-purpose software control ? timer channel stop mode clocking controls ? sci stop mode clocking control to support lin sleep mode stop recovery ? short addressing location control ? registers for containing the jtag id of the chip ? controls output to clko pin
56f8014 technical data, rev. 11 64 freescale semiconductor 6.3 register descriptions table 6-1 sim register s (sim_base = $00 f140) address offset address acronym register name section location base + $0 sim_ctrl control register 6.3.1 base + $1 sim_rstat res et status register 6.3.2 base + $2 sim_swc0 software control register 0 6.3.3 base + $3 sim_swc1 software control register 1 6.3.3 base + $4 sim_swc2 software control register 2 6.3.3 base + $5 sim_swc3 software control register 3 6.3.3 base + $6 sim_mshid most signi ficant half of jtag id 6.3.4 base + $7 sim_lshid least significant half of jtag id 6.3.5 base + $8 sim_pwr power control register 6.3.6 reserved base + $a sim_clkout cl ko select register 6.3.7 base + $b sim_gps gpio peri pheral select register 6.3.8 base + $c sim_pce peripheral clock enable register 6.3.9 base + $d sim_iosahi i/o short address location high register 6.3.10 base + $e sim_iosalo i/o short address location low register 6.3.10
register descriptions 56f8014 technical data, rev. 11 freescale semiconductor 65 figure 6-1 sim register map summary 6.3.1 sim control register (sim_ctrl) figure 6-2 sim control register (sim_ctrl) 6.3.1.1 timer channel 3 s top disable (tc3_sd)?bit 15 this bit enables the operation of the time r channel 3 peripheral clock in stop mode. ? 0 = timer channel 3 disabled in stop mode add. offset address acronym 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 sim_ ctrl r tc3_ sd tc2_ sd tc1_ sd tc0_ sd sci_ sd 0 tc3_ inp 0 0 0 once ebl 0 sw rst stop_ disable wait_ disable w $1 sim_ rstat r 0 0 0 0 0 0 0 0 0 0 swr copr extr por 0 0 w $2 sim_swc0 r software control data 0 w $3 sim_swc1 r software control data 1 w $4 sim_swc2 r software control data 2 w $5 sim_swc3 r software control data 3 w $6 sim_mshid r 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 w $7 sim_lshid r 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 w $8 sim_pwr r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lrstdby w reserved $a sim_ clkout r 0 0 0 0 0 0 pwm 3pwm 2pwm 1pwm 0 clk dis clkosel w $b sim_gps r tcr pcr 0 0 cfg_ b7 cfg_ b6 cfg_ b5 cfg_ b4 cfg_ b3 cfg_ b2 cfg_ b1 cfg_ b0 cfg_a5 cfg_a4 w $c sim_pce r i2c 0 adc 0 0 0 0 0 0 tmr 0 sci 0 spi 0 pwm w $d sim_iosahi r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 isal[23:22] w $e sim_iosalo r isal[21:6] w 0 = read as 0 1 = read as 1 = reserved = reserved base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tc3_ sd tc2_ sd tc1_ sd tc0_ sd sci_ sd 0 tc3_ inp 0 0 0 once ebl sw rst stop_ disable wait_ disable write reset 0000000000000000
56f8014 technical data, rev. 11 66 freescale semiconductor ? 1 = timer channel 3 enabled in stop mode 6.3.1.2 timer channel 2 s top disable (tc2_sd)?bit 14 this bit enables the operation of the time r channel 2 peripheral clock in stop mode. ? 0 = timer channel 2 disabled in stop mode ? 1 = timer channel 2 enabled in stop mode 6.3.1.3 timer channel 1 s top disable (tc1_sd)?bit 13 this bit enables the operation of the time r channel 1 peripheral clock in stop mode. ? 0 = timer channel 1 disabled in stop mode ? 1 = timer channel 1 enabled in stop mode 6.3.1.4 timer channel 0 s top disable (tc0_sd)?bit 12 this bit enables the operation of the time r channel 0 peripheral clock in stop mode. ? 0 = timer channel 0 disabled in stop mode ? 1 = timer channel 0 enabled in stop mode 6.3.1.5 sci stop disable (sci_sd)?bit 11 this bit enables the operation of the sci peripheral clock in stop mode. this is recommended for use in lin mode so that the sci can generate interrupts and recover from stop mode while the lin interface is in sleep mode and using stop m ode to reduce power consumption. ? 0 = sci disabled in stop mode ? 1 = sci enabled in stop mode 6.3.1.6 reserved?bit 10 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.3.1.7 timer channel 3 input (tc3_inp)?bit 9 this bit selects the input of timer channel 3 to be from the pwm s ync signal or gpio pin. ? 1 = timer channel 3 input from pwm sync signal ? 0 = timer channel 3 input controlled by si m_gps register cfg_b3 and cfg_a5 fields 6.3.1.8 reserved?bits 8?6 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.3.1.9 once enable (onceebl)?bit 5 ? 0 = once clock to 56800e core en abled when core tap is enabled ? 1 = once clock to 56800e core is always enabled 6.3.1.10 software reset (swrst)?bit 4 writing 1 to this field will cause the part to reset.
register descriptions 56f8014 technical data, rev. 11 freescale semiconductor 67 6.3.1.11 stop disable (sto p_disable[1:0])?bits 3?2 ? 00 = stop mode will be entered when the 56800e core executes a stop instruction ? 01 = the 56800e stop instruction will not cause entry into stop mode ? 10 = stop mode will be entered when the 5680 0e core executes a stop instruction and the stop_disable field is write-protected until the next reset ? 11 = the 56800e stop instruction will not cause entry into stop mode and the stop_disable field is write-protected until the next reset 6.3.1.12 wait disable (wait_disable[1:0])?bits 1?0 ? 00 = wait mode will be entered when th e 56800e core executes a wait instruction ? 01 = the 56800e wait instructio n will not cause entry into wait mode ? 10 = wait mode will be entered when the 568 00e core executes a wait instruction and the wait_disable field is write-pro tected until the next reset ? 11 = the 56800e wait instruction will not cause entry into wait mode and the wait_disable field is write-protected until the next reset 6.3.2 sim reset status register (sim_rstat) this register is updated upon any system reset and indi cates the cause of the most recent reset. it also controls whether the cop reset vector or regular reset vector in the vect or table is used. this register is asynchronously reset during power-on reset (see power supervisor module) and subsequently is synchronously updated based on th e level of the external reset, softwa re reset, or cop reset inputs. only one source will ever be indicated. in the event that multiple reset sources assert simultaneously, the highest-precedence source will be indicated. the pre cedence from highest to lowest is por, extr, copr, and swr. while por is always set during a power-on reset, extr wi ll become set if the external reset pin is asserted or remains assert ed after the power-on reset (por) has deasserted. figure 6-3 sim reset status register (sim_rstat) 6.3.2.1 reserved?bits 15?6 this bit field is reserved or not implemented. it is read as zero and cannot be modified by writing. 6.3.2.2 software reset (swr)?bit 5 when set, this bit indicates that the previous system reset occurred as a result of a softwa re reset (written 1 to sw rst bit in the sim_ctrl register). it will not be set if a cop, ex ternal, or por reset also occurred. 6.3.2.3 cop reset (copr)?bit 4 when set, this bit indicates that the previous syst em reset was caused by the computer operating properly base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 swr copr extr por 0 0 write reset 0000000000 00
56f8014 technical data, rev. 11 68 freescale semiconductor (cop) timer. it will not be set if an external or por reset also occurred. if co pr is set as code starts executing, the cop reset vector in the vector table will be us ed. otherwise, the normal reset vector is used. 6.3.2.4 external reset (extr)?bit 3 when set, this bit indicates that the previous system reset was caused by an external reset. it will only be set if the external reset pin was asserted or rema ined asserted after the power-on reset deasserted. 6.3.2.5 power-on reset (por)?bit 2 this bit is set during a power-on reset. 6.3.2.6 reserved?bits 1?0 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.3.3 sim software control registers (sim_swc0, sim_swc1, sim_swc2, and sim_swc3) only sim_swc0 is shown in th is section. sim_swc1, sim_swc2, and sim_swc3 are identical in functionality. figure 6-4 sim software cont rol register 0 (sim_swc0) 6.3.3.1 software control data 0 (field)?bits 15?0 this register is reset only by th e power-on reset (por). it has no part-specific functionality and is intended for use by a software develope r to contain data that will be unaffected by the other re set sources (reset pin, software reset, and cop reset). 6.3.4 most significant half of jtag id (sim_mshid) this read-only register displays the most significant half of the jtag id for the ch ip. this register reads $01f2. figure 6-5 most significant half of jtag id (sim_mshid) base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read software control data 0 write reset 0 0 0 0 0 0 0 0000 0 0000 base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 write reset 0 0 0 0 0 0 0 1111 1 0010
register descriptions 56f8014 technical data, rev. 11 freescale semiconductor 69 6.3.5 least significant half of jtag id (sim_lshid) this read-only register displays th e least significant half of the jtag id for the chip. this register reads $401d. figure 6-6 least significant half of jtag id (sim_lshid) 6.3.6 sim power control register (sim_pwr) this register controls the standby mode of the large regulator. the large regulato r derives the core digital logic power supply from the io power supply. in some circumstances, the large re gulator may be put in a reduced-power standby mode wit hout interfering with part opera tion. refer to the overview of power-down modes and the overview of clock generation for more in formation on the use of large regulator standby. figure 6-7 sim power cont rol register (sim_pwr) 6.3.6.1 reserved?bits 15?2 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.3.6.2 large regulator sta ndby mode[1:0] (lrstdby)?bits 1?0 this bit controls the pull-up resistors on the irqa pin. ? 00 = large regulator is in normal mode ? 01 = large regulator is in standby (reduced-power) mode ? 10 = large regulator is in normal mode and the lr stdby field is write-protected until the next reset ? 11 = large regulator is in standby mode and the lrstdby field is write-protected until the next reset note: standby mode can be used when the device operates below 200 khz if the pll is shut down. 6.3.7 clko select re gister (sim_clkout) the clko select register can be used to multiple x out selected clocks generated inside the clock generation and sim modules. all functionality is for test purposes only and is subject to unspecified latencies. glitches may be produ ced when the clock is enabled or switched. base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 write reset 0 1 0 0 0 0 0 0000 1 1101 base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 lrstdby write reset 0000000000000000
56f8014 technical data, rev. 11 70 freescale semiconductor the lower four bits of the gpio a register can function as gpio, pwm, or as additional clock output signals. gpio has priority and is enabled/disabled via the gp ioa_peren. if gpioa[3:0] are programmed to operate as peripheral outputs, then the choice be tween pwm and addi tional clock outputs is done here in the clkout. the default state is for the peripheral functi on of gpioa[3:0] to be programmed as pwm. this can be changed by altering pwm 3 through pwm 0. figure 6-8 clko select register (sim_clkout) 6.3.7.1 reserved?bits 15?10 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.3.7.2 pwm 3?bit 9 ? 0 = peripheral output function of gpioa[3] is defined to be pwm 3 ? 1 = peripheral output function of gpioa[3] is defined to be the relaxation oscillator clock 6.3.7.3 pwm 2?bit 8 ? 0 = peripheral output function of gpioa[2] is defined to be pwm 2 ? 1 = peripheral output function of gpioa[2] is defined to be the system clock 6.3.7.4 pwm 1?bit 7 ? 0 = peripheral output function of gpioa[1] is defined to be pwm 1 ? 1 = peripheral output function of gpioa[1] is defined to be two times the rate of the system clock 6.3.7.5 pwm 0?bit 6 ? 0 = peripheral output function of gpioa[0] is defined to be pwm 0 ? 1 = peripheral output function of gpioa[0] is defi ned to be three times the rate of the system clock 6.3.7.6 clockout disable (clkdis)?bit 5 ? 0 = clkout output is enabled and will output the signal indicated by clkosel ? 1 = clkout is 0 6.3.7.7 clockout select (clkosel)?bits 4?0 selects clock to be muxed out on the clko pin. ? 00000 = reserved for factory test?continuous system clock ? 01001 = reserved for factory test?occs mstr osc clock ? 01011 = reserved for factory test?adc clock ? 01100 = reserved for factory test?jtag tclk base + $a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 pwm 3 pwm 2 pwm 1pwm 0 clk dis clkosel write reset 0000000000100000
register descriptions 56f8014 technical data, rev. 11 freescale semiconductor 71 ? 01101 = reserved for factory test?continuous peripheral clock ? 01110 = reserved for factory test?con tinuous inverted peripheral clock ? 01111 = reserved for factory test?continuous high-speed peripheral clock 6.3.8 sim gpio peripheral select register (sim_gps) all of the peripheral pins on the 56f8014 share thei r input/output (i/o) with gpio ports. to select peripheral or gpio control, progr am the corresponding bit in the gp iox_peren register in the gpio module. (see mc56f8000rm , the 56f801x peripheral reference ma nual, for details.) in some cases, there are two possible peripherals as well as the gpio functiona lity available for control of the i/o. in these cases, the sim_gps register is used to determin e which peripheral has cont rol when the corresponding i/o pin is configured in peripheral mode. as shown in figure 6-9 , the gpio peripheral enable register (peren) has the fina l control over which pin controls the i/o. sim_gps si mply decides which peripheral w ill be routed to the i/o when peren = 1. figure 6-9 overall control of pads using si m_gps control figure 6-10 gpio peripheral se lect register (sim_gps) 6.3.8.1 quad timer clock rate (tcr)?bit 15 this bit selects the clock speed for the quad timer module. ? 0 = quad timer module clock rate equals sy stem clock rate, to a maximum 32 mhz (default) ? 1 = quad timer module clock ra te equals three times sytem cl ock rate, to a maximum 96 mhz base + $b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tcr pcr 0 0 cfg_ b7 cfg_ b6 cfg_ b5 cfg_ b4 cfg_ b3 cfg_ b2 cfg_ b1 cfg_ b0 cfg_a5 cfg_a4 write reset 000000000000 0000 gpiob_peren register gpio controlled i/o pad control sim_gps register quad timer controlled sci controlled 0 1 0 1
56f8014 technical data, rev. 11 72 freescale semiconductor note: this bit should only be changed while the quad timer module?s cl ock is disabled. see section 6.3.9 . note: high-speed clocking is only availa ble when the pll is being used. note: if the pwm sync signal is used as input to time r 3 (see sim_ctrl: tc3_inp, section 6.3.1.7 ), then the clocks of the quad timer and pwm must be related, as shown in table 6-2 . 6.3.8.2 pwm clock rate (pcr)?bit 14 this bit selects the clock speed for the pwm module. ? 0 = pwm module clock rate equals system clock rate, to a maxi mum 32 mhz (default) ? 1 = pwm module clock rate equals three tim es system clock rate, to a maximum 96 mhz note: this bit should only be changed while the pwm module?s clock is disabled. see section 6.3.9 . note: high-speed clocking is only availa ble when the pll is being used. note: if the pwm sync signal is used as input to time r 3 (see sim_ctrl: tc3_inp, section 6.3.1.7 ), then the clocks of the quad timer and pwm must be related, as shown in table 6-2 . 6.3.8.3 reserved?bits 13?12 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.3.8.4 configure gpiob7 (cfg_b7)?bit 11 this bit selects the alternate function for gpiob7. ? 0 = txd ? sci transmit data (default) ? 1 = scl ? i 2 c serial clock 6.3.8.5 configure gpiob6 (cfg_b6)?bit 10 this bit selects the alternate function for gpiob6. ? 0 = rxd ? sci receive data (default) ? 1 = sda ? i 2 c serial data note: the precs bit in the occs oscillator cont rol register can enable this pin as the table 6-2 allowable quad timer and pwm clock rates when using pwm reload pulse quad timer clock speed 1x 3x pwm 1x ok ok 3x no ok
register descriptions 56f8014 technical data, rev. 11 freescale semiconductor 73 source clock to the chip. in this mode, make sure that no on-chip peripheral (including the gpio) is driving this pin. 6.3.8.6 configure gpiob5 (cfg_b5)?bit 9 this bit selects the alternate function for gpiob5. ? 0 = t1 ? timer channel 1 input/output (default) ? 1 = fault3 ? pwm fault3 input 6.3.8.7 configure gpiob4 (cfg_b4)?bit 8 this bit selects the alternate function for gpiob4. ? 0 = t0 ? timer channel 0 input/output (default) ? 1 = clko ? clock output 6.3.8.8 configure gpiob3 (cfg_b3)?bit 7 this bit selects the alternate function for gpiob3. ? 0 = mosi ? spi master out/slave in (default) ? 1 = t3 ? timer channel 3 input/output 6.3.8.9 configure gpiob2 (cfg_b2)?bit 6 this bit selects the alternate function for gpiob2. ? 0 = miso ? spi master in/slave out (default) ? 1 = t2 ? timer channel 2 input/output 6.3.8.10 configure gpiob1 (cfg_b1)?bit 5 this bit selects the alternate function for gpiob1. ? 0 = ss ? spi slave select (default) ? 1 = sda ? i 2 c serial data 6.3.8.11 configure gpiob0 (cfg_b0)?bit 4 this bit selects the alternate function for gpiob0. ? 0 = sclk ? spi serial clock (default) ? 1 = scl ? i2c serial clock 6.3.8.12 configure gpio a5[1:0] (cfg_a5)?bits 3?2 these bits select the alternate function for gpioa5. ? 00 = pwm5 ? pwm5 output (default) ? 01 = pwm5 ? pwm5 output ? 10 = fault2 ? pwm fault2 input
56f8014 technical data, rev. 11 74 freescale semiconductor ? 11 = t3 ? timer channel 3 input/output 6.3.8.13 configure gpio a4[1:0] (cfg_a4)?bits 1?0 these bits select the alternate function for gpioa4. ? 00 = pwm4 ? pwm4 output ? 01 = pwm4 ? pwm4 output ? 10 = fault1 ? pwm fault1 input ? 11 = t2 ? timer channel 2 input/output note: when programming the cfg_* signals be careful so as not to connect two different i/o pins to the same peripheral input. for example, do not set cfg_b7 to select scl and also set cfg_b0 to select scl. if this occurs for an output signal, then th e signal will be routed to two i/o pins. for input signals, the values on the two i/o pins will be ored together before r eaching the peripheral. 6.3.9 peripheral clock enable register (sim_pce) the peripheral clock enable register is used to enab le or disable clocks to the peripherals as a power savings feature. the clocks can be individually controlled for each peripheral on the chip. the corresponding peripheral should itself be disabled while its clock is shut off. figure 6-11 peripheral clock en able register (sim_pce) 6.3.9.1 i 2 c clock enable (i2c)?bit 15 ? 0 = the clock is not provided to the i 2 c module (the i 2 c module is disabled) ? 1 = clocks to the i 2 c module are enabled 6.3.9.2 reserved?bit 14 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.3.9.3 analog-to-digital converte r ipbus clock enab le (adc)?bit 13 ? 0 = the clock is not provided to the adc module (the adc module is disabled) ? 1 = clocks to the adc module are enabled 6.3.9.4 reserved?bits 12?7 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.3.9.5 timer clock enable (tmr)?bit 6 ? 0 = the clock is not provided to the quad timer module (the quad timer module is disabled) base + $c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read i2c 0 adc 0 0 0 0 0 0 tmr 0 sci 0 spi 0 pwm write reset 0000000 0 00000 0 0 0
register descriptions 56f8014 technical data, rev. 11 freescale semiconductor 75 ? 1 = clocks to the quad timer module are enabled 6.3.9.6 reserved?bit 5 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.3.9.7 sci ipbus clock enable (sci)?bit 4 ? 0 = the clock is not provided to the sci module (the sci module is disabled) ? 1 = clocks to the sc i module are enabled 6.3.9.8 reserved?bit 3 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.3.9.9 spi clock enable (spi)?bit 2 ? 0 = the clock is not provided to the spi module (the spi module is disabled) ? 1 = clocks to the spi module are enabled 6.3.9.10 reserved?bit 1 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.3.9.11 pwm clock enable (pwm)?bit 0 ? 0 = the clock is not provided to the pwm module (the pwm module is disabled) ? 1 = clocks to the pwm module are enabled 6.3.10 i/o short address locat ion register (sim_iosahi and sim_iosalo) the i/o short address locat ion registers are used to specify the memory refe renced via the i/o short address mode. the i/o short address m ode allows the instruction to spec ify the lower six bits of address; the upper address bits are not directly controllable. this register set allows limited control of the full address, as shown in figure 6-12 .
56f8014 technical data, rev. 11 76 freescale semiconductor figure 6-12 i/o short address determination with this register set, an interrupt driver can set th e sim_iosalo register pair to point to its peripheral registers and then use the i/o short addressing mode to reference them. the isr should restore this register to its previous contents prio r to returning from interrupt. note: the default value of this register set points to the eonce registers. note: the pipeline delay between setting this register set and using shor t i/o addressing with the new value is five instruction cycles. figure 6-13 i/o short address locat ion high register (sim_iosahi) 6.3.10.1 reserved?bits 15?2 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.3.10.2 input/output short addres s location (isal[2 3:22])?bit 1?0 this field represents the upper two address bi ts of the ?hard code d? i/o short address. base + $d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 isal[23:22] write reset 000000 0 0 0000 0 0 11 instruction portion ? hard coded? address portion 6 bits from i/o short address mode instruction 16 bits from sim_iosalo register 2 bits from sim_iosahi register full 24-bit for short i/o address
clock generation overview 56f8014 technical data, rev. 11 freescale semiconductor 77 figure 6-14 i/o short address locat ion low register (sim_iosalo) 6.3.10.3 input/output short addres s location (isal[2 1:6])?bit 15?0 this field represents the lower 16 address bi ts of the ?hard code d? i/o short address. 6.4 clock generation overview the sim uses master clocks, 2x system clock at a maximum of 64 mhz, from the occs module to produce the peripheral and system (c ore and memory) clocks at a maxi mum of 32 mhz. it divides the master clock by two and ga tes it with appropriate power mode and clock gati ng controls. the high speed peripheral clock input from occs operates at three times the system clock for pwm and quad timer module at a maximum of 96 mhz. the occs configuration controls the operating frequenc y of the sim?s master cl ocks. in the occs, either an external clock or the relaxation oscillator can be sel ected as the master clock source (mstr_osc). when selected, the relaxation oscilla tor can be operated at full speed (8 mhz), standby speed (200 khz), or powered down. an 8 mhz clock can be multiplied to 192 mh z using the pll and postscaled to provide a variety of high speed clock rates. either the posts caled pll output or the input clock of the pll signal can be selected to produce the mast er clocks to the sim. when the pll is not selected, the high speed peripheral clock is disabled and the 2x system clock is the input cl ock from either the internal relaxation oscillator or from an external clock source. in combination with the occs module, the sim provides power modes (see section 6.5 ), clock enables (sim_pce register, clk_dis, once_ebl), and clock rate cont rols (tcr, pcr) to provide flexible control of clocking and power utiliz ation. the sim?s clock enable c ontrols can be used to disable individual clocks when not needed. the clock rate controls en able the high speed clocking option for the timer channels and pwm but require the pll to be on a nd selected. refer to the 56f801x peripheral reference manual for further details. 6.5 power-down modes the 56f8014 operates in one of five power-down modes, as shown in table 6-3 . base + $e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read isal[21:6] write reset 111111 1 1 1111 1 1 11 table 6-3 clock operation in power-down modes mode core clocks peripheral clocks description run core and memory clocks disabled peripheral clocks enabled device is fully functional
56f8014 technical data, rev. 11 78 freescale semiconductor the power modes provide additional means to disable clock domains, configure the voltage regulator, and configure clock generation to manage power utilizati on, as shown in table 6-3 . run, wait, and stop modes provide means of enabling/di sabling the peripheral a nd/or core clocking as a group. stop disable controls are provided for selected pe ripherals in the control register so that these peri pheral clocks can optionally continue to operate in st op mode and generate interrupts wh ich will return the part from stop to run mode. standby mode provides normal operation but at very low speed and pow er utilization. it is possible to invoke stop or wait mode while in standby mode for even greater le vels of power reduction. a 200 khz clock external clock can optionally be us ed in standby mode to produce the required standby 100 khz system bus rate. po wer-down mode, which select s the rosc clock source but shuts it off, fully disables the part and minimizes its power utilization but is only recoverable via reset. when the pll is not selected and the system bus is operating at around 100 khz, the large regulator can wait core and memory clocks disabled peripheral clocks enabled core executes wait instruction to enter this mode. typically used for power-conscious applications. possible recoveries from wait mode to run mode are: 1. any interrupt 2. executing a debug mode entry command during the 56800e core jtag interface 2. any reset (por, external, software, cop) stop master clock generation in the occs remains operational, but the sim disables the generation of system and peripheral clocks. core executes stop instruction to enter this mode. possible recoveries from stop mode to run mode are: 1. interrupt from timer channels that have been configured to operate in stop mode (tcx_sd) 2. interrupt for sci configured to operate in stop mode (sci_sd) 3. low-voltage interrupt 4. executing a debug mode entry command using the 56800e core jtag interface 5. any reset (por, external, software, cop) standby the occs generates the 2x system clock at a reduced frequency (200 khz). the pll and high speed pe ripheral clocks are disabled and the high-speed peripheral option is not available. system and peripheral clocks o perate at 100 khz. the user configures the occs and sim to select the relaxation oscillator clock source (precs), shut down the pll (pllpd), put the relaxation oscillator in standby mode (rosb), and put the large regulator in standby (lrstdby). the part is fully operational, but operating at a minimum frequency and power configuration. recovery requires reversing the sequence used to enter this mode (allowing for pll lock time). power-down master clock generation in the occs is completely shut down. all system and peripheral clocks are disabled. the user configures the occs and sim to enter standby mode as shown in the previous description, followed by powering down the oscillator (ropd). the only possible recoveries from this mode are: 1. external reset 2. power-on reset table 6-3 clock operation in power-down modes (continued) mode core clocks peripheral clocks description
resets 56f8014 technical data, rev. 11 freescale semiconductor 79 be put into its standby mode (lrstdby) to re duce the power utilizati on of that regulator. all peripherals, except th e cop/watchdog timer, run at the syst em clock (periphe ral bus) frequency 1 , which is the same as the main processor freque ncy in this architecture. the cop timer runs at mstr_osc / 1024. the maximum frequency of operati on is sys_clk = 32mhz. the only exception is the quad timer and pwm, which can be configured to oper ate at three times the system bus rate using tcr and pcr controls, provided the pll is active and selected. 6.6 resets the sim supports four source s of reset, as shown in figure 6-15 . the two asynchronous sources are the external reset pin and the power-on reset (por). the two synchronous sources ar e the software reset, which is generated within the sim itself by writing the sim_ ctrl register in section 6.3.1 , and the cop reset. the sim uses these to ge nerate resets for the internal logic. these are outlined in table 6-4 . the first column lists the four primary resets which are calculated. the jtag circuitry is reset by the power-on reset. columns two through five i ndicate which reset sources trigger these reset signals. the last column provides additional detail. figure 6-15 provides a graphic illustration of the details in table 6-4 . note that the por_delay blocks use the relaxation oscillator clock as their time base since other syst em clocks are inactive during this phase of reset. 1. the quad timer and pwm modules can be operat ed at three times the ipbus clock frequency. table 6-4 primary system resets reset sources reset signal por external software cop comments extended_por x stretche d version of por . relevant 64 relaxation oscillator clock cycles after por deasserts. clkgen_rst x x x x released 32 relaxation oscillator clock cycles after all reset sources have released. perip_rst x x x x releases 32 relaxation oscillator clock cycles after the clkgen_rst is released. core_rst x x x x releases 32 sys_clk periods after perip_rst is released.
56f8014 technical data, rev. 11 80 freescale semiconductor figure 6-15 sources of r eset functional diagram (t est modes not included) por resets are extende d 64 mstr_osc clocks to st abilize the power supply. al l resets are subsequently extended for an additional 32 mstr_o sc clocks and 64 system clocks as the various internal reset controls are released. given the nor mal relaxation oscillator rate of 8mhz, the duration of a por reset from when power comes on to when code is running is 28 s. an external reset generation chip may also be used. resets may be a sserted asynchronously, but th ey are always released internally on a rising edge of the system clock. extended_por jtag memory subsystem peripherals 56800e core_rst delay 32 sys clocks occs clkgen_rst perip_rst delay 32 sys clocks pulse shaper pulse shaper sw reset pulse shaper delay 32 mstr_osc clocks pulse shaper por power-on reset (active low) external reset in (active low) cop (active low) reset delay 64 mstr_osc clocks delay blocks assert immediately and deassert only after the programmed number of clock cycles. combined_rst
clocks 56f8014 technical data, rev. 11 freescale semiconductor 81 6.7 clocks the memory, peripheral and core cl ocks all operate at the same fr equency (32mhz max) with the exception of the tmr and pw m peripheral clocks, whic h have the option (using tcr and pcr) to operate three times faster. th e sim is responsible for stalling individual clocks as a response to various hold-off requests, low power modes, and ot her configuration para meters. the sim has access to the following signals from the occs module: while the sim generates the adc peripheral clock in th e same way it generates al l other peripheral clocks, the adc standby and conversion cloc ks are generated by a direct in terface between the adc and the occs module. figure 6-16 illustrates clock relationships to one another and to the various resets as the device comes out of reset. rst is assumed to be the logical and of all active-low system rese ts (for example, por, external reset, cop and software reset). in the 56f8014 architecture, this signal will be stretched by the sim for a period of time (up to 96 mstr_osc clock cycles, depending upon the stat us of the por) to create the clock generation rese t signal (clkgen_rst ). the sim should deassert clkgen_rst synchronously with the negative edge of osc_clk in or der to avoid skew problems. clkgen_rst is delayed 32 sys_clk cycles to create the pe ripheral reset signal (perip_rst ). perip_rst is then delayed by 32 sys_clk cycles to create core_rst . both perip_rst and core_rst should be released on the negative edge of sys_clk_d as show n. this phased releasing of system resets is necessary to give some peripherals (for example, the flas h interface unit) set-up time prior to the 56800e core becoming active. mstr_osc this comes from the input clock source mux of the occs. it is the output of the relaxation oscillator or the ex ternal clock source, depending on prec s. it is not guaranteed to be at 50% duty cycle (+ or - 10% can probably be a ssumed for design purposes ). this clock runs continuously, even during reset and is used for reset generation. hs_perf the pll multiplies the mstr_osc by 24, to a maximum of 192mhz. the zsrc field in occs selects the active source to be the pl l. this is divided by 2 and postscaled to produce this maximum 96mhz clock. it is us ed without further division to produce the high-speed (3x system bus rate) variants of the quad timer and pwm peripheral clocks. this clock is disabled when zsrc is selecting mstr_osc. sys_clk_x2 the pll can multiply th e mstr_osc by 24, to a maximu m of 192mhz. when the pll is selected by the occs zsrc field, the pll is divided by three and postscaled to produce this maximum 64mhz clock. when mstr_osc is selected by the occs zsrc field, mstr_osc feeds sys_clk_x2 directly. the sim ta kes this clock and di vides it by two to generate all the normal (1x system bus rate) peripheral and system clocks.
56f8014 technical data, rev. 11 82 freescale semiconductor figure 6-16 timing relationships of reset signal to clocks 6.8 interrupts the sim generates no interrupts. part 7 security features the 56f8014 offers security features intended to prevent unauthorized users from readi ng the contents of the flash memory (fm) array. the 56 f8014?s flash security consists of several hardware interlocks that prevent unauthorized users from ga ining access to the flash array. after flash security is set, an aut horized user is still able to access on-chip memory if the user purposely includes a subroutine to read and tr ansfer the contents of internal memory via serial communication peripherals, as this code would defeat the purpose of security. 7.1 operation with security enabled after the user has programmed the flash with hi s application code, the 56f8014 can be secured by programming a security word ($e70a) into program memory location $00 1ff 7. this nonvolatile word will keep the device secured through reset and th rough power-down of the devi ce. refer to the flash rst mstr_osc ckgen_rst sys_clk_x2 sys_clk sys_clk_d sys_clk_div2 perip_rst core_rst switch on falling osc_clk 96 mstr_osc cycles switch on falling sys_clk 32 sys_clk cycles delay 32 sys_clk cycles delay maximum delay = 64 mstr_osc cycles for por reset extensi on and 32 mstr_osc cycles for combined reset extension switch on falling sys_clk
flash access lock and unlock mechanisms 56f8014 technical data, rev. 11 freescale semiconductor 83 memory chapter in mc56f8000rm , the 56f8000 peripheral reference manual for details. when flash security mode is enabled, the 56f8014 will disable the co re eonce debug capabil ities. normal program execution is othe rwise unaffected. 7.2 flash access lock and unlock mechanisms there are several methods that effectively lock or unlock the on-chip flash. 7.2.1 disabling eonce access on-chip flash can be read by issuing commands acro ss the eonce port, which is the debug interface for the 56800e cpu. the tck, tms, td o, and tdi pins comprise a jtag interface onto which the eonce port functionality is mapped. when the device boots, the chip-level jtag tap (test access port) is active and provides the chip?s boundary scan capability and access to the id register, but proper implementation of flash security will block a ny attempt to access the internal fl ash memory via the eonce port when security is enabled. 7.2.2 flash lockout recovery using jtag if the device is secured, one lockout recovery mechan ism is the complete erasure of the internal flash contents, including the confi guration field, thus di sabling security (the protecti on register is cleared). this does not compromise security, as the entire contents of the user?s secu red code stored in flash are erased before security is disabled on the devi ce on the next reset or power-up sequence. to start the lockout recovery sequence via jtag, the jtag public instruction (lockout_recovery) must first be shifted into the chip-level tap c ontroller?s instruction register. once the lockout_recovery instruction has been sh ifted into the instruct ion register, the clock divider value must be shifted into the corresponding 7- bit data register. after th e data register has been updated, the user must transition the tap controller into the r un-test/idle state for the lockout sequence to commence. the controller must remain in this state until the erase sequence has completed. refer to mc56f8000rm , the 56f8000 peripheral refe rence manual, for more details, or contact freescale. note: once the lockout recovery seque nce has completed, the user must reset both the jtag tap controller and the device to return to normal unsecured operation. power-on reset will also reset both. 7.2.3 flash lockout recovery using codewarrior codewarrior can unlock a device by selecting the debug menu, then se lecting dsp56800e, followed by unlock flash. another mechanism is also built into codewarrior using th e device?s memory configuration file. the command unlock_flash_on_connect1 in the .cfg file accomplishes the sa me task as using the debug menu. this lockout recovery mechanism al so includes the complete erasure of the internal flash contents, including the configuration field, t hus disabling security (the pr otection register is cleared). 7.2.4 flash lockout recovery without mass erase the user can un-secure a secured device by program ming the word $0000 into program memory location $00 1ff7. after completing the programming, both the jtag tap controller and the device must be reset
56f8014 technical data, rev. 11 84 freescale semiconductor in order to return to normal unsecured ope ration. power-on reset will also reset both. the user is responsible for direct ing the device to invoke the flash programming subroutine to reprogram the word $0000 into program memory location $00 1ff7. this is done by, for example, toggling a specific pin, or by downloading a user-defin ed key through serial interfaces. note: flash contents can only be programmed for 1s to 0s. 7.3 product analysis the recommended method of unsecuring a secured device for product analysis of field failures is via the method suggested in section 7.2.4. the customer would need to supply technical support with the details of the protocol to access the subroutines in flash. an alternativ e method for performing analysis on a secured device would be to mass-erase and reprogr am the flash with the orig inal code, but also either modify the security word or else not program the security word. part 8 general purpose input/output (gpio) 8.1 introduction this section is intended to supplemen t the gpio information found in the 56f801x peripheral reference manual and contains only chip-specific information. this information supe rcedes the generic information in the 56f801x peripheral reference manual . 8.2 configuration there are four gpio ports define d on the 56f8014. the width of each por t, the associated peripheral and reset functions are shown in table 8-1 . the specific mapping of gpio port pins is shown in table 8-2 . table 8-1 gpio ports configuration gpio port available pins in 56f8014 peripheral function reset function a6 pwm, reset gpio, except gpioa7 b8 spi, sci, timer gpio c8 adc analog d4 jtag jtag
configuration 56f8014 technical data, rev. 11 freescale semiconductor 85 table 8-2 gpio external signals map pins in shaded rows are not available in 56f8014 gpio function peripheral function lqfp package pin notes gpioa0 pwm0 28 defaults to a0 gpioa1 pwm1 27 defaults toa1 gpioa2 pwm2 23 defaults to a2 gpioa3 pwm3 not bonded out in 56f8014 defaults to a3 gpioa4 pwm4 / fault1 / t2 22 sim register sim_gps is used to select between pwm4, fault1, and t2 defaults to a4 gpioa5 pwm5 / fault2 / t3 20 sim register sim_gps is used to select between pwm5, fault2, and t3 defaults to a5 gpioa6 fault0 not bonded out in 56f8014 defaults to a6 gpioa7 reset 16 defaults to reset gpiob0 sclk / scl 21 sim register sim_gps is used to select between sclk and scl defaults to b0 gpiob1 ss / sda 1 sim register sim_gps is used to select between ss and sda defaults to b1 gpiob2 miso / t2 18 sim regi ster sim_gps is used to select between miso and t2 defaults to b2 gpiob3 mosi / t3 17 sim regi ster sim_gps is used to select between mosi and t3 defaults to b3 gpiob4 t0 / clko 19 sim regi ster sim_gps is used to select between t0 and clko defaults to b4 gpiob5 t1 / fault3 3 sim register sim_gps is used to select between t1 and fault3 defaults to b5
56f8014 technical data, rev. 11 86 freescale semiconductor 8.3 reset values tables 4-16 through 4-19 detail registers fo r the 56f8014; figures 8-1 through 8-4 summarize register maps and reset values. gpiob6 rxd / sda / clkin 32 sim register sim_gps is used to select between rxd and sda. clkin functionality is enabled using the pll control register within the occs block. defaults to b6 gpiob7 txd / scl 2 sim regist er sim_gps is used to select between txd and scl defaults to b7 gpioc0 ana0 13 defaults to ana0 gpioc1 ana1 12 defaults to ana1 gpioc2 ana2 / v refh 11 defaults to ana2 gpioc3 ana3 10 defaults to ana3 gpioc4 anb0 4 defaults to anb0 gpioc5 anb1 5 defaults to anb1 gpioc6 anb2 / v refl 6 defaults to anb2 gpioc7 anb3 7 defaults to anb3 gpiod0 tdi 29 defaults to tdi gpiod1 tdo 31 defaults to tdo gpiod2 tck 15 defaults to tck gpiod3 tms 30 defaults to tms table 8-2 gpio external signals map (continued) pins in shaded rows are not available in 56f8014 gpio function peripheral function lqfp package pin notes
reset values 56f8014 technical data, rev. 11 freescale semiconductor 87 figure 8-1 gpioa register map summary add. offset register acronym 151413121110987654321 0 $0 gpioa_pupen r 0 0 0 0 0 0 0 0 pu w rs 0 0 0 0 0 0 0 0 11111111 $1 gpioa_data r 0 0 0 0 0 0 0 0 d w rs 0 0 0 0 0 0 0 0 01111111 $2 gpioa_ddir r 0 0 0 0 0 0 0 0 dd w rs 0 0 0 0 0 0 0 0 00000000 $3 gpioa_peren r 0 0 0 0 0 0 0 0 pe w rs 0 0 0 0 0 0 0 0 10000000 $4 gpioa_iassrt r 0 0 0 0 0 0 0 0 ia w rs 0 0 0 0 0 0 0 0 00000000 $5 gpioa_ien r 0 0 0 0 0 0 0 0 ien w rs 0 0 0 0 0 0 0 0 00000000 $6 gpioa_iepol r 0 0 0 0 0 0 0 0 iepol w rs 0 0 0 0 0 0 0 0 00000000 $7 gpioa_ipend r 0 0 0 0 0 0 0 0 ipr w rs 0 0 0 0 0 0 0 0 00000000 $8 gpioa_iedge r 0 0 0 0 0 0 0 0 ies w rs 0 0 0 0 0 0 0 0 00000000 $9 gpioa_ppoutm r 0 0 0 0 0 0 0 0 oen w rs 0 0 0 0 0 0 0 0 11111111 $a gpioa_rdata r 0 0 0 0 0 0 0 0 raw data w rs x x x x x x x x xxxxxxxx $b gpioa_drive r 0 0 0 0 0 0 0 0 drive w rs 0 0 0 0 0 0 0 0 00000000 r 0 read as 0 w reserved rs reset
56f8014 technical data, rev. 11 88 freescale semiconductor figure 8-2 gpiob register map summary add. offset register acronym 151413121110987654321 0 $0 gpiob_pupen r 0 0 0 0 0 0 0 0 pu w rs 0 0 0 0 0 0 0 0 11111111 $1 gpiob_data r 0 0 0 0 0 0 0 0 d w rs 0 0 0 0 0 0 0 0 11111111 $2 gpiob_ddir r 0 0 0 0 0 0 0 0 dd w rs 0 0 0 0 0 0 0 0 00000000 $3 gpiob_peren r 0 0 0 0 0 0 0 0 pe w rs 0 0 0 0 0 0 0 0 00000000 $4 gpiob_iassrt r 0 0 0 0 0 0 0 0 ia w rs 0 0 0 0 0 0 0 0 00000000 $5 gpiob_ien r 0 0 0 0 0 0 0 0 ien w rs 0 0 0 0 0 0 0 0 00000000 $6 gpiob_iepol r 0 0 0 0 0 0 0 0 iepol w rs 0 0 0 0 0 0 0 0 00000000 $7 gpiob_ipend r 0 0 0 0 0 0 0 0 ipr w rs 0 0 0 0 0 0 0 0 00000000 $8 gpiob_iedge r 0 0 0 0 0 0 0 0 ies w rs 0 0 0 0 0 0 0 0 00000000 $9 gpiob_ppoutm r 0 0 0 0 0 0 0 0 oen w rs 0 0 0 0 0 0 0 0 11111111 $a gpiob_rdata r 0 0 0 0 0 0 0 0 raw data w rs x x x x x x x x xxxxxxxx $b gpiob_drive r 0 0 0 0 0 0 0 0 drive w rs 0 0 0 0 0 0 0 0 00000000 r 0 read as 0 w reserved rs reset
reset values 56f8014 technical data, rev. 11 freescale semiconductor 89 figure 8-3 gpioc register map summary add. offset register acronym 151413121110987654321 0 $0 gpioc_pupen r 0 0 0 0 0 0 0 0 pu w rs 0 0 0 0 0 0 0 0 11111111 $1 gpioc_data r 0 0 0 0 0 0 0 0 d w rs 0 0 0 0 0 0 0 0 00000000 $2 gpioc_ddir r 0 0 0 0 0 0 0 0 dd w rs 0 0 0 0 0 0 0 0 00000000 $3 gpioc_peren r 0 0 0 0 0 0 0 0 pe w rs 0 0 0 0 0 0 0 0 11111111 $4 gpioc_iassrt r 0 0 0 0 0 0 0 0 ia w rs 0 0 0 0 0 0 0 0 00000000 $5 gpioc_ien r 0 0 0 0 0 0 0 0 ien w rs 0 0 0 0 0 0 0 0 00000000 $6 gpioc_iepol r 0 0 0 0 0 0 0 0 iepol w rs 0 0 0 0 0 0 0 0 00000000 $7 gpioc_ipend r 0 0 0 0 0 0 0 0 ipr w rs 0 0 0 0 0 0 0 0 00000000 $8 gpioc_iedge r 0 0 0 0 0 0 0 0 ies w rs 0 0 0 0 0 0 0 0 00000000 $9 gpioc_ppoutm r 0 0 0 0 0 0 0 0 oen w rs 0 0 0 0 0 0 0 0 11111111 $a gpioc_rdata r 0 0 0 0 0 0 0 0 raw data w rs x x x x x x x x xxxxxxxx $b gpioc_drive r 0 0 0 0 0 0 0 0 drive w rs 0 0 0 0 0 0 0 0 00000000 r 0 read as 0 w reserved rs reset
56f8014 technical data, rev. 11 90 freescale semiconductor add. offset register acronym 151413121110987654321 0 $0 gpiod_pupen r 0 0 0 0 0 0 0 0 0 0 0 0 pu w rs 0 0 0 0 0 0 0 0 0 0 0 0 1111 $1 gpiod_data r 0 0 0 0 0 0 0 0 0 0 0 0 d w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 $2 gpiod_ddir r 0 0 0 0 0 0 0 0 0 0 0 0 dd w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 $3 gpiod_peren r 0 0 0 0 0 0 0 0 0 0 0 0 pe w rs 0 0 0 0 0 0 0 0 0 0 0 0 1111 $4 gpiod_iassrt r 0 0 0 0 0 0 0 0 0 0 0 0 ia w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 $5 gpiod_ien r 0 0 0 0 0 0 0 0 0 0 0 0 ien w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 $6 gpiod_iepol r 0 0 0 0 0 0 0 0 0 0 0 0 iepol w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 $7 gpiod_ipend r 0 0 0 0 0 0 0 0 0 0 0 0 ipr w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 $8 gpiod_iedge r 0 0 0 0 0 0 0 0 0 0 0 0 ies w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 $9 gpiod_ppoutm r 0 0 0 0 0 0 0 0 0 0 0 0 oen w rs 0 0 0 0 0 0 0 0 0 0 0 0 1111 $a gpiod_rdata r 0 0 0 0 0 0 0 0 0 0 0 0 raw data w rs x x x x x x x x x x x x xxxx $b gpiod_drive r 0 0 0 0 0 0 0 0 0 0 0 0 drive w rs 0 0 0 0 0 0 0 0 0 0 0 0 0000 r 0 read as 0 w reserved
56f8014 information 56f8014 technical data, rev. 11 freescale semiconductor 91 figure 8-4 gpiod register map summary part 9 joint test action group (jtag) 9.1 56f8014 information please contact your freescale sales representative or authorized distributor fo r device/package-specific bsdl information. the trst pin is not available in this package. the pin is tied to v dd in the package. the jtag state machine is reset during por and can also be reset via a soft reset by holding tms high for five rising edges of tck, as described in the 56f8000 peripheral user manual . part 10 specifications 10.1 general characteristics the 56f8014 is fabricated in high-de nsity cmos with 5v-tolerant ttl- compatible digital inputs. the term ?5v-tolerant? refers to the capability of an i/o pin, built on a 3.3v-c ompatible process technology, to withstand a voltage up to 5.5v without damaging the devi ce. many systems have a mixture of devices designed for 3.3v and 5v pow er supplies. in such systems, a bus may carry both 3.3v- and 5v-compatible i/o voltage levels (a standard 3.3v i/o is designed to rece ive a maximum voltage of 3.3v 10% during normal operation without causing damage ). this 5v-tolerant capability therefore offers the power savings of 3.3v i/o levels, combined with the abi lity to receive 5v le vels without damage. absolute maximum ratings in table 10-1 are stress ratings only, and f unctional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliabi lity or cause permanent damage to the device. unless otherwise stated, all specificati ons within this chapter apply over the temperature range of -40oc to 125oc ambient temperature over the following supply ranges: v ss =v ss a=0v,v dd =v dda = 3.0?3.6v, cl < 50pf, f op = 32mhz rs reset
56f8014 technical data, rev. 11 92 freescale semiconductor caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. table 10-1 absolute maximum ratings (v ss = 0v, v ssa = 0v) characteristic symbol notes min max unit supply voltage range v dd -0.3 4.0 v analog supply voltage range v dda - 0.3 4.0 v adc high voltage reference v refh - 0.3 4.0 v voltage difference v dd_io to v dda v dd - 0.3 0.3 v voltage difference v ss_io to v ssa v ss - 0.3 0.3 v input voltage range (digital inputs) v in pin groups 1, 2 - 0.3 6.0 v input voltage range (adc inputs) 1 v ina pin group 3 - 0.3 4.0 v input clamp current, per pin (v in < 0) 2 v ic --20ma output clamp current, per pin (v o < 0) 2 v oc --20ma output voltage range (normal push-pull mode) v out pin group 1 -0.3 4.0 v output voltage range (open drain mode) v outod pin groups 1, 2 -0.3 6.0 v ambient temperatur e (automotive) t a -40 125 c ambient temperature (industrial) t a -40 105 c junction temperatur e (automotive) t j -40 150 c junction temperature (industrial) t j -40 125 c storage temperatur e (automotive) t stg -55 150 c storage temperature (industrial) t stg -55 150 c
general characteristics 56f8014 technical data, rev. 11 freescale semiconductor 93 default mode pin group 1: gpio, tdi, tdo, tms, tck pin group 2: reset , gpioa7 pin group 3: adc analog inputs 10.1.1 electrostatic discharge (esd) model 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per semi g38-87 and je dec jesd51-2 with the single layer board horizontal. 3. per jedec jesc51-6 with the board horizontal. 4. thermal resistance between the die and the printed ci rcuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 1. pin group 3 can tolerate 6v for less than 5 seconds when they are configured as adc inputs or during reset. pin group 3 can tolerate 6v if they are configured as gpio. 2. continuous input current per pin is -2 ma table 10-2 56f8014 esd protection characteristic min typ max unit esd for human body model (hbm) 2000 ? ? v esd for machine model (mm) 200 ? ? v esd for charge device model (cdm) 750 ? ? v table 10-3 lqfp package thermal characteristics 6 characteristic comments symbol value (lqfp) unit notes junction to ambient natural convection single layer board (1s) r ja 74 c/w 1,2 junction to ambient natural convection four layer board (2s2p) r jma 50 c/w 1,3 junction to ambient (@200 ft/min) single layer board (1s) r jma 67 c/w 1,3 junction to ambient (@200 ft/min) four layer board (2s2p) r jma 46 c/w 1,3 junction to board r jb 23 c/w 4 junction to case r jc 20 c/w 5 junction to package top natural convection jt 4c/w6
56f8014 technical data, rev. 11 94 freescale semiconductor 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indicating the temperat ure difference between package top and the junction temperature pe r jedec jesd51-2. when greek letters are not available, the t hermal characterization parameter is written as psi-jt. 7. see section 12.1 for more details on thermal design considerations.
general characteristics 56f8014 technical data, rev. 11 freescale semiconductor 95 note: total chip source or sink current cannot exceed 50ma default mode pin group 1: gpio, tdi, tdo, tms, tck pin group 2: reset , gpioa7 pin group 3: adc analog inputs table 10-4 recommended operating conditions (v refl = 0v, v ssa = 0v, v ss = 0v ) characteristic symbol notes min typ max unit supply voltage v dd 33.3 3.6 v adc supply voltage v dda 33.3 3.6 v adc high voltage reference v refh 3?v dda v voltage difference v dd_io to v dda v dd -0.1 0 0.1 v voltage difference v ss_io to v ssa v ss -0.1 0 0.1 v device clock frequency using relaxation oscillator using external clock source fsysclk 8 0 ? 32 32 mhz input voltage high (digital inputs) v ih pin groups 1, 2 2 ? 5.5 v input voltage low (digital inputs) v il pin groups 1, 2 -0.3 ? 0.8 v output source current high (at v oh min.) when programmed for low drive strength when programmed for high drive strength i oh pin group 1 pin group 1 ? ? ? ? -4 -8 ma output source current low (at v ol max.) when programmed for low drive strength when programmed for high drive strength i ol pin groups 1, 2 pin groups 1, 2 ? ? ? ? 4 8 ma ambient operating temperature (automotive) t a -40 ? 125 c ambient operating temperature (industrial) t a -40 ? 105 c flash endurance (automotive) (program erase cycles) n f t a = -40c to 125c 10,000 ? ? cycles flash endurance (industrial) (program erase cycles) n f t a = -40c to 105c 10,000 ? ? cycles flash data retention t r t j <= 85c avg 15 ? ? years flash data retention with <100 program/erase cycles t flret t j <= 85c avg 20 ? ? years
56f8014 technical data, rev. 11 96 freescale semiconductor 10.2 dc electrical characteristics default mode pin group 1: gpio, tdi, tdo, tms, tck pin group 2: reset , gpioa7 pin group 3: adc analog inputs figure 10-1 i in /i oz vs. v in (typical; pull-up disabled) table 10-5 dc electr ical characteristics at recommended operating conditions characteristic symbol notes min typ max unit test conditions output voltage high v oh pin group 1 2.4 ? ? v i oh = i ohmax output voltage low v ol pin groups 1, 2 ? ? 0.4 v i ol = i olmax digital input current high pull-up enabled or disabled 1 1. see figure 10-1 i ih pin groups 1, 2 ? 0 +/- 2.5 av in = 2.4v to 5.5v digital input current low pull-up enabled pull-up disabled 1 i il pin groups 1, 2 -15 ? -30 0 -60 +/- 2.5 av in = 0v output current high impedance state 1 i oz pin groups 1, 2 ? 0 +/- 2.5 av out = 2.4v to 5.5v or 0v schmitt trigger input hysteresis v hys pin groups 1, 2 ? 0.35 ? v ? input capacitance c in ?10 ? pf ? output capacitance c out ?10 ? pf ? 2.0 0.0 - 2.0 - 4.0 - 6.0 - 8.0 - 10.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 6.0 3.54.04.55.05.5 a volt
dc electrical characteristics 56f8014 technical data, rev. 11 freescale semiconductor 97 table 10-6 current consumption pe r power supply pin (typical) mode conditions typical @ 3.3v, 25c maximum@ 3.6v, 25c i dd 1 1. no output switching all ports configured as inputs all inputs low no dc loads i dda i dd 1 i dda run 32mhz device clock relaxation oscillator on pll powered on continuous mac instructi ons with fetches from program flash all peripheral modules enabled. quad timer and pwm using 1x clock adc powered on and clocked 42ma 13.5ma ? ? wait 32mhz device clock relaxation oscillator on pll powered on processor core in wait state all peripheral modules enabled. quad timer and pwm using 1x clock adc powered off 17ma 0 a? ? stop 4mhz device clock relaxation oscillator on pll powered off processor core in stop state all peripheral module an d core clocks are off adc powered off 5ma 0 a? ? standby > stop 100khz device clock relaxation oscillator in standby mode pll powered off processor core in stop state all peripheral module an d core clocks are off adc powered off voltage regulator in standby mode 430 a0 a 550 a1 a powerdown device clock is off relaxation oscillator powered off pll powered off processor core in stop state all peripheral module an d core clocks are off adc powered off voltage regulator in standby mode 300 a0 a 400 a1 a
56f8014 technical data, rev. 11 98 freescale semiconductor 10.2.1 voltage regulator specifications the 56f8014 has two on-chip regulators. one supplies the pll and relaxati on oscillator. it has no external pins and therefore has no external characteristics which mu st be guaranteed (other than proper operation of the device). the second regulator supplies ap proximately 2.5 v to the 56f8014?s core logic. this regulator requires an external 2.2 f, or greater, capacito r for proper operation. ceramic and tantalum capacitors tend to provide better performance tolerances. th e output voltage can be measured directly on the v cap pin. the specifications for th is regulator are shown in table 10-8 . 10.3 ac electrical characteristics tests are conducted using the input levels specified in table 10-5 . unless otherwise specified, propagation delays are measured fr om the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in figure 10-2 . table 10-7 power-on reset low-voltage parameters characteristic symbol min typ max unit low-voltage interrupt for 3.3v supply 1 1. when v dd drops below v ei3.3 , an interrupt is generated. v ei3.3 2.60 2.7 ? v low-voltage interrupt for 2.5v supply 2 2. when v dd drops below v ei32.5 , an interrupt is generated. v e12.5 2.05 2.15 ? v low-voltage interrupt recovery hysteresis v eih ?50?mv power-on reset 3 3. power-on reset occurs whenever the internally regulated 2.5v digital supply drops below 1.8v. while power is ramping up, this signal remains active for as long as the internal 2.5v is below 2.15v or the 3.3v 1/o voltage is below 2.7v, no matter how long the ramp-up rate is. the internally regulated voltage is typically 100mv less than v dd during ramp-up until 2.5v is reached, at which time it self-regulates. por ? 1.8 1.9 v table 10-8. regulator parameters characteristic symbol min typical max unit input voltage v in 3.0 ? 3.6 v output voltage v out 2.25 2.5 2.75 v short circuit current i ss ? 450 650 ma short circuit tolerance (output shorted to ground) t rsc ? ? 30 minutes
flash memory characteristics 56f8014 technical data, rev. 11 freescale semiconductor 99 figure 10-2 input signal measurement references figure 10-3 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state ? tri-stated, when a bus or signal is placed in a high impedance state ? data valid state, when a signal level has reached v ol or v oh ? data invalid state, when a signal level is in transition between v ol and v oh figure 10-3 signal states 10.4 flash memory characteristics table 10-9 flash timing parameters characteristic symbol min typ max unit program time 1 1. there is additional overhead which is part of the programming sequence. see the 56f801x peripheral reference manual for details. t prog 20 ? 40 s erase time 2 2. specifies page erase time. there are 512 by tes per page in the program flash memory. t erase 20 ? ? ms mass erase time t me 100 ? ? ms v ih v il fall time input signal note: the midpoint is v il + (v ih ? v il )/2. midpoint1 low high 90% 50% 10% rise time data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active
56f8014 technical data, rev. 11 100 freescale semiconductor 10.5 external clock operation timing figure 10-4 external clock timing 10.6 phase locked loop timing table 10-10 external clock op eration timing requirements 1 1. parameters listed are guaranteed by design. characteristic symbol min typ max unit frequency of operation (external clock driver) 2 2. see figure 10-4 for details on using the recommended connection of an external clock driver. f osc 488mhz clock pulse width 3 3. the high or low pulse width must be no smaller than 6.25ns or the chip may not function. t pw 6.25 ? ? ns external clock input rise time 4 4. external clock input rise time is measured from 10% to 90%. t rise ?? 3ns external clock input fall time 5 5. external clock input fall time is measured from 90% to 10%. t fall ?? 3ns table 10-11 pll timing characteristic symbol min typ max unit internal reference relaxation oscillator frequency for the pll f rosc ?8?mhz pll output frequency 1 (24 x reference frequency) 1. the core system clock will operate at 1/6 of the pll output frequency. f op ?192?mhz pll lock time 2 2. this is the time required after the pll is enabled to ensure reliable operation. t lock ? 40 100 s cycle to cycle jitter t jitterpll 350 ps external clock v ih v il note: the midpoint is v il + (v ih ? v il )/2. 90% 50% 10% 90% 50% 10% t pw t pw t fall t rise
relaxation oscillator timing 56f8014 technical data, rev. 11 freescale semiconductor 101 10.7 relaxation oscillator timing figure 10-5 relaxation oscill ator temperature variat ion (typical) after trim table 10-12 relaxation oscillator timing characteristic symbol minimum typical maximum unit relaxation oscillator output frequency normal mode 1 standby mode 1. output frequency after factory trim. f op ? 8.05 200 ? mhz khz relaxation oscillator stabilization time 2 2. this is the time required from standby to normal mode transition. t roscs ?1 3s cycle-to-cycle jitter. this is measured on the clko signal (program med prescaler_clock) over 264 clocks 3 3. j a is required to meet sci requirements. t jitterrosc ?400 ps minimum tuning step size .08 % maximum tuning step size 40 % variation over temperature -40 c to 150 c 4 4. see figure 10-5 . +1.0 to -1.5 +3.0 to -3.0 % variation over temperature 0 c to 105 c 4 0 to +1 +2.0 to -2.0 % 8.16 8.08 8 7.92 7.84 175 -25 -50 0 50 75 100 125 150 25 degrees c (junction) mhz
56f8014 technical data, rev. 11 102 freescale semiconductor 10.8 reset, stop, wait, mode select, and interrupt timing note: all the address and data bus es described here are internal. figure 10-6 gpio interrupt timi ng (negative edge-sensitive) table 10-13 reset, stop, wait, mode select, and interrupt timing 1,2 1. in the formulas, t = clock cycle and t osc = oscillator clock cycle. for an operating frequency of 32mhz, t = 31.25ns. at 8mhz (used during reset and stop modes), t = 125ns. 2. parameters listed are guaranteed by design. characteristic symbol typical min typical max unit see figure minimum reset assertion duration t ra 4t ? ns minimum gpio pin assertion for interrupt t iw 2t ? ns 10-6 reset deassertion to first address fetch 3 3. during power-on reset, it is possible to use the 56f8014 internal reset stretching circuitry to extend this period to 2^21t. t rda 96t osc + 64t 97t osc + 65t ns delay from interrupt assertion to fetch of first instruction (exiting stop) t if ?6tns gpio pin (input) t iw
serial peripheral interface (spi) timing 56f8014 technical data, rev. 11 freescale semiconductor 103 10.9 serial peripheral interface (spi) timing table 10-14 spi timing 1 characteristic symbol min max unit see figure cycle time master slave t c 125 62.5 ? ? ns ns 10-7 , 10-8 , 10-9 , 10-10 enable lead time master slave t eld ? 31 ? ? ns ns 10-10 enable lag time master slave t elg ? 125 ? ? ns ns 10-10 clock (sck) high time master slave t ch 50 31 ? ? ns ns 10-7 , 10-8 , 10-9 , 10-10 clock (sck) low time master slave t cl 50 31 ? ? ns ns 10-10 data set-up time required for inputs master slave t ds 20 0 ? ? ns ns 10-7 , 10-8 , 10-9 , 10-10 data hold time required for inputs master slave t dh 0 2 ? ? ns ns 10-7 , 10-8 , 10-9 , 10-10 access time (time to data active from high-impedance state) slave t a 4.8 15 ns 10-10 disable time (hold time to high-impedance state) slave t d 3.7 15.2 ns 10-10 data valid for outputs master slave (after enable edge) t dv ? ? 4.5 20.4 ns ns 10-7 , 10-8 , 10-9 , 10-10 data invalid master slave t di 0 0 ? ? ns ns 10-7 , 10-8 , 10-9 , 10-10 rise time master slave t r ? ? 11.5 10.0 ns ns 10-7 , 10-8 , 10-9 , 10-10 fall time master slave t f ? ? 9.7 9.0 ns ns 10-7 , 10-8 , 10-9 , 10-10
56f8014 technical data, rev. 11 104 freescale semiconductor 1 figure 10-7 spi master timing (cpha = 0) 1. parameters listed are guaranteed by design. sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in t f t c t cl t cl t r t r t f t ds t dh t ch t di t dv t di (ref) t r master msb out bits 14?1 master lsb out ss (input) t ch ss is held high on master t f
serial peripheral interface (spi) timing 56f8014 technical data, rev. 11 freescale semiconductor 105 figure 10-8 spi master timing (cpha = 1) figure 10-9 spi slave timing (cpha = 0) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in t r t c t cl t cl t f t ch t dv (ref) t dv t di (ref) t r t f master msb out bits 14? 1 master lsb out ss (input) t ch ss is held high on master t ds t dh t di t r t f sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 t c t cl t cl t f t ch t di msb in bits 14?1 lsb in ss (input) t ch t dh t r t elg t eld t f slave lsb out t d t a t ds t dv t di t r
56f8014 technical data, rev. 11 106 freescale semiconductor figure 10-10 spi slave timing (cpha = 1) 10.10 quad timer timing table 10-15 timer timing 1, 2 1. in the formulas listed, t = the clock cycle. for 32mhz operation, t = 31.25ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit see figure timer input period p in 2t + 6 ? ns 10-11 timer input high / low period p inhl 1t + 3 ? ns 10-11 timer output period p out 125 ? ns 10-11 timer output high / low period p outhl 50 ? ns 10-11 sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 t c t cl t cl t ch t di msb in bits 14?1 lsb in ss (input) t ch t dh t f t r slave lsb out t d t a t eld t dv t f t r t elg t dv t ds
quad timer timing 56f8014 technical data, rev. 11 freescale semiconductor 107 figure 10-11 timer timing p out p outhl p outhl p in p inhl p inhl timer inputs timer outputs
56f8014 technical data, rev. 11 108 freescale semiconductor 10.11 serial communication interface (sci) timing figure 10-12 rxd pulse width figure 10-13 txd pulse width table 10-16 sci timing 1 1. parameters listed are guaranteed by design. characteristic symbol min max unit see figure baud rate 2 2. f max is the frequency of operation of the system clock in mhz, which is 32mhz for the 56f8014 device. br ? (f max /16) mbps ? rxd 3 pulse width 3. the rxd pin in sci0 is named rxd0 and the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns 10-12 txd 4 pulse width 4. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. txd pw 0.965/br 1.04/br ns 10-13 lin slave mode deviation of slave node clock from nominal clock rate before synchronization f tol_unsyn ch -14 14 % deviation of slave node clock relative to the master node clock after synchronization f tol_synch -2 2 % minimum break character length t break 13 master node bit periods 11 slave node bit periods rxd pw rxd sci receive data pin (input) txd pw txd sci receive data pin (input)
inter-integrated circuit interface (i2c) timing 56f8014 technical data, rev. 11 freescale semiconductor 109 10.12 inter-integrated circuit interface (i 2 c) timing table 10-17 i 2 c timing characteristic symbol standard mode fast mode unit minimummaximumminimummaximum scl clock frequency f scl 0 100 0 400 khz hold time (rep eated ) start condition. after this period, the first clock pulse is generated. t hd; sta 4.0 0.6 s low period of the scl clock t low 4.7 1.25 s high period of the scl clock t high 4.0 0.6 s set-up time for a repeated start condition t su; sta 4.7 0.6 s data hold time for i 2 c bus devices t hd; dat 0 1 1. a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ih min of the scl signal) to bridge the undefined region of the falling edge of scl. 3.45 2 2. the maximum t hd; dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 0 1 0.9 2 s data set-up time t su; dat 250 100 3 3. a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but the requirement t su; dat > = 250ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device d oes stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250ns (according to the standard mode i 2 c bus specification) before the scl line is released. ns rise time of both sda and scl signals t r 1000 2 +0.1c b 4 4. c b = total capacitance of the one bus line in pf. 300 ns fall time of both sda and scl signals t f 300 2 +0.1c b 4 300 ns set-up time for stop condition t su; sto 4.0 0.6 s bus free time between stop and start condition t buf 4.7 1.3 s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a 0.0 50 ns
56f8014 technical data, rev. 11 110 freescale semiconductor figure 10-14 timing definiti on for fast and standard mode devices on the i 2 c bus 10.13 jtag timing figure 10-15 test clo ck input timing diagram table 10-18 jtag timing characteristic symbol min max unit see figure tck frequency of operation 1 1. tck frequency of operation must be less than 1/8 the processor rate. f op dc sys_clk/8 mhz 10-15 tck clock pulse width t pw 50 ? ns 10-15 tms, tdi data set-up time t ds 5?ns 10-16 tms, tdi data hold time t dh 5?ns 10-16 tck low to tdo data valid t dv ?30ns 10-16 tck low to tdo tri-state t ts ?30ns 10-16 sda scl t hd; sta t hd; dat t low t su; dat t high t su; sta br p s s t hd; sta t sp t su; sto t buf tck (input) v m v il v m = v il + (v ih ? v il )/2 t pw 1/f op t pw v m v ih
jtag timing 56f8014 technical data, rev. 11 freescale semiconductor 111 figure 10-16 test access port timing diagram input data valid output data valid t ds t dh t dv t ts tck (input) tdi (input) tdo (output) tdo (output ) tms
56f8014 technical data, rev. 11 112 freescale semiconductor 10.14 analog-to-digital converter (adc) parameters table 10-19 adc parameters 1 1. all measurements were made at v dd = 3.3v, v refh = 3.3v, and v refl = ground parameter symbol min typ max unit dc specifications resolution r es 12 ? 12 bits adc internal clock f adic 0.1 ? 5.33 mhz conversion range r ad v refl ?v refh v adc power-up time 2 2. includes power-up of adc and v ref t adpu ?6 13 t aic cycles 3 3. adc clock cycles recovery from auto standby t rec ?0 1 t aic cycles 3 conversion time t adc ?6 ? t aic cycles 3 sample time t ads ?1 ? t aic cycles 3 accuracy integral non-linearity 4 (full input signal range) 4. inl measured from v in = v refl to v in = v refh inl ? +/- 3 +/- 5 lsb 5 differential non-linearity dnl ? +/- .6 +/- 1 lsb 5 monotonicity guaranteed offset voltage internal ref v offset ? +/- 4 +/- 9 mv offset voltage external ref v offset ? +/- 6 +/- 12 mv gain error (transfer gain) e gain ? .998 to 1.002 1.01 to .99 ? adc inputs 6 (pin group 3) input voltage (external reference) v adin v refl ?v refh v input voltage (internal reference) v adin v ssa ?v dda v input leakage i ia ?0 +/- 2 a v refh current i vrefh ?0 ? a input injection current 7 , per pin i adi ?? 3ma input capacitance c adi ? see figure 10-17 ?pf input impedance x in ? see figure 10-17 ?ohms ac specifications signal-to-noise ratio snr 60 65 db total harmonic distortion thd 60 64 db spurious free dynamic range sfdr 61 66 db signal-to-noise plus distortion sinad 58 62 db effective number of bits enob ? 10.0 bits
equivalent circuit for adc inputs 56f8014 technical data, rev. 11 freescale semiconductor 113 10.15 equivalent circuit for adc inputs figure 10-17 illustrates the adc input circ uit during sample and hold. s1 and s2 are always open/closed at the same time that s3 is clos ed/open. when s1/s2 are closed & s3 is open, one input of the sample and hold circuit moves to (v refh -v refl )/2, while the other charges to th e analog input voltage. when the switches are flipped, the charge on c1 and c2 are averaged via s3, wi th the result that a single-ended analog input is switched to a diff erential voltage centered about (v refh -v refl )/2. the switches switch on every cycle of the adc clock ( open one-half adc clock, cl osed one-half adc cloc k). note that there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the s/h output voltage, as s1 provides is olation during the charge-sharing phase. one aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, v ref and the adc clock frequency. 5. lsb = least significant bit = 0.806mv 6. pin groups are detailed following table 10-1 . 7. the current that can be injected or sourced from an unselec ted adc signal input without impacting the performance of the adc.
56f8014 technical data, rev. 11 114 freescale semiconductor 1. parasitic capacitance due to package, pin- to-pin and pin-to-package base coupling; 1.8pf 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing; 2.04pf 3. equivalent resistance for the channel select mux; 100 ohms 4. sampling capacitor at the sample and hold circuit. capaci tor c1 is normally disconnected from the input and is only connected to it at sampling time; 1.4pf 5. equivalent input impedance, when the the input is selected = figure 10-17 equivalent ci rcuit for a/d loading 10.16 power consumption see section 10.1 for a list of idd requirements for the 56f8014. this section provides additional detail which can be used to optimize power consumption for a given application. power consumption is given by the following equation: total power = a: interna l [static component] +b: internal [state-d ependent component] 125 ohm esd resistor equivalent circuit for a/d loading channel mux equiv resistance 100 ohms (v refhx -v reflx ) / 2 c1 s/h s1 1 2 3 adc input 1. parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8 pf 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing; 2.04pf 3. 8 pf noise damping capacitor 4. c1 = 1.4 pf 5. s1 and s2 switch phases are non-overlapping and operate at the adc clock frequency s1 s2 s2 c1 : singled ended mode 2 x c1 : differential mode s1 s1 c1 c1 : singled ended mode 2 x c1 : differential mode s1 s2 6. equivalent input impedance, when the input is selected = ohm ohm rate clock adc 125 100 12 10 4 . 1 ) ( 1 + + ? 1 (adc clock rate) x 1.4 x 10 -12 please see http://www.freescale.com for the most current mechanical drawing.
power consumption 56f8014 technical data, rev. 11 freescale semiconductor 115 a, the internal [static component], is comprised of the dc bias currents for the oscillator, leakage currents, pll, and voltage referen ces. these sources operate independent ly of processor state or operating frequency. b, the internal [state-dependent component], re flects the supply current required by certain on-chip resources only when those resources are in use. these include ram, flash memory and the adcs. c, the internal [dynamic component], is classic c*v 2 *f cmos power dissipation corresponding to the 56800e core and standard cell logic. d, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. this is also commonly described as c*v 2 *f, although simulations on two of the i/o cell types used on the 56800e reveal that the power-versus-load curv e does have a non-zero y-intercept. power due to capacitive loading on output pins is (first order) a f unction of the capacitive load and frequency at which the outputs change. table 10-20 provides coefficients for calculating power dissipated in the i/o cells as a function of capacitive load. in these cases: totalpower = ((intercept + slope*cload)*frequency/10mhz) where: ? summation is performed over all ou tput pins with capacitive loads ? totalpower is expressed in mw ? cload is expressed in pf because of the low duty cycle on most device pins , power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. e, the external [static component], reflects the effects of placing resistive load s on the outputs of the device. sum the total of all v 2 /r or iv to arrive at the resistive load contribution to power. assume v = 0.5 for the purposes of these rough calculations. for instance, if there is a total of eight pwm outputs driving 10ma into leds, then p = 8*.5*.01 = 40mw. +c: internal [dynamic component] +d: external [dynamic component] +e: external [static] table 10-20 i/o loading coefficients at 10mhz intercept slope 8ma drive 1.3 0.11mw / pf 4ma drive 1.15mw 0.11mw / pf
56f8014 technical data, rev. 11 116 freescale semiconductor in previous discussions, power consum ption due to parasitics associated with pure input pins is ignored, as it is assumed to be negligible.
56f8014 package and pin-out information 56f8014 technical data, rev. 11 freescale semiconductor 117 part 11 packaging 11.1 56f8014 package an d pin-out information this section contains package and pin-out inform ation for the 56f8014. this de vice comes in a 32-pin low-profile quad flat pack (lqfp). figure 11-1 shows the package outli ne for the 32-pin lqfp, figure 11-2 shows the mechanical parameters for this package, and table 11-1 lists the pin-out for the 32-pin lqfp. figure 11-1 top view, 56f 8014 32-pin lqfp package pin 1 orientation mark pin 25 pin 1 7 pin 9 gpiob1 / ss/ sda gpiob7 / txd/scl gpiob5 /t1/fault3 anb0 /gpioc4 anb1 /gpioc5 anb2 /v refl /gpioc6 anb3 /gpioc7 v dda gpiob3 / mosi/t3 gpiob2 / miso/t2 gpiob4 / t0/clko gpioa5 / pwm5/fault2/t3 gpiob0 / sclk/scl gpioa4 / pwm4/fault1/t2 gpioa2 / pwm2 v cap gpioa0 / pwm0 v dd_io gpioa1 / pwm1 v ss_io tdi/ gpiod0 tms / gpiod3 tdo / gpiod1 gpiob6 / rxd/sda/clkin v ssa ana3 /gpioc3 ana2 /v refh /gpioc2 ana1 / gpioc1 ana0 / gpioc0 v ss_io tck / gpiod2 reset / gpioa7 note: alternate signals are in italic
56f8014 technical data, rev. 11 118 freescale semiconductor table 11-1 56f8014 32-pin lqfp package identifi cation by pin number 1 1.alternate signals are in iltalic pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1 gpiob1 ss, sda 9 v ssa 17 gpiob3 mosi,t3 25 v dd_io 2 gpiob7 txd,scl 10 ana3 gpioc3 18 gpiob2 miso,t2 26 v ss_io 3 gpiob5 t1,fault3 11 ana2 v refh ,gpioc2 19 gpiob4 t0,clko 27 gpioa1 pwm1 4 anb0 gpioc4 12 ana1 gpioc1 20 gpioa5 pwm5,fault2,t3 28 gpioa0 pwm0 5 anb1 gpioc5 13 ana0 gpioc0 21 gpiob0 sclk/,cl 29 tdi gpiod0 6 anb2 v refl ,gpioc6 14 v ss_io 22 gpioa4 pwm4/fault1/t2 30 tms gpiod3 7 anb3 gpioc7 15 tck gpiod2 23 gpioa2 pwm2 31 tdo gpiod1 8 v dda 16 reset gpioa7 24 v cap 32 gpiob6 rxd,sda,clkin
56f8014 package and pin-out information 56f8014 technical data, rev. 11 freescale semiconductor 119 figure 11-2 56f8014 32- pin lqfp mechanical information detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae?ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?ab? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?t?, ?u?, and ?z? to be determined at datum plane ?ab?. 5. dimensions s and v to be determined at seating plane ?ac?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?ab?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc detail ad a1 b1 v1 4x s 4x b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref 9 ?t? ?z? ?u? t?u 0.20 (0.008) z ac t?u 0.20 (0.008) z ab 0.10 (0.004) ac ?ac? ?ab? m 8x ?t?, ?u?, ?z? t?u m 0.20 (0.008) z ac
56f8014 technical data, rev. 11 120 freescale semiconductor part 12 design considerations 12.1 thermal desi gn considerations an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + (r j x p d ) where : the junction-to-ambient thermal resi stance is an industry-standard va lue that provides a quick and easy estimation of thermal perf ormance. unfortunately, there are two values in common usage: the value determined on a single-layer board and the value obtained on a board wi th two planes. for packages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. th e value obtained on a single layer board is appropriate for the tightly packed printed circuit board. the va lue obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: r ja = r jc + r ca where : r jc is device related and ca nnot be influenced by the user. the user controls the thermal e nvironment to change the case to ambient thermal resistance, r ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface mate rial, the mounting arrange ment on printed circuit board, or change the thermal dissipation on th e printed circuit board surrounding the device. to determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter ( jt ) can be used to determine th e junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt x p d ) where : t a = ambient temperature for the package ( o c) r j = junction-to-ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) r ja = package junction-to-ambient thermal resistance (c/w) r jc = package junction-to-case thermal resistance (c/w) r ca = package case-to-ambient thermal resistance (c/w) t t = thermocouple temperature on top of package ( o c)
electrical design considerations 56f8014 technical data, rev. 11 freescale semiconductor 121 the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top ce nter of the package case. the th ermocouple should be positioned so that the thermocouple junction re sts on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. when heat sink is used, the junction temperature is determined from a ther mocouple inserted at the interface between the case of the p ackage and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearan ce is important to mi nimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with th is technique, many engine ers measure the heat si nk temperature and then back-calculate the case temperatur e using a separate measurement of the thermal resistance of the interface. from this case temperat ure, the junction temperature is de termined from th e junction-to-case thermal resistance. 12.2 electrical design considerations use the following list of considerations to assure correct operation of the 56f8014: ? provide a low-impedance path from the board power supply to each v dd pin on the 56f8014 and from the board ground to each v ss (gnd) pin ? the minimum bypass requirement is to place 0.01?0.1 f capacitors positioned as close as possible to the package supply pins. the recommended bypass configura tion is to place one bypass capacitor on each of the v dd /v ss pairs, including v dda /v ssa. ceramic and tantalum capacito rs tend to provide better tolerances. ? ensure that capacitor leads and associated prin ted circuit traces that connect to the chip v dd and v ss (gnd) pins are as short as possible ? bypass the v dd and v ss with approximately 100 f, plus the number of 0.1 f ceramic capacitors jt = thermal characterization parameter ( o c/w) p d = power dissipation in package (w) caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
56f8014 technical data, rev. 11 122 freescale semiconductor ? pcb trace lengths should be mini mal for high-frequency signals ? consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in system s with higher capacitive loads that co uld create higher transient currents in the v dd and v ss circuits. ? take special care to minimize noise levels on the v ref , v dda and v ssa pins ? using separate power planes for v dd and v dda and separate ground planes for v ss and v ssa is recommended. connect the separate analog and digital power and ground planes as close as possible to power supply outputs. if both analog circuit and dig ital circuit are powered by the same power supply, it is advisable to connect a small inductor or ferrite bead in serial with both v dda and v ssa traces. ? it is highly desirable to physically separate analog components from noisy digital components by ground planes. do not place an analog trace in parallel with digital traces. it is also desirable to place an analog ground trace around an analog signal trace to isolate it from digital traces. ? because the flash memory is programmed through the jtag/eonce port, spi, sci or i 2 c, the designer should provide an interface to this port if in-circuit flash pr ogramming is desired.
electrical design considerations 56f8014 technical data, rev. 11 freescale semiconductor 123 part 13 ordering information table 13-1 lists the pertinent information needed to pl ace an order. consult a freescale semiconductor sales office or authorized di stributor to determine availability and to order parts. *this package is rohs compliant. part 14 appendix register acronyms are revised from previous device data sheets to pr ovide a cleaner register description. a cross reference to legacy and revised acronyms are provided in the following table. table 13-1 56f8014 ordering information part supply voltage package type pin count frequency (mhz) abient temperature range order number mc56f8014 3.0?3.6 v low-profile quad flat pack (lqfp) 32 32 -40 to + 105 c mc56f8014vfae* mc56f8014 3.0?3.6 v low-profile quad flat pack (lqfp) 32 32 ?40 to +125 c mc56f8014mfae* module register name peripheral reference manual data sheet processor expert acronym memory address new acronym legacy acronym new acronym legacy acronym start end adc control register 1 ctrl1 adcr1 adc_ctrl1 adc_adcr1 adc_adcr1 0xf080 control register 2 ctrl2 adcr2 adc_ctrl2 adc_adcr2 adc_adcr2 0xf081 zero crossing control register zxctrl adzcc adc_zxctrl adc_adzcc adc_adzcc 0xf082 channel list register 1 clist1 adlst1 adc_clist1 adc_adlst1 adc_adlst1 0xf083 channel list register 2 clist2 adlst2 adc_clist2 adc_adlst2 adc_adlst2 0xf084 sample disable register sdis adsdis adc_sdis adc_adsdis adc_adsdis 0xf085 status register stat adstat adc_stat adc_adstat adc_adstat 0xf086 limit status register limstat adlstat adc_limstat adc_adlstat adc_adlstat 0xf087 zero crossing status register zxstat adzcstat adc_zxstat adc_adzcstat adc_adzcstat 0xf088 result registers 0-7 rslt0-7 adrslt0-7 adc_rs lt0-7 adc_adrslt0-7 adc_adrslt0-7 0xf089 0xf090 low limit registers 0-7 lolim0-7 adllmt0-7 adc_lolim0-7 adc_adllmt0-7 adc_adllmt0-7 0xf091 0xf098 high limit registers 0-7 hilim0-7 adhlmt0-7 adc_hilim0-7 adc_adhlmt0-7 adc_adhlmt0-7 0xf099 0xf0a0 offset registers 0-7 offst0-7 adofs0-7 adc_offst0-7 adc_adofs0-7 adc_adofs0-7 0xf0a1 0xf0a8 power control register pwr adpower adc_pwr adc_adpower adc_adpower 0xf0a9 voltage reference register cal adcal adc_vref adc_adcal adc_cal 0xf0aa cop control register ctrl copctl cop_ctrl copctl copctl 0xf0e0 time-out register tout copto cop_tout copto copto 0xf0e1 counter register cntr copctr cop_cntr copctr copctr 0xf0e2
how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc. 2005. all rights reserved. mc56f8014 rev. 11 05/2008 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical ex perts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp .

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