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12 - bit , integrated, multiformat sdtv/hdtv video decoder and rgb graphics digitizer data sheet adv7403 features 4 noise shaped video (nsv) ? 12- bit analog - to - digital converters ( adcs ) sampling up to 140 mhz (140 mhz speed grade only) mux with 12 analog input channel s scart fast blank support internal antialias filters ntsc/pal/secam color standards support 525p/625p component progressive scan support 720p/1080i component hdtv support digitizes rgb graphics up to 1280 1024 at 75 hz (sxga) (140 mhz speed grade only) 24- bit digital input port supports data from dvi/hdmi receiver ic any - to - any, 3 3 color - spa ce conversion matrix industrial te mperature range : ? 40 c to +85c 12- bit 4:4:4 and 10 - /8 - bit 4:2:2 ddr pixel output interface programmable interrupt request output pin v ertical blanking interval ( vbi ) data slicer , including teletext applications lcd/dlp? rear projection hdtvs pdp hdtvs crt hdtvs lcd/dlp front projectors lcd tv (hdtv ready) hdtv stbs with pvr hard - disk - based video recorders multiformat scan converters dvd recorders with progressive scan input support avr receiver s general description the adv7403 is a high quality, single chip, multiformat video decode r and graphics digitizer. this multiformat decoder supports the conversion of pal, ntsc, and secam standards in the for m of composi te or s - v ideo into a digital itu - r bt.656 format . the adv7403 also supports the decoding of a component rgb/yprpb video signal into a digital ycrcb or rgb pixel output stream. the support for c omponent video includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i, 1250i, and many other hd and smpte standards. graphic digitization is also supported by the adv7403 ; it is capable of digitizing rgb graphics signals from vga to sxga rates and converting them into a digital rgb or ycrcb pixel output stream. scart and overlay functionality are enabled by the ability of the adv7403 to simultaneously process cvbs and standard definition rgb signals. the fast blank pin controls the mixing of these signals. the adv7403 contains two main processing sections. the firs t is the standard definition processor (sdp), which processes all pal, ntsc, and secam signal types , and t he second is the component processor (cp), which processes yprpb and rgb component formats, including rgb graphics. for additional descriptions of the features of the adv7403 , see the functional overview and the theory of operation sections. rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no licens e is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.32 9.4700 ? 2005 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com
adv7403 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 electrical characteristics ............................................................. 4 video specifications ..................................................................... 5 timing characteristics ................................................................ 6 analog specifications ................................................................... 8 absolute maximum ratings ............................................................ 9 package thermal performance ................................................... 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 functional overview ...................................................................... 12 analog front end ....................................................................... 12 standard definition processor (sdp) pixel data output modes ........................................................................................... 12 component processor (cp) pixel data output modes ........ 1 2 composite and s - video processing ......................................... 12 component video processing .................................................. 12 rgb graphics processing ......................................................... 13 dig ital video input port ............................................................ 13 general features ......................................................................... 13 theory of operation ...................................................................... 14 analog front end ....................................................................... 14 standard definition processor (sdp) ...................................... 14 component processor (cp) ...................................................... 14 pixel input/output formatting .................................................... 16 recommended external loop filter components .................... 18 typical connection di agram ........................................................ 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 9 / 13 revision b : initial ver sion rev. b | page 2 of 20
data sheet adv7403 functional block dia gram input mux d at a preprocessor decim a tion and downsampling fi l ters s t andard definition processor lum a fi l ter output fifo and form a tter ain1 t o ain12 adv7403 seria l inter f ace contro l and vbi d at a sclk1 sda1 alsb sync extract 20 cs/hs 8 8 p29 t o p20 p19 t o p10 p9 t o p0 pixe l d at a vs field/de llc1 sfl/ syncout cvbs s-video yprpb scart? (rgb + cvbs) graphics rgb 12 chrom a fi l ter chrom a demod f sc recove r y int lum a resample lum a 2d comb (5h max) resample contro l chrom a resample chrom a 2d comb (4h max) f ast blank overl a y contro l and a v code insertion fb y cb cr vbi d at a recove r y macrovision detection s t andard au t odetection cvbs/ y c cb cr cb y colors p ace conversion cvbs cr 8 component processor sclk2 sda2 sspd stdi sync processing and clock gener a tion dclk_in de_in hs_in/cs_in vs_in sog so y digi t a l input port dvi or hdmi x t a l x t al1 24 8 8 8 digi t a l fine clam p gain contro l offset contro l a v code insertion 30 12 12 12 12 12 12 12 active peak and agc macrovision detection cgms d at a extraction p40 t o p31 p29 t o p20 p 1 1 t o p10 p1 t o p0 12 a/d clam p anti- alias fi l ter 12 a/d clam p anti- alias fi l ter 12 a/d clam p anti- alias fi l ter 12 a/d clam p anti- alias fi l ter 05431-001 figure 1. rev. b | page 3 of 20
adv7403 data sheet specifications electrical character istics avdd = 3.15 v to 3.45 v, dvdd = 1.65 v to 2.0 v, dvddio = 3.0 v to 3.6 v, pvdd = 1.71 v to 1.89 v, nominal input range 1.6 v. o perating temperat ure range, unless otherwise noted is t min to t max : ?40c to +85c (0c to 70c temperature range for adv7403 kstz - 140) . to obtain all specifications the following write sequence must be included in the programming scripts: address 0x0e to data 0x80, address 0x54 to data 0x00, and address 0x0e to data 0x00 . table 1 . parameter symbol test conditions/comments min typ max unit static performance 1 resolution ( e ach adc) n 12 2 bits integral nonlinearity inl best st raight line ( bsl ) at 27 mhz at a 12 - bit level 2.0 8.0 2 lsb bsl at 54 mhz at a 12 - bit level ?2.0/+2.5 lsb bsl at 74 mhz at a 10 - bit level 1.0 lsb bsl at 110 mhz at a 10 - bit level ?3.0/+3.0 lsb bsl at 135 mhz at an 8 - bit level 3 1.3 lsb differential nonlinearity dnl at 27 mhz at a 12 - bit level ? 0.7/+0.85 ?0.99/+2.5 2 lsb at 54 mhz at a 12 - bit level ?0.75/+0.9 lsb at 74 mhz at a 10 - bit level 0.75 lsb at 110 mhz at a 10 - bit level ?0.7/+5.0 lsb at 135 mhz at an 8 - bit level 3 ?0.8/+2.5 lsb digital inputs input high voltage 4 v ih 2 v input low voltage 5 v il 0.8 v input high voltage v ih hs_in, vs_in low trigger mode 0.7 v input low voltage v il hs_in, vs_in low trigger mode 0.3 v input current i in p20 to p29, p31 to p40, sclk2, sda2, dclk_in, de_in, reset ?60 +60 a all other input pins ?10 +10 a input capacitance 6 c in 10 pf digital outputs output high voltage 7 v oh i source = 0.4 ma 2.4 v output low voltage 7 v ol i sink = 3.2 ma 0.4 v high impedance leakage current i leak int , p20 to p29, sda2 60 a all other output pins 10 a output capacitance 6 c out 20 pf power requirements 6 digital core power supply dvdd 1.65 1.8 2 v digital input/output power supply dvddio 3.0 3.3 3.6 v pll power supply pvdd 1.71 1.8 1.89 v analog power suppl y avdd 3.15 3.3 3.45 v digital core supply current i dvdd cvbs input sampling at 54 mhz 105 ma graphics rgb sampling at 135 mhz 137 ma scart rgb fb sampling at 54 mhz 106 ma digital input/output supply current i dvddio cvbs input sampling at 5 4 mhz 4 ma graphics rgb sampling at 135 mhz 19 ma pll supply current i pvdd cvbs input sampling at 54 mhz 11 ma graphics rgb sampling at135 mhz 12 ma rev. b | page 4 of 20
data sheet adv7403 parameter symbol test conditions/comments min typ max unit analog supply current 8 i avdd cvbs input sampling at 54 mhz 99 ma graphics rgb sampli ng at 135 mhz 242 ma scart rgb fb sampling at 54 mhz 269 ma power - down current i pwrdn 2.25 ma green mode power - down i pwrdng sync bypass function 16 ma power - up time t pwrup 20 ms 1 all adc linearity tests performed at input range of full scale ? 12.5% and at zero scale + 12.5%. 2 maximum inl and dnl specifications obtained with device configured for component video input. 3 this specification is for the adv7403kstz - 140 only. 4 to obtain specified v ih level on the xtal pin (pin 38), program subad dress 0x13 (write only) with 0x04 value. when subaddress 0x13 is set to 0x00 value, v ih level on the xtal pin = 1.2 v. 5 to obtain specified v il level on the xtal pin (pin 38), program subaddress 0x13 (write only) with 0x04 value. when subaddress 0x13 is s et to 0x00 value, v il level on the xtal pin (pin 38) = 0.4 v. 6 guaranteed by characterization. 7 v oh and v ol levels obtained using default drive strength value (0xd5) in subaddress 0xf4. 8 analog current measurements for cvbs made with only adc0 are pow ered up; for rgb, only adc0, adc1, and adc2 are powered up; and for scart fb, all adcs powered up. video specifications av dd = 3.15 v to 3.45 v, dvdd = 1.65 v to 2.0 v, dvddio = 3.0 v to 3.6 v, pvdd = 1.71 v to 1.89 v. o perating temperature range, unless otherwise noted is t min to t max : ?40c to +85c (0c to 70c temperature range for adv7403 kstz - 140) . guaranteed by characterization. table 2 . parameter symbol test conditions/comments min typ max uni t nonlinear specifications differential phase dp cvbs input, modulated 5 step 0.4 d egree s differential gain dg cvbs input, modulated 5 step 0.4 % luma nonlinearity lnl cvbs input, 5 step 0.4 % noise specifications snr unweighted l uma ramp 61 64 db luma flat field 64 65 db analog front end crosstalk 60 db lock time specifications horizontal lock range ?5 +5 % vertical lock range 40 70 hz f sc subcarrier lock range 1.3 khz color lock in time 60 l ine s sync depth range 1 20 200 % color burst range 5 200 % vertical lock time 2 fields horizontal lock time 100 lines chroma spe cifications hue accuracy hue 1 d egree s color saturation accuracy cl_ac 1 % color agc range 5 400 % chroma amplitude error 0.4 % chroma phase error 0.3 d egree s chroma luma intermodulation 0.1 % luma specifications luma accuracy brightness cvbs, 1 v input 1 % contrast cvbs, 1 v input 1 % 1 nominal sync depth is 300 mv at 100% sync depth range . rev. b | page 5 of 20
adv7403 data sheet timing characteristi cs avdd = 3.15 v to 3.45 v, dvdd = 1.65 v to 2.0 v, dvddio = 3.0 v to 3.6 v, pvdd = 1.71 v to 1.89 v. o perating temperature range, unless otherwi se noted is t min to t max : ?40c to +85c (0c to 70c temperature range for adv7403 kstz - 140) . guaranteed by characterization. table 3 . parameter symbol test conditions/ comments min typ max unit system clock and crystal crystal nominal frequency 28.63636 mhz crystal frequency stability 50 ppm horizontal sync input frequency 14.8 110 khz llc1 frequency range 1 12.825 140 mhz i 2 c port 2 sclk frequency 400 khz sclk min imum pulse width high t 1 0.6 s sclk min imum pulse width low t 2 1.3 s hold time (start condition) t 3 0.6 s setup time (start condition) t 4 0.6 s sda setup time t 5 100 ns sclk and sda rise time t 6 30 0 ns sclk and sda fall time t 7 300 ns setup time for stop condition t 8 0.6 s reset feature reset pulse width 5 ms clock outputs llc1 mark space ratio t 9 :t 10 45:55 55:45 % duty cycle data and control outputs data outpu t transition time sdr (sdp) 3 t 11 negative clock edge to start of valid data 3.6 ns t 12 end of valid data to negative clock edge 2.4 ns data output transition time sdr (cp) 4 t 13 end of valid data to negative clock edge 2.8 ns t 14 negative cloc k edge to start of valid data 0.1 ns data output transition time ddr (cp) 4 , 5 t 15 positive clock edge to end of valid data ?4 + tllc1/4 ns t 16 positive clock edge to start of valid data 0.25 + tllc 1/4 ns t 17 negative clock edge to end of valid data ?2.95 + tllc1/4 ns t 18 negative clock edge to start of valid data ?0.5 + tllc1/4 ns data and control inputs 2 input setup time (digital input port) t 19 hs_in, vs_in 9 ns de_in, data inputs 2.2 ns input hold time (digital input port) t 20 hs_in, vs_in 7 ns de_in, data inputs 2 ns 1 maximum llc1 frequency is 110 mhz for adv7403bstz - 110. 2 ttl input values are 0 v to 3 v with rise /fall times 3 ns measured between the 10% and 90% points. 3 sdp timing figures obtained using default drive strength value (0xd5) in subaddress 0xf4. 4 cp timing figures obtained using maximum drive strength value (0xff) in subaddress 0xf4. 5 ddr timing spec ifications dependent on llc1 output pixel clock; tlcc1/4 = 9.25 ns at llc1 = 27 mhz. rev. b | page 6 of 20
data sheet adv7403 timing diagram sd a 1 / sd a 2 sc l k 1 / sc l k 2 t 5 t 3 t 4 t 8 t 6 t 7 t 2 t 1 t 3 05431-003 figure 2. i 2 c timing 05431-004 llc1 p0 t o p29, vs, hs, field/de, sfl/sync_out t 9 t 10 t 12 t 11 figure 3 . pixel port and control sdr output timing (sd core) llc1 p0 t o p29, vs, hs, field/de t 14 t 9 t 13 t 10 05431-005 figure 4 . pixel port and control sdr output timing (cp core) 05431-006 llc1 p6 t o p9, p10 t o p19 t 16 t 18 t 15 t 17 figure 5 . pixel port and control ddr output timing (cp core) t 9 t 10 t 20 t 19 dclk_in de_in hs_in vs_in control inputs 05431-007 p0 t o p1, p10 t o p11, p20 t o p21, p22 t o p29, p31 t o p32, p33 t o p40 figure 6 . digital input port and control input timing rev. b | page 7 of 20
adv7403 data sheet analog specification s av dd = 3.15 v to 3.45 v, dvdd = 1.65 v to 2.0 v, dvddio = 3.0 v to 3.6 v, pvdd = 1.71 v to 1.89 v. o perating temperature range, unless otherwise noted is t min to t max : ?40 c to +85c (0c to 70c temperature range for adv7403 kstz - 140) . recommended analog input video signal range: 0.5 v to 1.6 v, typically 1 v p - p. guaranteed by characterization. table 4 . parameter test conditions/comments min typ max unit clamp circuitry external clamp capacitor 0.1 f input impedance (except the fb pin, pin 51) clamps switched off 10 m? input impedance of pin 51 (fb) 20 k? cml 1.86 v adc full - scale level cml + 0.8 v adc zero - scale level cml ? 0.8 v adc dynamic range 1.6 v clamp level (when locked) cvbs input cml ? 0.292 v scart rgb input (r, g, b signals) cml ? 0.4 v s- video input (y signal) cml ? 0.292 v s- video input (c signal) cml ? 0 v component input (y, pr, pb signals) cml ? 0.3 v pc rgb input (r, g, b signals) cml ? 0.3 v large clamp sdp only source current 0.75 ma sin k current 0.9 ma fine clamp sdp only source current 17 a sink current 17 a rev. b | page 8 of 20
data sheet adv7403 absolute maximum rat ings table 5 . parameter rating avdd to agnd 4 v dvdd to dgnd 2.2 v pvdd to agnd 2.2 v dvddio to dgnd 4 v dvdd io to avdd ? 0.3 v to +0.3 v pvdd to dvdd ? 0.3 v to +0.3 v dvddio to pvdd ? 0.3 v to +2 v dvddio to dvdd ? 0.3 v to +2 v avdd to pvdd ? 0.3 v to +2 v avdd to dvdd ? 0.3 v to +2 v digital inputs voltage to dgnd dgnd ? 0.3 v to dvddio + 0.3 v digital outputs voltage to dgnd dgnd ? 0.3 v to dvddio + 0.3 v analog inputs to agnd agnd ? 0.3 v to avdd + 0.3 v maximum junction temperature (t j max ) 125c storage temperature range ? 65c to +150c infrared reflow soldering (20 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exp osure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal perf ormance to reduce power consumption when using the device, the user is advised to turn off any unused adcs. keep t he junction temperature less than the maximum junction temperature (t j max ) of 125c. the junction temperature is calculate d by t j = t a max + ( ja w max ) w here: t a max = 85c . ja = 30c/w . w max = (( av d d i av d d ) + ( dvdd i dvdd ) + ( dvddio i dvddio ) + ( pvdd i pvdd )). thermal res istance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 6 . package type ja 1 jc 2 unit 100 - lead lqfp 30 7 c/w 1 it is a 4 - layer printed circuit boar d ( pcb ) with a solid ground plane (still air) . 2 it is a 4 - layer pcb with a solid ground plane . esd caution rev. b | page 9 of 20
adv7403 data sheet pin configuration an d function descripti ons 26 p6 27 p5 28 p4 29 p26 30 p25 31 p24 32 p23 33 p22 34 p21 35 dclk_in 36 llc1 37 xtal1 38 xtal 39 dvdd 2 3 4 7 6 5 1 8 9 1 0 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 1 1 74 73 72 69 70 71 75 68 67 66 64 63 62 61 60 59 58 57 56 55 54 53 52 51 65 40 dgnd 41 p3 42 p2 43 p1 44 p0 45 p20 46 elpf 47 pvdd 48 pvdd 49 agnd 50 agnd 05431-002 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pin 1 adv7403 lqfp top view (not to scale) p11 p32 p31 int cs/hs dgnd dvddio p15 p14 p13 p12 dgnd dvdd p29 p28 sfl/sync_out sclk2 dgnd dvddio sda2 p10 p9 p8 p27 p7 ain2 ain8 ain1 ain7 sog ain9 ain3 test1 agnd capy1 capy2 avdd refout cml agnd bias capc1 capc2 test0 ain10 ain4 ain11 ain5 ain12 fb field/de de_in soy ain6 alsb sda1 sclk1 p40 p39 vs_in hs_in/cs_in p38 p37 dgnd dvdd p19 p17 p16 p36 p35 p34 vs p33 p18 reset figure 7. pin configuration table 7 . pin function descriptions pin no. mnemonic type 1 description 1, 2, 83, 84, 87, 88 , 95 to 9 7, 100 p31 to p40 i video pixel input port. 3 int o interrupt. this pin can be active low or active high. when sdp/cp status bits change, this pin t riggers. the set of events that triggers an interrupt is under user control. 4 cs / hs o digital composite synchronization signal (cs). the cs pin can be selected while in cp mode. horizontal synchronization output signal (hs). the hs pin can be select ed while in sdp or cp modes. 5, 11, 17, 40, 89 dgnd g digital ground. 6, 18 dvddio p digital input/output supply voltage (3.3 v). 7 to 10, 22, 23, 2 5 to 2 8 , 41, 42, 91 to 94 p2 to p9, p12 to p19 o video pixel output port. 12, 39, 90 dvdd p digital core supply voltage (1.8 v). 13, 14, 20, 21, 24, 29 to 34 , 43 to 45 p0 to p1, p10 to p11, p20 to p29 i/o video pixel input/output port. rev. b | page 10 of 20
data sheet adv7403 pin no. mnemonic type 1 description 15 sfl/sync_out o subcarrier frequency lock (sfl). this pin contains a serial output stream that can be used to lock the s ubcarrier frequency when th e decoder is connected to any analog devices , inc., digital video encoder. sliced sync output signal (sync_out). this pin is only available in cp mode. 16, 82 sclk1, sclk2 i i 2 c port serial clock input ( m ax imum c lock r ate o f 400 khz) pins . sclk1 is the clock line for the c ontrol port , and sclk2 is the clock line for the vbi data readback port. 19, 81 sda1, sda2 i/o i 2 c port serial data input/output pins. sda1 is the data line for the control port, and sda2 is the data line for the vbi readback port. 35 dclk_in i clock input signal. this pin is u sed in 24 - bit digital input mode (for example, processing 24- bit rgb data from a dvi receiver ic) and also in digital cvbs input mode. 36 llc1 o line - locked output clock for pixel d ata. this pin range is 12.825 mhz to 140 mhz for the adv7403 kstz - 140 , and 12.825 mhz to 110 mhz for the adv7403 bstz - 110. 37 xtal1 o connect t his pin to the 28.63636 mhz crystal , or if an external 3.3 v, 28.63636 mhz clock oscillator source is used to clock the adv7403 , le ave this pin as no connect. in crystal mode , the c rystal must be a fundamental crystal. 38 xtal i input pin for 28.63636 mhz crystal . to clock the adv7403 , this pin can also be overdriven by an external 3.3 v, 28.63636 mhz clock oscillator so urce. 46 elpf o external loop pll filter . connect t he recommend external loop filter to th e elpf pin. 47, 48 pvdd p pll supply voltage (1.8 v). 49, 50, 60, 66 agnd g analog ground. 51 fb i fast switch overlay input. this pin switches between cvbs and r gb analog signals. 52 sog i sync on green input. this pin is u sed in embedded sync mode. 53 to 58, 71 to 76 ain1 to ain12 i analog video input channels. 59 test1 o leave t his pin unconnected. 61, 62 capy1, capy2 i adc capacitor network. 63 avdd p ana log supply voltage (3.3 v). 64 refout o internal voltage reference output. 65 cml o common - mode level (cml) pin for the i nternal adcs. 67 bias o external bias setting pin. connect the recommended resistor (1.35 k ? ) between the bias pin and ground. 68, 69 capc1, capc2 i adc capacitor network. 70 test0 nc leave this pin unconnected, or alternately , tie this pin to agnd. 77 soy i sync on luma input. this pin is u sed in embedded sync mode. 78 reset i system reset input ( active l ow ) . a minimum low reset pulse width of 5 ms is required to reset the circuitry of the adv7403 . 79 de_in i data enable input signal. this pin is u sed in 24- bit digital input port mode (for example, processing 24 - bit rgb data from a dvi receiver ic). 80 alsb i this pin selects the i 2 c device address for the control and vbi readback ports of the adv7403 . when alsb is set to logic 0 , it sets the address for a write to the control port to a ddress 0x40 and the readback address for the vbi port to a ddress 0x21. when alsb is set to l ogic 1, it sets the address for a write to the control port to a ddre ss 0x42 and the readback address for the vbi port to a ddress 0x23. 85 vs_in i vs input signal. this pin is u sed in cp mode for 5 - wire timing mode. 86 hs_in/cs_in i can be configured in cp mode to be either a digital hs input signal or a digital cs input signal used to extract timing in a 5 - wire or 4 - wire rgb mode. 98 field/de o field synchronization output signal for a ll interlaced video modes (field ). this is a multifunction pin . it can also be enabled as a data enable signal (de) in cp mode to allow di rect connection to a hdmi/dvi transmitter ic. 99 vs o vertical synchronization output signal (sdp and cp m odes). 1 g = ground, p = power, i = input, o = output, i/o = input/output, and nc = no connect. rev. b | page 11 of 20
adv7403 data sheet functional overview the following overview provides a brief description of the functionality of the adv7403 . more details are available in the theory of operation section. analog front end the analog front end of the adv7403 provides four 14 0 mhz ( adv7403 kstz - 140), nsv, 1 2 - bit adcs to enable 10 - bit video decoding, a multiplexer with 12 analog input channels to enable multisource connection without the requirement of an external mu ltiplexer, and four current and voltage clamp control loops to ensure that dc offsets are removed from the video signal. scart functionality and standard definition rgb overlay with cvbs are controlled by the fast blank input. this front end also features f our antialias filters to remove out - of - band noise on standard definition input video signals. standard definition processor (sdp) pixel data output modes the adv7403 features the following sdp output modes: ? 8 - /10 - bit itu - r bt.656 4:2:2 ycrcb with embedded time codes and/or hs, vs, and field ? 16- /20 - bit ycrcb with embedded time codes and/or hs, vs, and field ? 24- /30 - bit ycrcb with embedded time codes and/or hs, vs, and field component processor (c p) pixel data output modes the adv7403 features two single data rate (sdr) outputs: 16- /20 - bit 4:2:2 ycrcb for all standards, and 24 - /30 - bit 4:4:4 ycrcb/rgb for all standards . the adv7403 also features two double data rate (ddr) outputs : 8 - /10 - bit 4:2:2 ycrcb for all standards , and 12- bit 4:4:4 ycrcb/rgb for all standards . composite and s - video processing the adv7403 supports ntsc ( j, m, 4.43), pal (b, d, i, g, h, m, n, nc, 60), and secam (b, d, g, k, l) standards for cvbs and s - video formats. superadaptive 2d, 5 - line comb filters for ntsc and pal provide superior chromin ance and luminance separation for composite video. the composite and s - video processing functionalities also include fully automatic detection of switching among worldwide standards (pal/ntsc/secam); automatic gain control (agc) with white peak mode to en sure that the video is processed without compromising the video processing range; adaptive digital line length tracking (adllt?); and proprietary architecture for locking to weak, noisy, and unstable sources from vcrs and tuners. the if filter block compen sates for high frequency luma attenuation due to the tuner saw filter. the adv7403 also features chroma transient improvement (cti) and luminance digital noise reduction (dnr), as well as tel etext, closed captioning (cc), extended data service (eds), and wide - screen signaling (wss). it offers certified macrovision ? copy protection detection on composite and s - video for all worldwide formats (pal/ntsc/secam), and a copy generation management sy stem (cgms). other features include 4 oversampling (54 mhz) for cvbs, s - video, and yuv modes; line - locked clock output (llc); vertical interval time codes (vitc); support for letterbox detection; a free - run output mode for stable timing when no video inpu t is present; clocking from a single 28.63636 mhz crystal; gemstar? 1/2 electronic program guide compatible; and subcarrier frequency lock (sfl) output for downstream video encoders. in addition, the device has color controls for hue, brightness, satura tion, and contrast and controls for cr and cb offsets. the adv7403 also incorporates a vertical blanking interval data processor and a video programming system (vps) on the device. the differen tial gain of the adv7403 is 0. 4 % typical, and the differential phase is 0. 4 typical. component video proc essing the adv7403 suppo rts 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other hdtv formats. it provides automatic adjustments for gain (contrast) and offset (brightness), as well as manual adjustment controls. furthermore, the adv7403 not only supports analog component yprpb/rgb video formats with embedded synchronization or with separate hs, vs, and cs, but also supports ycrcb - to - rgb and rgb - to - ycrcb conversions by any - to - any, 3 3 color - space conversion mat rices. s tandard identification (stdi) enables detection of the component format at the system level, and a s ynchronization source polarity detector (sspd) determines the source and polarity of the synchronization signals that accompany the input video. cer tified macrovision copy protection detection is available on component formats (525i, 625i, 525p, and 625p). when no video input is present, free - run output mode provides stable timing. the adv 7403 also supports arbitrary pixel sampling for nonstandard video sources. rev. b | page 12 of 20
data sheet adv7403 rgb graphics process ing the adv7403 provides 140 msps conversion rate support of rgb input resolutions up to 1280 1024 at 75 hz (sxga ) and 110 msps conversion rate for the adv7403 bstz - 110 . it also provides a utomatic or manual clamp and gain controls for graphics modes . the rgb graphics processing fu nctionality features c ontrast and brightness controls , automatic detection of synchronization source and polarity by the sspd block, standard identification enabled by the stdi block, and arbitrary pixel sampling support for nonstandard video sources. addi tional rgb graphics processing features of the adv7403 include the following: ? 32- phase dll support of optimum pixel clock sampling. ? color - space conversion of rgb to ycrcb and decimation to a 4: 2:2 format for videocentric back - end ic interfacing. ? data enable (de) output signal supplied for direct connection to the hdmi/dvi transmitter ic. digital video input port the adv7403 s upports raw 8 - /10 - bit cvbs data from a digital tuner and 24- bit rgb input data from a dvi receiver chip, output converted to ycrcb 4:2:2 . it also supports 24 - bit 4:4: 4, 16- /20 - bit 4:2:2 525i, 625i, 525p, 625p, 1080i, 720p, vga to sxga at 60 hz input data from hdmi receiver chip, output converted to 16 - bit 4:2:2 ycrcb . general features the adv7403 features hs , vs, and field output signals with programmable position, polarity, and width . it also includes a p rogrammable interrupt request output pin ( int ), signals sdp/cp status changes , and supports two i 2 c host port interfaces (control and vbi). the adv7403 offers low power co nsumption: 1.8 v digital core, 3.3 v analog and digital input/output, low power power - down mode, and green pc mode. the adv7403 bstz - 110 operates over the industrial temperature range ( ? 40c to +85c ) and is available in a 100 - lead, 14 mm 14 mm, rohs - compliant lqfp . it is also available in a 140 mhz speed grade ( adv7403 kst - 140). rev. b | page 13 of 20
adv7403 data sheet theory of operation analog front end the adv7403 a nalog front end comprise s four noise shaped video (nsv ? ) , 12 - bit adcs that digitize the analog video signal before applying it to the standard definition processor ( sdp ) or component processo r ( cp ) . s ee table 8 for the maximum sampling rates . the analog front end uses differential channels to each adc to ens ure high performance in a mixed signal application. the front end also includes a 12 - channel in put mux that enables multiple video signals to be applied to the adv7403 . current and voltage clamps are positioned in front of each adc to ensure that the video signal remains within the range of the converter. fine clamping of the video signals is performed downstream by digital fine clamping either in the cp or sdp. optional antialiasing filters are positioned in front of each adc. these filters can be used to band - limit standard definition video signals, removing spurious, out - of - band noise. the adcs are configured to run in 4 oversampling mode when decoding composite and s - v ideo inputs; 2 oversampling is performed for component 525i, 625i, 525p, and 625p sources. all other video standards are 1 oversampled. oversampling the video signals reduces the cost and complexity of external antialiasing filters with the benefit of an increased signal - to - noise ratio (snr). the adv7403 c an support simultaneous processing of cvbs and rgb standard definition signals to enable scart compatibility and overlay functionality. a combination of cvbs and rgb inputs can be mixed and output under control of i 2 c registers and the fast blank pin. tabl e 8 . maximum adc sampling rates model maximum adc sampling rate (mhz) adv7403 bstz - 110 110 adv7403 kstz - 1 40 140 standard definition processor (sdp) the sdp section is capable of decoding a large selection of baseband video signals in composite s - v ideo and yuv formats. the video standards supported by the sdp include pal (b, d, i, g, h, m, n, nc, 60), ntsc (j , m, 4.43) , and secam (b, d, g, k, l) . t he adv7403 can automatically detect the video standard and process it accordingly. the sdp has a super adaptive 2 - d, 5 - line comb filter that gives superi or chrominance and luminance separation when decoding a composite video signal. this highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality with no user intervention required. the sdp has an if filte r block that compensate s for attenuation in the high frequency luma spectrum due to the tuner saw filter. the sdp has specific luminance and chrominance parameter control for brightness, contrast, saturation, and hue. the adv7403 implements a patented adaptive digital line length tracking ( adllt ? ) algorithm to track varying video line lengths from sources such as a vcr. adllt enables the adv7403 to track and decode poor quality video sources such as vcrs, noisy sources from tuner outputs, vcd players, and camcorders. the sdp also contains a chroma transient improvement (cti) processor. this processor increases the edge rate on chrom a transitions, resulting in a sharper video image. the sdp can process a variety of vbi data services, such as teletext, closed captioning (cc), wide screen signaling (wss), video programming system (vps), vertical interval time codes (vitc), copy generat io n management system (cgms) , gemstar 1/2, and extended data service (xds). the adv7403 sdp section has a macrovision 7.1 detection circuit that allows it to detect types i, ii, and iii prote ction levels. the decoder is also fully robust to all macrovision signal inputs. component processor (cp) the cp section is capable of decoding/digitizing a wide range of component video formats in any color space. component video standards supported by th e cp are 525i, 625i, 525p, 625p, 720p, 1080i, 1250i, vga up to sxga at 75 hz ( adv7403 kstz - 140 only) , and many other standards not listed here. the cp section of the adv7403 contains an agc block. when no embedded sync is present, the video gain can be set manually . the agc section is followed by a digital clamp circuit that ensures that the video signal is clamped to the correct bla nking level. automatic adjustments within the cp include gain (contrast) and offset (brightness); manual adjustment controls are also supported. a fully programmable any - to - any, 3 3 color space conversion matrix is placed between the analog front end and the cp section . this enables yprpb - to - rgb and rgb - to - ycrcb conversions. many other standards of color space can be implemented using the color space converter. the output section of the cp is highly flexible. it can be configured in sdr with one data pac ket per clock cycle or in a ddr mode where data is presented on the rising and falling edge s of the clock. in sdr mode, a 16 - /20 - bit 4:2:2 or 24 - /30 - bit 4:4:4 output is possible. in these modes, hs, vs, and field/de (where applicable) timing reference sign als are provided. in ddr mode, the adv7403 can be configured in an 8 - /10 - bit 4:2:2 ycrcb or 12- bit 4:4:4 yc r c b / rgb pixel output interface with corresponding timing signals. rev. b | page 14 of 20
data sheet adv7403 the adv7403 is capable of supporting an external dvi/hdmi receiver. the digital interface expect s 24 - bit 4:4:4 or 16- /20 - bit 4: 2:2 bit data (either graphics rgb or component video ycrcb), accompanied by hs, vs , de, and a fully synchronous clock signal. the data is processed in the cp and output as 16 - bit 4:2:2 ycrcb data. the cp section contains circuitry to enable the detection of macrovision encoded yprpb signals for 525i, 625i, 525p, and 625p. it is designed to be fully robust when decoding these types of signals. vbi extraction of cgms data is performed by the cp section of the adv7403 for interlaced, progressive, and high definition scanning rat es. the data extracted can be read back over the i 2 c interface. for more detailed product information , see the adv7403 product page. rev. b | page 15 of 20
adv7403 data sheet pixel input/output f ormatting table 9 . sdp, cp pixel input/output pin map (p19 to p0) pixel port pins p[19:0] processor mode format 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdp video out, 8 - bit, 4:2:2 ycrcb[7:0] out sdp video out, 10 - bit, 4:2:2 ycrcb[9:0] out sdp video out, 16 - bit, 4:2:2 y[7:0] out crcb[7:0] out sdp video out, 20 - bit, 4:2:2 y[9:0] out crcb[9:0] out sdp video out, 24 - bit, 4:4:4 y[7:0] out cb[7:0] out sdp video out, 30 - bit, 4:4:4 y[9:0] out cb[9:0] out sm - sdp digital tuner input[1] output choices are the same as video out 16 - /20 - bit or pseudo 8 - /10- bit ddr cp 8 - bit, 4:2:2, ddr d7 d6 d5 d4 d3 d2 d1 d0 cp 10 - bit, 4:2:2, ddr d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cp 12- bit, 4:4:4, rgb ddr d7 d6 d5 d4 d3 d2 d1 d0 d11 d 10 d9 d8 cp video out, 16 - bit, 4:2:2 cha[7:0] out (for example, y[7:0]) chb/c[7:0] out (for example, cr/cb[7:0]) cp video out, 20 - bit, 4:2:2 cha[9:0] out (for example, y[9:0]) chb/c[9:0] out (for example, cr/cb[9:0]) cp video out, 24 - bit, 4:4:4 ch a[7:0] out (for example, g[7:0]) chb[7:0] out (for example, b[7:0]) cp video out, 30 - bit, 4:4:4 cha[9:0] out (for example, g[9:0]) chb[9:0] out (for example, b[9:0]) sm - cp hdmi receiver support, 24- bit, 4:4:4 input cha[7:0] out (for example, y[7:0]) r[5:4 ] in chb/c[7:0] out (for example, cr/cb[7:0]) r[1:0] in sm - cp hdmi receiver support 16- bit pass through cha[7:0] out (for example, y[7:0]) chb/c[7:0] out (for example, cr/cb[7:0]) sm - cp hdmi receiver support, 20- bit, pass through cha[9:0] out (for example, y[9:0]) chb/c[9:0] out (for example, cr/cb[9:0]) rev. b | page 16 of 20
data sheet adv7403 table 10 . sdp, cp pixel input/output pin map (p40 to p20 ) pixel port pins p[40:31], p[29:20] processor mode format 40 39 38 37 36 35 34 33 32 31 29 28 27 26 25 24 23 22 21 20 sdp video out, 8 - bit, 4:2:2 sdp video out, 10 - bit, 4:2:2 sdp video out, 16 - bit, 4:2:2 sdp video out, 20 - bit, 4:2:2 sdp video out, 24 - bit, 4:4:4 cr[7:0] out sdp video out, 30 - bit, 4:4:4 cr[9:0] out sm - sdp digital tuner input[1] dcvbs[9:0] in cp 8 - bit, 4:2:2, ddr cp 10- bit, 4:2:2, ddr cp 12- bit, 4:4:4, rgb ddr cp video out, 16 - bit, 4:2:2 cp video out, 20 - bit, 4:2:2 cp video out, 24 - bit, 4:4:4 input chc[7:0] out (for example, r[7:0]) cp video out, 30 - bit, 4:4:4 input chc[9:0] out (for example, r[9:0]) sm - cp hdmi receiver support, 24- bit, 4:4:4 input g[7:0] in r[7:6] in b[7:0] in r[3:2] in sm - cp hdmi receiver support, 16- bit, pass through cha[7:0] in (for example, y[7:0]) chb/c[7:0] in (for example, cr/cb[7:0]) sm - cp hdmi receiver support, 20- bit, pass thro ugh cha[9:0] in (for example, y[9:0]) chb/c[9:0] in (for example, cr/cb[9:0]) rev. b | page 17 of 20
adv7403 data sheet recommended external loop filter components place t he external loop filter components for the elpf pin as close as possible to the respective pins. figure 8 shows the recommended component values . 05431-008 1.69k? 82nf 10nf pvdd = 1.8v pin 46?elpf figure 8 . elpf components rev. b | page 18 of 20
data sheet adv7403 t ypical c onnection d iagram 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 75 ? 56 ? agnd 10nf 0.1 f 10nf 0.1 f 10nf 0.1 f dvdd_1.8v dgnd u1 bypass capacitors 10nf 0.1 f 10nf 0.1 f dvddio dgnd u1 bypass capacitors 10nf 0.1 f agnd pvdd_1.8v 10nf 0.1 f agnd avdd_3.3v 75 ? green blue red rgb graphics p5?2 p5?3 p5?1 p5?13 p5?14 p6?5 p6?6 p5?7 p5?8 p5?10 hs_in vs_in 1 3 5 21 2 4 6 p4 scart_21_pin 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 4 3 2 1 p8 mini-din-4 s-video sog ain1 ain2 ain3 ain4 ain5 ain6 soy ain10 ain11 ain12 ain7 ain8 ain9 capc2 capc1 capy2 capy1 cml refout bias xtal xtal1 elpf sda sclk sda2 sclk2 alsb reset 1 3 2 4 19 ? 19 ? 20 cvbs/y cvbs p9 agnd 19 ? 56 ? 0.1f pvdd pvdd avdd dvdd dvdd dvdd dvddio dvddio de_in p40 p39 p38 p37 p36 p35 p34 p33 p32 p31 int dclk_in p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 llc1 cs/hs vs field hs_in/cs_in vs_in sfl/sync_out fb test1 test0 agnd agnd pvss pvss dgnd dgnd dgnd dgnd dgnd adv7403 33 ? vp41 79 33 ? vp40 83 33 ? vp39 84 33 ? vp38 87 33 ? vp37 88 33 ? vp36 95 33 ? vp35 96 33 ? vp34 97 33 ? vp33 100 33 ? vp32 1 33 ? vp31 2 33 ? vp30 3 33 ? vp29 13 33 ? vp28 14 33 ? vp27 24 33 ? vp26 29 33 ? vp25 30 33 ? vp24 31 33 ? vp23 32 33 ? vp22 33 33 ? vp21 34 33 ? vp20 45 33 ? vp19 91 33 ? vp18 92 33 ? vp17 93 33 ? vp16 94 33 ? vp15 7 33 ? vp14 8 33 ? vp13 9 33 ? vp12 10 33 ? vp11 20 33 ? vp10 21 33 ? vp09 22 33 ? vp08 23 33 ? vp07 25 33 ? vp06 26 33 ? vp05 27 33 ? vp04 28 vp[00:41] int dclck_in 33 ? vp03 41 33 ? vp02 42 33 ? vp01 43 33 ? vp00 44 100 ? 4 100 ? 99 100 ? 98 100 ? 86 100 ? 85 33 ? 15 hs vs field hs_in vs_in sfl/sync_out 100 ? 36 10nf 0.1 f 10 f 0.1 f agnd 10nf 0.1 f 10 f 0.1 f agnd 0.1 f 10 f 10 f 0.1 f 2.7k ? 2.7k ? y2 28.63636mhz 1m ? 47pf 1 47pf 1 dgnd 10nf 82nf pvdd_1.8v 1.69k ? 100 ? 100 ? 5.6k ? sda sclk reset dvddio k1 k2 bat54c dvddio pvdd_1.8v dvdd_1.8v avdd_3.3v dvddio u1 47 48 63 12 39 90 6 18 c22 1nf c94 1nf d1 bzx399-c3v3 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f y c agnd 1 load cap values are dependant on crystal attributes agnd pr/pb pb/pr y red/c green f_blnk blue phono3 agnd 05431-009 u1 bypass capacitors 10k ? 35 70 66 60 49 50 5 17 11 40 89 llc1 52 54 56 58 72 74 76 77 71 73 75 53 55 57 69 68 62 61 65 64 67 38 37 46 81 82 19 16 80 78 51 59 agnd + + p7 16 2 11 15 agnd dgnd figure 9. adv7403 typical connectio n diagram rev. b | page 19 of 20
adv7403 data sheet outline dimensions compliant t o jedec s t andards ms-026-bed t o p view (pins down) 1 25 26 51 50 75 76 100 0.50 bsc lead pitch 0.27 0.22 0.17 1.60 max 0.75 0.60 0.45 view a pin 1 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 7 3.5 0 14.20 14.00 sq 13.80 16.20 16.00 sq 15.80 051706- a figure 10 . 100 - lead low profile quad flat package [lqfp] (st - 100) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package description package option adv7403bstz - 110 ?40c to +85c 100- lead low profile quad flat package [ lqfp ] st - 100 adv7403kstz - 140 0c to 70c 100- lead low profile quad flat package [ lqfp ] st - 100 eval - adv7403eb z evaluation b oard 1 the adv7403 is a pb - free , environmentally friendly product. it is manufactured using the most up - to - date materials and processes. the coating on the leads of each device is 100% pure sn electroplate. the device is suitable for pb - free applications and is able to withstand surface - mount soldering at up to 255c (5c). in addition, it is backward - compatible with conventional snpb soldering processes. this means that the electroplated sn coating can be soldered with snpb solder pastes at conventional reflow temperatures of 22 0c to 235c. 2 z = rohs compliant part. ? 2005 C 2013 analog d evices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05431 - 0- 9/13(b) rev. b | page 20 of 20

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