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12-bit, 105 msps/125 msps, if sampling adc ad9433 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2001C2009 analog devices, inc. all rights reserved. features if sampling up to 350 mhz snr: 67.5 db, f in up to nyquist at 105 msps sfdr: 83 dbc, f in = 70 mhz at 105 msps sfdr: 72 dbc, f in = 150 mhz at 105 msps 2 v p-p analog input range on-chip clock duty cycle stabilization on-chip reference and track-and-hold sfdr optimization circuit excellent linearity dnl: 0.25 lsb (typical) inl: 0.5 lsb (typical) 750 mhz full power analog bandwidth power dissipation: 1.35 w (typical) at 125 msps twos complement or offset binary data format 5.0 v analog supply operation 2.5 v to 3.3 v ttl/cmos outputs applications cellular infrastructure communication systems 3g single- and multicarrier receivers if sampling schemes wideband carrier frequency systems point-to-point radios lmds, wireless broadband mmds base station units cable reverse path communications test equipment radar and satellite ground systems general introduction the ad9433 is a 12-bit, monolithic sampling analog-to-digital converter (adc) with an on-chip track-and-hold circuit and is designed for ease of use. the product operates up to a 125 msps conversion rate and is optimized for outstanding dynamic per- formance in wideband and high if carrier systems. the adc requires a 5 v analog power supply and a differential encode clock for full performance operation. no external refer- ence or driver components are required for many applications. the digital outputs are ttl-/cmos-compatible, and a separate output power supply pin supports interfacing with 3.3 v or 2.5 v logic. functional block diagram 12 12 pipeline adc t/h ref encode timing output staging ad9433 v cc v dd gnd vrefout vrefin d11 to d0 dfs sfdr mode encode encode ain ain 01977-001 figure 1. a user-selectable, on-chip proprietary circuit optimizes spurious-free dynamic range (sfdr) vs. signal-to-noise and distortion (sinad) ratio performance for different input signal frequencies, providing as much as 83 dbc sfdr performance over the dc to 70 mhz band. the encode clock supports either differential or single-ended input and is pecl-compatible. the output format is user- selectable for offset binary or twos complement and provides an overrange (or) signal. fabricated on an advanced bicmos process, the ad9433 is available in a 52-lead thin quad flat package (tqfp_ep) that is specified over the industrial temperature range of ?40c to +85c. the ad9433 is pin-compatible with the ad9432. product highlights 1. if sampling. the ad9433 maintains outstanding ac performance up to input frequencies of 350 mhz. suitable for 3g wideband cellular if sampling receivers. 2. pin-compatibility with the ad9432. the ad9433 has the same footprint and pin layout as the ad9432 12-bit 80 msps/105 msps adc. 3. sfdr performance. a user-selectable, on-chip circuit optimizes sfdr performance as much as 83 dbc from dc to 70 mhz. 4. sampling rate. at 125 msps, the ad9433 is ideally suited for wireless and wired broadband applications such as lmds/mmds and cable reverse path.
ad9433 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general introduction ....................................................................... 1 ? functional block diagram .............................................................. 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? dc specifications ......................................................................... 3 ? ac specifications .......................................................................... 4 ? switching specifications .............................................................. 5 ? timing diagram ........................................................................... 5 ? absolute maximum ratings ............................................................ 6 ? explanation of test levels ........................................................... 6 ? thermal characteristics .............................................................. 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ..............................................8 ? terminology .................................................................................... 14 ? equivalent circuits ......................................................................... 16 ? theory of operation ...................................................................... 17 ? encode input ............................................................................... 17 ? encode voltage level definition .............................................. 17 ? analog input ............................................................................... 18 ? sfdr optimization.................................................................... 18 ? digital outputs ........................................................................... 18 ? voltage reference ....................................................................... 18 ? timing ......................................................................................... 18 ? applications information .............................................................. 19 ? layout information .................................................................... 19 ? replacing the ad9432 with the ad9433 ................................ 19 ? outline dimensions ....................................................................... 20 ? ordering guide .......................................................................... 20 ? revision history 6/09rev. 0 to rev. a updated format .................................................................. universal reorganized layout ............................................................ universal added tqfp_ep package ................................................. universal deleted lqfp_ed package ............................................... universal changes to thermal characteristics section ................................ 6 changes to pin configuration and function descriptions section ................................................................................................ 7 deleted evaluation board section ................................................ 16 updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 20 10/01revision 0: initial version
ad9433 rev. a | page 3 of 20 specifications dc specifications v dd = 3.3 v, v cc = 5 v; internal reference; differential encode input, unless otherwise noted. table 1. test 105 msps 125 msps parameter temp level min typ max min typ max unit resolution 12 12 bits accuracy no missing codes full vi guaranteed guaranteed offset error full vi ?5 0 +5 ?5 0 +5 mv gain error 1 25c i ?7 1 +3 ?7 1 +3 % fs differential nonlinearity (dnl) 2 25c i ?0.75 0.25 +0.75 ?0.75 0.3 +0.75 lsb full vi ?1 +1 ?1 +1 lsb integral nonlinearity (inl) 2 25c i ?1.0 0.5 +1.0 ?1.0 0.5 +1.0 lsb full vi ?1.3 +1.3 ?1.3 +1.3 lsb thermal drift offset error full v ?50 ?50 ppm/c gain error 1 full v ?125 ?125 ppm/c reference full v 80 80 ppm/c reference internal reference voltage (vrefout) full i 2.4 2.5 2.6 2.4 2.5 2.6 v output current (vrefout) full v 100 100 a input current (vrefin) full iv 50 50 a analog inputs (ain, ain ) input voltage range full v 2.0 2.0 v p-p common-mode voltage full v 4.0 4.0 v input resistance full vi 2 3 4 2 3 4 k input capacitance full v 4 4 pf analog bandwidth, full power full v 750 750 mhz power supply v cc full iv 4.75 5.0 5.25 4.75 5.0 5.25 v v dd full iv 2.7 3.3 2.7 3.3 v power dissipation 3 full vi 1275 1425 1350 1500 mw i vcc 3 full vi 255 285 270 300 ma i vdd 3 full vi 12.5 14 16 18 ma power supply rejection ratio (psrr) 25c i 3 3 mv/v encode inputs internal common-mode bias full v 3.75 3.75 v differential input (encode, encode ) full v 500 500 mv input voltage range full iv ?0.5 v cc + 0.05 ?0.5 v cc + 0.05 v input common-mode range full iv 2.0 4.25 2.0 4.25 v input resistance full vi 6 6 k input capacitance 25c v 3 3 pf digital inputs input high voltage full i 2.0 2.0 v input low voltage full i 0.8 0.8 v input high current (vin = 5 v) full v 50 50 a input low current (vin = 0 v) full v 50 50 a
ad9433 rev. a | page 4 of 20 test 105 msps 125 msps parameter temp level min typ max min typ max unit digital outputs logic 1 voltage full vi v dd ? 0.05 v dd ? 0.05 v logic 0 voltage full vi 0.05 0.05 v output coding twos complement or offset binary twos complement or offset binary 1 gain error and gain temperature coefficients are based on the adc only (with a fixed 2.5 v external reference and a 2 v p-p di fferential analog input). 2 sfdr mode disabled (sfdr mode = g nd) for dnl and inl specifications. 3 power dissipation measured with rated encode and a dc analog input (outputs static, i vdd = 0). i vcc and i vdd measured with 10.3 mhz analog input @ ?0.5 dbfs. ac specifications v dd = 3.3 v, v cc = 5 v; differential encode input, unless otherwise noted. table 2. test 105 msps 125 msps parameter temp level min typ max min typ max unit dynamic performance 1 signal-to-noise ratio (snr) (without harmonics) f in = 10.3 mhz 25c i 66.5 68.0 66.0 67.7 db f in = 49 mhz 25c i 65.5 67.5 64.0 66.0 db f in = 70 mhz 25c v 67.0 65.4 db f in = 150 mhz 25c v 65.4 62.0 db f in = 250 mhz 25c v 63.7 60.0 db signal-to-noise and distortion (sinad) ratio (with harmonics) f in = 10.3 mhz 25c i 66.0 68.0 65.0 67.0 db f in = 49 mhz 25c i 64.0 67.5 63.5 65.5 db f in = 70 mhz 25c v 66.9 64.5 db f in = 150 mhz 25c v 64.0 61.5 db f in = 250 mhz 25c v 61.2 57.7 db effective number of bits (enob) f in = 10.3 mhz 25c i 11.1 10.9 bits f in = 49 mhz 25c i 11.0 10.7 bits f in = 70 mhz 25c v 10.9 10.6 bits f in = 150 mhz 25c v 10.4 10.0 bits f in = 250 mhz 25c v 9.9 9.4 bits second-order and third-order harmonic distortion f in = 10.3 mhz 25c i ?78 ?85 ?76 ?85 dbc f in = 49 mhz 25c i ?73 ?80 ?72 ?76 dbc f in = 70 mhz 25c v ?83 ?78 dbc f in = 150 mhz 25c v ?72 ?67 dbc f in = 250 mhz 25c v ?67 ?65 dbc worst other harmonic or spur (excluding second-order and third-order harmonics) f in = 10.3 mhz 25c i ?88 ?92 ?84 ?90 dbc f in = 49 mhz 25c i ?82 ?89 ?82 ?87 dbc f in = 70 mhz 25c v ?87 ?85 dbc f in = 150 mhz 25c v ?87 ?84 dbc f in = 250 mhz 25c v ?85 ?76 dbc two-tone intermodulation distortion (imd3) f in1 = 49.3 mhz; f in2 = 50.3 mhz 25c v ?92 ?90 dbc f in1 = 150 mhz; f in2 = 151 mhz 25c v ?80 ?76 dbc 1 snr/harmonics based on an analog input voltage of ?0.5 dbfs referenced to a 2 v full-scale input range. harmonics are specifie d with the sfdr mode enabled (sfdr mode = 5 v). snr/sinad specified with the sfdr mode disabled (sfdr mode = ground).
ad9433 rev. a | page 5 of 20 switching specifications v dd = 3.3 v, v cc = 5 v; differential encode input, unless otherwise noted. table 3. test 105 msps 125 msps parameter temp level min typ max min typ max unit encode rate full iv 10 105 10 125 msps encode pulse width high (t eh ) full iv 2.9 2.4 ns encode pulse width low (t el ) full iv 2.9 2.4 ns aperture delay (t a ) 25c v 2.1 2.1 ns aperture uncertainty (jitter) 1 25c v 0.25 0.25 ps rms output valid time (t v ) 2 full vi 2.5 4.0 2.5 4.0 ns output propagation delay (t pd ) 2 full vi 4.0 5.5 4.0 5.5 ns output rise time (t r ) 2 full v 2.1 2.1 ns output fall time (t f ) 2 full v 1.9 1.9 ns out-of-range recovery time 25c v 2 2 ns transient response time 25c v 2 2 ns latency full iv 10 10 cycles 1 aperture uncertainty includes contr ibution of the ad9433, crystal clock re ference, and encode drive circuit. 2 t v and t pd are measured from the transition points of the encode input to the 50%/50% levels of the digital output swing. the digital out put load during testing is not to exceed an ac load of 10 pf or a dc current of 50 a. rise and fall times are measured from 10% to 90%. timing diagram t el t eh t a 1/ f s sample n ? 1 sample n + 1 sample n + 8 sample n + 9 sample n + 10 sample n ain encode t v t pd data n ? 11 data n ? 10 data n ? 1 data n data n + 1 data n ? 9 data n ? 2 d11 to d0 encode 01977-003 figure 2. timing diagram
ad9433 rev. a | page 6 of 20 absolute maximum ratings table 4. parameter rating v dd ?0.5 v to +6.0 v v cc ?0.5 v to +6.0 v analog inputs ?0.5 v to v cc + 0.5 v digital inputs ?0.5 v to v dd + 0.5 v digital output current 20 ma operating temperature range (t a ) ?40c to +85c storage temperature range ?65c to +125c maximum junction temperature (t j ) 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. explanation of test levels i 100% production tested. ii 100% production tested at 25c and sample tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi 100% production tested at 25c; guaranteed by design and characterization testing for industrial temperature range. thermal characteristics table 5 lists ad9433 thermal characteristics for simulated typical performance in a 4-layer jedec board, horizontal orientation. table 5. thermal resistance package type ja jma jc unit 52-lead tqfp_ep (sv-52-2) 1 2 c/w no airflow 19.3 c/w 1.0 m/s airflow 16 c/w 1 bottom of package (exposed pad soldered to ground plane). esd caution
ad9433 rev. a | page 7 of 20 pin configuration and fu nction descriptions 52 v cc 51 gnd 50 ain 49 ain 48 gnd 47 v cc 46 vrefout 45 vrefin 44 v cc 43 gnd 42 sfdr mode 41 dfs 40 gnd 38 gnd 37 v cc 36 v cc 33 gnd 34 gnd 35 gnd 39 gnd 32 v dd 31 dgnd 30 d0 (lsb) 28 d2 27 d3 29 d1 2 v cc 3 gnd 4 gnd 7 encode 6 v cc 5 v cc 1 gnd 8 encode 9 gnd 10 v cc 12 dgnd 13 v dd 11 gnd 14 or 15 d11 (msb) 16 d10 17 d9 18 d8 19 d7 20 d6 21 dgnd 22 v dd 23 v dd 24 dgnd 25 d5 26 d4 pin 1 ad9433 top view (not to scale) 01977-002 notes 1. the exposed paddle on the underside of the package must be soldered to the ground plane. soldering the exposed paddle to the pcb increases the reliability of the solder joints, maximizing the thermal capability of the package. figure 3. pin configuration table 6. pin function descriptions pin no. mnemonic description 1, 3, 4, 9, 11, 33, 34, 35, 38, 39, 40, 43, 48, 51 gnd analog ground. 2, 5, 6, 10, 36, 37, 44, 47, 52 v cc analog supply (5 v). 7 encode encode clock for adc, complementary. 8 encode encode clock for adc, true. adc samples on rising edge of encode. 12, 21, 24, 31 dgnd digital output ground. 13, 22, 23, 32 v dd digital output power supply (3 v). 14 or out-of-range output. 15 to 20, 25 to 30 d11 to d6, d5 to d0 digital output. 41 dfs data format select. logic low = twos complement, logic high = offset binary; floats low. 42 sfdr mode cmos control pin. this pin enables sfdr mode, a proprietary circuit that can improve the sfdr performance of the ad9433. sfdr mode is useful in applications where the dynamic range of the system is limited by discrete spurious freq uency content caused by nonlinearities in the adc transfer function. set this pin to 0 for normal operation; floats low. 45 vrefin reference input for adc (2.5 v typical). bypass with 0.1 f capacitor to ground. 46 vrefout internal reference output (2.5 v typical). 49 ain analog input, true. 50 ain analog input, complementary. exposed pad (ep) the exposed paddle on the underside of the pack age must be soldered to the ground plane. soldering the exposed paddle to the pcb increases the reliability of the solder joints, maximiz- ing the thermal capability of the package.
ad9433 rev. a | page 8 of 20 typical performance characteristics 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 0 13.1 26.3 39.4 52.5 frequency (mhz) amplitude (dbfs) 01977-009 snr = 67.5db sfdr = 85dbfs ? 95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 0 50 100 150 200 250 ain (mhz) harmonics (dbc) 01977-012 worst other third harmonic second harmonic figure 4. fft: f s = 105 msps, f in = 49.3 mhz, differential ain @ ?0.5 dbfs, sfdr mode enabled figure 7. harmonics (second, third, worst other) vs. ain frequency, ain @ ?0.5 dbfs, f s = 105 msps, sfdr mode enabled 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 0 13.1 26.3 39.4 52.5 frequency (mhz) amplitude (dbfs) 01977-010 snr = 68db sfdr = 80dbfs snr 68 67 66 65 64 63 62 61 60 11.1 10.9 10.8 10.6 10.4 10.3 10.1 9.9 9.8 0 50 100 150 200 250 300 ain (mhz) snr/sinad (db) enob (bits) 01977-013 sinad 100 95 90 85 80 75 70 65 60 10 30 50 70 90 110 130 encode (msps) snr/sinad (db) 01977-014 figure 5. fft: f s = 105 msps, f in = 49.3 mhz, differential ain @ ?0.5 dbfs, sfdr mode disabled figure 8. snr/sinad and enob vs. ain frequency, differential ain @ ?0.5 dbfs, f s = 105 msps, sfdr mode disabled 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 0 15.6 31.2 46.8 62.5 frequency (mhz) amplitude (dbfs) 01977-011 snr = 67.7db sfdr = 76dbfs third harmonic (dbc) second harmonic (dbc) figure 6. fft: f s = 125 msps, f in = 49.3 mhz, differential ain @ ?0.5 dbfs, sfdr mode enabled sinad snr figure 9. snr/sinad and harmonic distortion vs. encode frequency, differential ain @ ?0.5 dbfs
ad9433 rev. a | page 9 of 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 0 7.5 15.0 22.5 30.0 37.5 45.0 52.5 amplitude (dbfs) 7-015 20 frequency (mhz) 0197 imd3 = 92dbfs figure 10. fft: f s = 105 msps, f in = 49.3 mhz and 50.3 mhz, differential ain @ ?7 dbfs for each tone, sfdr mode enabled 110 100 90 80 70 60 50 40 30 20 10 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (db) 7-016 ain level (dbfs) 0197 sfdr (dbfs) 90dbfs reference snr (dbfs) sfdr (dbc) figure 11. snr and sfdr vs. ain level, f s = 105 msps, f in = 49.3 mhz, differential ain, sfdr mode enabled 110 100 90 80 70 60 third-order imd (db) 50 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ain level (dbfs) 01977-017 figure 12. third-order imd vs. ain level, f s = 105 msps, f in = 49.3 mhz and 50.3 mhz, differential ain, sfdr mode enabled 69 67 65 63 61 59 57 55 10.3 49.3 80.3 170.3 250.3 ain (mhz) snr/sinad (db) 01977-018 enob (bits) 8.9 9.6 9.9 10.3 10.6 10.9 11.3 9.3 snr sinad figure 13. snr/sinad and enob vs. ain fr equency, differential ain @ ?0.5 dbfs, f s = 125 msps, sfdr mode enabled 100 90 80 70 60 50 40 30 20 10 0 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 ain common-mode voltage (v) dynamic performance (db) 01977-019 third harmonic second harmonic snr figure 14. dynamic performance vs. ain common-mode voltage, differential ain @ ?0.5 dbfs, f in = 49.3 mhz, f s = 105 msps 69 68 67 66 65 64 63 62 61 60 snr (db) 0 ?40c +25c +85c 10.3 49.3 80.3 170.3 250.3 ain (mhz) 01977-02 figure 15. snr vs. ain frequency over temperature, f s = 105 msps, differential ain, sfdr mode disabled
ad9433 rev. a | page 10 of 20 ? 95 ?90 ?85 ?80 ?75 ?70 300 280 260 240 220 200 180 18 15 12 9 6 3 0 0 25 50 75 100 125 encode frequency (mhz) i cc (ma) i cc (ma) i dd (ma) i dd (ma) 01977-024 ?65 0 102030405060708090 dynamic performance (db) 7-021 worst other (dbc) third harmonic (dbc) second harmonic (dbc) snr (db) duty cycle high (%) 0197 figure 16. dynamic performance vs. encode duty cycle, f s = 105 msps, f in = 49.3 mhz, differential ain @ ?0.5 dbfs, sfdr mode enabled 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 0 512 1024 1536 2048 2560 3072 3584 4096 inl (lsb) 977-022 output code 01 figure 17. integral nonlinearity vs. ou tput code with sfdr mode disabled 0.5 0.4 0.3 0.2 0.1 0 ?0.2 ?0.1 ?0.3 dnl (lsb) ?0.4 ?0.5 0 512 1024 1536 2048 2560 3072 3584 4096 output code 01977-023 figure 18. differential nonlinearity vs. output code figure 19. i dd and i cc vs. encode rate, f in = 10.3 mhz, differential ain @ ?0.5 dbfs 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 0 512 1024 1536 2048 2560 3072 3584 4096 output code inl (lsb) 01977-025 figure 20. integral nonlinearity vs. output code with sfdr mode enabled 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 amplitude (dbfs) ?120 0 7.68 15.36 23.04 30.72 frequency (mhz) 01977-026 figure 21. fft: f s = 61.44 msps, f in = 46.08 mhz, four wcdma carriers, differential ain, sfdr mode enabled
ad9433 rev. a | page 11 of 20 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 0 7.5 15.0 22.5 30.0 37.5 45.0 52.5 amplitude (dbfs) 977-027 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 0 7.5 15.0 22.5 30.0 37.5 45.0 52.5 frequency (mhz) amplitude (dbfs) 01977-029 imd3 = 85dbc snr = 66.8db sfdr = 83dbfs frequency (mhz) 01 figure 22. fft: f s = 105 msps, f in = 70.3 mhz, differential ain @ ?0.5 dbfs, sfdr mode enabled 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 0 7.5 15.0 22.5 30.0 37.5 45.0 52.5 amplitude (dbfs) 7-030 frequency (mhz) 0197 snr = 67db sfdr = 80dbfs figure 23. fft: f s = 105 msps, f in = 70.3 mhz, differential ain @ ?0.5 dbfs, sfdr mode disabled 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 amplitude (dbfs) ?110 ?120 0 6.2 12.5 18.7 25.0 31.2 37.5 43.7 50.0 56.2 62.5 frequency (mhz) 01977-028 snr = 65.5db sfdr = 78dbfs figure 24. fft: f s = 125 msps, f in = 70.3 mhz, differential ain @ ?0.5 dbfs, sfdr mode enabled figure 25. fft: f s = 105 msps, f in = 69.3 mhz and 70.3 mhz, differential ain @ ?7 dbfs for each tone, sfdr mode enabled 110 100 90 80 70 60 50 40 30 20 10 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ain level (dbfs) snr/sfdr (db) 01977-031 sfdr (dbfs) snr (dbfs) sfdr (dbc) 80dbfs reference line f s = 105msps f in = 70.3mhz differential ain sfdr enabled figure 26. snr and sfdr vs. ain level, f s = 105 msps, f in = 70.3 mhz, differential ain, sfdr mode enabled ? 110 ?100 ?90 ?80 ?70 ?60 ?50 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 third-order imd (dbfs) 977-032 ain level (dbfs) 01 figure 27. third-order imd vs. ain level, f s = 105 msps, f in = 70.3 mhz and 69.3 mhz, differential ain, sfdr mode enabled
ad9433 rev. a | page 12 of 20 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 0 6.25 12.5 18.7 25.0 31.2 37.5 43.7 50.0 56.2 62.5 frequency (mhz) amplitude (dbfs) 01977-036 ?110 ?120 0 7.5 15.0 22.5 30.0 37.5 45.0 52.5 amplitude (dbfs) 7-033 snr = 64db sfdr = 78dbfs snr = 62db sfdr = 70dbfs frequency (mhz) 0197 figure 28. fft: f s = 105 msps, f in = 150.3 mhz, differential ain @ ?0.5 dbfs, sfdr mode enabled 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 0 7.5 15.0 22.5 30.0 37.5 45.0 52.5 amplitude (dbfs) 977-034 frequency (mhz) 01 snr = 61.2db sfdr = 67dbfs figure 29. fft: f s = 105 msps, f in = 250.3 mhz, differential ain @ ?0.5 dbfs, sfdr mode enabled 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 amplitude (dbfs) ?110 ?120 0 7.5 15.0 22.5 30.0 37.5 45.0 52.5 frequency (mhz) 01977-035 snr = 55.3db sfdr = 61dbfs figure 30. fft: f s = 105 msps, f in = 350.3 mhz, differential ain @ ?0.5 dbfs, sfdr mode enabled figure 31. fft: f s = 125 msps, f in = 150.3 mhz, differential ain @ ?0.5 dbfs, sfdr mode enabled 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 0 6.2 12.5 18.7 25.0 31.2 37.5 43.7 50.0 56.2 62.5 frequency (mhz) amplitude (dbfs) 01977-037 snr = 54.6db sfdr = 58dbfs figure 32. fft: f s = 125 msps, f in = 350.3 mhz, differential ain @ ?0.5 dbfs, sfdr mode enabled ? 110 ?90 ?100 ?70 ?80 ?60 ?20 ?30 ?40 ?50 ?10 0 third-order imd (dbfs) 38 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ain level (dbfs) 01977-0 figure 33. third-order imd vs. ain level, f s = 105 msps, f in = 150.3 mhz and 151.3 mhz, differential ain, sfdr mode enabled
ad9433 rev. a | page 13 of 20 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 amplitude (dbfs) ?110 ?120 0 9.6 19.2 28.8 38.4 frequency (mhz) 01977-039 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 0 11.52 23.04 34.56 46.08 amplitude (dbfs) 977-040 frequency (mhz) 01 figure 34. fft: f s = 76.8 msps, f in = 59.6 mhz, two wcdma carriers, differential ain, sfdr mode enabled figure 35. fft: f s = 92.16 msps, f in = 70.3 mhz, wcdma @ 70.0 mhz, sfdr mode enabled
ad9433 rev. a | page 14 of 20 terminology analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential analog input resistance, differential analog input capacitance, and differential analog input impedance the real and complex impedances measured at each analog input port. the resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 out of phase. peak-to-peak differential voltage is computed by rotating the input phase 180 and taking the peak measure- ment again. the difference is then computed between both peak measurements. differential nonlinearity (dnl) the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) the effective number of bits (enob) is calculated from the measured snr based on the following equation: 02.6 ? ? = enob log20db76.1 ? ? ? ? ? ? ? +? amplitude input amplitude scalefull snr measured encode pulse width/duty cycle pulse width high is the minimum amount of time that the encode pulse should be left in the logic 1 state to achieve the rated performance. pulse width low is the minimum amount of time that the encode pulse should be left in the logic 0 state. at a given clock rate, these specifications define an acceptable encode duty cycle. full-scale input power expressed in dbm. computed using the following equation: gain error the difference between the measured and the ideal full-scale input voltage range of the adc. harmonic distortion the ratio of the rms signal amplitude fundamental frequency to the rms signal amplitude of a single harmonic component (second, third, and so on); reported in dbc. integral nonlinearity (inl) the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least square curve fit. maximum conversion rate the maximum encode rate at which parametric testing is performed. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. noise (for any range within the adc) noise can be calculated using the following equation: ? ? ? ? ? ? ? ? ?? = 10 100.001 dbfs dbc dbm noise signal snrfs zv where: z is the input impedance. fs is the full scale of the device for the frequency in question. snr is the value for the particular input level. signal is the signal level within the adc reported in db below full scale. this value includes both thermal and quantization noise. output propagation delay the delay between a differential crossing of encode and encode and the time when all output data bits are within valid logic levels. power supply rejection ratio (psrr) the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise and distortion (sinad) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. signal-to-noise ratio (snr) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral com- ponents, excluding the first five harmonics and dc. ? ? ? ? 001.0 ? ? ? ? ? ? ? ? = log10 2 z fullscalev power rms fullscale
ad9433 rev. a | page 15 of 20 spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious compo- nent may or may not be a harmonic. may be reported in dbc (degrades as signal level is lowered) or in dbfs (always related back to converter full scale). two-tone intermodulation distortion rejection the ratio of the rms value of either input tone (f 1 , f 2 ) to the rms value of the worst third-order intermodulation product; reported in dbc. products are located at 2f 1 ? f 2 and 2f 2 ? f 1 . two-tone sfdr the ratio of the rms value of either input tone (f 1 , f 2 ) to the rms value of the peak spurious component. the peak spurious com- ponent may or may not be an imd product. may be reported in dbc (degrades as signal level is lowered) or in dbfs (always related back to converter full scale). worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second-order and third-order harmonic); reported in dbc.
ad9433 rev. a | page 16 of 20 equivalent circuits v cc vrefin v cc vrefout 01977-006 01977-007 01977-008 01977-005 figure 36. voltage reference input circuit 3.75k ? 15k? 3.75k ? 15k? v cc a in a in figure 37. analog input circuit v dd dx figure 39. voltage reference output circuit 01977-004 figure 38. digital output circuit 24k? 24k? 8k ? 8k? v cc encode encode figure 40. encode input circuit
ad9433 rev. a | page 17 of 20 theory of operation the ad9433 is a 12-bit pipeline converter that uses a switched- capacitor architecture. optimized for high speed, this converter provides flat dynamic performance up to and beyond the nyquist limit. dnl transitional errors are calibrated at final test to a typical accuracy of 0.25 lsb or less. encode input any high speed adc is extremely sensitive to the quality of the sampling clock provided by the user. a track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the adc output. for this reason, considerable care has been taken in the design of the encode input of the ad9433, and the user is advised to give commensurate thought to the clock source. the ad9433 has an internal clock duty cycle stabilization circuit that locks to the rising edge of encode (falling edge of encode if driven differentially) and optimizes timing internally. this allows for a wide range of input duty cycles at the input without degrading performance. jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. this circuit is always on and cannot be disabled by the user. the encode and encode inputs are internally biased to 3.75 v (nominal) and support either differential or single- ended signals. for best dynamic performance, a differential signal is recommended. good performance is obtained using an mc10el16 translator in the circuit to directly drive the encode inputs (see ). figure 41 0 1977-041 pecl gate encode ad9433 encode 510? 510? figure 41. using pecl to drive the encode inputs often, the cleanest clock source is a crystal oscillator producing a pure, single-ended sine wave. in this configuration, or with any roughly symmetrical, single-ended clock source, the signal can be ac-coupled to the encode input. to minimize jitter, the signal amplitude should be maximized within the input range described in table 7 . the 12 k resistors to ground at each of the inputs, in parallel with the internal bias resistors, set the common-mode voltage to approximately 2.5 v, allowing the maximum swing at the input. the encode input should be bypassed with a capacitor to ground to reduce noise. this ensures that the internal bias voltage is centered on the encode signal. for best dynamic performance, impedances at encode and encode should match. 01977-042 encode ad9433 encode 12k? 25? 50? 12k ? 0.1f 0.1f 50 ? sine source 01977-043 figure 42. single-ended sine source encode circuit figure 43 shows another preferred method for clocking the ad9433. the clock source (low jitter) is converted from single- ended to differential using an rf transformer. the back-to-back schottky diodes across the transformer secondary limit clock excursions into the ad9433 to approximately 0.8 v p-p differ- ential. this helps to prevent the large voltage swings of the clock from feeding through to other portions of the ad9433 and limits the noise presented to the encode inputs. a crystal clock oscilla- tor can also be used to drive the rf transformer if an appropriate limiting resistor (typically 100 ) is placed in series with the primary. encode ad9433 encode 0.1f t1-4t 100 ? hms2812 diodes clock source figure 43. transformer-coupled encode circuit encode voltage level definition the voltage level definitions for driving encode and encode in single-ended and differential mode are shown in . figure 44 v ihd v icm , v ecm v ild encode encode v id v ihs v icm , v ecm v ils encode encode 01977-044 0.1f figure 44. differential and single-ended input levels table 7. encode inputs input min nominal max differential signal amplitude (v id ) 200 mv 750 mv 5.5 v input voltage range (v ihd , v ild , v ihs , v ils ) ?0.5 v v cc + 0.5 v internal common-mode bias (v icm ) 3.75 v external common-mode bias (v ecm ) 2.0 v 4.25 v
ad9433 rev. a | page 18 of 20 01977-045 analog input the analog input to the ad9433 is a differential buffer. the input buffer is self-biased by an on-chip resistor divider that sets the dc common-mode voltage to a nominal 4 v (see the equivalent circuits section). rated performance is achieved by driving the input differentially. the minimum input offset voltage is obtained when driving from a source with a low differential source impedance, such as a transformer in ac applications (see figure 45 ). capacitive coupling at the inputs increases the input offset voltage by as much as 50 mv. ain ad9433 ain 0.1f 25? 50? 1:1 25? a nalog signal source figure 45. transformer-coupled analog input circuit in the highest frequency applications, two transformers con- nected in series may be necessary to minimize even-order harmonic distortion. the first transformer isolates and converts the signal to a differential signal, but the grounded input on the primary side degrades amplitude balance on the secondary winding. capacitive coupling between the windings causes this imbalance. because one input to the first transformer is grounded, there is little or no capacitive coupling, resulting in an amplitude mismatch at the output of the first transformer. a second transformer improves the amplitude balance, and thus improves the harmonic distortion. a wideband transformer, such as the adt1-1wt from mini-circuits?, is recommended for these applications, because the bandwidth through the two transformers is reduced by 2. 01977-046 ain ad9433 ain 0.1f 25? 50? analog signal 1:1 1:1 25? source figure 46. driving the analog input with two transformers for improved even-order harmonics driving the adc single-ended degrades performance, partic- ularly even-order harmonics. for best dynamic performance, impedances at ain and ain should match. special care was taken in the design of the analog input section of the ad9433 to prevent damage and corruption of data when the input is overdriven. sfdr optimization when set to logic 1, the sfdr mode pin enables a proprietary circuit that can improve the spurious-free dynamic range (sfdr) performance of the ad9433. this pin is useful in applications where the dynamic range of the system is limited by discrete enabling this circuit gives the circuit a dynamic transfer functi meaning that the voltage t spurious frequency content caused by nonlinearities in the adc transfer function. on, hreshold between two adjacent output er consumption. the output data v) codes can change from clock cycle to clock cycle. while improving spurious frequency content, this dynamic aspect of the transfer function may be inappropriate for some time domain applications of the converter. connecting the sfdr mode pin to ground disables this function. the improvement in the linearity of the converter and its effect on spurious free dynamic range is shown in figure 4 and figure 5 and in figure 22 and figure 23 . digital outputs the digital outputs are 3 v (2.7 v to 3.3 v) ttl-/cmos- compatible for lower pow format is selectable through the data format select (dfs) cmos input. dfs = 1 selects offset binary; dfs = 0 selects twos complement coding (see table 8 and table 9 ). table 8. offset binary output coding (dfs = 1, v ref = 2.5 code ain ? ain (v) digital out put 4095 +1.000 1111 1111 1111 2048 0 1000 0000 0000 2047 0049 1 1111 1111 ?0.0 011 0 ?1.000 0000 0000 0000 table 9. twos comple nt output c fs = 0, v ref = me 2.5 v) odin g (d code ain ? ain (v) digital output +2047 +1.000 0111 1111 1111 0 0 0000 0000 0000 ?1 ?0.00049 1 1111 1111 111 ?2048 ?1.000 1000 0000 0000 vo ltage re ence and acc v voltage refer he mal operation, the internal refer- hed data outputs, with 10 pipeline a outputs are available one propagation delay (t pd ) he fer a stable urate 2.5 ence is built into t ad9433 (vrefout). in nor ence is used by strapping pin 45 to pin 46 and placing a 0.1 f decoupling capacitor at vrefin. the input range can be adjusted by varying the reference voltage applied to the ad9433. no appre- ciable degradation in performance occurs when the reference is adjusted 5%. the full-scale range of the adc tracks reference voltage changes linearly. timing the ad9433 provides latc delays. dat after the rising edge of the encode command (see figure 2 ). t length of the output data lines and the loads placed on them should be minimized to reduce transients within the ad9433; these transients can detract from the dynamic performance of the converter. the minimum guaranteed conversion rate of the ad9433 is 10 msps. at internal clock rates below 10 msps, dynamic performance may degrade.
ad9433 rev. a | page 19 of 20 a multilayer board is recommended to achieve best results. it is highly recommended that high qual ity, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. the pinout of the ad9433 facilitates ease of use in the imple- mentation of high frequency, high resolution design practices. all of the digital outputs and their supply and ground pin connections are segregated on one side of the package, with the inputs on the opposite side for isolation purposes. care should be taken when routing the digital output traces. to prevent coupling through the digital outputs into the analog portion of the ad9433 (v cc , ain, and vref), minimal capacitive loading should be placed on these outputs. it is recommended that a fanout of only one gate be used for all ad9433 digital outputs. the layout of the encode circuit is equally critical and should be treated as an analog input. any noise received on this circuitry results in corruption in the digitization process and lower over- all performance. the encode clock must be isolated from the digital outputs and the analog inputs. replacing the ad9432 with the ad9433 the ad9433 is pin-compatible with the ad9432, although there are two control pins on the ad9433 that are do not connect (dnc) and supply (v cc ) connections on the ad9432 (see tabl e 10 ). table 10. ad9432/ad9433 pin differences pin ad9432 ad9433 applications information layout information 41 dnc dfs 42 v cc sfdr mode using the ad9433 in an ad9432 pin assignment configures the ad9433 as follows: ? the sfdr improvement circuit is enabled. ? the dfs pin floats low, selecting twos complement coding for the digital outputs. (twos complement coding is the only output coding available on the ad9432.) table 11 summarizes the differences between the ad9432 and ad9433 analog and encode input common-mode voltages. these inputs can be ac-coupled so that the devices can be used interchangeably. table 11. ad9432/ad9433 analog and encode input common-mode voltages input pins common-mode voltage ad9432 ad9433 encode/ encode 1.6 v 3.75 v ain/ ain 3.0 v 4.0 v
ad9433 rev. a | page 20 of 20 compliant to jedec standards outline dimensions ms-026-acc 40 52 1 14 13 26 27 39 12.00 bsc sq 1.20 max 0.75 0.60 0.45 10.00 b q sc s view a top vi (pins down ew ) pin 1 40 52 39 14 1 13 26 27 0.65 bsc lead pitch 0.38 0.32 0.22 bottom view (pins up) 7.30 b sq sed d sc expo pa seating plane 1.05 0.20 0 72508-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sh eet. 1.00 0.95 0.09 0.08 max coplanarity 0 min 7 3.5 0 0.15 0.05 view a rotated 90 ccw age, exposed pad [tqfp_ep] millimeters figure 47. 52-lead thin quad dimensions sho ordering guide flat pack (sv-52-2) wn in model temperature range packag e description package option ad9433bsvz-105 1 ?40c to +85c 52-lead thin quad flat package, exposed pad [tqfp_ep] sv-52-2 AD9433BSVZ-125 1 ?40c to +85c 52-lead thin quad flat pa ed pad [tqfp_ s ckage, expos ep] v-52-2 1 z = rohs compliant part. ?2001C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d01977-0-6/09(a)

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