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1 typical a pplica t ion fea t ures descrip t ion 100v in forward converter controller the lt ? 8310 is a simple-to-use resonant reset forward converter controller that drives the gate of a low side n-channel mosfet from an internally regulated 10 v sup- ply. the lt8310 features duty mode control that generates a stable, regulated, isolated output using a single power transformer. with the addition of output voltage feedback, via opto-coupler ( isolated) or directly wired (nonisolated), current mode regulation is activated, improving output accuracy and load response. the flexibility to choose transformer turns ratio makes high step-down or step-up ratios possible without operating at duty cycle extremes. the user can program the switching frequency from 100khz to 500 khz to optimize efficiency, performance or external component size. a synchronous output is available for controlling secondary side synchronous rectification to improve efficiency. user programmable protection features include monitors on input voltage ( uvlo and ovlo) and switch current ( overcurrent limit). the lt8310 soft-start feature helps protect the transformer from flux saturation. 78 watt isolated forward converter, 8% v out output voltage load regulation a pplica t ions n input voltage range: 6v to 100v n duty mode control regulates an isolated output without an opto n high efficiency synchronous control n short-circuit (hiccup mode) overcurrent protection n programmable ovlo and uvlo with hysteresis n programmable frequency (100khz to 500khz) n synchronizable to an external clock n positive or negative polarity output voltage feedback with a single fbx pin n programmable soft-start n low shutdown current < 1a n available in fe20 tssop with hv pin spacing n industrial, automotive and military systems n 48 v telecommunication isolated power supplies n isolated and nonisolated dc/dc converters l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. lt8310 uvlo ovlo dfilt rt ss sync intv cc rdvin gate sense gnd v c nc nc fbx sout 4.7f v in 36v to 72v v out 12v 0.6a to 6.5a ?v out ?v in v in 86.6k 1.74k 1.43k 0.025 1% 102k 49.9k 200khz 2.2f 100v 4 47h 2:1 150pf npo ?? 8310 ta01a 10nf 1f 100v 0.47f nc 22f 8 100f + i out (a) 0 v out (v) 13.5 3 8310 ta01b 12.0 11.0 1 2 4 10.5 10.0 14.0 13.0 12.5 11.5 5 6 7 v in = 72v v in = 48v v in = 36v lt 8310 8310f for more information www.linear.com/lt8310
2 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , uvlo ............................................................... 10 0 v intv cc , rdvin , sync .............................................. 20 v d filt ...........................................................................8v v c , ovlo , ss , rt ........................................................ 3 v fbx ................................................................. C3 v to 3v sense ....................................................... C 0.3 v to 0.3 v gate , sout .......................................................... no te 3 operating junction temperature range ( notes 4, 5) lt 83 10 e ............................................. C 40 c to 125 c lt 83 10 i .............................................. C4 0 c to 125 c lt 83 10 h ............................................ C 40 c to 150 c lt 83 10 mp ......................................... C 55 c to 150 c storage temperature range .................. C 65 c to 150 c lead temperature range ( soldering , 10 sec ) ........ 30 0 c (notes 1, 2) fe package 20-lead plastic tssop 1 3 5 6 7 8 9 10 top view 20 18 16 15 14 13 12 11 uvlo ovlo dfilt rt sync ss v c fbx nc v in rdvin intv cc gate sense nc sout 21 gnd t jmax = 125c (e-, i-grades), t jmax = 150c (h-grade), jc = 10c/w, ja = 38c/w exposed pad ( pin 21) is gnd, must be soldered to the ground plane o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt8310efe#pbf lt8310efe#trpbf lt8310fe 20-lead plastic tssop C40c to 125c lt8310ife#pbf lt8310ife#trpbf lt8310fe 20-lead plastic tssop C40c to 125c lt8310hfe#pbf lt8310hfe#trpbf lt8310fe 20-lead plastic tssop C40c to 150c lt8310mpfe#pbf lt8310mpfe#trpbf lt8310fe 20-lead plastic tssop C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ lt 8310 8310f for more information www.linear.com/lt8310
3 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 24v, uvlo = 24v, ovlo = 0v, sync = 0v, sense = 0v, unless otherwise noted. parameter conditions min typ max units supply operating input voltage l 6 100 v v in supply current in shutdown uvlo = 0v uvlo = 1.15v 0.3 5 1 7 a a v in operating current not switching 3.8 4.6 ma uvlo uvlo threshold voltage uvlo falling l 1.196 1.220 1.250 v uvlo threshold hysteresis uvlo rising 40 mv uvlo low quiescent current threshold i vin < 1a l 0.36 0.62 0.85 v uvlo pin input current uvlo = 1.15v uvlo = 1.30v 4.5 5.7 20 6.8 150 a na ovlo ovlo threshold voltage ovlo rising l 1.225 1.250 1.275 v ovlo threshold hysteresis ovlo falling C33 mv ovlo pin input current ovlo = 1.17v ovlo = 1.32v 10 120 150 400 na na linear regulator intv cc regulation voltage i intvcc = 0ma to 20ma l 9.6 10.0 10.3 v regulator dropout voltage (v in C intv cc ) v in = 9v, i intvcc = 20ma 600 mv intv cc undervoltage lockout threshold intv cc falling 4.60 4.75 4.90 v intv cc undervoltage hysteresis 0.45 v intv cc overvoltage lockout threshold intv cc rising 17.0 17.4 17.8 v intv cc overvoltage hysteresis C0.65 v intv cc current limit v in = 12v l 25 33 39 ma intv cc current in shutdown uvlo = 0v, intv cc = 10v 125 a intv cc line regulation 10.8v v in 100v 0.001 0.01 %/v intv cc load regulation 0ma i intvcc 20ma C3.0 C0.4 % duty cycle control minimum gate on-time 190 ns maximum duty cycle v in = 12v l 75 78 82 % rdvin pin input current l 19.7 20.0 20.3 a duty control transconductance (note 6) (i dfilt / v set ) v set = 1v 22.5 25.0 27.5 a/v duty mode control gain (notes 6, 7), gain = v in / v set at i dfilt = 0a v set = 0.5v to 6v l 11.76 12.00 12.24 v/v duty cycle foldback, foldback = duty at v ss = 1.15v/duty (nom) ss = 1.15v 0.14 %/% error amplifier fbx error amp reference voltage fbx > 0v fbx < 0v l l 1.568 C0.820 1.600 C0.800 1.632 C0.780 v v fbx over voltage threshold fbx > 0v fbx < 0v 6 5.5 7.5 7.5 9 10 % % lt 8310 8310f for more information www.linear.com/lt8310
4 parameter conditions min typ max units feedback mode threshold voltage (below = duty mode/above = current mode) fbx > 0v fbx < 0v 0.2 C0.3 0.3 C0.2 0.4 C0.13 v v feedback mode threshold hysteresis fbx > 0v fbx < 0v 20 20 mv mv fbx pin input current fbx = 1.6v fbx = C0.8v C100 70 0 100 100 na na transconductance (i vc /v fbx ) 250 a/v v c source current v fbx = 0v, v vc = 1.3v C14 a v c sink current v fbx = 1.7v, v vc = 1.3v v fbx = C0.85v, v vc = 1.3v 13 11 a a v c pin output impedance 3.3 m v c pin current mode gain 5 v/v gate driver gate rise time c gate = 3.3nf 30 ns gate fall time c gate = 3.3nf 27 ns gate low voltage 0.05 v gate high voltage intv cc C 0.05 v current sense sense pin maximum current threshold l 115 125 135 mv sense pin input current C200 a oscillator switching frequency r t = 100k to gnd, v ss 2.9v r t = 33.2k to gnd, v ss 2.9v r t = 20k to gnd, v ss 2.9v l l l 95 285 475 100 300 500 105 315 525 khz khz khz switching frequency line regulation v in = 6v to 100v 0.01 % rt pin voltage v ss = 3v 0.8 1.0 1.3 v frequency foldback foldback = (f osc at v ss = 1.15v)/f osc(nom) v ss = 1.15v 0.15 0.20 0.25 hz/hz sync pin input high threshold voltage l 2.00 v sync pin input low threshold voltage l 1.00 v sync pin input resistance sync = 2v 200 k sync frequency operating range r t = 33.2k l 260 400 khz minimum sync high setup time f sw = 400khz l 250 ns minimum sync low hold time f sw = 400khz l 250 ns sout driver sout rise time c sout = 1nf 20 ns sout fall time c sout = 1nf 25 ns sout low voltage 0.05 v sout high voltage intv cc C 0.05 v e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 24v, uvlo = 24v, ovlo = 0v, sync = 0v, sense = 0v, unless otherwise noted. lt 8310 8310f for more information www.linear.com/lt8310
5 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 24v, uvlo = 24v, ovlo = 0v, sync = 0v, sense = 0v, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages are relative to gnd unless otherwise noted. all pin currents are defined positive into the pin unless otherwise noted. note 3: do not apply a positive or negative voltage or current source to the gate or sout pins, otherwise permanent damage may occur. note 4: the lt8310e is guaranteed to meet performance specifications from the 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt8310i is guaranteed over the full ?40c to 125c operating junction temperature range. the lt8310h is guaranteed over the full C40c to 150c operating junction temperature range. the lt8310mp is guaranteed over the full C55c to 150c operating junction temperature range. operating lifetime is derated at junction temperatures greater than 125c. note 5: the lt8310 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. continuous operation above the specified maximum junction temperature may impair device reliability. note 6: v set = v intvcc C v rdvin . note 7: line regulation in duty mode control applications is constrained by the accuracy of the rdvin pin input current, the duty mode control gain, and the external set resistor, r set . r set should be specifiied to 1% or better. note 8: see the timing diagrams section. parameter conditions min typ max units sout-to-gate delay (t pre ) sout falling to gate rising (note 8) l 190 240 300 ns gate-to-sout delay (t post ) gate falling to sout rising (note 8) l 0 12 25 ns soft-start ss active switching level (gate switches) 0.95 1.00 1.05 v ss frequency foldback complete f osc within specified limits l 2.5 v ss pin current (note 8) soft-up slow wake hard-down, v ss = 0.4v l l C60 C6 C50 C5 6 C40 C4 a a ma ss reset threshold voltage 0.27 v lt 8310 8310f for more information www.linear.com/lt8310
6 typical p er f or m ance c harac t eris t ics uvlo hysteresis current vs uvlo voltage uvlo hysteresis current vs temperature ovlo threshold voltage vs temperature switching frequency and (period) vs programming resistance duty ? v in line regulation (normalized) duty ? v in temperature regulation duty set current vs temperature t a = 25c, unless otherwise noted. switching frequency vs temperature uvlo threshold vs temperature v in (v) 0 duty ? v in /(12 ? v set ) (v/v) 1.00 1.01 80 8310 g01 0.99 0.98 20 40 60 100 1.02 v set = 2v v set = 1v v set = 0.5v temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 150 duty ? v in (v) error (%) 12.00 12.12 8310 g02 11.88 11.76 175 12.24 0 1 ?1 ?2 2 v set = 1v v in = 96v v in = 48v v in = 24v temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 150 i rdvin (a) 20.0 20.1 8310 g03 19.9 19.8 175 20.2 0 0.5 ?0.5 ?1.0 1.0 v set = 1v error (%) r t (k) 0 0 f sw (khz) t sw (s) 100 200 300 400 600 20 40 60 80 8310 g04 100 120 500 0 2 4 6 8 12 10 f sw t sw temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 150 f sw (khz) 300 303 8310 g05 297 294 175 306 0 1 ?1 ?2 2 r t = 33.2k error (%) temperature (c) ?75 v uvlo (v) 1.26 1.28 1.30 125 8310 g06 1.24 1.22 1.25 1.27 1.29 1.23 1.21 1.20 ?25 25 75 ?50 150 0 50 100 175 rising falling v uvlo (v) 0 i uvlo (a) 4 5 6 1.2 1.4 0.6 0.8 1.0 8310 g07 3 2 0.2 0.4 1.6 1 0 ?1 uvlo falling temperature (c) 4.0 i uvlo (a) 5.0 6.0 7.0 4.5 5.5 6.5 ?25 25 75 125 8310 g08 175 ?50?75 0 50 100 150 v uvlo = 1.15v temperature (c) 1.20 v ovlo (v) 1.22 1.24 1.26 1.21 1.23 1.25 ?25 25 75 125 8310 g09 175 ?50?75 0 50 100 150 rising falling lt 8310 8310f for more information www.linear.com/lt8310
7 sense overcurrent threshold voltage vs temperature intv cc current limit vs input voltage typical p er f or m ance c harac t eris t ics v in quiescent current vs temperature gate driver transition time vs capacitance sout driver transition time vs capacitance fbx regulation voltage vs temperature intv cc voltage vs temperature and load current intv cc dropout voltage vs load current, temperature intv cc current limit vs temperature t a = 25c, unless otherwise noted. temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 150 v sense (v) 125.0 127.5 8310 g10 122.5 120.0 175 130.0 0 2 ?2 ?4 4 error (%) t a , ambient temperature (c) ?75 v intvcc (v) 10.0 10.2 10.4 125 8310 g11 9.8 9.6 9.4 ?50 ?25 0 25 50 75 100 150 175 shutdown at t j 165c load = 1ma load = 10ma load = 20ma intv cc load (ma) 0 0 dropout voltage (v) 0.4 0.8 1.2 1.6 2.4 4 8 12 16 8310 g12 20 24 2.0 t a = 125c t a = ?65c t a = 25c t a , ambient temperature (c) ?75 ?i intvcc (ma) 32 34 36 125 8310 g14 30 28 26 ?50 ?25 0 25 50 75 100 150 175 v in = 12v t j t a + 15c temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 150 positive v fbx (v) 1.600 1.616 8310 g15 1.584 1.568 175 positive negative 1.632 ?0.800 ?0.808 ?0.792 ?0.784 ?0.816 negative v fbx (v) temperature (c) ?75 i vin (ma) 4.4 4.5 4.6 150125 8310 g16 4.3 4.2 4.0 ?25 25 75 ?50 175 0 50 100 4.1 4.8 4.7 gate, sout pins not switching v in (v) 0 20 ?i intvcc (ma) 25 30 35 40 45 50 20 40 60 80 8310 g13 100 instantaneous from off, t a = t c = 25c thermally settled, t a = 25c c gate (nf) 0 time (ns) 60 80 100 20 8310 g17 40 20 50 70 90 30 10 0 5 10 15 25 t rise v in = 48v f sw = 100khz t fall c sout (nf) 0 time (ns) 60 80 100 6.0 8310 g18 40 20 50 70 90 30 10 0 1.5 3.0 4.5 7.5 t fall v in = 48v f sw = 100khz t rise lt 8310 8310f for more information www.linear.com/lt8310
8 t a = 25c, unless otherwise noted. typical p er f or m ance c harac t eris t ics driver nonoverlap delays vs temperature set current vs soft-start voltage switching frequency (normalized) vs soft-start voltage gate duty cycle (normalized) vs soft-start voltage output voltage transient response (typical applications, pages 1 and 31) temperature (c) ?75 t dly (ns) 150 200 250 300 125 8310 g19 100 50 125 175 225 275 75 25 0 ?25 25 75 ?50 150 0 50 100 175 sout fall to gate rise gate fall to sout rise v ss (v) 0 0 i rdvin (a) 5 10 15 20 25 0.5 1.0 1.5 2.0 8310 g20 2.5 3.0 v ss (v) 0 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 1.5 2.5 8310 g21 0.5 1.0 2.0 3.0 f sw /f sw(nom) (khz/khz) v ss (v) 0 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 1.5 2.5 8310 g22 0.5 1.0 2.0 3.0 duty/duty (norm) (%/%) 100khz 300khz 500khz 1ms/div 8310 g23 v in = 48v i out = 4.5a to 6.5a to 4.5a v out 1v/div lt 8310 8310f for more information www.linear.com/lt8310
9 p in func t ions uvlo ( pin 1): system undervoltage lockout input. program the system falling uvlo threshold (minimum v in voltage) with a resistive voltage divider from v in to this pin. the pin voltage is compared internally to an ac- curate 1.22 v threshold . program the system rising uvlo hysteresis via this pins 5.7 a hysteretic current and the values of the external resistors. the device is shut down below the uvlo threshold and draws 1 a or less from v in when v uvlo 0.36 v ( min). the uvlo pin can withstand 100v maximum. ovlo ( pin 3): system overvoltage lockout input. program the system rising ovlo threshold ( maximum v in voltage) with a resistive voltage divider from v in to this pin. the pin voltage is compared internally to an accurate 1.25v threshold. exceeding the ovlo threshold sets the fault latch and forces a system shutdown. dfilt (pin 5): duty cycle loop filter pin. set the duty cycle loop filter pole by connecting a capacitor to gnd from this pin in both duty mode and current mode ap - plications. consult the applications information section to choose the capacitor value to reduce load step ringing in duty mode control applications. do not float this pin, a capacitor is required. rt ( pin 6): switching period set input. set the oscillator switching period ( frequency) via a resistor to gnd from this pin, typically 20 k to 100 k for 2 s to 10s (500 khz to 100khz). in applications where an external clock drives the sync pin, program the switching period to the expected sync frequency value. place the resistor close to the pin and minimize stray capacitance. do not leave the rt pin open. sync (pin 7): external clock input. drive this pin with an external fixed-frequency clock signal to synchronize switching to it. the sync falling edge is automatically detected and converted to a pulse that starts the minimum off-time of the duty cycle. the sync pulse low and highs times must both be 250 ns. select an r t resistor that programs the internal switch frequency to the external sync frequency to keep the maximum duty cycle limit accurate. when v ss < 1v, the sync pin is ignored. ss (pin 8): soft-start input. program start and hiccup timing by tying an external capacitor between ss and gnd. during normal soft-start this pin sources 50 a. during faults and initial start, a 6ma ( typ) current sink discharges this pin to 0.27v ( typ). the gate pin is shut off until v ss 1 v. after an overcurrent shutdown, the pin sources only 5a until v ss 1 v, which provides an extended wake-up period that reduces power dissipation during repeated start-up retries ( hiccup mode). switching frequency and duty cycle are folded back until ss > 2.5 v. above 1 v, the pin sources 50a until charged to an internal 3v clamp. v c (pin 9): transconductance error amp output. compen- sate the converter loop at this pin with an external series resistor and capacitor to gnd in feedback applications. in opto-isolated feedback applications, compensation is generally done on the secondary side ( see the applica - tions information section). in duty mode control applica- tions that have no output voltage feedback, leave this pin unconnected. fbx (pin 10): feedback input and mode control. standard input for nonisolated applications that require voltage feedback. program output voltage with a resistive voltage divider to compare to the internal 1.6 v reference for positive output applications, or to the C0.8 v reference for negative output applications. when C0.2v < v fbx < 0.3 v, duty mode controls the gate pin, otherwise fbx is assumed to be in control. fbx exceeding its reference by 7.5% ends the switching cycle in progress without triggering a system reset. tie fbx to gnd if duty mode only is desired. sout ( pin 11): synchronization output. pulse transformer driver for applications with synchronous secondary-side control, complementary to gate. the sout falling edge leads gate turn-on by 240ns ( typ), and the rising edge trails gate turn off by 12ns ( typ). actively pulled to intv cc during shutdown. nc (pin 12): no internal connection. connect to gnd. lt 8310 8310f for more information www.linear.com/lt8310
10 p in func t ions sense (pin 13): switch current sense input. positive input of the low side current sense to the control loops and the overcurrent comparator. kelvin - connect this pin to the sense resistor at the source of the n-channel mosfet switch. exceeding 125 mv at this pin triggers an overcur - rent fault , and sends the system into fast shutdown, slow wake-up, and soft-start. ga te (pin 14): switch control output. low side switch drive ( gnd to intv cc ) for external n- channel mosfet. the maximum duty cycle is limited to 78% ( typ) because reso- nant reset forward converters require time for transformer flux to reset. actively pulled to gnd during shutdown. int v cc (pin 15): regulated supply output. a 10 v ldo supply generated from v in and capable of supplying the gate pin. must be bypassed with a 4.7 f capacitor or higher. the regulator voltage can be externally driven up to 17 v, as long as v in v intvcc , to reduce internal power dissipation from v in or to accommodate more than 10v gate drive for high voltage n-channel mosfets. rdvin (pin 16): duty cycle control input. this pin sinks a precise 20 a in normal operation, but less during soft- start, when the duty cycle is folded back. connect a resistor r set between the intv cc and rdvin pins to program the desired (no opto) application output voltage: r set = n p n s ? ? ? ? ? ? ? v out 12 ? ? ? ? ? ? 20a resistor value accuracy contributes directly to the output voltage accuracy, choose appropriate tolerance. in current mode applications, feedback sets v out , therefore program r set to set a maximum duty cycle guardrail that constrains the volt- seconds of flux in the transformer during transients. this pin must be connected to intv cc by a resistor. v in (pin 18): supply input and system input voltage sense. input supply for the part; operational from 6 v to 100v. accurate duty cycle requires accurate sensing of the v in voltage, so keep the connection to the transformer primary short to minimize resistive voltage drops. bypass to gnd with 1f. nc (pin 20): no internal connection. connect to v in . gnd ( exposed pad pin 21): ground. this pin also senses the negative terminal of the current sense resistor. solder the exposed pad directly to the ground plane. lt 8310 8310f for more information www.linear.com/lt8310
11 b lock diagra m c in c dfilt r t uvlo v in i ref 1.22v v out r3 r2 r1 l1 t1 n p :n s d1 d2 ?? 8310 f01 c l 1 ovlo dfilt rt c2 c reg m1 qr s qs r + + rst duty rst pcm ss duty cycle foldback 20a nom. 0a to 20a ss frequency foldback duty ramp clock pulse slope comp 0.25v to 1v + ? 5.7a sys uv 50a 1.6v nc ?0.2v g m = 250a/v ?0.8v fbx 3v hiccup fbx clk hiccup logic 5a 3v 1 1.25v sys ov 1 reg uv g m = 25a/v 4.75v intv cc + 10v intv cc v in rdvin 17.4v rising hyst 0.45v falling hyst ?0.65v reg ov + tim 165c duty loop ramp generator 1v nom. duty latch duty pcm latch pcm gate driver sys ot + ? i ref + ? + ? + + + + + 125mv isw max fb mode ss low i sup g m = 25a/v fb mode ss low + ? 16 gate nc 15 v in 18 + ? 12 v in r set v set r sense sns + + sys uv sys ov sys ot reg uv reg ov isw max 0 1 fbx ov + ? 5 c ss ss 8 v c fbx fb mode 10 6 sync 7 100khz to 500khz oscillator slope comp ramp generator pwm control logic 200k ss low 0.3v 0.27v 1v ss clamps v c 15a + + rq s fault latch fault intv cc ?0.86v fbx ov 1.72v 14 sout driver sout 11 sense 13 gnd exposed pad 21 + ? 3 9 a = 5 c rst figure 1. lt8310 block diagram configured as a nonsynchronous duty mode converter lt 8310 8310f for more information www.linear.com/lt8310
12 ti m ing diagra m s start-up/ soft-start / fault / shutdown / restart nonoverlapping gate/sout v in v uvlo rising ~ 1.26v start up falling 1.22v shut down regulator capacitor dissipating v intvcc v ss v gate v sense 5.2v 1v 1v fast down 0.27v soft-start 8310 td01 overcurrent 125mv t ss t hiccup not to scale 125mv ? ? ? ? ? ? ? ? ? ? ? ? slow wake v sout v gate t pre d ? t sw (1 C d) ? t sw t post t sw 8310 td02 lt 8310 8310f for more information www.linear.com/lt8310
13 o pera t ion i ntroduction the lt8310 is a constant-frequency forward converter controller with a low side n-channel mosfet gate driver and low side switch current sensing that offers two oper- ating modes: duty mode control and peak current mode control. duty mode control that requires no output voltage feedback is targeted for ( but not limited to) isolated duty mode control applications, to which it brings a simple schematic, low parts count, and only one isolation element, a transformer. in current mode control applications, feed- back determines the output voltage, but the duty control loop enforces a programmable relative maximum duty cycle that clamps the volt-seconds of core flux to avoid transformer saturation during transients. at all times the lt8310 also enforces an absolute maximum duty cycle that provides time to reset the core each switching period. with a patent pending architecture, the lt8310s duty control loop imposes volt-second accuracy over the span of input voltage that translates into both accurate output voltage without feedback and protection from transformer saturation. duty mode control the duty mode control loop compels a pwm duty cycle that is inversely proportional to the system input voltage, d(v in ) 1 / v in , which is the correct function for a buck (or buck derived) converter to generate a constant output regardless of the line input. for a given scaling constant k d , d(v in ) = k d v [ ] v in [1] in a forward converter with transformer turns ration n p /n s , v out = d(v in ) ? v in n p / n s = k d n p / n s [2] in the discussion that follows it will be helpful to refer to the block diagram in figure 1. duty mode control governs operation when the feedback pin ( fbx) is tied to gnd. it serves as an accurate volt-second clamp when current mode control governs operation because feedback is present. the system clock starts the pwm duty cycle by driving the gate pin high to close the external mosfet switch and initiating a timing ramp in the duty loop ramp generator. while gate is high, current proportional to v in discharges a capacitor (c dfilt ) between the dfilt pin and gnd; when gate is pulled low, a fixed current charges it. the duty cycle ends when the ramp voltage plus some switch current feedback exceeds the dfilt voltage, at which point gate falls and shuts off the primary-side switch until the start of the next period. the condition of the main switch ( on or off, as indicated by gate pin voltage) controls the sourcing and sinking of current at the dfilt pin. the voltage imposed between the intv cc and rdvin pins, v set , establishes an inter- nal reference current (i ref ). during the switch on-time, d ? t sw , a current proportional to the system input voltage v in ( which is sensed at the v in supply pin) is subtracted from the reference current and driven at dfilt. during the switch off-time , (1-d ) ? t sw , only the reference current is driven. the external capacitor to gnd at dfilt (c dfilt ) integrates the current. in steady-state operation with suf- ficient load , the feedback loop forces the net cycle current to zero, which produces a duty cycle inversely proportional to v in ( equation 3), and ultimately a constant output voltage (equation 4). an external resistor (r set ) between intv cc and rdvin and a precise 20 a sink at rdvin program v set and thus, v out . d = 12 ? v set v in [3] v out = 12 ? v set n p / n s [4] lt 8310 8310f for more information www.linear.com/lt8310
14 o pera t ion several system operation and protection features are exclu - sive to current mode control. when the load is light, auto- matic pulse skipping allows the effective switching period to extend, which lowers the duty cycle without necessitating impractically narrow gate pulses. if fbx pin overvoltage is detected during a cycle, the duty cycle ends, gate falls, and the switch turns off, which allows the output voltage to coast down. when current mode control governs opera - tion, the duty loop circuitry acts as a relative maximum duty cycle clamp that protects the transformer from developing excessive volt- seconds of flux during transients and it limits the output voltage. this feature also allows the system to revert to duty mode control if fbx is grounded. the duty cycle clamp margin is user-programmable. common operation and protection features a programmable soft-start pin ( ss) controls the power-up time and folds back the switching frequency and the duty cycle during start-up to protect the transformer and to limit inrush current. a minimum on-time of 190ns (typ) ensures that the mosfet switch has enough time to turn on reliably, and a maximum duty cycle of 78% guarantees time for core reset each cycle. the sync pin allows an external pulse signal to override the lt8310s oscillator and set the switching period. the sout pin supplies a non-overlapping signal complementary to the gate that may be used for synchronous converter applications. the sout pin driver has about 40% of the gate pins drive strength, and may be used to drive a pulse transformer (isolated) for forced continuous mode (fcm) operation. other protection mechanisms end the normal switching cycle or force system shutdown to protect the applica - tion cir cuit. the minimum and maximum v in operating thresholds are programmed at the uvlo and ovlo pins, respectively. input voltages outside of the set limits shut down the system. shutdown also occurs when the intv cc regulator voltage goes above or below its operating range, and when the die temperature exceeds 165 c. the switch with no output voltage feedback, the secondary-side lc filter might freely ring ( depending on load resistance and parasitics) in response to load current steps; the primary- side switch current that feeds into the duty mode control loop limits the ringing. during the switch on-time, induc - tor current translates to switch current that is scaled and added to the timing ramp. constant current is absorbed into the dc level of the dfilt voltage, which does not af- fect duty cycle, but changing current dynamically adjusts the duty cycle to dampen the ringing. the dfilt capacitor is chosen with respect to the output lc time constant (l 1?c l ) to track out the oscillation. the selection of this capacitor is discussed in the section, compensating the duty mode control loop. duty mode control operation requires a minimum load in steady-state to balance the sum of the transformer mag - netization current and output inductor ripple current, see the section, minimum load requirements. current mode control to serve applications that require tighter output voltage regulation and faster load response, the lt8310 offers standard constant-frequency peak current mode control when output voltage feedback ( opto-isolated or noniso - lated) is connected. the system clock starts the pw m duty cycle by driving the gate pin high to close the external mosfet switch. the switch current flows through the external current sensing resistor r sense and generates a voltage proportional to the switch current. the current sense voltage is amplified and added to a stabilizing slope compensation ramp. when the resulting sum exceeds the control pin ( v c ) voltage, the duty cycle ends, and the main switch is opened. the v c pin level is set by the error ampli- fier, which amplifies the difference between the reference voltage (1.6 v or C0.8 v, depending on the configuration) and the feedback pin ( fbx) voltage. in this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation. lt 8310 8310f for more information www.linear.com/lt8310
15 figure 3. forward converter architecture (nonsynchronous) v in v out l1 n p :n s t1 d2 c rst gate i out i l1 m1 sw fwd cat ?? 8310 f02 c l load d1 o pera t ion overcurrent limit threshold is programmed at the sense pin. if the maximum current limit is reached, a fault latch is set and the system shuts down. upon restart the system will operate in hiccup mode, which extends the soft-start time and thus reduces average power dissipated in the mosfet during repeated retries. forward converter basics a forward converter is a buck - derived topology that comprises a transformer, a primary-side pwm -controlled switch, secondary - side switches, an inductor, and a capaci - tor, as shown in figure 3. the secondary - side switches may be nonsynchronous ( diodes), synchronous ( mosfets), or a combination thereof. the transformer provides galvanic isolation for isolated applications. refer to figure 2 in the following discussion of signals in a forward converter. when the gate signal goes high, the primary winding sees the full input voltage, and the secondary winding voltage has a value scaled by the turns ratio, v in /(n p /n s ). during this period the forward diode figure 2. typical signals in a forward converter d ? t sw (1 C d) ? t sw t sw v sw(max) v sw(pk) v sw(pk) n p /n s v in v gate v sw v fwd v cat i l1 core flux time v in n p /n s i out 0a t rst 8310 f03 lt 8310 8310f for more information www.linear.com/lt8310
16 o pera t ion d1 conducts, which imposes v in /(n p /n s ) C v out across inductor l 1 ( ignoring voltage drop across the diode), for the switch on-time, d ? t sw . when the gate signal goes low, the switch turns off, and the primary winding volt- age collapses as the primary current charges the reset resistor c rst . the switch node voltage (v sw ) resonates past v in , which takes the primary winding voltage nega- tive. the secondary winding voltage also goes negative, for ward diode d1 turns off, and the inductor current flows through the catch diode, d2, which imposes C v out (again ignoring diode drop) across inductor l1 for the switch off-time , (1 C d ) ? t sw . the output voltage may be calculated by considering the volt-second balance in the inductor under steady-state conditions (equation 5), and then solving for v out . equation 6 makes it clear that forcing the duty cycle to be inversely proportional to the input voltage would create a constant output voltage as desired. v in n p / n s ? v out ? ? ? ? ? ? ? d ? t sw + ( ? v out ) ? (1 ? d) ? t sw = 0 [5] v out = d ? v in n p / n s [6] to keep the transformer from saturating, its core flux must be reset periodically. the lt8310 relies on resonant reset each cycle uses a capacitor between the switch node, sw, and ground ( see figure 2). when the main switch turns off at the end of the duty cycle, v sw ramps up to and beyond v in , which cuts off secondary-side current and forces primary-side current to charge the switching node. node sw resonates for half a sine wave until the transformer voltage and current are both zero, which leaves v sw = v in until the next switch activation. note that (1) the maximum voltage on the primary switch exceeds the input voltage, and may be well above it, and (2) ideally, the flux reset completes within the switch off-time before the next cycle begins. the lt8310 controller imposes an absolute maximum duty cycle that provides a predictable minimum off-time ( at a given switching frequency) in which to reset the core. lt 8310 8310f for more information www.linear.com/lt8310
17 intv cc regulator bypassing and operation the gate and sout pin drivers and other chip loads are powered from the intv cc pin, which is an internally regulated supply. the internal low dropout regulator re- quires a capacitor from the in tv cc pin to gnd for stable operation and to store the charge for the large gate and sout switching currents; a 4.7 f capacitor is adequate for most applications. choose a 16 v rated low esr, x7r ceramic capacitor for best performance. place the capaci - tor close to the lt8310 to minimize the trace length both to the intv cc pin and to the chip ground. in shutdown, the intv cc pin sinks 125a ( typical) until the pin voltage falls below 4.75v. an internal current limit on the intv cc output protects the lt8310 from excessive on-chip power dissipation. the minimum specified current limit should be consid - ered when choosing the switching n-channel mosfet and the operating frequency. careful selection of a lower q g mosfet allows higher gate switching frequencies, which leads to smaller magnetics. sout switching current must be accounted for when that pin drives a mosfet gate, but in typical applications where sout is unused or drives an ac -coupled pulse transformer, gate switching dominates the steady-state regulator load and the sout current may be ignored. the mosfet gate drive switching current required may be calculated using equation 7, see the thermal considerations section for further information. i drive = q g ? f sw [7] the in tv cc voltage tracks a few hundred millivolts below the supply voltage until the regulation loop closes when v in exceeds about 10.5 v. the intv cc pin has its own undervoltage disable set to 4.75v ( typical) that protects the external mosfet from excessive power dissipation caused by not being fully enhanced. if the intv cc pin drops below its undervoltage threshold, the gate pin will be forced to gnd, the sout pin will follow the intv cc voltage, and the soft-start pin will be reset. the regulator may be overdriven from external circuitry to reduce switching power dissipation in the lt8310 package, or to drive a mosfet switch with a high threshold. the overdriven intv cc pin voltage must be less than the ic supply to avoid back-driving the v in pin. the intv cc pin a pplica t ions i n f or m a t ion has its own overvoltage threshold set to 17.4v ( typical) that disables the system to protect mosfets rated for v gs( max) = 20 v, a common specification. as with undervoltage shutdown, the gate pin will be forced to gnd, the sout pin will follow the intv cc voltage, and the soft-start pin will be reset. a 4.7f 25 v rated low esr, x7r capacitor is recommended when intv cc is overdriven. programming the system turn-on and turn-off thresholds the system undervoltage and overvoltage thresholds are programmed by a resistive voltage divider from v in to uvlo and ovlo, respectively (figure 4). the falling uvlo threshold,1.22v ( nom), accurately sets the minimum op - erating v in (equation 8), below which the system goes into low power mode. a 5.7a ( typical) pull-down current that is active when the uvlo pin is below its falling threshold provides rising hysteresis that sets the minimum start- up v in (equation 9). the built-in comparator hysteresis contributes a small amount to the rising threshold as well. v in(uvlo falling) = 1.22v ? r3 + r2 + r1 r2 + r1 ? ? ? ? ? ? [8] v in(uvlo rising) = v in(uvlo falling) + 5.7a ? r3 + 40mv ? r3 + r2 + r1 r2 + r1 ? ? ? ? ? ? [9] the rising ovlo threshold , 1.25v ( nom), accurately sets the maximum operating v in (equation 10), above which the system stops switching and awaits soft-start. the built-in comparator hysteresis provides falling hysteresis that sets the maximum restart v in (equation 11). figure 4. resistor connections for system uvlo and ovlo threshold programming gnd lt8310 uvlo ovlo v in v in r3 r2 r1 8310 f04 lt 8310 8310f for more information www.linear.com/lt8310
18 a pplica t ions i n f or m a t ion v in(ovlo rising) = 1.25v ? r3 + r2 + r1 r1 ? ? ? ? ? ? [10] v in(ovlo falling) = v in(ovlo rising) ? 33mv ? r3 + r2 + r1 r1 ? ? ? ? ? ? [11] selecting the resistor values best proceeds as follows: 1. choose v in(uvlo falling) and v in(ovlo rising) for the system 2. choose a rising hysteresis voltage, v hyst(uvlo rising) , and calculate r3 = v hyst(uvlo rising) / 5.7a 3. calculate the sum of r2 + r1 from equation 8 4. calculate r1 from equation 10, which then determines r2, and 5. recheck the thresholds using actual resistor values. programming the duty cycle loop output voltage target in all applications, the lt8310 duty mode control loop must have a programmed output voltage target, v out(targ) , that is the value the converter would produce, without output voltage feedback, using ideal components. for the forward converter, this is characterized by equation 6 (here recast with the target output). v out(targ) = d ? v in n p / n s [12] this is accomplished by setting the scaling factor (k d ) of the duty cycle versus v in function and choosing the transformer turns ratio (n p /n s ). in applications without output voltage feedback, the target voltage minus any voltage drops ( e.g ., diode thresholds, ohmic losses) yields the nominal output voltage, v out . in applications using an opto-coupler, the target is used as an upper guard rail level to the nominal output voltage that is set by feedback, and it is a measure of the relative duty cycle clamp margin. first consider the transformer turns ratio in the core schematic in figure 5. since duty mode control forces the duty cycle to be inversely proportional the input voltage, the largest duty cycle occurs at the lowest operating input voltage. for a given target output voltage and minimum input voltage, the lt8310s maximum duty cycle limit, 75% (min) , constrains the turns ratio per equation 13. n p n s < 0.75 ? v in(min) v out(targ) [13] after fixing the turns ratio, consider the duty cycle. in gen- eral, the highest operating duty cycle should be maximized to best utilize the mosfet each switching period, and to reduce the effect of switching losses each in cycle. the figure 5. forward nonsynchronous converter core schematic lt8310 gate +v in +v out ?v out ?v in v in l1 n p :n s t1 d1 d2 c rst r sense c reg m1 ?? 8310 f05 v c nc c l dfilt intv cc rdvin sense gnd fbx r set c f lt lt 8310 8310f for more information www.linear.com/lt8310
19 a pplica t ions i n f or m a t ion duty cycle should be checked for feasibility and margin over the full v in operating range. the minimum input volt- age produces the maximum duty cycle, which must not exceed the lt8310s minimum-specified maximum duty cycle limit (75%). the maximum input voltage produces the minimum duty cycle, which must be greater than duty cycle of the minimum gate pulse width, f sw ? t on(min) , as in equation 14. f sw ? t on(min) < v out(targ) v in ? n p n s < 0.75 [14] finally, the duty cycle scaling must be programmed. as discussed in the latter part of the section, duty mode control, the voltage difference between the intv cc and rdvin pins, v set , and an accurate internal gain of 12 v/ v sets the duty mode loop scaling constant, k d . the rdvin pin sinks a precise 20 a that permits a single resistor, r set , to program the voltage difference. k d = 12v v ? v set = 12v v ? (20a ? r set ) [15] resistor r set may be chosen to achieve the desired v out(targ) based on equation 16. r set = v out(targ) 12v / v ? n p n s 20a [16] the tolerance of the set resistor contributes directly to the accuracy of the target output voltage, which is especially important to the accuracy of converters operating without output voltage feedback, so always use a 1% or better resistor. keep r set close to the rdvin and intv cc pins of the chip to minimize trace length and avoid cross-coupling with other signals. during soft-start, the rdvin sinking current is reduced to fold back the duty cycle while the clock frequency is also reduced. this protects the transformer by limiting the volt-seconds of flux generated when the clock period is made longer. take care to consider the flux conditions during soft-start if external currents are employed for trimming or margining. programming the switching frequency the rt frequency adjust pin allows the user to program the switching frequency from 100 khz to 500 khz to optimize efficiency and performance or external component size. higher frequency operation yields smaller component size, but increases switching losses and gate driving current, and may not allow sufficiently high or low duty cycle operation. it also decreases magnetization current, which reduces the minimum load requirement under duty cycle mode control. lower frequency operation gives bet - ter performance at the cost of larger external component size. table 1 shows the r t values for several frequencies that match the design equation, equation 17. table 1. resistor selection guidance for some common switching frequencies frequency (f sw ) (khz) period (t sw ) (s) closest 1% resistor (r t ) (k) 100 10.0 100 150 6.67 66.5 200 5.00 49.9 250 4.00 40.2 300 3.33 33.2 350 2.86 28.7 400 2.50 24.9 450 2.22 22.1 500 2.00 20.0 r t = 1000khz f sw ? 10k = t sw 1s ? 10k [17] minimize stray-coupling to the adjacent dfilt and sync pins by keeping the traces short. an external resistor from the rt pin to gnd is required do not leave this pin open. programming the current sense the lt8310 features primary-side switch current sensing that protects the system from excessive load current, damps output ringing when duty mode control dominates, and sets the duty cycle when current mode control dominates. when v sense exceeds 125mv ( nom), the maximum switch current threshold, the system shuts down and attempts a restart after a slow wake-up period ( see programming the soft-start interval and hiccup period). in converter lt 8310 8310f for more information www.linear.com/lt8310
20 a pplica t ions i n f or m a t ion applications operating without output voltage feedback, current sense information is fed back to the duty cycle loop to reduce output voltage ringing due to load current steps that excite the output lc tank. in supply applications, each cycle ends when the amplified sense voltage exceeds the v c pin control level. in all cases, during the cycle on-time, the switch sees the rippling inductor current (i l1 ), scaled by the transformer turns ratio ( equation? 18) plus the transformers primary magnetizing current, i ,p . applying v in across the magnetizing inductance generates a peak magnetizing current of approximately 12 ? v set ? t sw /l ,p . i switch = i l1 n p / n s + i ,p [18] resistor r sense connected between the sense and gnd pins converts the switch current to a voltage. it should be selected to provide the maximum switch current required by the application, including inductor ripple current, without exceeding the sense pins overcurrent threshold. a good rule of thumb is to allow 10% margin on the minimum overcurrent threshold of 115mv. during steady- state operation, the average inductor current equals the load current. in applications under duty mode control, which require a minimum load, less inductor ripple means a lower minimum load current, so peak inductor current might be 10% or less above the maximum load current. output voltage ring damping operates best with a strong average current signal, so r sense should be chosen as large as allowed by the sense pin threshold. equation 19 provides a good value for r sense that accounts for the minimum sense threshold: r sense 115mv 1.1 ? i switch(max) [19] in applications with output voltage feedback, current mode control is most agile with a steep slope to the ripple, so peak inductor current might be 20% or more above the average load current. equation 20 provides a good value for r sense that accounts for the minimum sense threshold: r sense 115mv 1.4 ? i switch(max) [20] it is always prudent to verify the peak inductor current in the application to ensure the sense resistor selection provides margin to the sense overcurrent limit threshold. the placement of r sense should be close to the source of the n-channel mosfet and gnd of the lt8310. the sense input to lt8310 should be a kelvin connection to the positive terminal of r sense . verify the power in the resistor to ensure that it does not exceed its rated maximum. programming the soft-start interval and hiccup period the built - in soft - start circuit significantly reduces the inrush current spike and output voltage overshoot at start-up. please refer to figure 6 and the timing diagrams section for the following discussion of soft-start behavior. the soft-start interval is programmed by a capacitor connected from the ss pin to gnd. in a normal start-up, after the intv cc voltage exceeds its rising threshold of about 5.2v, the ss pin sources 50 a ( typical), which ramps the capacitor voltage. switching commences when the 1.00v switching threshold is exceeded (en_gate high). assuming the ss pin starts fully discharged, the soft-start time, t ss , may be programmed by choosing c ss using equation 21. a 100 nf soft-start capacitor produces about 2ms of delay, which suits many applications. c ss = 50nf ? t ss ms [ ] 1ms [21] the ss pin voltage is discharged when the fault latch is set under any of the following conditions: the uvlo pin voltage falls below its threshold ( sys_uv high), the ovlo pin voltage exceeds its threshold ( sys_ov high), the die temperature exceeds 165c ( sys_ot high), the intv cc voltage falls below or rises above its operating range (reg_uv or reg_ov high), or the sense pin voltage exceeds its maximum threshold because the switch current is too large ( isw_max high). when the fault condition ceases and v ss < 0.27 v, the fault latch clears, which brings about restart as ss rises through the 1v threshold. exceeding maximum switch current sets the hiccup latch, which extends the soft-start time by reducing the pull-up current to 5a ( typical). after the fault latch is reset, the lt 8310 8310f for more information www.linear.com/lt8310
21 a pplica t ions i n f or m a t ion slow wake-up time keeps the retry rate low during over- current conditions to reduce power dissipation. hiccup mode ends and the hiccup latch clears when v ss exceeds 1.00v, after which the pull-up current reverts to 50 a. for practical purposes, the hiccup interval is approximately 8 times the soft-start time (equation 22). t hiccup 8 ? t ss compensating the duty mode control loop in applications without output voltage feedback, little to no output voltage ringing is the desired response; in cur - rent mode applications that have output voltage feedback (isolated or not), this programming ensures controlled operation if the output feedback fails. for best results, the duty mode control loop compensation should be programmed in relation to the lc tank resonance of the output filter to best attenuate output voltage ringing due to load current steps in duty mode control applications , and to best provide the volt-second guardrail in supply converters. the duty control transconductance, nominally g m( dfilt ) = 25 a/v , and the external compensation capaci - tance, c dfilt , define the duty control loop time constant, while the output inductance and capacitance, l1 and cl, define the output resonance time constant. dfilt = c dfilt g m(dfilt) [23] lc = l1 ? c l [24] the output ringing is decently damped when the loop time constant is approximately twice the transformer ratio times the lc resonance, as in equation 25. for more damping and a slower response, increase c dfilt , for less damping and a faster response, decrease c dfilt . c dfilt = 2 ? n p n s ? 25 a v ? l1 ? c l [25] in rare applications where a very fast duty loop response is more advantageous than output voltage ring reduction (e.g., sharp input voltage steps occur more regularly than sharp load current steps), the compensation capacitor may be chosen small for faster loop speed, independent of the lc tanks natural period. 8310 f06 isw_max sys_uv ss_low + 50a 3v hiccup 5a 3v c ss ss 8 en_gate sys uv sys ov sys ot reg uv reg ov isw max qs r fault latch fault_rst fault 0.25v 1v + qs r hiccup latch figure 6. soft-start control logic lt 8310 8310f for more information www.linear.com/lt8310
22 a pplica t ions i n f or m a t ion compensating the direct-wired current mode control loop when output voltage feedback is directly wired to the fbx pin, the lt8310 uses current mode control to regulate the output. to compensate the current mode feedback loop of the lt8310, a series resistor-capacitor network is usually connected from the v c pin to gnd (figure 7). for most applications, a capacitor (c c ) in the range of 1nf to 22 nf is suitable, with 4.7 nf being typical. the resistor (r z ) should fall in the range of 10 k to 50 k, with 20 k being typical. an estimate for r z based on the output voltage, the output capacitance ( c l ), the compensation capacitance (c c ), the sense resistor ( r sense ), the turns ratio ( n p /n s ), and the absolute value of the feedback reference (|v ref | = 1.6v or 0.8v) is: r z = r sense ? 100k ? c l c c ? n p / n s ( ) ? v out v ref [26] a small capacitor is sometimes connected in parallel with the r c compensation network to attenuate the v c voltage ripple induced from the output voltage ripple through the internal error amplifier. the parallel capacitor usually ranges in value from 10pf to 100pf. a practical approach to design the compensation network is to start with the typical c c = 4.7 nf and r z = 20 k, calcu- late an new r z when all the component values in equation 26 are available, then tune the compensation network to optimize the performance. stability should be checked across all operating conditions, including load current, input voltage and temperature. minimum load requirements in standard current mode converters, the controller senses rising output voltage and activates pulse-skipping mode that reduces the power delivered to the load as the output current demand decreases, until there is no load and the main switch is turned off. with no output voltage sensing to command pulse skipping and a v in -based control loop that operates continuously, lt8310 nonsynchronous duty mode control applications require a minimum load in steady state operation to dissipate transformer magnetization and inductor ripple currents. failure to provide the minimum load current results in an increased steady-state output voltage, which peaks at v in /(n p /n s ) when i out = 0a. in equation 27, given an output voltage (v out ), the mini- mum load current is expressed as a function of (1) the figure 7. forward nonsynchronous direct-wired nonisolated basic schematic lt8310 gate +v in +v out ?v out ?v in v in l1 n p :n s t1 d1 d2 c rst r sense c reg m1 ?? 8310 f07 v c r z c c r6 r5 c l dfilt intv cc rdvin sense gnd fbx r set c f lt lt 8310 8310f for more information www.linear.com/lt8310
23 a pplica t ions i n f or m a t ion switching frequency (f sw ), (2) the transformers primary magnetizing inductance (l ) as seen on the secondary- side through the turns ratio (n p /n s ), and (3) the ripple current in the inductor ( l1) during the off-time portion of the duty cycle (1 C d min ). i out(min) = v out 2 ? f sw ? n p / n s ( ) 2 l + 1 ? d min ( ) l1 ? ? ? ? ? ? ? ? [27] the minimum load current may be reduced in three ways, given a fixed output voltage. first, the switching frequency, f sw , may be increased while keeping the same transformer and output inductor. operating at higher frequency tends to decrease efficiency as switching transients account for a higher percentage of the period. some power transfer lost to lower efficiency generally outweighs power spent on burning dummy load current if the natural load is too light. second, the transformer magnetizing inductance may be increased by using more turns to reduce the magnetiz - ing current . within the same family of transformers, an 8:4 transformer will have more magnetizing inductance than a 2:1 transformer, but more turns also means more winding resistance losses. third, the output inductor may be increased, which directly reduces the output ripple current, and thus the minimum load. if an applications natural load is not sufficient, a dedicated load resistor that guarantees the minimum current for a given output voltage may be selected using equation 28. consider the power dissipation when choosing the rating and type of resistor r out . ? r out < 2 ? f sw ? l n p / n s ( ) 2 ? l1 (1 ? d min ) ? ? ? ? ? ? ? ? [28] ohmic loss matters before a more specific discussion of component selection, a general note about dc resistance in the power path is warranted. for duty mode control applications, no volt - age feedback exists to compensate for voltage drops in the system. contributors include the on-resistance of all switches, the current sense resistor, and the dcrs of the transformer and inductor. take care to select components for their low ohmic losses to control both the absolute accuracy of the output voltage and the load regulation effect. once ohmic losses are estimated or measured for a given application, the output voltage target may be adjusted upward, and a new value of set resistor chosen to compensate, see programming the duty cycle loop output voltage target. transformer selection important parameters that guide the choice of transformer include the primary - to - secondary turns ratio, the presence or absence of auxiliary windings and their turns ratios, the power rating, the operating frequency, the magnetiz - ing inductance , the leakage inductance, the dc winding resistances of the primary and secondary and the isolation voltage rating. an applications input voltage range and output voltage target drive the choice of turns ratio between the primary and secondary windings ( see equation 12). dc/dc power transformer winding ratios should be specified to 1%, a variation that directly affects the accuracy of converters without output voltage feedback, but that only influences the duty cycle range in circuits with output voltage feedback. some application circuits require auxiliary primary- or secondary-side rails to accommodate the supply limits of other external devices. switching power dissipation in the lt8310 may be reduced by driving the intv cc regulator externally from a third winding. rather than stipulate a maximum current and core flux limit for dc/dc converter transformers, most vendors specify a power rating, an operating frequency range and a minimum magnetizing inductance. while flux capability ( saturation) is important, most manufacturers specify a power rating. for a lower minimum load current, choose less magnetiz - ing current / more magnetizing inductance. lt 8310 8310f for more information www.linear.com/lt8310
24 a pplica t ions i n f or m a t ion table 2 provides some recommended transformer vendors. table 2.recommended transformer manufacturers manufacturer web address champs technologies www.champs-tech.com coilcraft www.coilcraft.com cooper-coiltronics www.cooperet.com pulse electronics www.pulseelectronics.com wrth-midcom www.we-online.com resonant reset capacitor selection the reset capacitor value must be sized to allow a half period of a sine wave to complete during the shortest off-time the switch normally experiences, namely when v in is lowest and the duty cycle is greatest. the lt8310s maximum duty cycle clamp of 78% typical/82% maximum ( see the electrical characteristics section) sets a lower bound on the off-time of 18% of the period. minimum input voltage, turns ratio, and output voltage target determine the largest duty cycle in steady state operation, d max . the resonant reset time, t rst , must fall between the two: 0.18 ? t sw < t rst < (1 - d max ) ? t sw [29] the maximum switch node voltage, v sw( max) , occurs at the peak of the resonance when the input voltage is greatest. in practical circuits, the switch node might slew beyond v in before resonating, it might initially spike, and then have a high frequency ripple, or it might not complete resonance if the available reset time is too shortall of which change the peak voltage. estimate the maximum switch voltage with equation 30, and increase it by at least 20% when choosing the voltage rating of the reset capacitor. v sw(max) = v in(max) + v out(targ) ? n p n s ? ? ? ? ? ? ? 2 ? t sw t rst [30] a cog/npo type capacitor is the best choice for the reso- nant reset capacitorfirst, for its negligible microphonic action that would otherwise cause electronic or audio interference, and second, for its excellent voltage linearity and flatness over temperature, which makes for consistent timing across operating conditions and less margining of other components and specifications. an initial design value for the resonant reset capacitor requires estimates of the transformers magnetizing in - ductance ( l) and mosfet output capacitance (c oss ), in addition to the reset time target (equation 31). c rst = t rst ? ? ? ? ? ? 2 ? 1 l ? c oss [31] board layout, transformer windings, and the forward diodes also contribute to the total switch node capacitances, and may be subtracted from the resonant capacitor value as required. keep the resonant reset capacitor close to the mosfets drain at one terminal and well grounded with a short trace at the other terminal. prototyping to characterize the actual reset behavior is highly recommended. in step-up applications ( where n p /n s < 1), splitting the capacitance between the primary-side switch node and the secondary-side forward node may help reduce switch node ringing. the secondary-side capacitor value reflects to the primary-side by a factor of (n s /n p ) 2 . primary switch mosfet selection important parameters for the primary n-channel mosfet switch include the maximum drain-source voltage rating (v ds ), the gate-source threshold voltage ( v gs ), the on- resistance (r ds(on) ), the gate charge (q g ), the maximum drain current ( i d ), and the thermal resistances ( jc and ja ). the drain-source breakdown voltage (bv dss or v ds(max) ) is the key to mosfet selection because the primary switch experiences a maximum voltage significantly above the input ( see figure 3), which was estimated in equation 30. many available power mosfets are avalanche-rated, and will easily withstand occasional overvoltage, but regular avalanching is inefficient, and can be destructive depend - ing on energy, frequency, and temperature. derating the result of equation 30 by at least 20% and prototyping the circuit are recommended design procedures. an internal current limit on the intv cc output protects the lt8310 from excessive on-chip power dissipation. the minimum value of this current should be considered when choosing the main n-channel mosfet and the operating frequency. selection of a lower q g mosfet allows higher lt 8310 8310f for more information www.linear.com/lt8310
25 a pplica t ions i n f or m a t ion switching frequencies, which leads to smaller magnetics. the required switching current, i gate , can be calculated using equation 32, see the thermal considerations section for further details. i gate = q g ? f sw [32] the power dissipated in the primary mosfet in a forward converter is described by equation 33. the first term represents the conduction loss in the device, and the second term represents the switching loss. c rss is the reverse-transfer capacitance, which is usually specified in the mosfet characteristics. for maximum efficiency, r ds(on) and c rss should be minimized. p sw = i 2 l(max) ? r ds(on) ? d max + 2 ? v 2 in ? c rss ? f sw ? i l(max) 1a [33] from the known power dissipated in the main mosfet, its junction temperature can be obtained using equation 34. t j must not exceed the mosfet maximum junction temperature rating. it is recommended to measure the mosfet temperature in steady state to ensure that absolute maximum ratings are not exceeded. t j = t a + p sw ? ja = t a + p sw ? ( jc + ca ) [34] input capacitor selection the input capacitor supplies the transient input current through to the transformer and main switch, so it must be sized according to transient current requirements. forward converters experience discontinuous input currents on par with the load current divided by the transformer turns ratio . the switching frequency, output current, and tolerable input voltage ripple are key inputs to estimating the capacitor value required to limit input voltage ripple to a specified level. an x7r type ceramic capacitor is usually the best choice since it has the least variation with temperature and dc bias. low esr and esl at the switching frequency are necessary to avoid excess spiking of the input voltage. to achieve rms input ripple of v in(ripple) , the input capacitor for a forward converter can be estimated using equation 35. for example , 15 f is an appropriate selec- tion for 100 mv rms ripple on a 350 khz converter with 2a maximum load current and a transformer turns ratio of n p /n s = 2. c in = 0.5 ? i l(max) f sw ? v in(ripple) ? n p / n s ( ) [35] table 3 provides some recommended ceramic capacitor vendors. table 3.recommended ceramic capacitor manufacturers manufacturer web address kemet www.kemet.com murata www.murata.com taiyo yuden www.t-yuden.com tdk www.tdk.com inductor selection the inductor used with the lt8310 should have a saturation current rating appropriate to the maximum load current, and thus appropriate to the switch current rating and r sense resistor. for applications with no output voltage feedback, choose an inductor value that keeps ripple current low in support of the minimum load current target, i l(min) . if the contribution of the output inductor equals that of the reflected transformer magnetizing inductance ( l), a first cut for the inductor value based on operating frequency, output voltage, and minimum duty cycle is: l1 = v out ? 1 ? d min ( ) f sw ? i l(min) [36] once both the transformer and inductor are chosen, the minimum load current estimate in equation 27 should be re-evaluated, and the component selections modified if necessary. lt 8310 8310f for more information www.linear.com/lt8310
26 a pplica t ions i n f or m a t ion for applications where current mode control dominates, choose an inductor value that provides a current mode ramp on sense during the switch on- time of approximately 20mv magnitude based on operating frequency, output voltage, minimum duty cycle and transformer turns ratio. the following equation is useful to estimate the inductor value for continuous conduction mode operation: l1 = v out ? 1 ? d min ( ) f sw ? r sense n p / n s ( ) ? 20mv [37] table 4 provides some recommended inductor vendors. table 4. recommended inductor manufacturers manufacturer web address champs technologies www.champs-tech.com coilcraft www.coilcraft.com cooper-coiltronics www.cooperet.com vishay www.vishay.com wrth-midcom www.we-online.com secondary-side switch selection a nonsynchronous application, with or without output voltage feedback, requires only schottky diode switches in the secondary. the forward diode conducts the full (increasing) inductor current when the primary switch is closed, and the reflected magnetization current (much smaller) after resonant reset completes. the catch diode conducts the full ( decreasing) inductor current when the main switch turns off, which is reduced by the magnetiza - tion current after resonant reset completes ( see figure 3). three - pin dual- packaged diodes may be used to save board space because the diodes share a node, but the switches see different reverse voltages, which may favor different parts in higher current applications. the forward diode must withstand in reverse the full primary switch node resonance voltage divided by the primary-to-secondary turns ratio (n p /n s ); see equation 30 for an estimate of the resonant maximum. the catch diode must withstand the maximum input voltage divided by the turns ratio in reverse. however in step-up applications, the catch node may ring, which would require a higher rating for the switch , or a snubber to limit the peak voltage. when choosing diode breakdown ratings consider the likelihood of abnormal operating conditions. for example: incomplete resonant reset increasing the switch node voltage and reverse stress on the forward diode, or sub minimum load current resulting in increased output voltage and reverse stress on the catch diode. as in any converter, the voltage drop across the switches reduces efficiency, which is reason enough to use low threshold schottky diodes with low series resistance. in duty mode control dominated applications, the actual output voltage is reduced from the target voltage by the diode drop. the nominal forward voltage drop at a fixed load can be planned into the target voltage if desired ( see the section, programming the duty loop output voltage target. both the forward and catch diodes must be rated for the maximum inductor current, have suitable power dissipation ratings, and be fast enough relative to the switching frequency to achieve crisp turn-on and turn- off edges. table 5 provides some recommended diode vendors. table 5. recommended diode manufacturers. manufacturer web address central semiconductor www.centralsemi.com diodes, inc. www.diodes.com on semiconductor www.onsemi.com vishay www.vishay.com synchronous applications with mosfet switches in the secondary have the same stresses and requirements as diodes, but the advantage of smaller forward voltage drops. the lt8310 provides the non-overlapping sout signal that is the inverse of the gate drive for synchronizing switch drivers such as the lt8311 or ltc3900 to avoid cross-conduction, see their data sheets for details. synchronous switches will experience body diode con - duction at start-up, shutdown, and during small delays each switching period. consider body diode current and reverse recovery time when selecting mosfet switches. lt 8310 8310f for more information www.linear.com/lt8310
27 a pplica t ions i n f or m a t ion output capacitor selection the inductor in the output stage of a forward converter ensures continuous load current, hence for constant or slowly varying loads, the output capacitance has a relatively easy task of filtering inductor ripple current. fast load steps withdraw or deposit capacitor charge that changes the output voltage until inductor current reacts to restore it and meet the new load demand. in current mode control applications, tight coupling between the voltage and current feedback loops and the compensation zero at the v c pin make for excellent load regulation. the recommended output capacitors for these circuits are a 220 f electrolytic in parallel with a small x7r type ceramic capacitor with low equivalent series resistance (esr). in duty mode control applications, no load voltage feed - back is present, so the peak transient output excursion (v out(pk) ) goes as the product of the l-c filter output impedance (l1/c l ), and the magnitude of the load cur- rent step ( i l(max) ). assuming l1 is fixed by other con- siderations, maximize the load capacitance to minimize the transient peak, as shown in equation 38. the esr specification of the capacitor should be chosen to satisfy equation 39, to minimize its effect. arrange multiple x7r type ceramic capacitors in paral- lel to achieve very low esr and the desired amount of capacitance with good temperature and bias stability. substituting a high valued electrolytic with high esr in parallel with a small x7r capacitor does not provide the same performance, and should be avoided. c l i l(max) v out(pk) ? ? ? ? ? ? ? ? 2 ? l 1 [38] ? esr 2 ? l1 c l [39] in steady-state, output voltage ripple arises from induc- tor ripple current that charges and discharges the output capacitor, and from the voltage drop across its esr. equation 40 provides an estimate of the output ripple in relation to the nominal output voltage. v out(ripple) 1 l1 ? c l ? f 2 sw + esr l1 ? f sw ? ? ? ? ? ? ? ? ? v out(nom) [40] programming the output v oltage in direct-wired feedback applications for nonisolated applications, direct-wired feedback from the load to the fbx pin configures the lt8310 as a tra - ditional peak current mode controlled forward converter. the fbx pin features dual references (1.6 v and C0.8v) that support dc/dc conversion or dc/dc inversion auto - matically. proper selection of the transformer turns ratio also makes large conversion/inversion ratios (step-down or step-up) possible without relying on extremely low or high duty cycles, which improves efficiency. in wired ap - plications, the output voltage (v out ) is set by a resistor divider, as shown in figure 8. figure 8. wired feedback for nonisolated supply applications lt8310 v intvcc v out 8310 f08 v c r z c c r6 r5 dfilt intv cc rdvin fbx gnd r set c dfilt c0 o p t. lt 8310 8310f for more information www.linear.com/lt8310
28 a pplica t ions i n f or m a t ion equations 41 and 42 provide suitable resistor ratios for positive and negative output converters: r6 r5 = v out(pos) 1.6v ? 1 [41] r6 r5 = v out(neg) ? 0.8v ? 1 [42] in this configuration, compensate the lt8310 directly at the v c pin using the guidelines in the compensating the direct- wired current mode control loop section. also, the duty loop must still be programmed and compensated so the volt-second clamp can protect the transformer. select the r set resistor to program a target v out greater than the feedback resistors do to give the volt-second clamp operating headroom; see the programming the duty cycle loop output voltage target section. select the dfilt pin capacitor as described in the compensating the duty mode control loop section. programming the output voltage in opto-isolated feedback applications application circuits requiring both isolation and excellent line regulation can use the lt8310 with opto-isolated feedback. the opto-coupler must be paired with an opto- coupler driver device, e.g., the lt8311 or the lt4430, which usually governs the output voltage programming. in figure 9, a resistive voltage divider, r5 and r6, feeds the fb pin of the lt8311. in general, the output voltage programming in terms of the resistor ratio and opto driver reference level, v ref(opto) , is then: r6 r5 ? ? ? ? ? ? = v out v ref(opto) ? 1 [43] figure 9. key components of an isolated nonsynchronous supply lt8310 gate v in ?v in v out ?v out v in l1 t1 n p :n s d1 d2 c rst r sense c reg v intvcc ?? 8310 f07 v c c l dfilt intv cc rdvin sense gnd fbx r set c f lt c8 lt8311 opto gnd v in fb comp r8 c7 r7 r13 r12 r11 r9 r10 v intvcc v intvcc m1 8310 f09 r6 r5 lt 8310 8310f for more information www.linear.com/lt8310
29 a pplica t ions i n f or m a t ion thermal considerations the lt8310 is rated to a maximum input voltage of 100v. careful attention must be paid to the internal power dis - sipation of the ic at higher input voltages to ensure that a junction temperature of 125c (150 c for h-grade) is not exceeded. this junction limit is especially important when operating at high ambient temperatures. at a junction temperature of 165 c, the thermal limiter shuts down the system, which pulls the gate pin to gnd, pulls the sout pin to intv cc , and discharges the soft-start ( ss) pin to gnd. switching can resume after the device temperature falls by 10c . this function is intended to protect the device during momentary thermal overload. in many applications, the majority of the power dissipation in the ic comes from the supply current needed to drive the gate capacitance of the external power mosfet(s). for the main switch driven by the gate pin, and a switch (if present) on the sout pin, the gate-drive current can be calculated for each as in equation 7. a low q g power mosfet should always be used when op- erating at high input voltages and the switching frequency should also be chosen carefully to ensure that the ic does not exceed a safe junction temperature. the internal junc- tion temperature of the ic can be estimated by: t j = t a + v in ? (i q + i drive (tot) ) ? ja [44] where t a is the ambient temperature, i q is the quiescent current of the part ( maximum 4 ma), and ja is the pack- ages junction -to-ambient thermal impedance (38c/w). for example, an application having t a( max) = 85 c, v in(max) = 80 v, f sw = 200 khz, and having a mosfet with q g = 30 nc, the maximum ic junction temperature will be approximately: t j = 85c + 80v ? (4ma + 30nc ? 200khz) ? 38c/w 115c [45] the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should then be connected to an internal copper ground plane with thermal vias placed directly under the package to spread out the heat dissipated by the ic. the lt8310s internal power dissipation can be reduced by supplying the gate and sout pins ( and some internal circuits) from an external source, such as a regulated auxiliary transformer winding. the intv cc pin may be overdriven as long as 10.5v < v intvcc(max) < v in(min) , which avoids back-driving the v in pin. the practical up- per limit of in tv cc overdrive is 17.4v ( typ) where the regulators overvoltage threshold shuts down switching. pcb layout / thermal guidelines for proper operation, pcb layout must be given special attention. critical programming signals must be able to coexist with high dv/dt signals. compact layout can be achieved but not at the cost of poor thermal management. the following guidelines should be followed to approach optimal performance. 1. ensure that a local bypass capacitor is used ( and placed as close as possible) between v in and gnd for the controller ic(s). 2. the critical programming resistor for timing, r t , must use short traces to both the rt pin and the gnd pin (exposed pad ). keep traces to the rt pin and the dfilt pin separated. 3. the critical programming resistor for duty cycle, r set , must use short traces to both the rdvin pin and the intv cc pin. 4. the current sense resistor for the forward converter must use short kelvin connections to the sense pin and gnd pin (exposed pad). lt 8310 8310f for more information www.linear.com/lt8310
30 a pplica t ions i n f or m a t ion 5. high dv/dt lines should be kept away from both critical programming resistors (r t , r set ), the current sense inputs, the vc pin, the uvlo and ovlo pins, and the fbx feedback traces. 6. gate driver ( gate) and synchronization ( sout) traces should be kept as short as possible. 7. when working with high power components, multiple parallel components are the best method for spread- ing out power dissipation and minimizing temperature rise. in particular, multiple copper layers connected by vias should be used to sink heat away from each power mosfet and power diode. 8. keep high switching current paths away from signal grounding. also minimize trace lengths for those high current switching paths to minimize parasitic inductance. 9. for synchronous applications, ensure that the pulse transformer ( from lt8310s sout pin to the sync pin of the secondary-side controller) is properly damped and not effected by high dv/dt traces. this will prevent false triggering of the synchronous fets, avoiding cross-conduction and repeated soft-start retry (hiccup mode) behavior. lt 8310 8310f for more information www.linear.com/lt8310
31 typical a pplica t ions 78 watt isolated nonsynchronous forward converter lt8310 uvlo ovlo dfilt rt ss sync intv cc rdvin gate sense gnd v c nc nc fbx sout 4.7f v in 36v to 72v v out 12v 0.6a to 6.5a ?v out ?v in v in 86.6k 1.74k 1.43k r sense 0.025 m1 102k 49.9k 200khz c1 2.2f 100v 4 l1 47h t1 2:1 c3 150pf 250v npo ?? 8310 ta02a c4 22f 35v 8 c5 33f 35v tant 3 10nf 1f 100v 0.47f nc d1 d2 d1: vishay vb30120s d2: vishay vbt3080s l1: w rth we74435584700 m1: infineon ipd600n25n3 t1: w rth we750313917 + output voltage line regulation efficiency vs load current v in (v) 30 v out (v) 11.5 12.0 12.5 60 80 8310 ta02b 11.0 10.5 10.0 40 50 70 13.0 13.5 14.0 i out = 0.6a i out = 1.5a i out = 3.5a i out = 6.5a i out (a) 0 90 92 96 3 5 8310 ta02c 88 86 1 2 4 6 7 84 82 94 efficiency (%) v in = 36v v in = 48v v in = 60v v in = 72v lt 8310 8310f for more information www.linear.com/lt8310
32 78 watt isolated synchronous forward converter typical a pplica t ions output voltage line regulation efficiency vs load current lt8310 ltc3900 uvlo cg cs + v cc cs ? sync fg ovlo timer gnd gate sense gnd sout fbxv c nc c1 2.2f 100v 4 v in 36v to 72v v out 12v 0a to 6.5a ?v out ?v in v in 86.6k 1.74k 1.43k 1f 100v l1 22h t1 2:1 t2 1:1 220pf c3 150pf 250v npo r sense 0.025 m3 5.6k m1 m2 c5 22f 25v 4 c6 47f 25v tant 3 330 ?? ?? 8310 ta03a l1: wrth we74435572200 m1: infineon ipd600n25n3 m2: infineon bsc077n12ns3 m3: infineon bsc076n06ns3 q1: central semi mmbt5551 t1: wrth we750313917 t2: pulse pe-68386nl dfilt rt ss sync intv cc rdvin nc 4.7f 16v 102k 49.9k 200khz 10nf 0.47f 5.6k 0.1f 50v 10k 270k 10 100pf 4.7f q1 10v + i out (a) 0 v out (v) 13.5 3 8310 ta03b 12.0 11.0 1 2 4 10.5 10.0 14.0 13.0 12.5 11.5 5 6 7 v in = 36v v in = 48v v in = 72v i out (a) 0 90 92 96 3 5 8310 ta03c 88 86 1 2 4 6 7 84 82 94 efficiency (%) v in = 36v v in = 48v v in = 60v v in = 72v lt 8310 8310f for more information www.linear.com/lt8310
33 typical a pplica t ions 78 watt isolated nonsynchronous forward converter with opto feedback lt8310 uvlo ovlo dfilt rt ss sync intv cc rdvin gate sense gnd fbx sout nc v c 4.7f 16v 2.2nf 0.01f 10k 100k 0.1f 50v r sense 0.025 l2 3300h v in 36v to 72v v out 12v 0a to 6.5a ?v out ?v in v in 86.6k 1.74k 1.43k m1 130k v intvcc v intvcc 6.8nf 49.9k 200khz c1 2.2f 100v 4 l1 22h t1 2:1 c3 150pf 250v npo 2k 6.65k 909k 20.0k moc 207 d1: vishay vb30120s d2: vishay vbt3080s d3, d4: bav3004 d5: bas516 l1: wrth we744355722 l2: coilcraft lps5030-335mrb m1: infineon ipd600n25n3 q1: central semi mmbt5551 t1: wrth we750313917 11.3k 8310 ta04a 215k 6.34k 330 10 330 4.7f 16v 220pf ?? c4 22f 25v 4 c5 33f 25v tant 3 1f 100v 0.47f nc d1 d3 d2 d4 d5 lt4430 v in gnd opto fb oc comp q1 10v + output voltage line regulation efficiency vs load current i out (a) 0 v out (v) 11.5 12.0 12.5 3 7 8310 ta04b 11.0 10.5 10.0 1 2 4 5 6 13.0 13.5 14.0 v in = 36v to 72v i out (a) 0 90 92 96 3 5 8310 ta03c 88 86 1 2 4 6 7 84 82 94 efficiency (%) v in = 36v v in = 48v v in = 60v v in = 72v lt 8310 8310f for more information www.linear.com/lt8310
34 typical a pplica t ions wide v in , 60 watt isolated 8v rail for low voltage regulators output voltage line regulation efficiency vs load current lt8310 ltc3900 uvlo cg cs + v cc cs ? sync fg ovlo timer gnd gate sense gnd sout fbxv c nc c1 2.2f 100v 4 v in 9v to 42v v out 8v 0a to 7.5a ?v out ?v in v in 39.2k 5.62k 1.24k 1f 100v l2 3300h t1 3:4 t2 1:1 220pf c3 2200pf 100v npo 2 r sense 0.008 m3 30.1k m1 m2 c5 22f 25v 4 c6 22f 25v tant 5 l1 33h 330 ?? ?? 8310 ta05a d1, d2: bav3004 d3: central semi cmmr1u-02 l1: wrth we74435583300 l2: coilcraft lps5030-335mrb m1: infineon bsc057n08s3-gl note 1: in general, two stacked 5v to 6v zeners will have less thermal variation than a single 10v to 12v zener note 2: for example, use three (3) paralleled 10k, 1w resistors m2: infineon bsc067n06ls3-g m3: infineon bsc060n10s3-g q1: central semi mmbt5551 t1: wrth we750341138 t2: pulse pe-68386nl dfilt 10nf 10 rt ss sync intv cc rdvin nc 4.7f 16v 25.5k 49.9k 200khz 2.2nf 0.47f 30.1k 0.1f 50v 470 d1 d2 10 3.3k 3w note 2 note 1 5.6v 5.6v 220pf 4.7f 16v 33nf 100v q1 270k + i out (v) 0 v out (v) 8.0 9.0 8 8310 ta05b 7.0 6.0 2 4 6 1 3 5 7 10.0 7.5 8.5 6.5 9.5 v in = 9v v in = 18v v in = 30v v in = 42v i out (a) 0 72 efficiency (%) 76 80 84 88 2 4 6 8 8310 ta05c 92 96 1 3 5 7 v in = 9v v in = 18v v in = 30v v in = 42v lt 8310 8310f for more information www.linear.com/lt8310
35 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. fe20(16) (cb) tssop rev 0 0512 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 5 6 7 8 9 10 111214 13 6.40 ? 6.60* (.252 ? .260) 3.86 (.152) 2.74 (.108) 20 18 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package variation: fe20(16) 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1924 rev ?) exposed pad variation cb lt 8310 8310f for more information www.linear.com/lt8310
36 ? linear technology corporation 2014 lt 0814 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt8310 r ela t e d p ar t s typical a pplica t ion part number description comments lt3752/lt3752-1 active clamp synchronous forward controllers with internal housekeeping controller input voltage range: lt3752: 6.5v to 100v,?lt3752-1: limited only by external components lt3753 active clamp synchronous synchronous forward controller input voltage range: 8.5v to 100v lt8311 preactive secondary-side synchronous forward controller optimized for use with primary-side lt3752/-1, lt3753 and lt8310 controllers lt c ? 3765/ltc3766 synchronous no-opto forward controller chip set with active clamp reset direct flux limit?, supports self-starting secondary forward control ltc3723-1/ltc3723-2 synchronous push-pull and full-bridge controllers high efficiency with on-chip mosfet drivers, adjustable synchronous rectification timing ltc3721-1/ltc3721-2 nonsynchronous push-pull and full-bridge controllers minimizes external components, on-chip mosfet drivers ltc3722/ltc2722-2 synchronous full-bridge controllers adaptive or manual delay control for zero voltage switching, adjustable synchronous rectification timing lt3748 100v isolated flyback controller 5v v in 100v, no-opto flyback , msop-16 with high voltage spacing lt3798 off-line isolated no-opto flyback controller with active pfc v in and v out limited only by external components ltc3900 synchronous rectifier n-channel mosfet driver for forward converters programmable timeout and reverse-inductor protection, transformer synchronization, ssop-16 lt4430 secondary-side optocoupler driver with reference voltage overshoot control prevents output overshoot during start-up and short-cir cuit recovery 94% efficient, 150w isolated synchronous forward converter lt8310 uvlo ovlo dfilt rt ss sync intv cc rdvin gate sense gnd sout nc v c fbx 4.7f 16v 3.9nf 220pf v in 36v to 72v ?v in v in 86.6k 1.74k 1.43k r sense 0.012 m1 m2 121k v intvcc v intvcc 40.2k 249khz c1 4.7f 100v 4 t1 8:4 390pf 250v 90.9k 178 d1 l1 8h 178 ?? t2 1.25:1 ?? 1f 100v 0.47f 20k 62k 10k 499k 3.3k 100k 11.3k 100k 20k 4k 22nf 4k 499 560 ps2801-1 100pf 1f 22nf 4.7f d1: central semi cmmr1u-02 l1: champs hrpqi2050-08 m1: infineon bsc320n20ns3g m2: infineon bsc042ne7ns3 m3: fairchild semi fdms86101dc t1: pulse pa0423 t2: pulse pa3493nl 2.2f 8310 ta06a v out ?v out 68pf 47f 2 470f v out 12v 0a to 12.5a 3.9nf m3 fg csp cg csn fb fsw csw v in sync comp opto pgood intvcc pmode ss gnd timer lt8311 + lt 8310 8310f for more information www.linear.com/lt8310

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