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| datasheet specifications in this document are tentative and subject to change. rl78/g1a renesas mcu combines multi-channel 12-bit a/d converter, true low power platform (as low as 66 a/mhz, and 0.57 a for rtc + lvd), 1.6 v to 3.6 v operation, 16 to 64 kbyte flash, 41 dmips at 32 mhz page 1 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 r01ds0151ej0100 rev.1.00 2013.09.25 1. outline 1.1 features ultra-low power technology ? 1.6 v to 3.6 v operation from a single supply ? stop (ram retained): 0.23 a, (lvd enabled): 0.31 a ? halt (rtc + lvd): 0.57 a ? snooze: 0.7 ma (uart), 0.6 ma (adc) ? operating: 66 a/mhz 16-bit rl78 cpu core ? delivers 41 dmips at maximum operating frequency of 32 mhz ? instruction execution: 86% of instructions can be executed in 1 to 2 clock cycles ? cisc architecture (harvard) with 3-stage pipeline ? multiply signed & unsigned: 16 x 16 to 32-bit result in 1 clock cycle ? mac: 16 x 16 to 32-bit result in 2 clock cycles ? 16-bit barrel shifter for shi ft & rotate in 1 clock cycle ? 1-wire on-chip debug function code flash memory ? density: 16 kb to 64 kb ? block size: 1 kb ? on-chip single voltage flash memory with protection from block erase/writing ? self-programming with secure boot swap function and flash shield window function data flash memory ? data flash with background operation ? data flash size: 4 kb ? erase cycles: 1 million (typ.) ? erase/programming voltage: 1.8 v to 3.6 v ram ? 2 kb to 4 kb size options ? supports operands or instructions ? back-up retention in all modes high-speed on-chip oscillator ? 32 mhz with +/ ? 1% accuracy over voltage (1.8 v to 3.6 v) and temperature ( ? 20 c to +85 c) ? pre-configured settings: 32 mhz, 24 mhz, 16 mhz, 12 mhz, 8 mhz, 6 mhz, 4 mhz, 3 mhz, 2 mhz, and 1 mhz reset and supply management ? power-on reset (por) monitor/generator ? low voltage detection (lvd) with 12 setting options (interrupt and/or reset function) data memory access (dma) controller ? up to 2 fully programmable channels ? transfer unit: 8- or 16-bit multiple communication interfaces ? up to 6 x i 2 c master ? up to 1 x i 2 c multi-master ? up to 6 x csi/spi (7-, 8-bit) ? up to 3 x uart (7-, 8-, 9-bit) ? up to 1 x lin extended-function timers ? multi-function 16-bit timers: up to 8 channels ? real-time clock (rtc): 1 channel (full calendar and alarm function with watch correction function) ? interval timer: 12-bit, 1 channel ? 15 khz watchdog timer: 1 channel (window function) rich analog ? adc: up to 28 channels, 12-bit resolution, 3.375 s conversion time ? supports 1.6 v ? internal voltage reference (1.45 v) ? on-chip temperature sensor safety features (iec or ul 60730 compliance) ? flash memory crc calculation ? ram parity error check ? ram write protection ? sfr write protection ? illegal memory access detection ? clock stop/ frequency detection ? adc self-test general purpose i/o ? 3.6 v tolerant, high-current (up to 20 ma per pin) ? open-drain, internal pull-up support operating ambient temperature ? standard: ? 40 c to +85 c ? extended: ? 40 c to +105 c package type and pin count from 3 mm x 3 mm to 10 mm x 10 mm qfp: 48, 64 qfn: 32, 48 lga: 25 bga: 64 rl78/g1a 1. outline page 2 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 { rom, ram capacities rl78/g1a flash rom data flash ram 25 pins 32 pins 48 pins 64 pins 64 kb 4 kb 4 kb note r5f10e8e r5f10ebe r5f10ege r5f10ele 48 kb 4 kb 3 kb r5f10e8d r5f10ebd r5f10egd r5f10eld 32 kb 4 kb 2 kb r5f10e8c r5f10ebc r5f10egc r5f10elc 16 kb 4 kb 2 kb r5f10e8a r5f10eba r5f10ega ? note this is about 3 kb when the self-programming function and data flash function are used. rl78/g1a 1. outline page 3 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 1.2 list of part numbers figure 1-1. part number, memo ry size, and package of rl78/g1a part no. r 5 f 1 0 e l c a x x x f b # v 0 package type: rom number (omitted with blank products) rom capacity: rl78/g1a group renesas mcu renesas semiconductor product bg : vfbga, 0.40 mm pitch fb : lfqfp, 0.50 mm pitch la : wflga, 0.50 mm pitch na : hwqfn, 0.50 mm pitch a : 16 kb c : 32 kb d : 48 kb e : 64 kb pin count: 8 : 25-pin b : 32-pin g : 48-pin l : 64-pin classification: a : consumer applications : t a = ? 40?c to 85?c g : industrial applications : t a = ? 40?c to 105?c memory type: f : flash memory packing #u0 : tray (hwqfn, vfbga, wflga) #v0 : tray (lfqfp) #w0 : embossed tape (hwqfn, vfbga, wflga) #x0 : embossed tape (lfqfp) caution the part number above is valid as of when this manual was issued. for the latest part number, see the web page of the target product on the renesas el ectronics website. rl78/g1a 1. outline page 4 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 table 1-1. list of ordering part numbers pin count package fields of application note 1 ordering part number a r5f10e8aala#u0, r5f10e8cala#u0, r5f10e8dala#u0, r5f10e8eala#u0, r5f10e8aala#w0, r5f10e8cala#w0, r5f10e8dala#w0, r5f10e8eala#w0 25 pins 25-pin plastic wflga (3 3 mm, 0.5 mm pitch) g note 2 r5f10e8agla#u0, r5f10e8cgla#u0, r5f10e8dgla#u0, r5f10e8egla#u0, r5f10e8agla#w0, r5f10e8cgla#w0, r5f10e8dgla#w0, r5f10e8egla#w0 a r5f10ebaana#u0, r5f10ebcana#u0, r5f10ebdana#u0, r5f10ebeana#u0, r5f10ebaana#w0, r5f10ebcana#w0, r5f10ebdana#w0, r5f10ebeana#w0 32 pins 32-pin plastic hwqfn (5 5 mm, 0.5 mm pitch) g r5f10ebagna#u0, r5f10ebcgna#u0, r5f10ebdgna#u0, r5f10ebegna#u0, r5f10ebagna#w0, r5f10ebcgna#w0, r5f10ebdgna#w0, r5f10ebegna#w0 a r5f10egaafb#v0, r5f10egcafb#v0, r5f10egdafb#v0, r5f10egeafb#v0, r5f10egaafb#x0, r5f10egcafb#x0, r5f10egdafb#x0, r5f10egeafb#x0 48-pin plastic lfqfp (7 7 mm, 0.5 mm pitch) g r5f10ebagna#v0, r5f10ebcgna#v0, r5f10ebdgna#v0, r5f10ebegna#v0, r5f10ebagna#x0, r5f10ebcgna#x0, r5f10ebdgna#x0, r5f10ebegna#x0 a r5f10egaana#u0, r5f10egcana#u0, r5f10egdana#u0, r5f10egeana#u0, r5f10egaana#w0, r5f10egcana#w0, r5f10egdana#w0, r5f10egeana#w0 48 pins 48-pin plastic hwqfn (7 7 mm, 0.5 mm pitch) g r5f10egagna#u0, r5f10egcgna#u0, r5f10egdgna#u0, r5f10egegna#u0, r5f10egagna#w0, r5f10egcgna#w0, r5f10egdgna#w0, r5f10egegna#w0 a r5f10elcafb#v0, r5f10eldafb#v0, r5f10eleafb#v0, r5f10elcafb#x0, r5f10eldafb#x0, r5f10eleafb#x0 64-pin plastic lfqfp (10 10 mm, 0.5 mm pitch) g r5f10elcgfb#v0, r5f10eldgfb#v0, r5f10elegfb#v0, r5f10elcgfb#x0, r5f10eldgfb#x0, r5f10elegfb#x0 a r5f10elcabg#u0, r5f10eldabg#u0, r5f10eleabg#u0, r5f10elcabg#w0, r5f10eldabg#w0, r5f10eleabg#w0 64 pins 64-pin plastic vfbga (4 4 mm, 0.4 mm pitch) g note 2 r5f10elcgbg#u0, r5f10eldgbg#u0, r5f10elegbg#u0, r5f10elcgbg#w0, r5f10eldgbg#w0, r5f10elegbg#w0 notes 1. for the fields of application, see figure 1-1 part number, memory size, and package of rl78/g1a . 2. in planning caution the part number above is valid as of when this manual was issued. for the latest part number, see the web page of the target product on the renesas el ectronics website. rl78/g1a 1. outline page 5 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 1.3 pin configuration (top view) 1.3.1 25-pin products ? 25-pin plastic wflga (3 3 mm, 0.50 mm pitch) index mark top view bottom view 5 4 3 2 1 abcde edcba index mark a b c d e 5 p40/tool0 reset p03/ani16/ rxd1/to00/ (kr1) p23/ani3/ (kr3) av ss 5 4 p122/x2/ exclk p137/intp0 p02/ani17/ txd1/ti00/ (kr0) p22/ani2/ (kr2) av dd 4 3 p121/x1 v dd p21/ani1/ av refm p11/ani20/ si00/sda00/ rxd0/ toolrxd p10/ani18/ sck00/scl00 3 2 regc v ss p30/ani27/ sck11/scl11/ intp3 p51/ani25/ so11/intp2 p50/ani26/ si11/sda11 intp1 2 1 p60/scla0 p61/sdaa0 p31/ani29/ti03/ to03/pclbuz0 /intp4 p12/ani21/ so00/txd0/ tooltxd p20/ani0/ av refp 1 a b c d e caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 6 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 1.3.2 32-pin products ? 32-pin plastic hwqfn (5 5 mm, 0.5 mm pitch) 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 p24/ani4/(kr5) p23/ani3/ (kr4) p22/ani2/ (kr3) p21/ani1 /av refm p20/ani0 /av refp p03/ani16/rxd1/to00/(kr2) p02/ani17/txd1/ti00/(kr1) p120/ani19/(kr0) p51/so11/intp2 p50/ani26/si11/sda11/intp1 p30/ani27/sck11/scl11/intp3 p70/ani28/kr0 p31/ani29/ti03/to03/pclbuz0/intp4 p62 p61/sdaa0 p60/scla0 exposed die pad av ss av dd p10/ani18/sck00/scl00/(kr0) p11/ani20/si00/sda00/rxd0/toolrxd/(kr1) p12/ani21/so00/txd0/tooltxd/(kr2) p13/ani22/so20/txd2/(kr3) p14/ani23/si20/sda20/rxd2/(kr4) p15/ani24/sck20/scl20/pclbuz1/(kr5) p40/tool0 reset p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd index mark caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). 3. it is recommended to connect an exposed die pad to v ss . rl78/g1a 1. outline page 7 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 1.3.3 48-pin products ? 48-pin plastic lfqfp (7 7 mm, 0.5 mm pitch) 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 p120/ani19 p41/ani30/ti07/to07 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p140/pclbuz0/intp6 p02/ani17/txd1/ti00/(kr0) p03/ani16/rxd1/to00/(kr1) p130 p20/ani0/av refp p21/ani1/av refm p22/ani2/(kr2) p23/ani3/(kr3) p24/ani4/(kr4) p25/ani5/(kr5) p26/ani6 p27/ani7 av ss av dd p150/ani8 p10/ani18/sck00/scl00/(kr0) p11/ani20/si00/sda00/rxd0/toolrxd/(kr1) p12/ani21/so00/txd0/tooltxd/(kr2) p13/ani22/so20/txd2/(kr3) p14/ani23/si20/sda20/rxd2/(kr4) p15/ani24/sck20/scl20/pclbuz1/(kr5) p16/ti01/to01/intp5 p51/ani25/so11/intp2 p50/ani26/si11/sda11/intp1 p60/scla0 p61/sdaa0 p62 p63 p31/ani29/ti03/to03/intp4 p75/sck01/scl01/intp9/kr5 p74/si01/sda01/intp8/kr4 p73/so01/kr3 p72/so21/kr2 p71/si21/sda21/kr1 p70/ani28/sck21/scl21/kr0 p30/ani27/sck11/scl11/intp3/rtc1hz caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 8 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 ? 48-pin plastic hwqfn (7 7 mm, 0.5 mm pitch) 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 p120/ani19 p41/ani30/ti07/to07 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss v dd p140/pclbuz0/intp6 p02/ani17/txd1/ti00/(kr0) p03/ani16/rxd1/to00/(kr1) p130 p20/ani0/av refp p21/ani1/av refm p22/ani2/(kr2) p23/ani3/(kr3) p24/ani4/(kr4) p25/ani5/(kr5) p26/ani6 p27/ani7 av ss av dd p150/ani8 p10/ani18/sck00/scl00/(kr0) p11/ani20/si00/sda00/rxd0/toolrxd/(kr1) p12/ani21/so00/txd0/tooltxd/(kr2) p13/ani22/so20/txd2/(kr3) p14/ani23/si20/sda20/rxd2/(kr4) p15/ani24/sck20/scl20/pclbuz1/(kr5) p16/ti01/to01/intp5 p51/ani25/so11/intp2 p50/ani26/si11/sda11/intp1 p60/scla0 p61/sdaa0 p62 p63 p31/ani29/ti03/to03/intp4 p75/sck01/scl01/intp9/kr5 p74/si01/sda01/intp8/kr4 p73/so01/kr3 p72/so21/kr2 p71/si21/sda21/kr1 p70/ani28/sck21/scl21/kr0 p30/ani27/sck11/scl11/intp3/rtc1hz caution connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification . 2. functions in parentheses in the above figure can be assigned via setting s in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 9 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 1.3.4 64-pin products ? 64-pin plastic lfqfp (10 10 mm, 0.5 mm pitch) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p27/ani7 p26/ani6/(kr9) p25/ani5/(kr8) p24/ani4/(kr7) p23/ani3/(kr6) p22/ani2/(kr5) p21/ani1/av refm p20/ani0/av refp p130 p04/sck10/scl10/(kr4) p03/ani16/si10/sda10/rxd1/(kr3) p02/ani17/so10/txd1/(kr2) p01/to00/(kr1) p00/ti00/(kr0) p141/pclbuz1/intp7 p140/pclbuz0/intp6 p30/ani27/sck11/scl11/intp3/rtc1hz p05/ti05/to05/kr8 p06/ti06/to06/kr9 p70/ani28/sck21/scl21/kr0 p71/si21/sda21/kr1 p72/so21/kr2 p73/so01/kr3 p74/si01/sda01/intp8/kr4 p75/sck01/scl01/intp9/kr5 p76/intp10/kr6 p77/intp11/kr7 p31/ani29/ti03/to03/intp4 p63 p62 p61/sdaa0 p60/scla0 av ss av dd p150/ani8 p151/ani9/(kr6) p152/ani10/(kr7) p153/ani11/(kr8) p154/ani12/(kr9) p10/ani18/sck00/scl00/(kr0) p11/ani20/si00/sda00/rxd0/toolrxd/(kr1) p12/ani21/so00/txd0/tooltxd/(kr2) p13/ani22/so20/txd2/(kr3) p14/ani23/si20/sda20/rxd2/(kr4) p15/ani24/sck20/scl20/(kr5) p16/ti01/to01/intp5 p51/ani25/so11/intp2 p50/ani26/si11/sda11/intp1 p120/ani19 p43 p42/ti04/to04 p41/ani30/ti07/to07 p40/tool0 reset p124/xt2/exclks p123/xt1 p137/intp0 p122/x2/exclk p121/x1 regc v ss ev ss0 v dd ev dd0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 cautions 1. make ev ss0 pin the same potential as v ss pin. 2. make v dd pin the potential that is higher than ev dd0 pin. 3. connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification. 2. when using the microcontroller for an applicat ion where the noise generated inside the microcontroller must be reduced, it is reco mmended to supply separate powers to the v dd and ev dd0 pins and connect the v ss and ev ss 0pins to separate ground lines. 3. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 10 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 ? 64-pin plastic vfbga (4 4 mm, 0.4 mm pitch) 1 hgfedcba 2 3 4 5 6 7 8 abcdefgh top view bottom view index mark pin no. name pin no. name pin no. name pin no. name a1 p05/ti05/to05/kr8 c1 p51/ani25/so11 /intp2 e1 p153/ani11/(kr8) g1 av dd a2 p30/ani27/sck11 /scl11/intp3 /rtc1hz c2 p71/si21/sda21/kr1 e2 p154/ani12/(kr9) g2 p25/ani5/(kr8) a3 p70/ani28/sck21 /scl21/kr0 c3 p74/si01/sda01 /intp8/kr4 e3 p10/ani18/sck00 /scl00/(kr0) g3 p24/ani4/(kr7) a4 p75/sck01/scl01 /intp9/kr5 c4 p16/ti01/to01/intp5 e4 p11/ani20/si00 /sda00/rxd0 /toolrxd/(kr1) g4 p22/ani2/(kr5) a5 p77/intp11/kr7 c5 p15/ani24/sck20 /scl20/(kr5) e5 p03/ani16/si10 /sda10/rxd1/(kr3) g5 p130 a6 p61/sdaa0 c6 p63 e6 p41/ani30/ti07/to07 g6 p02/ani17/so10/txd1 /(kr2) a7 p60/scla0 c7 v ss e7 reset g7 p00/ti00/(kr0) a8 ev dd0 c8 p121/x1 e8 p137/intp0 g8 p124/xt2/exclks b1 p50/ani26 /si11 /sda11/intp1 d1 p13/ani22/so20 /txd2/(kr3) f1 p150/ani8 h1 av ss b2 p72/so21/kr2 d2 p06/ti06/to06/kr9 f2 p151/ani9/(kr6) h2 p27/ani7 b3 p73/so01/kr3 d3 p12/ani21/so00 /txd0/tooltxd/(kr2) f3 p152/ani10/(kr7) h3 p26/ani6/(kr9) b4 p76/intp10/kr6 d4 p14/ani23/si20/ sda20/rxd2/(kr4) f4 p21/ani1/av refm h4 p23/ani3/(kr6) b5 p31/ani29/ti03/to03 /intp4 d5 p42/ti04/to04 f5 p04/sck10/scl10 /(kr4) h5 p20/ani0/av refp b6 p62 d6 p40/tool0 f6 p43 h6 p141/pclbuz1/intp7 b7 v dd d7 regc f7 p01/to00/(kr1) h7 p140/pclbuz0/intp6 b8 ev ss0 d8 p122/x2/exclk f8 p123/xt1 h8 p120/ani19 cautions 1. make ev ss0 pin the same potential as v ss pin. 2. make v dd pin the potential that is higher than ev dd0 pin. 3. connect the regc pin to vss via a capacitor (0.47 to 1 f). remarks 1. for pin identification, see 1.4 pin identification. 2. when using the microcontroller for an appl ication where the no ise generated inside the microcontroller must be reduced, it is reco mmended to supply separate powers to the v dd and ev dd0 pins and connect the v ss and ev ss0 pins to separate ground lines. 3. functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 11 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 1.4 pin identification ani0 to ani12, ani16 to ani30: analog input av dd : analog power supply av ss : analog ground av refm : a/d converter reference potential ( ? side) input av refp : a/d converter reference potential (+ side) input ev dd0 : power supply for port ev ss0 : ground for port exclk: external clock input (main system clock) exclks: external clock input (subsystem clock) intp0 to intp11: interrupt request from external kr0 to kr9: key return p00 to p06: port 0 p10 to p16: port 1 p20 to p27: port 2 p30, p31: port 3 p40 to p43: port 4 p50, p51: port 5 p60 to p63: port 6 p70 to p77: port 7 p120 to p124: port 12 p130, p137: port 13 p140, p141: port 14 p150 to p154: port 15 pclbuz0, pclbuz1: programmable clock output/buzzer output regc: regulator capacitance reset: reset rtc1hz: real-time cloc k correction clock (1 hz) output rxd0 to rxd2: receive data sck00, sck01, sck10, sck11, sck20, sck21: serial clock input/output scla0, scl00, scl01, scl10, scl11, scl20, scl21: serial clock output sdaa0, sda00, sda01, sda10, sda11, sda20, sda21: serial data input/output si00, si01, si10, si11, si20, si21: serial data input so00, so01, so10, so11, so20, so21: serial data output ti00, ti01, ti03 to ti07: timer input to00, to01, to03 to to07: timer output tool0: data input/output for tool toolrxd, tooltxd: data inpu t/output for external device txd0 to txd2: transmit data v dd : power supply v ss : ground x1, x2: crystal oscillator (main system clock) xt1, xt2: crystal oscillator (subsystem clock) rl78/g1a 1. outline page 12 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 1.5 block diagram 1.5.1 25-pin products port 1 p10 to p12 port 2 p20 to p23 4 port 3 p30, p31 2 port 4 port 5 3 port 12 p121, p122 p40 voltage regulator regc interrupt control ram power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11 txd0/p12 rxd1/p03 txd1/p02 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ch3 ti03/to03/p31 ch0 ch1 ch4 ch5 ch6 ch7 intp0/p137 intp3/p30, intp4/p31 intp1/p50 a/d converter 4 ani0/p20 to ani3/p23 av refp /p20 av refm /p21 2 port 13 p137 csi11 sck11/p30 so11/p51 si11/p50 iic11 scl11/p30 sda11/p50 ti00/p02 to00/p03 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss av ss toolrxd/p11, tooltxd/p12 v dd av dd serial interface iica0 sdaa0/p61 scla0/p60 2 intp2/p51 multiplier& divider, mulitiply- accumulator port 0 p02, p03 2 9 ani16/p03, ani17/p02, ani18/p10, ani20/p11, ani21/p12, ani25/p51, ani26/p50, ani27/p30, ani29/p31 direct memory access control port 6 p60, p61 2 buzzer output pclbuz0/p31 clock output control window watchdog timer real-time clock rl78 cpu core code flash memory data flash memory interval timer p50, p51 2 (key return) (4) (kr0/p02, kr1/p03, kr2/p22, kr3/p23) crc low-speed on-chip oscillator remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 13 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 1.5.2 32-pin products port 1 p10 to p15 port 2 p20 to p24 5 port 3 p30, p31 2 port 4 port 5 6 port 12 p121, p122 p40 p50, p51 2 voltage regulator regc interrupt control ram power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11 txd0/p12 rxd1/p03 txd1/p02 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ch3 ti03/to03/p31 ch0 ch1 ch4 ch5 ch6 ch7 2 intp0/p137 intp3/p30, intp4/p31 intp1/p50, intp2/p51 rxd2/p14 a/d converter 5 ani0/p20 to ani4/p24 av refp /p20 av refm /p21 2 p120 port 13 p137 csi11 sck11/p30 so11/p51 si11/p50 iic11 scl11/p30 sda11/p50 ti00/p02 to00/p03 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss , av ss toolrxd/p11, tooltxd/p12 v dd , av dd serial interface iica0 sdaa0/p61 scla0/p60 2 multiplier& divider, mulitiply- accumulator port 0 p02, p03 2 buzzer output clock output control 13 ani16/p01, ani17/p00, ani18/p10, ani19/p120 to ani24/p15, ani26/p50, ani27/p30, ani28/p70, ani29/p31 serial array unit1 (2ch) uart2 linsel iic20 rxd2/p14 txd2/p13 scl20/p15 sda20/p14 sck20/p15 so20/p13 si20/p14 csi20 direct memory access control port 6 port 7 p70 p60 to p62 3 pclbuz0/p31, pclbuz1/p15 2 window watchdog timer low-speed on-chip oscillator real-time clock rl78 cpu core code flash memory data flash memory interval timer key return 1(6) kr0/p70 (kr0/p10 to kr5/p15) (kr0/p120, kr1/p02, kr2/p03, kr3/p22 to kr5/p24) rxd2/p14 crc remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 14 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 1.5.3 48-pin products voltage regulator regc interrupt control ram window watchdog timer power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11 txd0/p12 rxd1/p03 txd1/p02 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ti03/to03/p31 ch3 ch0 ch1 ch4 ch5 ch6 ch7 intp8/p74, intp9/p75 2 intp0/p137 intp3/p30, intp4/p31 intp6/p140 intp1/p50, intp2/p51 rxd2/p14 a/d converter 9 ani0/p20 to ani7/p2, ani8/p150 av refp /p20 av refm /p21 csi11 sck11/p30 so11/p51 si11/p50 iic01 scl01/p75 sda01/p74 iic11 scl11/p30 sda11/p50 ti07/to07/p41 ti00/p02 to00/p03 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss , av ss toolrxd/p11, tooltxd/p12 v dd , av dd serial interface iica0 sdaa0/p61 scla0/p60 2 2 intp5/p16 multiplier& divider, mulitiply- accumulator xt1/p123 xt2/exclks/p124 port 0 p02, p03 2 buzzer output pclbuz0/p140, pclbuz1/p15 clock output control key return 6(6) kr0/p70 to kr5/p75 (kr0/p10 to kr5/p15) (kr0/p02, kr1/p03, kr2/p22 to kr5/p25) 15 ani16/p03, ani17/p02, ani18/p147, ani19/p120, ani20/p11 to ani24/p15, ani25, p51, ani26/p50, p30/ani27, ani28/p70, ani29/p31, ani30/p41 sck01/p75 so01/p73 si01/p74 csi01 serial array unit1 (2ch) uart2 linsel iic20 rxd2/p14 txd2/p13 scl20/p15 sda20/p14 iic21 scl21/p70 sda21/p71 sck20/p15 so20/p13 si20/p14 csi20 sck21/p70 so21/p72 si21/p71 csi21 direct memory access control port 15 2 ti01/to01/p16 rtc1hz/p30 rxd2/p14 real-time clock rl78 cpu core code flash memory data flash memory interval timer port 1 p10 to p16 port 2 p20 to p27 8 port 3 p30, p31 2 port 4 port 5 7 port 12 p121 to p124 p40, p41 2 p50, p51 2 4 p120 port 13 p130 p137 port 6 port 7 p70 to p75 6 p60 to p63 4 port 14 p140 p150 low-speed on-chip oscillator crc remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 15 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 1.5.4 64-pin products port 2 p20 to p27 8 port 3 p30, p31 2 port 1 p10 to p16 7 port 4 p40 to p43 4 port 5 p50, p51 2 voltage regulator regc interrupt control ram rl78 cpu core window watchdog timer power on reset/ voltage detector por/lvd control reset control system control reset x1/p121 x2/exclk/p122 high-speed on-chip oscillator on-chip debug tool0/p40 serial array unit0 (4ch) uart0 uart1 iic00 rxd0/p11 txd0/p12 rxd1/p03 txd1/p02 scl00/p10 sda00/p11 timer array unit (8ch) ch2 ch3 ti03/to03/p31 ch0 ch1 ch4 ti04/to04/p42 ch5 ti05/to05/p05 ch6 ti06/to06/p06 ch7 intp8/p74, intp9/p75 2 intp0/p137 intp3/p30, intp4/p31 intp6/p140, intp7/p141 intp1/p50, intp2/p51 rxd2/p14 csi10 sck10/p04 so10/p02 si10/p03 a/d converter 13 ani0/p20 to ani7/p27, ani8/p150 to ani12/p154 av refp /p20 av refm /p21 port 12 p121 to p124 4 p120 port 13 p130 p137 csi11 sck11/p30 so11/p51 si11/p50 iic01 scl01/p75 sda01/p74 iic10 scl10/p04 sda10/p03 iic11 scl11/p30 sda11/p50 ti07/to07/p41 ti00/p00 to00/p01 bcd adjustment sck00/p10 so00/p12 si00/p11 csi00 v ss , ev ss0 , av ss toolrxd/p11, tooltxd/p12 v dd , ev dd0 , av dd serial interface iica0 sdaa0/p61 scla0/p60 2 2 2 intp5/p16 multiplier& divider, mulitiply- accumulator xt1/p123 xt2/exclks/p124 port 0 p00 to p06 7 buzzer output pclbuz0/p140, pclbuz1/p141 clock output control key return 10 (10) kr0/p70 to kr7/p77, kr8/p05, kr9/p06 (kr0/p00 to kr4/p04, kr5/p22 to kr9/p26) (kr0/p10 to kr5/p15, kr6/p151 to kr9/p154) 15 ani16/p03, ani17/p02, ani18/p10, ani19/p120, ani20/p11 to ani24/p15, ani25//p51, ani26/p50, ani27/p30, ani28/p70ani29/p31, ani30/p41 sck01/p75 so01/p73 si01/p74 csi01 serial array unit1 (2ch) uart2 linsel iic20 rxd2/p14 txd2/p13 scl20/p15 sda20/p14 iic21 scl21/p70 sda21/p71 sck20/p15 so20/p13 si20/p14 csi20 sck21/p70 so21/p72 si21/p71 csi21 direct memory access control port 7 p70 to p77 8 port 6 p60 to p63 4 port 14 p140, p141 2 2 ti01/to01/p16 rtc1hz/p30 rxd2/p14 real-time clock code flash memory data flash memory interval timer intp10/p76, intp11/p77 2 port 15 p150 to p154 5 low-speed on-chip oscillator crc remark functions in parentheses in the above figure can be assigned via settings in the peripheral i/o redirection register (pior). rl78/g1a 1. outline page 16 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 1.6 outline of functions (1/2) 25-pin 32-pin 48-pin 64-pin item r5f10e8x r5f10ebx r5f10egx r5f10elx code flash memory (kb) 16 to 64 16 to 64 16 to 64 32 to 64 data flash memory (kb) 4 4 4 4 ram (kb) 2 to 4 note1 2 to 4 note1 2 to 4 note1 2 to 4 note1 address space 1 mb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) 1 to 20 mhz: v dd = 2.7 to 3.6 v, 1 to 8 mhz: v dd = 1.8 to 2.7 v, 1 to 4 mhz: v dd = 1.6 to 1.8 v main system clock high-speed on-chip oscillator hs (high-speed main) mode : 1 to 32 mhz (v dd = 2.7 to 3.6 v), hs (high-speed main) mode : 1 to 16 mhz (v dd = 2.4 to 3.6 v), ls (low-speed main) mode : 1 to 8 mhz (v dd = 1.8 to 3.6 v), lv (low-voltage main) mode : 1 to 4 mhz (v dd = 1.6 to 3.6 v) subsystem clock ? xt1 (crystal) oscillation, external subsystem clock input (exclks) 32.768 khz (typ.) low-speed on-chip oscillator 15 khz (typ.) general-purpose register (8-bit register 8) 4 bank 0.03125 s (high-speed on-chip oscillator: f ih = 32 mhz operation) 0.05 s (high-speed system clock: f mx = 20 mhz operation) minimum instruction execution time ? 30.5 s (subsystem clock: f sub = 32.768 khz operation) instruction set ? data transfer (8/16 bits) ? adder and subtractor/logical operation (8/16 bits) ? multiplication (8 bits 8 bits) ? rotate, barrel shift, and bit manipulation (s et, reset, test, and boolean operation), etc. total 19 26 42 56 cmos i/o 14 (n-ch o.d. i/o [v dd withstand voltage]: 6) 20 (n-ch o.d. i/o [v dd withstand voltage]: 9) 32 (n-ch o.d. i/o [v dd withstand voltage]: 11) 46 (n-ch o.d. i/o [v dd withstand voltage]: 12) cmos input 3 3 5 5 cmos output ? ? 1 1 i/o port n-ch open-drain i/o (6 v tolerance) 2 3 4 4 16-bit timer 8 channels watchdog timer 1 channel real-time clock (rtc) 1 channel note 2 1 channel 12-bit interval timer (it) 1 channel timer output 2 channels (pwm outputs: 1 note 3 ) 4 channels (pwm outputs: 3 note 3 ) 7 channels (pwm outputs: 6 note 3 ) timer rtc output ? 1 ? 1 hz (subsystem clock: f sub = 32.768 khz) notes 1. in the case of the 4 kb, this is about 3 kb when the self-programming function and data flash function are used. 2. only the constant-period inte rrupt function when the low-spee d on-chip oscillator clock (f il ) is selected. 3. the number of pwm outputs varies depending on the setting of channels in use (the number of masters and slaves). rl78/g1a 1. outline page 17 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (2/2) 25-pin 32-pin 48-pin 64-pin item r5f10e8x r5f10ebx r5f10egx r5f10elx 1 2 2 2 clock output/buzzer output ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 2.44 khz, 4.88 khz, 9.76 khz, 1.25 mhz, 2.5 mhz, 5 mhz, 10 mhz (main system clock: f main = 20 mhz operation) ? 256 hz, 512 hz, 1.024 khz, 2.048 khz, 4.096 khz, 8.192 khz, 16.384 khz, 32.768 khz (subsystem clock: f sub = 32.768 khz operation) 8/12-bit resolution a/d converter 13 c hannels 18 channels 24 channels 28 channels serial interface [25-pin products] ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel [32-pin products] ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel ? csi: 1 channel/simplified i 2 c: 1 channel/uart (uart supporting lin-bus): 1 channel [48-pin products] ? csi: 2 channels/simplified i 2 c: 2 channels/uart: 1 channel ? csi: 1 channel/simplified i 2 c: 1 channel/uart: 1 channel ? csi: 2 channels/simplified i 2 c: 2 channels/uart (uart supporting lin-bus): 1 channel [64-pin products] ? csi: 2 channels/simplified i 2 c: 2 channels/uart: 1 channel ? csi: 2 channels/simplified i 2 c: 2 channels/uart: 1 channel ? csi: 2 channels/simplified i 2 c: 2 channels/uart (uart supporting lin-bus): 1 channel i 2 c bus 1 channel 1 channel 1 channel 1 channel multiplier and divider/multipl y-accumulator ? 16 bits 16 bits = 32 bits (unsigned or signed) ? 32 bits 32 bits = 32 bits (unsigned) ? 16 bits 16 bits + 32 bits = 32 bits (unsigned or signed) dma controller 2 channels internal 24 27 27 27 vectored interrupt sources external 6 6 10 13 key interrupt 0 ch (4 ch) note 1 1 ch (6 ch) note 1 6 ch 10 ch reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on-reset ? internal reset by voltage detector ? internal reset by illegal instruction execution note 2 ? internal reset by ram parity error ? internal reset by illegal-memory access power-on-reset circuit ? power-on-reset: 1.51 v (typ.) ? power-down-reset: 1.50 v (typ.) voltage detector ? rising edge : 1.67 v to 3.14 v (12 stages) ? falling edge : 1.63 v to 3.06 v (12 stages) on-chip debug function provided power supply voltage v dd = 1.6 to 3.6 v operating ambient temperature t a = ? 40 to +85 c (a: consumer application), t a = ? 40 to +105 c (g: industrial application) notes 1. can be used by the peripheral i/o redirection register (pior). 2. the illegal instruction is generated wh en instruction code ffh is executed. reset by the illegal instruction execution not issu ed by emulation with the in-circuit emulator or on-chip debug emulator. rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 18 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 2. electrical specifications (t a = ? 40 to +85 c) this chapter describes the following electrical specifications. target products a: consumer applications t a = ? 40 to +85 c r5f10e8aala, r5f10e8cala, r5f10e8dala, r5f10e8eala r5f10ebaana, r5f10ebcana, r5f10ebdana, r5f10ebeana r5f10egaafb, r5f10egcafb, r5f10egdafb, r5f10egeafb r5f10egaana, r5f10egcana, r5f10egdana, r5f10egeana r5f10elcafb, r5f10e ldafb, r5f10eleafb r5f10elcabg, r5f10eldabg, r5f10eleabg g: industrial applications when t a = ? 40 to +105 c products is used in the range of t a = ? 40 to +85 c r5f10ebagna, r5f10ebcgna, r5f10ebdgna, r5f10ebegna r5f10egagfb, r5f10egcgfb, r5f10egdgfb, r5f10egegfb r5f10egagna, r5f10egcgna, r5f10egdgna, r5f10egegna r5f10elcgfb, r5f10eldgfb, r5f10elegfb cautions 1. the rl78 microcontrollers have an on- chip debug function, wh ich is provided for development and evaluation. do not use th e on-chip debug function in products designated for mass production, because the gua ranteed number of rewritable times of the flash memory may be exceeded when this func tion is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liable for problems occurring when the on-chip debug function is used. 2. with products not provided with an ev dd0 or ev ss0 pin, replace ev dd0 with v dd , or replace ev ss0 with v ss . 3. the pins mounted depend on the product. see 1.3.1 25-pin products to 1.3.4 64-pin products. rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 19 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 2.1 absolute maximum ratings absolute maximum ratings (t a = 25 c) (1/2) parameter symbols conditions ratings unit v dd ? 0.5 to +6.5 v ev dd0 ? 0.5 to +6.5 v av dd ? 0.5 to +4.6 v av refp ? 0.3 to av dd +0.3 note 3 v ev ss0 ? 0.5 to +0.3 v av ss ? 0.5 to +0.3 v supply voltage av refm ? 0.3 to av dd +0.3 note 3 and av refm av refp v regc pin input voltage v iregc regc ? 0.3 to +2.8 and ? 0.3 to v dd +0.3 note 1 v v i1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p140, p141 ? 0.3 to ev dd0 +0.3 and ? 0.3 to v dd +0.3 note 2 v v i2 p60 to p63 (n-ch open-drain) ? 0.3 to +6.5 v v i3 p121 to p124, p137, exclk, exclks, reset ? 0.3 to v dd +0.3 note 2 v input voltage v i4 p20 to p27, p150 to p154 ? 0.3 to av dd +0.3 note 2 v v o1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p60 to p63, p70 to p77, p120, p130, p140, p141 ? 0.3 to ev dd0 +0.3 note 2 v output voltage v o2 p20 to p27, p150 to p154 ? 0.3 to av dd +0.3 note 2 v v ai1 ani16 to ani30 ? 0.3 to ev dd0 +0.3 and ? 0.3 to av ref(+) +0.3 notes 2, 4 v analog input voltage v ai2 ani0 to ani12 ? 0.3 to av dd +0.3 and ? 0.3 to av ref(+) +0.3 notes 2, 4 v notes 1. connect the regc pin to v ss via a capacitor (0.47 to 1 f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. 2. must be 6.5 v or lower. 3. must be 4.6 v or lower. 4. do not exceed av ref(+) + 0.3 v in case of a/d conversion target pin. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum rati ngs are rated values at which the product is on the verge of suffering physical damage, and theref ore the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. remarks 1. unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins. 2. av ref(+) : + side reference voltage of the a/d converter. 3. v ss : reference voltage rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 20 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 absolute maximum ratings (t a = 25 c) (2/2) parameter symbols conditions ratings unit per pin p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 ? 40 ma p00 to p04, p40 to p43, p120, p130, p140, p141 ? 70 ma i oh1 total of all pins ? 170 ma p05, p06, p10 to p16, p30, p31, p50, p51, p70 to p77, ? 100 ma per pin ? 0.1 ma output current, high i oh2 total of all pins p20 to p27, p150 to p154 ? 1.3 ma per pin p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p60 to p63, p70 to p77, p120, p130, p140, p141 40 ma p00 to p04, p40 to p43, p120, p130, p140, p141 70 ma i ol1 total of all pins 170 ma p05, p06, p10 to p16, p30, p31, p50, p51, p60 to p63, p70 to p77 100 ma per pin 0.4 ma output current, low i ol2 total of all pins p20 to p27, p150 to p154 6.4 ma in normal operation mode operating ambient temperature t a in flash memory programming mode ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum rati ngs are rated values at which the product is on the verge of suffering physical damage, and theref ore the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are the same as those of the port pins. rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 21 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 2.2 oscillator characteristics 2.2.1 x1, xt1 oscillator characteristics (t a = ? 40 to +85 c, 1.6 v v dd 3.6 v, v ss = 0 v) parameter resonator conditions min. typ. max. unit 2.7 v v dd 3.6 v 1.0 20.0 mhz 2.4 v v dd < 2.7 v 1.0 16.0 mhz 1.8 v v dd < 2.4 v 1.0 8.0 mhz x1 clock oscillation frequency (f x ) note ceramic resonator/c rystal resonator 1.6 v v dd < 1.8 v 1.0 4.0 mhz xt1 clock oscillation frequency (f x ) note crystal resonator 32 32.768 35 khz note indicates only permissible oscillator frequency ranges. see ac characteristics for instruction execution time. request evaluation by the manufacturer of t he oscillator circuit mounted on a board to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip oscillator cl ock after a reset release, check the x1 clock oscillation stabilization time using th e oscillation stabilization time counter status register (ostc) by the user. de termine the oscillation stabilizat ion time of the ostc register and the oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time wit h the resonator to be used. 2.2.2 on-chip oscillator characteristics (t a = ? 40 to +85 c, 1.6 v v dd 3.6 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator clock frequency notes 1, 2 f ih 1 32 mhz 1.8 v v dd 3.6 v ? 1.0 +1.0 % ? 20 to +85 c 1.6 v v dd < 1.8 v ? 5.0 +5.0 % 1.8 v v dd 3.6 v ? 1.5 +1.5 % high-speed on-chip oscillator clock frequency accuracy ? 40 to ? 20 c 1.6 v v dd < 1.8 v ? 5.5 +5.5 % low-speed on-chip oscillator clock frequency f il 15 khz low-speed on-chip oscillator clock frequency accuracy ? 15 +15 % notes 1. high-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000c2h/010c2h) and bits 0 to 2 of hocodiv register. 2. this indicates the oscillator characteristics only. see ac characteristics for instruction execution time. rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 22 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 2.3 dc characteristics 2.3.1 pin characteristics (t a = ? 40 to +85 c, 1.6 v av dd v dd 3.6 v, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (1/5) items symbol conditions min. typ. max. unit per pin for p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 1.6 v ev dd0 3.6 v ? 10.0 note 2 ma 2.7 v ev dd0 3.6 v ? 10.0 ma 1.8 v ev dd0 < 2.7 v ? 5.0 ma total of p00 to p04, p40 to p43, p120, p130, p140, p141 (when duty 70% note 3 ) 1.6 v ev dd0 < 1.8 v ? 2.5 ma 2.7 v ev dd0 3.6 v ? 19.0 ma 1.8 v ev dd0 < 2.7 v ? 10.0 ma total of p05, p06, p10 to p16, p30, p31, p50, p51, p70 to p77, (when duty 70% note 3 ) 1.6 v ev dd0 < 1.8 v ? 5.0 ma i oh1 total of all pins (when duty 70% note 3 ) 1.6 v ev dd0 3.6 v ? 29.0 ma per pin for p20 to p27, p150 to p154 1.6 v av dd 3.6 v ? 0.1 note 2 ma output current, high note 1 i oh2 total of all pins (when duty 70% note 3 ) 1.6 v av dd 3.6 v ? 1.3 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from the ev dd0 , v dd pins to an output pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor 70%. the output current value that has changed to the dut y factor > 70% the duty ratio can be calculated with the following expression (when changi ng the duty factor from 70% to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 23 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (t a = ? 40 to +85 c, 1.6 v av dd v dd 3.6 v, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (2/5) items symbol conditions min. typ. max. unit per pin for p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 20.0 note 2 ma per pin for p60 to p63 15.0 note 2 ma 2.7 v ev dd0 3.6 v 15.0 ma 1.8 v ev dd0 < 2.7 v 9.0 ma total of p00 to p04, p40 to p43, p120, p130, p140, p141 (when duty 70% note 3 ) 1.6 v ev dd0 < 1.8 v 4.5 ma 2.7 v ev dd0 3.6 v 35.0 ma 1.8 v ev dd0 < 2.7 v 20.0 ma total of p05, p06, p10 to p16, p30, p31, p50, p51, p60 to p63, p70 to p77 (when duty 70% note 3 ) 1.6 v ev dd0 < 1.8 v 10.0 ma i ol1 total of all pins (when duty 70% note 3 ) 50.0 ma per pin for p20 to p27, p150 to p154 0.4 note 2 ma output current, low note 1 i ol2 total of all pins (when duty 70% note 3 ) 1.6 v av dd 3.6 v 5.2 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from an output pin to the ev ss0 and v ss pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor 70%. the output current value that has changed to the duty factor > 70% the duty ratio can can be calculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 24 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (t a = ? 40 to +85 c, 1.6 v av dd v dd 3.6 v, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (3/5) items symbol conditions min. typ. max. unit v ih1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p140, p141 normal input buffer 0.8ev dd0 ev dd0 v ttl input buffer 3.3 v ev dd0 3.6 v 2.0 ev dd0 v v ih2 p01, p03, p04, p10, p11, p13 to p16, p43 ttl input buffer 1.6 v ev dd0 < 3.3 v 1.5 ev dd0 v v ih3 p20 to p27, p150 to p154 0.7av dd av dd v v ih4 p60 to p63 0.7ev dd0 6.0 v input voltage, high v ih5 p121 to p124, p137, exclk, exclks, reset 0.8v dd v dd v v il1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p140, p141 normal input buffer 0 0.2ev dd0 v ttl input buffer 3.3 v ev dd0 3.6 v 0 0.5 v v il2 p01, p03, p04, p10, p11, p13 to p16, p43 ttl input buffer 1.6 v ev dd0 < 3.3 v 0 0.32 v v il3 p20 to p27, p150 to p154 0 0.3av dd v v il4 p60 to p63 0 0.3ev dd0 v input voltage, low v il5 p121 to p124, p137, exclk, exclks, reset 0 0.2v dd v caution the maximum value of v ih of pins p00, p02 to p04, p10 to p15, p43, p50, p71, and p74 is ev dd0 , even in the n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins. rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 25 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (t a = ? 40 to +85 c, 1.6 v av dd v dd 3.6 v, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (4/5) items symbol conditions min. typ. max. unit 2.7 v ev dd0 3.6 v, i oh1 = ? 2.0 ma ev dd0 ? 0.6 v 1.8 v ev dd0 3.6 v, i oh1 = ? 1.5 ma ev dd0 ? 0.5 v v oh1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 1.6 v ev dd0 3.6 v, i oh1 = ? 1.0 ma ev dd0 ? 0.5 v output voltage, high v oh2 p20 to p27, p150 to p154 1.6 v av dd 3.6 v, i oh2 = ? 100 a av dd ? 0.5 v 2.7 v ev dd0 3.6 v, i ol1 = 3.0 ma 0.6 v 2.7 v ev dd0 3.6 v, i ol1 = 1.5 ma 0.4 v 1.8 v ev dd0 3.6 v, i ol1 = 0.6 ma 0.4 v v ol1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 1.6 v ev dd0 < 1.8 v, i ol1 = 0.3 ma 0.4 v v ol2 p20 to p27, p150 to p154 1.6 v av dd 3.6 v, i ol2 = 400 a 0.4 v 2.7 v ev dd0 3.6 v, i ol3 = 3.0 ma 0.4 v 1.8 v ev dd0 3.6 v, i ol3 = 2.0 ma 0.4 v output voltage, low v ol3 p60 to p63 1.6 v ev dd0 < 1.8 v, i ol3 = 1.0 ma 0.4 v caution p00, p02 to p04, p10 to p1 5, p43, p50, p71, and p74 do not ou tput high level in n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins. rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 26 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (t a = ? 40 to +85 c, 1.6 v av dd v dd 3.6 v, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (5/5) items symbol conditions min. typ. max. unit i lih1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p60 to p63, p70 to p77, p120, p140, p141 v i = ev dd0 1 a i lih2 p137, reset v i = v dd 1 a in input port or external clock input 1 a i lih3 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v dd in resonator connection 10 a input leakage current, high i lih4 p20 to p27, p150 to p154 v i = av dd 1 a i lil1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p60 to p67, p70 to p77, p120, p140, p141 v i = ev ss0 ? 1 a i lil2 p137, reset v i = v ss ? 1 a in input port or external clock input ? 1 a i lil3 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v ss in resonator connection ? 10 a input leakage current, low i lil4 p20 to p27, p150 to p154 v i = av ss ? 1 a on-chip pull-up resistance r u p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p140, p141 v i = ev ss0 , in input port 10 20 100 k remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins. rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 27 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 2.3.2 supply current characteristics (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (1/3) parameter symbol conditions min. typ. max. unit basic operation v dd = 3.0 v 2.1 ma f ih = 32 mhz note 3 normal operation v dd = 3.0 v 4.6 7.0 ma f ih = 24 mhz note 3 normal operation v dd = 3.0 v 3.7 5.5 ma hs (high-speed main) mode note 5 f ih = 16 mhz note 3 normal operation v dd = 3.0 v 2.7 4.0 ma v dd = 3.0 v 1.2 1.8 ls (low-speed main) mode note 5 f ih = 8 mhz note 3 normal operation v dd = 2.0 v 1.2 1.8 ma v dd = 3.0 v 1.2 1.7 lv (low-voltage main) mode note 5 f ih = 4 mhz note 3 normal operation v dd = 2.0 v 1.2 1.7 ma square wave input 3.0 4.6 f mx = 20 mhz note 2 , v dd = 3.0 v normal operation resonator connection 3.2 4.8 ma square wave input 1.9 2.7 hs (high-speed main) mode note 5 f mx = 10 mhz note 2 , v dd = 3.0 v normal operation resonator connection 1.9 2.7 ma square wave input 1.1 1.7 f mx = 8 mhz note 2 , v dd = 3.0 v normal operation resonator connection 1.1 1.7 ma square wave input 1.1 1.7 ls (low-speed main) mode note 5 f mx = 8 mhz note 2 , v dd = 2.0 v normal operation resonator connection 1.1 1.7 ma square wave input 4.1 4.9 f sub = 32.768 khz note 4 t a = ? 40 c normal operation resonator connection 4.2 5.0 a square wave input 4.2 4.9 f sub = 32.768 khz note 4 t a = +25 c normal operation resonator connection 4.3 5.0 a square wave input 4.3 5.5 f sub = 32.768 khz note 4 t a = +50 c normal operation resonator connection 4.4 5.6 a square wave input 4.5 6.3 f sub = 32.768 khz note 4 t a = +70 c normal operation resonator connection 4.6 6.4 a square wave input 4.8 7.7 supply current note 1 i dd1 operating mode subsystem clock mode f sub = 32.768 khz note 4 t a = +85 c normal operation resonator connection 4.9 7.8 a ( notes and remarks are listed on the next page.) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 28 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 notes 1. total current flowing into v dd and ev dd0 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 or v ss , ev ss0 . the values below the max. column include the peripheral operation current. however, not includin g the current flowing into the a/d converter, lvd circuit, i/o port, on-chip pull-up/pull-down resistors, and data flash rewriting. 2. when high-speed on-chip oscillator and subsystem clock are stopped. 3. when high-speed system clock and s ubsystem clock are stopped. 4. when high-speed on-chip oscillator and high-speed syst em clock are stopped. when setting ultra-low power consumption oscillation (amphs1 = 1). not in cluding the current flowing into the rtc, 12-bit interval timer and watchdog timer 5. relationship between operation voltage width, oper ation frequency of cpu and operation mode is as below. hs (high-speed main) mode: v dd = 2.7 v to 3.6 v@1 mhz to 32 mhz v dd = 2.4 v to 3.6 v@1 mhz to 16 mhz ls (low-speed main) mode: v dd = 1.8 v to 3.6 v@1 mhz to 8 mhz lv (low-voltage main) mode: v dd = 1.6 v to 3.6 v@1 mhz to 4 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation, temper ature condition of t he typ. value is t a = 25 c rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 29 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (2/3) parameter symbol conditions min. typ. max. unit f ih = 32 mhz note 4 v dd = 3.0 v 0.54 1.63 ma f ih = 24 mhz note 4 v dd = 3.0 v 0.44 1.28 ma hs (high-speed main) mode note 7 f ih = 16 mhz note 4 v dd = 3.0 v 0.40 1.00 ma v dd = 3.0 v 270 530 ls (low-speed main) mode note 7 f ih = 8 mhz note 4 v dd = 2.0 v 270 530 a v dd = 3.0 v 435 640 lv (low-voltage main) mode note 7 f ih = 4 mhz note 4 v dd = 2.0 v 435 640 a square wave input 0.28 1.00 f mx = 20 mhz note 3 , v dd = 3.0 v resonator connection 0.45 1.17 ma square wave input 0.19 0.60 hs (high-speed main) mode note 7 f mx = 10 mhz note 3 , v dd = 3.0 v resonator connection 0.26 0.67 ma square wave input 95 330 f mx = 8 mhz note 3 , v dd = 3.0 v resonator connection 145 380 a square wave input 95 330 ls (low-speed main) mode note 7 f mx = 8 mhz note 3 , v dd = 2.0 v resonator connection 145 380 a square wave input 0.25 0.57 f sub = 32.768 khz note 5 t a = ? 40 c resonator connection 0.44 0.76 a square wave input 0.30 0.57 f sub = 32.768 khz note 5 t a = +25 c resonator connection 0.49 0.76 a square wave input 0.38 1.17 f sub = 32.768 khz note 5 t a = +50 c resonator connection 0.57 1.36 a square wave input 0.52 1.97 f sub = 32.768 khz note 5 t a = +70 c resonator connection 0.71 2.16 a square wave input 0.97 3.37 i dd2 note 2 halt mode subsystem clock mode f sub = 32.768 khz note 5 t a = +85 c resonator connection 1.16 3.56 a t a = ? 40 c 0.16 0.50 t a = +25 c 0.23 0.50 t a = +50 c 0.34 1.10 t a = +70 c 0.46 1.90 supply current note 1 i dd3 note 6 stop mode note 8 t a = +85 c 0.75 3.30 a ( notes and remarks are listed on the next page.) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 30 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 notes 1. total current flowing into v dd and ev dd0 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 or v ss , ev ss0 . the values below the max. column include the peripheral operation current. however, not includin g the current flowing into the a/d converter, lvd circuit, i/o port, on-chip pull-up/pull-down resistors, and data flash rewriting. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator and subsystem clock are stopped. 4. when high-speed system clock and subsystem clock are stopped. 5. when high-speed on-chip oscillator and high-speed system clock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). including the current flowing into the rtc. however, not including the current flowing into the 12-bit interval timer, and watchdog timer. 6. when subsystem clock is stopped. not including the cu rrent flowing into the rtc, 12-bit interval timer, watchdog timer. 7. relationship between operation voltage width, oper ation frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 3.6 v@1 mhz to 32 mhz 2.4 v v dd 3.6 v@1 mhz to 16 mhz ls (low-speed main) mode: 1.8 v v dd < 3.6 v@1 mhz to 8 mhz lv (low-voltage main) mode: 1.6 v v dd 3.6 v@1 mhz to 4 mhz 8. regarding the value for current to operate the subsyst em clock in stop mode, refer to that in halt mode. remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25 c rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 31 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (3/3) parameter symbol conditions min. typ. max. unit low-speed on-chip oscillator operating current i fil note 1 0.20 a rtc operating current i rtc notes 1, 2, 3 0.02 a 12-bit interval timer operating current i it notes 1, 2, 4 0.02 a watchdog timer operating current i wdt notes 1, 2, 5 f il = 15 khz 0.22 a a/d converter operating current i adc notes 6, 7 av dd = 3.0 v, when conversion at maximum speed 420 720 a av dd = 3.0 v, adrefp1 = 0, adrefp0 = 0 note 7 14.0 25.0 a av refp = 3.0 v, adrefp1 = 0, adrefp0 = 1 note 10 14.0 25.0 a av ref(+) current i avref note 8 adrefp1 = 1, adrefp0 = 0 note 1 14.0 25.0 a a/d converter reference voltage current i adref notes 1, 9 v dd = 3.0 v 75.0 a temperature sensor operating current i tmp note 1 v dd = 3.0 v 75.0 a lvd operating current i lvd notes 1, 11 0.08 a bgo operating current i bgo notes 1, 12 2.5 12.2 ma self-programming operating current i fsp notes 1, 13 2.5 12.2 ma the mode is performed notes 1 0.50 0.60 ma during a/d conversion note 1 0.60 0.75 ma a/d converter operation (av dd = 3.0 v) during a/d conversion note 7 420 720 a snooze operating current i snoz csi/uart operation note 1 0.70 0.84 ma ( notes and remarks are listed on the next page.) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 32 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 notes 1. current flowing to v dd . 2. when high-speed on-chip oscillator and high-speed system clock are stopped. 3. current flowing only to the real-time clock (rtc) (excluding the operating current of the low-speed on-chip ocsillator and the xt1 oscillator). the supply current of the rl78 microc ontrollers is the sum of the values of either i dd1 or i dd2 , and i rtc , when the real-time clock operates in operation mode or halt mode. when the low-speed on-ch ip oscillator is selected, i fil should be added. i dd2 subsystem clock operation includes the operational current of the real-time clock. 4. current flowing only to the 12-bit interval timer (e xcluding the operating current of the low-speed on-chip ocsillator and the xt1 oscillator). the supply current of the rl78 mi crocontrollers is the sum of the values of either i dd1 or i dd2 , and i it , when the 12-bit interval timer operates in operation mode or halt mode. when the low-speed on-chip oscillator is selected, i fil should be added. 5. current flowing only to the watchdog timer (inclu ding the operating current of the low-speed on-chip oscillator). the supply current of t he rl78 microcontrollers is the sum of i dd1 , i dd2 , or i dd3 and i wdt when the watchdog timer is in operation. 6. current flowing only to the a/d conv erter. the supply current of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc , i avref , i adref when the a/d converter operates in an operation mode or the halt mode. 7. current flowing to the av dd . 8. current flowing from the referenc e voltage source of a/d converter. 9. operation current flowing to the internal reference voltage. 10. current flowing to the av refp . 11. current flowing only to the lvd circuit. the supply current of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvd when the lvd circuit is in operation. 12. current flowing only during data flash rewrite. 13. current flowing only during self programming. remarks 1. f il : low-speed on-chip oscillator clock frequency 2. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 3. f clk : cpu/peripheral hardware clock frequency 4. temperature condition of the typ. value is t a = 25 c rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 33 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 2.4 ac characteristics (t a = ? 40 to +85 c, av dd v dd 3.6 v, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) items symbol conditions min. typ. max. unit 2.7 v v dd 3.6 v 0.03125 1 s hs (high-speed main) mode 2.4 v v dd < 2.7 v 0.0625 1 s ls (low-speed main) mode 1.8 v v dd 3.6 v 0.125 1 s main system clock (f main ) operation lv (low-voltage main) mode 1.6 v v dd 3.6 v 0.25 1 s subsystem clock (f sub ) operation 1.8 v v dd 3.6 v 28.5 30.5 31.3 s 2.7 v v dd 3.6 v 0.03125 1 s hs (high-speed main) mode 2.4 v v dd < 2.7 v 0.0625 1 s ls (low-speed main) mode 1.8 v v dd 3.6 v 0.125 1 s instruction cycle (minimum instruction execution time) t cy in the self programming mode lv (low-voltage main) mode 1.6 v v dd 3.6 v 0.25 1 s 2.7 v v dd 3.6 v 1.0 20.0 mhz 2.4 v v dd < 2.7 v 1.0 16.0 mhz 1.8 v v dd < 2.4 v 1.0 8.0 mhz f ex 1.6 v v dd < 1.8 v 1.0 4.0 mhz external system clock frequency f exs 32 35 khz 2.7 v v dd 3.6 v 24 ns 2.4 v v dd < 2.7 v 30 ns 1.8 v v dd < 2.4 v 60 ns t exh , t exl 1.6 v v dd < 1.8 v 120 ns external system clock input high-level width, low-level width t exhs , t exls 13.7 s ti00, ti01, ti03 to ti07 input high-level width, low-level width t tih , t til 1/f mck +10 ns note 2.7 v ev dd0 3.6 v 8 mhz 1.8 v ev dd0 < 2.7 v 4 mhz hs (high-speed main) mode 1.6 v ev dd0 < 1.8 v 2 mhz 1.8 v ev dd0 3.6 v 4 mhz ls (low-speed main) mode 1.6 v ev dd0 < 1.8 v 2 mhz to00, to01, to03 to to07 output frequency f to lv (low-voltage main) mode 1.6 v ev dd0 3.6 v 2 mhz 2.7 v ev dd0 3.6 v 8 mhz 1.8 v ev dd0 < 2.7 v 4 mhz hs (high-speed main) mode 1.6 v ev dd0 < 1.8 v 2 mhz 1.8 v ev dd0 3.6 v 4 mhz ls (low-speed main) mode 1.6 v ev dd0 < 1.8 v 2 mhz 1.8 v ev dd0 3.6 v 4 mhz pclbuz0, pclbuz1 output frequency f pcl lv (low-voltage main) mode 1.6 v ev dd0 < 1.8 v 2 mhz intp0 1.6 v v dd 3.6 v 1 s interrupt input high-level width, low-level width t inth , t intl intp1 to intp11 1.6 v ev dd0 3.6 v 1 s 1.8 v ev dd0 3.6 v, 1.8 v av dd0 3.6 v 250 ns key interrupt input high-level width, low-level width t kr kr0 to kr9 1.6 v ev dd0 < 1.8 v, 1.6 v av dd0 < 1.8 v 1 s reset low-level width t rsl 10 s ( note and remark are listed on the next page.) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 34 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 note the following conditions are required for low-voltage interface when ev dd0 < v dd . 1.8 v ev dd0 < 2.7 v : min. 125 ns 1.6 v ev dd0 < 1.8 v : min. 250 ns remark f mck : timer array unit operation clock frequency (operation clock to be set by the cks0n bit of ti mer clock select register 0 (tps0) and timer mode register 0n (tmr0n). n: channel number (n = 0 to 7)) minimum instruction execution time dur ing main system clock operation t cy vs v dd (hs (high-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 3.6 2.7 0.01 2.4 0.03125 0.0625 0.05 cycle time t cy [ s] supply voltage v dd [v] when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 35 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 t cy vs v dd (ls (low-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 0.01 1.8 0.125 3.6 cycle time t cy [ s] supply voltage v dd [v] when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected t cy vs v dd (lv (low-voltage main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 0.01 1.8 0.25 1.6 3.6 cycle time t cy [ s] supply voltage v dd [v] when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 36 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 ac timing test points v ih /v oh v il /v ol test points v ih /v oh v il /v ol external system clock timing exclk 0.7 v dd min. 0.3 v dd max. 1/f ex t exl t exh ti/to timing ti00, ti01, ti03 to ti07 t til t tih to00, to01, to03 to to07 1/f to interrupt request input timing intp0 to intp11 t intl t inth key interrupt input timing kr0 to kr9 t kr reset input timing reset t rsl rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 37 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 2.5 peripheral functions characteristics ac timing test points v ih /v oh v il /v ol test points v ih /v oh v il /v ol 2.5.1 serial array unit (1) during communication at same potential (uart mode) (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) hs note 1 ls note 2 lv note 3 parameter symbol conditions min. max. min. max. min. max. unit 2.4 v ev dd 3.6 v f mck /6 f mck /6 f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 6 5.3 note 5 1.3 0.6 mbps 1.8 v ev dd 3.6 v f mck /6 f mck /6 f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 6 5.3 note 5 1.3 0.6 mbps 1.7 v ev dd 3.6 v f mck /6 f mck /6 f mck /6 bps theoretical value of the maximum transfer rate f mck = f clk note 6 5.3 note 5 1.3 note 5 0.6 mbps 1.6 v ev dd 3.6 v ? f mck /6 f mck /6 bps transfer rate note 4 theoretical value of the maximum transfer rate f mck = f clk note 6 ? 1.3 note 5 0.6 mbps notes 1. hs is condition of hs (high-speed main) mode. 2. ls is condition of ls (low-speed main) mode. 3. lv is condition of lv (low-voltage main) mode. 4. transfer rate in the snooze mode is 4800 bps. 5. the following conditions are required for low-voltage interface when ev dd0 < v dd . 2.4 v ev dd0 < 2.7 v : max. 2.6 mbps 1.8 v ev dd0 < 2.4 v : max. 1.3 mbps 1.6 v ev dd0 < 1.8 v : max. 0.6 mbps 6. f clk in each operating mode is as below. hs (high-speed main) mode: f clk = 32 mhz ls (low-speed main) mode: f clk = 8 mhz lv (low-voltage main) mode: f clk = 4 mhz caution select the normal input buffer for the rxdq pi n and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 38 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 uart mode connection diagram (duri ng communication at same potential) rl78 microcontroller txdq rxdq rx tx user device uart mode bit width (dur ing communication at same potential) (reference) baud rate error tolerance high-/low-bit width 1/transfer rate txdq rxdq remarks 1. q: uart number (q = 0 to 2), g: pim and pom number (g = 0, 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10, 11)) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 39 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (2) during communication at same pot ential (csi mode) (master mode , sckp... internal clock output, corresponding csi00 only) (t a = ? 40 to +85 c, 2.7 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) notes 1. hs is condition of hs (high-speed main) mode. 2. ls is condition of ls (low-speed main) mode. 3. lv is condition of lv (low-voltage main) mode. 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpm n = 1. the sip setup time or sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 5. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 6. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port ou tput mode register g (pomg). remarks 1. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom numbers (g = 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00)) hs note 1 ls note 2 lv note 3 parameter symbol conditions min. max. min. max. min. max. unit sckp cycle time t kcy1 2.7 v ev dd 3.6 v t kcy1 2/f clk 83.3 250 500 ns sckp high-/low-level width t kh1 , t kl1 2.7 v ev dd 3.6 v t kcy1 /2 ? 10 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns sip setup time (to sckp ) note 4 t sik1 2.7 v ev dd 3.6 v 33 110 110 ns sip hold time (from sckp ) note 4 t ksi1 2.7 v ev dd 3.6 v 10 10 10 ns delay time from sckp to sop output note 5 t kso1 c = 20 pf note 6 10 10 10 ns rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 40 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (3) during communication at same pot ential (csi mode) (master mode, sckp... internal clock output) (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) hs note 1 ls note 2 lv note 3 parameter symbol conditions min. max. min. max. min. max. unit 2.7 v ev dd0 3.6 v t kcy1 4/f clk 125 500 1000 ns 2.4 v ev dd0 3.6 v t kcy1 4/f clk 250 500 1000 ns 1.8 v ev dd0 3.6 v t kcy1 4/f clk 500 500 1000 ns 1.7 v ev dd0 3.6 v t kcy1 4/f clk 1000 1000 1000 ns sckp cycle time t kcy2 1.6 v ev dd0 3.6 v t kcy1 4/f clk ? 1000 1000 ns 2.7 v ev dd0 3.6 v t kcy2 /2 ? 18 t kcy2 /2 ? 50 t kcy2 /2 ? 50 ns 2.4 v ev dd0 3.6 v t kcy2 /2 ? 38 t kcy2 /2 ? 50 t kcy2 /2 ? 50 ns 1.8 v ev dd0 3.6 v t kcy2 /2 ? 50 t kcy2 /2 ? 50 t kcy2 /2 ? 50 ns 1.7 v ev dd0 3.6 v t kcy2 /2 ? 100 t kcy2 /2 ? 100 t kcy2 /2 ? 100 ns sckp high-/low-level width t kh2 , t kl2 1.6 v ev dd0 3.6 v ? t kcy2 /2 ? 100 t kcy2 /2 ? 100 ns 2.7 v ev dd0 3.6 v 44 110 110 ns 2.4 v ev dd0 3.6 v 75 110 110 ns 1.8 v ev dd0 3.6 v 110 110 110 ns 1.7 v ev dd0 3.6 v 220 220 220 ns sip setup time (to sckp ) note 4 t sik2 1.6 v ev dd0 3.6 v ? 220 220 ns 1.7 v ev dd 3.6 v 19 19 19 ns sip hold time (from sckp ) note 4 t ksi2 1.6 v ev dd 3.6 v ? 19 19 ns 1.7 v ev dd 3.6 v c = 30 pf note 6 25 25 25 ns delay time from sckp to sop output note 5 t kso2 1.6 v ev dd 3.6 v c = 30 pf note 6 ? 25 25 ns notes 1. hs is condition of hs (high-speed main) mode. 2. ls is condition of ls (low-speed main) mode. 3. lv is condition of lv (low-voltage main) mode. 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpm n = 1. the sip setup time or sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 5. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 6. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port ou tput mode register g (pomg). remark p: csi number (p = 00, 01, 10, 11, 20, 21), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom numbers (g = 0, 1) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 41 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (4) during communication at same potential (csi mode) (slave m ode, sckp... external clock input) (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) hs note 1 ls note 2 lv note 3 parameter symbol conditions min. max. min. max. min. max. unit 16 mhz < f mck 8/f mck ? ? ns 2.7 v ev dd0 3.6 v f mck 16 mhz 6/f mck 6/f mck 6/f mck ns 2.4 v ev dd0 3.6 v 6/f mck and 500ns 6/f mck and 500ns 6/f mck and 500ns ns 1.8 v ev dd0 3.6 v 6/f mck and 750ns 6/f mck and 750ns 6/f mck and 750ns ns 1.7 v ev dd0 3.6 v 6/f mck and 1500ns 6/f mck and 1500ns 6/f mck and 1500ns ns sckp cycle time note 4 t kcy2 1.6 v ev dd0 3.6 v ? 6/f mck and 1500ns 6/f mck and 1500ns ns 2.7 v ev dd 3.6 v t kcy2 /2 ? 8 t kcy2 /2 ? 8 t kcy2 /2 ? 8 ns 1.8 v ev dd0 3.6 v t kcy2 /2 ? 18 t kcy2 /2 ? 18 t kcy2 /2 ? 18 ns 1.7 v ev dd0 3.6 v t kcy2 /2 ? 66 t kcy2 /2 ? 66 t kcy2 /2 ? 66 ns sckp high-/low-level width t kh2 , t kl2 1.6 v ev dd0 3.6 v ? t kcy2 /2 ? 66 t kcy2 /2 ? 66 ns 2.7 v ev dd0 3.6 v 1/f mck +20 1/f mck +30 1/f mck +30 ns 1.8 v ev dd0 3.6 v 1/f mck +30 1/f mck +30 1/f mck +30 ns 1.7 v ev dd0 3.6 v 1/f mck +40 1/f mck +40 1/f mck +40 ns sip setup time (to sckp ) note 5 t sik2 1.6 v ev dd0 3.6 v ? 1/f mck +40 1/f mck +40 ns 1.8 v ev dd0 3.6 v 1/f mck +31 1/f mck +31 1/f mck +31 ns 1.7 v ev dd0 3.6 v 1/f mck + 250 1/f mck + 250 1/f mck + 250 ns sip hold time (from sckp ) note 5 t ksi2 1.6 v ev dd0 3.6 v ? 1/f mck + 250 1/f mck + 250 ns 2.7 v ev dd0 3.6 v 2/f mck +44 2/f mck +110 2/f mck +110 ns 2.4 v ev dd0 3.6 v 2/f mck +75 2/f mck +110 2/f mck +110 ns 1.8 v ev dd0 3.6 v 2/f mck +110 2/f mck +110 2/f mck +110 ns 1.7 v ev dd0 3.6 v 2/f mck +220 2/f mck +220 2/f mck +220 ns delay time from sckp to sop output note 6 t kso2 c = 30 pf note 7 1.6 v ev dd0 3.6 v ? 2/f mck +220 2/f mck +220 ns ( note, caution and remark are listed on the next page.) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 42 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 notes 1. hs is condition of hs (high-speed main) mode. 2. ls is condition of ls (low-speed main) mode. 3. lv is condition of lv (low-voltage main) mode. 4. transfer rate in the snooze mode: max. 1 mbps 5. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpm n = 1. the sip setup time or sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 6. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 7. c is the load capacitance of the sop output lines. caution select the normal input buffer for the sip pi n and sckp pin and the normal output mode for the sop pin by using port input mode register g (pimg) and port out put mode register g (pomg). remarks 1. p: csi number (p = 00, 01, 10, 11, 20, 21), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim number (g = 0, 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of se rial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10, 11)) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 43 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 csi mode connection diagram (duri ng communication at same potential) rl78 microcontroller sckp sop sck si user device sip so csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip sop t kcy1, 2 t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 input data t kso1, 2 output data sckp csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip sop t kcy1, 2 t kh1, 2 t kl1, 2 t sik1, 2 t ksi1, 2 input data t kso1, 2 output data sckp remarks 1. p: csi number (p = 00, 01, 10, 11, 20, 21) 2. m: unit number, n: channel nu mber (mn = 00 to 03, 10, 11) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 44 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (5) during communication at sam e potential (simplified i 2 c mode) (1/2) (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) hs note 1 ls note 2 lv note 3 parameter symbol conditions min. max. min. max. min. max. unit 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 1000 note 4 400 note 4 400 note 4 khz 1.8 v ev dd0 3.6 v, c b = 100 pf, r b = 3 k 400 note 4 400 note 4 400 note 4 khz 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 300 note 4 300 note 4 300 note 4 khz 1.7 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k 250 note 4 250 note 4 250 note 4 khz sclr clock frequency f scl 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? 250 note 4 250 note 4 khz 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 475 1150 1150 ns 1.8 v ev dd0 3.6 v, c b = 100 pf, r b = 3 k 1150 1150 1150 ns 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 1550 1550 1550 ns 1.7 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k 1850 1850 1850 ns hold time when sclr = ?l? t low 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? 1850 1850 ns 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 475 1150 1150 ns 1.8 v ev dd0 3.6 v, c b = 100 pf, r b = 3 k 1150 1150 1150 ns 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 1550 1550 1550 ns 1.7 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k 1850 1850 1850 ns hold time when sclr = ?h? t high 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? 1850 1850 ns 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 1/f mck + 85 note 5 1/f mck + 145 note 5 1/f mck + 145 note 5 ns 1.8 v ev dd 3.6 v, c b = 100 pf, r b = 3 k 1/f mck + 145 note 5 1/f mck + 145 note 5 1/f mck + 145 note 5 ns 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 1/f mck + 230 note 5 1/f mck + 230 note 5 1/f mck + 230 note 5 ns 1.7 v ev dd < 1.8 v, c b = 100 pf, r b = 5 k 1/f mck + 290 note 5 1/f mck + 290 note 5 1/f mck + 290 note 5 ns data setup time (reception) t su:dat 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? 1/f mck + 290 note 5 1/f mck + 290 note 5 ns ( notes , caution and remarks are listed on the next page.) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 45 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (5) during communication at sam e potential (simplified i 2 c mode) (2/2) (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) hs note 1 ls note 2 lv note 3 parameter symbol conditions min. max. min. max. min. max. unit 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 0 305 0 305 0 305 ns 1.8 v ev dd0 3.6 v, c b = 100 pf, r b = 3 k 0 355 0 355 0 355 ns 1.8 v ev dd0 < 2.7 v, c b = 100 pf, r b = 5 k 0 405 0 405 0 405 ns 1.7 v ev dd0 1.8 v, c b = 100 pf, r b = 5 k 0 405 0 405 0 405 ns data hold time (transmission) t hd:dat 1.6 v ev dd0 < 1.8 v, c b = 100 pf, r b = 5 k ? ? 0 405 0 405 ns notes 1. hs is condition of hs (high-speed main) mode. 2. ls is condition of ls (low-speed main) mode. 3. lv is condition of lv (low-voltage main) mode. 4. the value must also be f clk /4 or lower. 5. set the f mck value to keep the hold time of sclr = ?l? and sclr = ?h?. caution select the normal input buffe r and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) mode for the sdar pin and the normal output mode for the sclr pin by using por t input mode register g (pimg) and port output mode register h (pomh). simplified i 2 c mode mode connection diagram (dur ing communication at same potential) rl78 microcontroller sdar sclr sda scl user device v dd r b simplified i 2 c mode serial transfer timing (dur ing communication at same potential) sdar t low t high t hd : dat sclr t su : dat 1/f scl remarks 1. r b [ ]: communication line (sdar) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance 2. r: iic number (r = 00, 01, 10, 11, 20, 21), g: pim number (g = 0, 1), h: pom number (h = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number, mn = 00 to 03, 10, 11) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 46 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (6) communication at different potential (1.8 v, 2.5 v) (uart mode) (dedicated baud rate generator output) (1/2) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) hs note 1 ls note 2 lv note 3 parameter symbol conditions min. max. min. max. min. max. unit f mck /6 f mck /6 f mck /6 bps 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v theoretical value of the maximum transfer rate f mck = f clk note 7 5.3 1.3 0.6 mbps f mck / 6 f mck /6 f mck /6 bps transfer rate note 4 reception 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 5 theoretical value of the maximum transfer rate f mck = f clk note 7 5.3 note 6 1.3 0.6 mbps notes 1. hs is condition of hs (high-speed main) mode. 2. ls is condition of ls (low-speed main) mode. 3. lv is condition of lv (low-voltage main) mode. 4. transfer rate in the snooze mode is 4800 bps. 5. use it with ev dd0 v b . 6. the following conditions are required for low-voltage interface when ev dd0 < v dd . 2.4 v ev dd0 < 2.7 v : max. 2.6 mbps 1.8 v ev dd0 < 2.4 v : max. 1.3 mbps 7. f clk in each operating mode is as below. hs (high-speed main) mode: f clk = 32 mhz ls (low-speed main) mode: f clk = 8 mhz lv (low-voltage main) mode: f clk = 4 mhz caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) m ode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remarks 1. v b [v]: communication line voltage 2. q: uart number (q = 0 to 2), g: pim and pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10, 11) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 47 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (6) communication at different potential (1.8 v, 2.5 v) (uart mode) (dedicated baud rate generator output) (2/2) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) hs note 1 ls note 2 lv note 3 parameter symbol conditions min. max. min. max. min. max. unit note 4 note 4 note 4 bps 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note 5 1.2 note 5 1.2 note 5 mbps note 7 note 7 note 7 bps transfer rate transmission 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 6 theoretical value of the maximum transfer rate c b = 50 pf, r b = 5.5 k , v b = 1.6 v 0.43 note 8 0.43 note 8 0.43 note 8 mbps notes 1. hs is condition of hs (high-speed main) mode. 2. ls is condition of ls (low-speed main) mode. 3. lv is condition of lv (low-voltage main) mode. 4. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v ev dd0 3.6 v and 2.3 v v b 2.7 v 1 maximum transfer rate = { ? c b r b ln (1 ? 2.0 v b )} 3 [bps] 1 transfer rate 2 ? { ? c b r b ln (1 ? 2.0 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relati ve difference between the transmission and reception sides. 5. this value as an example is calculated when the c onditions described in the ?conditions? column are met. see note 4 above to calculate the maximum transfer rate under conditions of the customer. 6. use it with ev dd0 v b . 7. the smaller maximum transfer rate derived by using f mck /6 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 1.8 v ev dd0 < 3.3 v and 1.6 v v b 2.0 v 1 maximum transfer rate = [bps] { ? c b r b ln (1 ? 1.5 v b )} 3 1 transfer rate 2 ? { ? c b r b ln (1 ? 1.5 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relati ve difference between the transmission and reception sides. 8. this value as an example is calculated when the c onditions described in the ?conditions? column are met. see note 7 above to calculate the maximum transfer rate under conditions of the customer. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) m ode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 48 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 uart mode connection diagram (during communication at different potential) rl78 microcontroller txdq rxdq rx tx user device v b r b uart mode bit width (during communication at different potential) (reference) baud rate error tolerance high-/low-bit width 1/transfer rate baud rate error tolerance high-bit width low-bit width 1/transfer rate txdq rxdq remarks 1. r b [ ]: communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage 2. q: uart number (q = 0 to 2), g: pim and pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel nu mber (mn = 00 to 03, 10, 11)) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 49 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (7) communication at different potential (2.5 v) (csi mode) (master mode, sckp... internal clock output, corresponding csi00 only) (t a = ? 40 to +85 c, 2.7 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) hs note 1 ls note 2 lv note 3 parameter symbol conditions min. max. min. max. min. max. unit sckp cycle time t kcy1 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k t kcy1 2/f clk 300 1150 1150 ns sckp high-level width t kh1 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k t kcy1 /2 ? 120 t kcy1 /2 ? 120 t kcy1 /2 ? 120 ns sckp low-level width t kl1 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k t kcy1 /2 ? 10 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns sip setup time (to sckp ) note 4 t sik1 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 121 479 479 ns sip hold time (from sckp ) note 4 t ksi1 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 10 10 ns delay time from sckp to sop output note 4 t kso1 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 130 130 130 ns sip setup time (to sckp ) note 5 t sik1 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 33 110 110 ns sip hold time (from sckp ) note 5 t ksi1 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 10 10 ns delay time from sckp to sop output note 5 t kso1 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 20 pf, r b = 2.7 k 10 10 10 ns notes 1. hs is condition of hs (high-speed main) mode. 2. ls is condition of ls (low-speed main) mode. 3. lv is condition of lv (low-voltage main) mode. 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. 5. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remarks 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00), m: unit number (m = 0), n: channel number (n = 0), g: pim and pom number (g = 1) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 50 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (8) communication at different potential (1.8v, 2.5 v) (csi mode) (master mode, sckp... internal clock output) (1/2) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) hs note 1 ls note 2 lv note 3 parameter symbol conditions min. max. min. max. min. max. unit 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 4/f clk 500 1150 1150 ns sckp cycle time t kcy1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 4 , c b = 30 pf, r b = 5.5 k t kcy1 4/f clk 1150 1150 1150 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 170 t kcy1 /2 ? 170 t kcy1 /2 ? 170 ns sckp high-level width t kh1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 4 , c b = 30 pf, r b = 5.5 k t kcy1 /2 ? 458 t kcy1 /2 ? 458 t kcy1 /2 ? 458 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 18 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns sckp low-level width t kl1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 4 , c b = 30 pf, r b = 5.5 k t kcy1 /2 ? 50 t kcy1 /2 ? 50 t kcy1 /2 ? 50 ns notes 1. hs is condition of hs (high-speed main) mode. 2. ls is condition of ls (low-speed main) mode. 3. lv is condition of lv (low-voltage main) mode. 4. use it with ev dd0 v b . caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remarks 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00, 10, 20), m: unit number , n: channel number (mn = 00, 02, 10), g: pim and pom number (g = 0, 1) 3. csi01, csi11, and csi21 cannot communicate at different potential. use other csi for communication at different potential. rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 51 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (8) communication at different potential (1.8 v, 2.5 v) (csi mode) (master mode, sckp... internal clock output) (2/2) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) hs note 1 ls note 2 lv note 3 parameter symbol conditions min. max. min. max. min. max. unit 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 177 479 479 ns sip setup time (to sckp ) note 4 t sik1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 6 , c b = 30 pf, r b = 5.5 k 479 479 479 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 19 19 19 ns sip hold time (from sckp ) note 4 t ksi1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 6 , c b = 30 pf, r b = 5.5 k 19 19 19 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 195 195 195 ns delay time from sckp to sop output note 4 t kso1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 6 , c b = 30 pf, r b = 5.5 k 483 483 483 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 44 110 110 ns sip setup time (to sckp ) note 5 t sik1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 6 , c b = 30 pf, r b = 5.5 k 110 110 110 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 19 19 19 ns sip hold time (from sckp ) note 5 t ksi1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 6 , c b = 30 pf, r b = 5.5 k 19 19 19 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 25 25 25 ns delay time from sckp to sop output note 5 t kso1 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 6 , c b = 30 pf, r b = 5.5 k 25 25 25 ns notes 1. hs is condition of hs (high-speed main) mode. 2. ls is condition of ls (low-speed main) mode. 3. lv is condition of lv (low-voltage main) mode. 4. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. 5. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 6. use it with ev dd0 v b . caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) mode for the sop pin and sckp pin by using port input mode regi ster g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. (remarks are listed on the next page.) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 52 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 csi mode connection diagram (during communication at different potential) v b r b sckp sop sck si user device sip so v b r b rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 53 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip sop t kcy1 t kl1 t kh1 t sik1 t ksi1 input data t kso1 output data sckp csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip sop t kcy1 t kl1 t kh1 t sik1 t ksi1 input data t kso1 output data sckp remarks 1. p: csi number (p = 00, 10, 20), m: unit number, n: channel number (m = 00, 02, 10), g: pim and pom number (g = 0, 1) 2. csi01, csi11, and csi21 cannot communicate at different potential. use other csi for communication at different potential. rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 54 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (9) communication at different potential (1.8 v, 2.5 v) (csi mode) (slave mode, s ckp... external clock input) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) hs note 1 ls note 2 lv note 3 parameter symbol conditions min. max. min. max. min. max. unit 24 mhz < f mck 20/f mck ? ? ns 20 mhz < f mck 24 mhz 16/f mck ? ? ns 16 mhz < f mck 20 mhz 14/f mck ? ? ns 8 mhz < f mck 16 mhz 12/f mck ? ? ns 4 mhz < f mck 8 mhz 8/f mck 16/f mck ? ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v f mck 4 mhz 6/f mck 10/f mck 10/f mck ns 24 mhz < f mck 48/f mck ? ? ns 20 mhz < f mck 24 mhz 36/f mck ? ? ns 16 mhz < f mck 20 mhz 32/f mck ? ? ns 8 mhz < f mck 16 mhz 26/f mck ? ? ns 4 mhz < f mck 8 mhz 16/f mck 16/f mck ? ns sckp cycle time note 4 t kcy2 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 5 f mck 4 mhz 10/f mck 10/f mck 10/f mck ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v t kcy2 /2 ? 18 t kcy2 /2 ? 50 t kcy2 /2 ? 50 ns sckp high-/low-level width t kh2 , t kl2 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 5 t kcy2 /2 ? 50 t kcy2 /2 ? 50 t kcy2 /2 ? 50 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v 1/f mck + 20 1/f mck + 30 1/f mck + 30 ns sip setup time (to sckp ) note 6 t sik2 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 5 1/f mck + 30 1/f mck + 30 1/f mck + 30 ns sip hold time (from sckp ) note 6 t ksi2 1/f mck + 31 1/f mck + 31 1/f mck + 31 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 2/f mck + 214 2/f mck + 573 2/f mck + 573 ns delay time from sckp to sop output note 7 t kso2 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 5 , c b = 30 pf, r b = 5.5 k 2/f mck + 573 2/f mck + 573 2/f mck + 573 ns notes 1. hs is condition of hs (high-speed main) mode. 2. ls is condition of ls (low-speed main) mode. 3. lv is condition of lv (low-voltage main) mode. 4. transfer rate in the snooze mode : max. 1 mbps 5. use it with ev dd0 v b . 6. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpm n = 1. the sip setup time or sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 7. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pi n and sckp pin and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) mode for the sop pin by using port input mode re gister g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed on the next page.) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 55 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 csi mode connection diagram (during communication at different potential) rl78 microcontroller sckp sop sck si user device sip so v b r b rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 56 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 csi mode serial transfer timi ng (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip sop t kcy2 t kl2 t kh2 t sik2 t ksi2 input data t kso2 output data sckp csi mode serial transfer timi ng (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip sop t kcy2 t kl2 t kh2 t sik2 t ksi2 input data t kso2 output data sckp remarks 1. p: csi number (p = 00, 10, 20), m: unit number, n: channel number (mn = 00, 02, 10), g: pim and pom number (g = 0, 1) 2. csi01, csi11, and csi21 cannot communicate at different potential. use other csi for communication at different potential. rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 57 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (10) communication at different potent ial (1.8 v, 2.5 v) (simplified i 2 c mode) (1/2) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) hs note 1 ls note 2 lv note 3 parameter symbol conditions min. max. min. max. min. max. unit 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 1000 note 4 300 note 4 300 note 4 khz 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 400 note 4 300 note 4 300 note 4 khz sclr clock frequency f scl 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 5 , c b = 100 pf, r b = 5.5 k 300 note 4 300 note 4 300 note 4 khz 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 475 1550 1550 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1150 1550 1550 ns hold time when sclr = ?l? t low 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 5 , c b = 100 pf, r b = 5.5 k 1550 1550 1550 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 200 610 610 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 600 610 610 ns hold time when sclr = ?h? t high 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 5 , c b = 100 pf, r b = 5.5 k 610 610 610 ns ( notes , caution and remarks are listed on the next page.) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 58 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (10) communication at different potent ial (1.8 v, 2.5 v) (simplified i 2 c mode) (2/2) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) hs note 1 ls note 2 lv note 3 parameter symbol conditions min. max. min. max. min. max. unit 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 1/f mck + 135 note 6 1/f mck + 190 note 6 1/f mck + 190 note 6 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1/f mck + 190 note 6 1/f mck + 190 note 6 1/f mck + 190 note 6 ns data setup time (reception) t su:dat 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 5 , c b = 100 pf, r b = 5.5 k 1/f mck + 190 note 6 1/f mck + 190 note 6 1/f mck + 190 note 6 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 0 305 0 305 0 305 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 0 355 0 355 0 355 ns data hold time (transmission) t hd:dat 1.8 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v note 5 , c b = 100 pf, r b = 5.5 k 0 405 0 405 0 405 ns notes 1. hs is condition of hs (high-speed main) mode. 2. ls is condition of ls (low-speed main) mode. 3. lv is condition of lv (low-voltage main) mode. 4. the value must also be f clk /4 or lower. 5. use it with ev dd0 v b . 6. set the f mck value to keep the hold time of sclr = ?l? and sclr = ?h?. caution select the ttl input buffer and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) mode fo r the sdar pin and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) mode for the sclr pin by using po rt input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. ( remarks are listed on the next page.) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 59 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 simplified i 2 c mode connection diagram (during communication at different potential) sdar sclr sda scl user device v b r b v b r b rl78 microcontroller simplified i 2 c mode serial transfer timing (during co mmunication at different potential) sdar t low t high t hd : dat sclr t su : dat 1/f scl remarks 1. r b [ ]: communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage 2. r: iic number (r = 00, 10, 20), g: pim, pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 02, 10) 4. iic01, iic11, and iic21 cannot communicate at di fferent potential. use iic00, iic10, or iic20 for communication at different potential. rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 60 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 2.5.2 serial interface iica (1) i 2 c standard mode (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) standard mode note 1 hs note 2 ls note 3 lv note 4 parameter symbol conditions min. max. min. min. max. min. unit 2.7 v ev dd0 3.6 v 0 100 0 100 0 100 1.8 v ev dd0 3.6 v 0 100 0 100 0 100 1.7 v ev dd0 3.6 v 0 100 0 100 0 100 scla0 clock frequency f scl 1.6 v ev dd0 3.6 v ? 0 100 0 100 khz 2.7 v ev dd0 3.6 v 4.7 4.7 4.7 1.8 v ev dd0 3.6 v 4.7 4.7 4.7 1.7 v ev dd0 3.6 v 4.7 4.7 4.7 setup time of restart condition t su:sta 1.6 v ev dd0 3.6 v ? 4.7 4.7 s 2.7 v ev dd0 3.6 v 4.0 4.0 4.0 1.8 v ev dd0 3.6 v 4.0 4.0 4.0 1.7 v ev dd0 3.6 v 4.0 4.0 4.0 hold time note 5 t hd:sta 1.6 v ev dd0 3.6 v ? 4.0 4.0 s 2.7 v ev dd0 3.6 v 4.7 4.7 4.7 1.8 v ev dd0 3.6 v 4.7 4.7 4.7 1.7 v ev dd0 3.6 v 4.7 4.7 4.7 hold time when scla0 = ?l? t low 1.6 v ev dd0 3.6 v ? 4.7 4.7 s 2.7 v ev dd0 3.6 v 4.0 4.0 4.0 1.8 v ev dd0 3.6 v 4.0 4.0 4.0 1.7 v ev dd0 3.6 v 4.0 4.0 4.0 hold time when scla0 = ?h? t high 1.6 v ev dd0 3.6 v ? 4.0 4.0 s 2.7 v ev dd0 3.6 v 250 250 250 1.8 v ev dd0 3.6 v 250 250 250 1.7 v ev dd0 3.6 v 250 250 250 data setup time (reception) t su:dat 1.6 v ev dd0 3.6 v ? 250 250 ns 2.7 v ev dd0 3.6 v 0 3.45 0 3.45 0 3.45 1.8 v ev dd0 3.6 v 0 3.45 0 3.45 0 3.45 1.7 v ev dd0 3.6 v 0 3.45 0 3.45 0 3.45 data hold time (transmission) note 6 t hd:dat 1.6 v ev dd0 3.6 v ? ? 0 3.45 0 3.45 s 2.7 v ev dd0 3.6 v 4.0 4.0 4.0 1.8 v ev dd0 3.6 v 4.0 4.0 4.0 1.7 v ev dd0 3.6 v 4.0 4.0 4.0 setup time of stop condition t su:sto 1.6 v ev dd0 3.6 v ? 4.0 4.0 s 2.7 v ev dd0 3.6 v 4.7 4.7 4.7 1.8 v ev dd0 3.6 v 4.7 4.7 4.7 1.7 v ev dd0 3.6 v 4.7 4.7 4.7 bus-free time t buf 1.6 v ev dd0 3.6 v ? 4.7 4.7 s ( note and remark are listed on the next page.) rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 61 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (2) i 2 c fast mode, fast mode plus (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) fast mode note 7 fast mode plus note 8 hs note 2 ls note 3 lv note 4 hs note 2 parameter symbol conditions min. max. min. min. max. min. max. min. unit 2.7 v ev dd0 3.6 v 0 400 0 400 0 400 0 1000 scla0 clock frequency f scl 1.8 v ev dd0 3.6 v 0 400 0 400 0 400 ? khz 2.7 v ev dd0 3.6 v 0.6 0.6 0.6 0.26 setup time of restart condition t su:sta 1.8 v ev dd0 3.6 v 0.6 0.6 0.6 ? s 2.7 v ev dd0 3.6 v 0.6 0.6 0.6 0.26 hold time note 5 t hd:sta 1.8 v ev dd0 3.6 v 0.6 0.6 0.6 ? s 2.7 v ev dd0 3.6 v 1.3 1.3 1.3 0.5 hold time when scla0 = ?l? t low 1.8 v ev dd0 3.6 v 1.3 1.3 1.3 ? s 2.7 v ev dd0 3.6 v 0.6 0.6 0.6 0.26 hold time when scla0 = ?h? t high 1.8 v ev dd0 3.6 v 0.6 0.6 0.6 ? s 2.7 v ev dd0 3.6 v 100 100 100 50 data setup time (reception) t su:dat 1.8 v ev dd0 3.6 v 100 100 100 ? ns 2.7 v ev dd0 3.6 v 0 0.9 0 0.9 0 0.9 0 450 data hold time (transmission) note 6 t hd:dat 1.8 v ev dd0 3.6 v 0 0.9 0 0.9 0 0.9 ? s 2.7 v ev dd0 3.6 v 0.6 0.6 0.6 0.26 setup time of stop condition t su:sto 1.8 v ev dd0 3.6 v 0.6 0.6 0.6 ? s 2.7 v ev dd0 3.6 v 1.3 1.3 1.3 0.5 bus-free time t buf 1.8 v ev dd0 3.6 v 1.3 1.3 1.3 ? s notes 1. in normal mode, use it with f clk 1 mhz, 1.6 v ev dd 3.6 v. 2. hs is condition of hs (high-speed main) mode. 3. ls is condition of ls (low-speed main) mode. 4. lv is condition of lv (low-voltage main) mode. 5. the first clock pulse is generated after this per iod when the start/restart condition is detected. 6. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. 7. in fast mode, use it with f clk 3.5 mhz, 1.8 v ev dd 3.6 v. 8. in fast mode plus, use it with f clk 10 mhz, 2.7 v ev dd 3.6 v. remark the maximum value of c b (communication line capacitance) and the value of r b (communication line pull-up resistor) at that time in each mode are as follows. standard mode: c b = 400 pf, r b = 2.7 k fast mode: c b = 320 pf, r b = 1.1 k fast mode plus: c b = 120 pf, r b = 1.1 k rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 62 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 iica serial transfer timing t low t high t hd : sta t buf stop condition start condition restart condition stop condition t su : dat t su : sta t su : sto t hd : sta t hd : dat scl0 sda0 rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 63 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 2.6 analog characteristics 2.6.1 a/d converter characteristics division of a/d converter characteristics reference voltag input channel reference voltage (+) = av refp reference voltage ( ? ) = av refm reference voltage (+) = av dd reference voltage ( ? ) = av ss reference voltage (+) = internal refrence voltage reference voltage ( ? ) = av ss high-accuracy channel; ani0 to ani12 (input buffer power supply: av dd ) see 2.6.1 (1) see 2.6.1 (2) see 2.6.1 (3) standard channel; ani16 to ani30 (input buffer power supply: v dd or ev dd0 ) see 2.6.1 (4) see 2.6.1 (5) see 2.6.1 (6) temperature sensor, internal reference voltage output see 2.6.1 (4) see 2.6.1 (5) ? (1) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target for conversion: ani2 to ani12 (t a = ? 40 to +85 c, 2.7 v av refp av dd v dd 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v, halt mode) parameter symbol conditions min. typ. max. unit resolution r es 12 bit overall error notes 1, 2, 3 ainl 12-bit resolution 1.7 3.3 lsb conversion time t conv adtyp = 0, 12-bit resolution 3.375 s zero-scale error notes 1, 2, 3 e zs 12-bit resolution 1.3 3.2 lsb full-scale error notes 1, 2, 3 e fs 12-bit resolution 0.7 2.9 lsb integral linearity error notes 1, 2, 3 ile 12-bit resolution 1.0 1.4 lsb differential linearity error notes 1, 2, 3 dle 12-bit resolution 0.9 1.2 lsb analog input voltage v ain 0 av refp v notes 1. typ. value is the average value at av dd = av refp = 3 v and t a = 25 c. max. value is the average value 3 at normalized distribution. 2. these values are the results of characteristic evaluation and are not checked for shipment. 3. excludes quantization error ( 1/2 lsb). cautions 1. route the wiring so th at noise will not be superimposed on each power line and ground line, and insert a capacitor to suppress noise. in addition, separate the reference voltage line of av refp from the other power lines to keep it free from the influences of noise. 2. during a/d conversion, keep a pulse, such as a digital signal, th at abruptly changes its level from being input to or output fr om the pins adjacent to the con verter pins and p20 to p27 and p150 to p154. rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 64 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (2) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target for conversion: ani2 to ani12 (t a = ? 40 to +85 c, 1.6 v av refp av dd v dd 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit 2.4 v av refp av dd 3.6 v 8 12 bit 1.8 v av refp av dd 3.6 v 8 10 note 1 resolution r es 1.6 v av refp av dd 3.6 v 8 note 2 12-bit resolution 2.4 v av refp av dd 3.6 v 6.0 lsb 10-bit resolution 1.8 v av refp av dd 3.6 v 5.0 overall error note 3 ainl 8-bit resolution 1.6 v av refp av dd 3.6 v 2.5 adtyp = 0, 12-bit resolution 2.4 v av refp av dd 3.6 v 3.375 adtyp = 0, 10-bit resolution note 1 1.8 v av refp av dd 3.6 v 6.75 adtyp = 0, 8-bit resolution note 2 1.6 v av refp av dd 3.6 v 13.5 2.4 v av refp av dd 3.6 v 2.5625 1.8 v av refp av dd 3.6 v 5.125 conversion time t conv adtyp = 1, 8-bit resolution 1.6 v av refp av dd 3.6 v 10.25 s 12-bit resolution 2.4 v av refp av dd 3.6 v 4.5 lsb 10-bit resolution 1.8 v av refp av dd 3.6 v 4.5 zero-scale error note 3 e zs 8-bit resolution 1.6 v av refp av dd 3.6 v 2.0 12-bit resolution 2.4 v av refp av dd 3.6 v 4.5 lsb 10-bit resolution 1.8 v av refp av dd 3.6 v 4.5 full-scale error note 3 e fs 8-bit resolution 1.6 v av refp av dd 3.6 v 2.0 12-bit resolution 2.4 v av refp av dd 3.6 v 2.0 lsb 10-bit resolution 1.8 v av refp av dd 3.6 v 1.5 integral linearity error note 3 ile 8-bit resolution 1.6 v av refp av dd 3.6 v 1.0 12-bit resolution 2.4 v av refp av dd 3.6 v 1.5 lsb 10-bit resolution 1.8 v av refp av dd 3.6 v 1.5 differential linearity error note 3 dle 8-bit resolution 1.6 v av refp av dd 3.6 v 1.0 analog input voltage v ain 0 av refp v notes 1. cannot be used for lower 2 bit of adcr register 2. cannot be used for lower 4 bit of adcr register 3. excludes quantization error ( 1/2 lsb). rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 65 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (3) when reference voltage (+) = av dd (adrefp1 = 0, adrefp0 = 0), reference voltage ( ? ) = av ss (adrefm = 0), target for conversion: ani0 to ani12 (t a = ? 40 to +85 c, 1.6 v av dd v dd 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av dd , reference voltage ( ? ) = av ss = 0 v) parameter symbol conditions min. typ. max. unit 2.4 v av dd 3.6 v 8 12 bit 1.8 v av dd 3.6 v 8 10 note 1 resolution r es 1.6 v av dd 3.6 v 8 note 2 12-bit resolution 2.4 v av dd 3.6 v 7.5 lsb 10-bit resolution 1.8 v av dd 3.6 v 5.5 overall error note 3 ainl 8-bit resolution 1.6 v av dd 3.6 v 3.0 adtyp = 0, 12-bit resolution 2.4 v av dd 3.6 v 3.375 adtyp = 0, 10-bit resolution note 1 1.8 v av dd 3.6 v 6.75 adtyp = 0, 8-bit resolution note 2 1.6 v av dd 3.6 v 13.5 2.4 v av dd 3.6 v 2.5625 1.8 v av dd 3.6 v 5.125 conversion time t conv adtyp = 1, 8-bit resolution 1.6 v av dd 3.6 v 10.25 s 12-bit resolution 2.4 v av dd 3.6 v 6.0 lsb 10-bit resolution 1.8 v av dd 3.6 v 5.0 zero-scale error note 3 e zs 8-bit resolution 1.6 v av dd 3.6 v 2.5 12-bit resolution 2.4 v av dd 3.6 v 6.0 lsb 10-bit resolution 1.8 v av dd 3.6 v 5.0 full-scale error note 3 e fs 8-bit resolution 1.6 v av dd 3.6 v 2.5 12-bit resolution 2.4 v av dd 3.6 v 3.0 lsb 10-bit resolution 1.8 v av dd 3.6 v 2.0 integral linearity error note 3 ile 8-bit resolution 1.6 v av dd 3.6 v 1.5 12-bit resolution 2.4 v av dd 3.6 v 2.0 lsb 10-bit resolution 1.8 v av dd 3.6 v 2.0 differential linearity error note 3 dle 8-bit resolution 1.6 v av dd 3.6 v 1.5 analog input voltage v ain 0 av dd v notes 1. cannot be used for lower 2 bit of adcr register 2. cannot be used for lower 4 bit of adcr register 3. excludes quantization error ( 1/2 lsb). rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 66 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (4) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target for conversion: ani 16 to ani30, interanal reference voltage, temperature sensor output voltage (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd 3.6 v, 1.6 v av refp av dd v dd 3.6 v, v ss = ev ss0 = 0 v, av ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit 2.4 v av refp av dd 3.6 v 8 12 bit 1.8 v av refp av dd 3.6 v 8 10 note 1 resolution r es 1.6 v av refp av dd 3.6 v 8 note 2 12-bit resolution 2.4 v av refp av dd 3.6 v 7.0 lsb 10-bit resolution 1.8 v av refp av dd 3.6 v 5.5 overall error note 3 ainl 8-bit resolution 1.6 v av refp av dd 3.6 v 3.0 adtyp = 0, 12-bit resolution 2.4 v av refp av dd 3.6 v 4.125 adtyp = 0, 10-bit resolution note 1 1.8 v av refp av dd 3.6 v 9.5 adtyp = 0, 8-bit resolution note 2 1.6 v av refp av dd 3.6 v 57.5 2.4 v av refp av dd 3.6 v 3.3125 1.8 v av refp av dd 3.6 v 7.875 conversion time t conv adtyp = 1, 8-bit resolution 1.6 v av refp av dd 3.6 v 54.25 s 12-bit resolution 2.4 v av refp av dd 3.6 v 5.0 lsb 10-bit resolution 1.8 v av refp av dd 3.6 v 5.0 zero-scale error note 3 e zs 8-bit resolution 1.6 v av refp av dd 3.6 v 2.5 12-bit resolution 2.4 v av refp av dd 3.6 v 5.0 lsb 10-bit resolution 1.8 v av refp av dd 3.6 v 5.0 full-scale error note 3 e fs 8-bit resolution 1.6 v av refp av dd 3.6 v 2.5 12-bit resolution 2.4 v av refp av dd 3.6 v 3.0 lsb 10-bit resolution 1.8 v av refp av dd 3.6 v 2.0 integral linearity error note 3 ile 8-bit resolution 1.6 v av refp av dd 3.6 v 1.5 12-bit resolution 2.4 v av refp av dd 3.6 v 2.0 lsb 10-bit resolution 1.8 v av refp av dd 3.6 v 2.0 differential linearity error note 3 dle 8-bit resolution 1.6 v av refp av dd 3.6 v 1.5 0 av refp and ev dd0 v interanal reference voltage (2.4 v v dd 3.6 v, hs (high-speed main) mode) v bgr note 4 v analog input voltage v ain temperature sensor output voltage (2.4 v v dd 3.6 v, hs (high-speed main) mode) v tmps25 note 4 v notes 1. cannot be used for lower 2 bit of adcr register 2. cannot be used for lower 4 bit of adcr register 3. excludes quantization error ( 1/2 lsb). 4. see 2.6.2 temperature sensor, internal re ference voltage output characteristics . rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 67 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (5) when reference voltage (+) = av dd (adrefp1 = 0, adrefp0 = 0), reference voltage ( ? ) = av ss (adrefm = 0), target for conversion: ani16 to ani30, interanal reference voltage, temperature sensor output voltage (t a = ? 40 to +85 c, 1.6 v ev dd0 v dd0 3.6 v, 1.6 v av dd v dd 3.6 v, v ss = ev ss0 = 0 v, av ss = 0 v, reference voltage (+) = av dd , reference voltage ( ? ) = av ss = 0 v) parameter symbol conditions min. typ. max. unit 2.4 v av dd 3.6 v 8 12 bit 1.8 v av dd 3.6 v 8 10 note 1 resolution r es 1.6 v av dd 3.6 v 8 note 2 12-bit resolution 2.4 v av dd 3.6 v 8.5 lsb 10-bit resolution 1.8 v av dd 3.6 v 6.0 overall error note 3 ainl 8-bit resolution 1.6 v av dd 3.6 v 3.5 adtyp = 0, 12-bit resolution 2.4 v av dd 3.6 v 4.125 s adtyp = 0, 10-bit resolution note 1 1.8 v av dd 3.6 v 9.5 adtyp = 0, 8-bit resolution note 2 1.6 v av dd 3.6 v 57.5 2.4 v av dd 3.6 v 3.3125 s 1.8 v av dd 3.6 v 7.875 conversion time t conv adtyp = 1, 8-bit resolution 1.6 v av dd 3.6 v 54.25 12-bit resolution 2.4 v av dd 3.6 v 8.0 lsb 10-bit resolution 1.8 v av dd 3.6 v 5.5 zero-scale error note 3 e zs 8-bit resolution 1.6 v av dd 3.6 v 3.0 12-bit resolution 2.4 v av dd 3.6 v 8.0 lsb 10-bit resolution 1.8 v av dd 3.6 v 5.5 full-scale error note 3 e fs 8-bit resolution 1.6 v av dd 3.6 v 3.0 12-bit resolution 2.4 v av dd 3.6 v 3.5 lsb 10-bit resolution 1.8 v av dd 3.6 v 2.5 integral linearity error note 3 ile 8-bit resolution 1.6 v av dd 3.6 v 1.5 12-bit resolution 2.4 v av dd 3.6 v 2.5 lsb 10-bit resolution 1.8 v av dd 3.6 v 2.5 differential linearity error note 3 dle 8-bit resolution 1.6 v av dd 3.6 v 2.0 0 av dd and ev dd0 v interanal reference voltage (2.4 v v dd 3.6 v, hs (high-speed main) mode) v bgr note 4 v analog input voltage v ain temperature sensor output voltage (2.4 v v dd 3.6 v, hs (high-speed main) mode) v tmps25 note 4 v notes 1. cannot be used for lower 2 bit of adcr register 2. cannot be used for lower 4 bit of adcr register 3. excludes quantization error ( 1/2 lsb). 4. see 2.6.2 temperature sensor, internal re ference voltage output characteristics . rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 68 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (6) when reference voltage (+) = inte rnal reference voltage (1.45 v) (adrefp1 = 1, adrefp0 = 0), reference voltage ( ? ) = av ss (adrefm = 0), target ani pi n: ani0 to ani12, ani16 to ani30 (t a = ? 40 to +85 c, 2.4 v v dd 3.6 v, 1.6 v ev dd v dd , 1.6 v av dd v dd , v ss = ev ss0 = 0 v, av ss = 0 v, reference voltage (+) = internal reference voltage, reference voltage ( ? ) = av ss = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution r es 8 bit conversion time t conv 8-bit resolution 16 s zero-scale error note e zs 8-bit resolution 4.0 lsb integral linearity error note ile 8-bit resolution 2.0 lsb differential linearity error note dle 8-bit resolution 2.5 lsb reference voltage (+) av ref(+) = internal reference voltage (v bgr ) 1.38 1.45 1.5 v analog input voltage v ain 0 v bgr v note excludes quantization error ( 1/2 lsb). 2.6.2 temperature sensor, internal reference voltage output characteristics (t a = ? 40 to +85 c, 2.4 v v dd 3.6 v, v ss = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25 c 1.05 v internal reference voltage v bgr setting ads register = 81h 1.38 1.45 1.5 v temperature coefficient f vtmps temperature sensor output voltage that depends on the temperature ? 3.6 mv/ c operation stabilization wait time t amp 10 s 2.6.3 por circuit characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit v por power supply rise time 1.47 1.51 1.55 v detection voltage v pdr power supply fall time 1.46 1.50 1.54 v minimum pulse width note t pw 300 s note this is the time required for the por circuit to execute a reset when v dd falls below v pdr . when the microcontroller enters stop mode or if the main system clock (f main ) has been stopped by setting bit 0 (hiostop) and bit 7 (mstop) of the cl ock operation status control register (csc), this is the time required for the por circuit to execute a reset before v dd rises to v por after having fallen below 0.7 v. v por t pw power supply voltage (v dd ) v por or 0.7 v rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 69 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 2.6.4 lvd circuit characteristics lvd detection voltage of reset mode and interrupt mode (t a = ? 40 to +85 c, v pdr v dd 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply rise time 3.07 3.13 3.19 v v lvd2 power supply fall time 3.00 3.06 3.12 v power supply rise time 2.96 3.02 3.08 v v lvd3 power supply fall time 2.90 2.96 3.02 v power supply rise time 2.86 2.92 2.97 v v lvd4 power supply fall time 2.80 2.86 2.91 v power supply rise time 2.76 2.81 2.87 v v lvd5 power supply fall time 2.70 2.75 2.81 v power supply rise time 2.66 2.71 2.76 v v lvd6 power supply fall time 2.60 2.65 2.70 v power supply rise time 2.56 2.61 2.66 v v lvd7 power supply fall time 2.50 2.55 2.60 v power supply rise time 2.45 2.50 2.55 v v lvd8 power supply fall time 2.40 2.45 2.50 v power supply rise time 2.05 2.09 2.13 v v lvd9 power supply fall time 2.00 2.04 2.08 v power supply rise time 1.94 1.98 2.02 v v lvd10 power supply fall time 1.90 1.94 1.98 v power supply rise time 1.84 1.88 1.91 v v lvd11 power supply fall time 1.80 1.84 1.87 v power supply rise time 1.74 1.77 1.81 v v lvd12 power supply fall time 1.70 1.73 1.77 v power supply rise time 1.64 1.67 1.70 v detection voltage supply voltage level v lvd13 power supply fall time 1.60 1.63 1.66 v minimum pulse width t lw 300 s detection delay time 300 s caution set the detection voltage (v lvd ) to be within the operating voltage range. the operating voltage range depends on the setting of the user option byte (000c2h/010c2h). the following shows the operating voltage range. hs (high-speed main) mode: v dd = 2.7 to 3.6 v@1 mhz to 32 mhz v dd = 2.4 to 3.6 v@1 mhz to 16 mhz ls (low-speed main) mode: v dd = 1.8 to 3.6 v@1 mhz to 8 mhz lv (low-voltage main) mode: v dd = 1.6 to 3.6 v@1 mhz to 4 mhz rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 70 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 lvd detection voltage of interrupt & reset mode (t a = ? 40 to +85 c, v pdr v dd 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit v lvd13 vpoc2, vpoc1, vpoc0 = 0, 0, 0, falling reset voltage 1.60 1.63 1.66 v rising release reset voltage 1.74 1.77 1.81 v v lvd12 lvis1, lvis0 = 1, 0 falling interrupt voltage 1.70 1.73 1.77 v rising release reset voltage 1.84 1.88 1.91 v v lvd11 lvis1, lvis0 = 0, 1 falling interrupt voltage 1.80 1.84 1.87 v rising release reset voltage 2.86 2.92 2.97 v v lvd4 lvis1, lvis0 = 0, 0 falling interrupt voltage 2.80 2.86 2.91 v v lvd11 vpoc2, vpoc1, vpoc0 = 0, 0, 1, falling reset voltage 1.80 1.84 1.87 v rising release reset voltage 1.94 1.98 2.02 v v lvd10 lvis1, lvis0 = 1, 0 falling interrupt voltage 1.90 1.94 1.98 v rising release reset voltage 2.05 2.09 2.13 v v lvd9 lvis1, lvis0 = 0, 1 falling interrupt voltage 2.00 2.04 2.08 v rising release reset voltage 3.07 3.13 3.19 v v lvd2 lvis1, lvis0 = 0, 0 falling interrupt voltage 3.00 3.06 3.12 v v lvd8 vpoc2, vpoc1, vpoc0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 v rising release reset voltage 2.56 2.61 2.66 v v lvd7 lvis1, lvis0 = 1, 0 falling interrupt voltage 2.50 2.55 2.60 v rising release reset voltage 2.66 2.71 2.76 v v lvd6 lvis1, lvis0 = 0, 1 falling interrupt voltage 2.60 2.65 2.70 v v lvd5 vpoc2, vpoc1, vpoc0 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 v rising release reset voltage 2.86 2.92 2.97 v v lvd4 lvis1, lvis0 = 1, 0 falling interrupt voltage 2.80 2.86 2.91 v rising release reset voltage 2.96 3.02 3.08 v interrupt & reset mode v lvd3 lvis1, lvis0 = 0, 1 falling interrupt voltage 2.90 2.96 3.02 v caution set the detection voltage (v lvd ) to be within the operating voltage range. the operating voltage range depends on the setting of the user option byte (000c2h/010c2h). the following shows the operating voltage range. hs (high-speed main) mode: v dd = 2.7 to 3.6 v@1 mhz to 32 mhz v dd = 2.4 to 3.6 v@1 mhz to 16 mhz ls (low-speed main) mode: v dd = 1.8 to 3.6 v@1 mhz to 8 mhz lv (low-voltage main) mode: v dd = 1.6 to 3.6 v@1 mhz to 4 mhz 2.6.5 supply voltage rise slope characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit supply voltage rise sv dd 54 v/ms caution be sure to maintain the internal reset state until v dd reaches the operating voltage range specified in 2.4 ac characteristics, by using the lvd circuit or external reset pin. rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 71 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 2.7 data memory stop mode low supply voltage data retention characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.46 note 3.6 v note the value depends on the por detec tion voltage. when the voltage dr ops, the data is retained before a por reset is effected, but data is not re tained when a por reset is effected. v dd stop instruction execution standby release signal (inerrupt request) stop mode data hold mode v dddr operation mode 2.8 flash memory programming characteristics (t a = ? 40 to +85 c, 1.8 v v dd 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit cpu/peripheral hardware clock frequency f clk 1.8 v v dd 3.6 v 1 32 mhz number of code flash rewrites notes 1, 2 retained for 20 years t a = 85 c note 3 1,000 retained for 1 years t a = 25 c note 3 1,000,000 retained for 5 years t a = 85 c note 3 100,000 number of data flash rewrites notes 1, 2 c erwr retained for 20 years t a = 85 c note 3 10,000 times notes 1. 1 erase + 1 write after the er ase is regarded as 1 rewrite. the retaining years are until ne xt rewrite after the rewrite. 2. when using flash memory programmer and renesas electronics self programming library 3. these are the characteristics of the flash memory and the results obtained from reliability testing by renesas electronics corporation. 2.9 dedicated flash memory programmer communication (uart) (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during flash memory programming 115.2 k 1 m bps rl78/g1a 2. electrical specifications (t a = ? 40 to +85 c) page 72 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 2.10 timing specs for switching flash memory programming modes (t a = ? 40 to +85 c, 1.8 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit how long from when an external reset ends until the initial communication settings are specified t suinit por and lvd reset must end before the external reset ends. 100 ms how long from when the tool0 pin is placed at the low level until a external reset ends t su por and lvd reset must end before the external reset ends. 10 s how long the tool0 pin must be kept at the low level after an external reset ends (except flash firmware processing time) t hd por and lvd reset must end before the external reset ends. 1 ms reset tool0 <1> <2> <3> t suinit 00h reception (toolrxd, tooltxd mode) t su <4> 723 s + t hd process time <1> the low level is input to the tool0 pin. <2> the pins reset ends (por and lvd reset must end before the external reset ends.). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programmi ng mode by uart reception and complete the baud rate setting. remark t suinit : the segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. t su : how long from when the tool0 pin is placed at the low level until a external reset ends t hd : how long to keep the tool0 pin at the low level from when the external resets end (except flash firmware processing time) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 73 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 3. electrical specifications (g: industrial applications t a = ? 40 to +105 c) this chapter describes the following electrical specifications. target products g: industrial applications t a = ? 40 to +105 c r5f10ebagna, r5f10ebcgna, r5f10ebdgna, r5f10ebegna r5f10egagfb, r5f10egcgfb, r5f10egdgfb, r5f10egegfb r5f10egagna, r5f10egcgna, r5f10egdgna, r5f10egegna r5f10elcgfb, r5f10eldgfb, r5f10elegfb cautions 1. the rl78/g1a has an on-chip debug functi on, which is provided for development and evaluation. do not use the on-chip debug f unction in products designated for mass production, because the guarant eed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. renesas electronics is not liabl e for problems occurri ng when the on-chip debug function is used. 2. with products not provided with an ev dd0 or ev ss0 pin, replace ev dd0 with v dd , or replace ev ss0 with v ss . 3. the pins mounted depend on the product. see 1.3.1 25-pin products to 1.3.4 64-pin products. 4. please contact renesas electronics sales office for derating of operation under t a = +85c to +105c. derating is the systematic reduction of load for the sake of improved reliability. remark when rl78/g1a is used in the range of t a = ? 40 to +85 c, see 2. electrical specifications (t a = ? 40 to +85c) . rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 74 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 3.1 absolute maximum ratings absolute maximum ratings (t a = 25 c) (1/2) parameter symbols conditions ratings unit v dd ? 0.5 to +6.5 v ev dd0 ? 0.5 to +6.5 v av dd ? 0.5 to +4.6 v av refp ? 0.3 to av dd +0.3 note 3 v ev ss0 ? 0.5 to +0.3 v av ss ? 0.5 to +0.3 v supply voltage av refm ? 0.3 to av dd +0.3 note 3 and av refm av refp v regc pin input voltage v iregc regc ? 0.3 to +2.8 and ? 0.3 to v dd +0.3 note 1 v v i1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p140, p141 ? 0.3 to ev dd0 +0.3 and ? 0.3 to v dd +0.3 note 2 v v i2 p60 to p63 (n-ch open-drain) ? 0.3 to +6.5 v v i3 p121 to p124, p137, exclk, exclks, reset ? 0.3 to v dd +0.3 note 2 v input voltage v i4 p20 to p27, p150 to p154 ? 0.3 to av dd +0.3 note 2 v v o1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p60 to p63, p70 to p77, p120, p130, p140, p141 ? 0.3 to ev dd0 +0.3 note 2 v output voltage v o2 p20 to p27, p150 to p154 ? 0.3 to av dd +0.3 note 2 v v ai1 ani16 to ani30 ? 0.3 to ev dd0 +0.3 and ? 0.3 to av ref(+) +0.3 notes 2, 4 v analog input voltage v ai2 ani0 to ani12 ? 0.3 to av dd +0.3 and ? 0.3 to av ref(+) +0.3 notes 2, 4 v notes 1. connect the regc pin to v ss via a capacitor (0.47 to 1 f). this value regulates the absolute maximum rating of the regc pin. do not use this pin with voltage applied to it. 2. must be 6.5 v or lower. 3. must be 4.6 v or lower. 4. do not exceed av ref(+) + 0.3 v in case of a/d conversion target pin. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum rati ngs are rated values at which the product is on the verge of suffering physical damage, and theref ore the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. remarks 1. unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins. 2. av ref(+) : + side reference voltage of the a/d converter. 3. v ss : reference voltage rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 75 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 absolute maximum ratings (t a = 25 c) (2/2) parameter symbols conditions ratings unit per pin p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 ? 40 ma p00 to p04, p40 to p43, p120, p130, p140, p141 ? 70 ma i oh1 total of all pins ? 170 ma p05, p06, p10 to p16, p30, p31, p50, p51, p70 to p77, ? 100 ma per pin ? 0.1 ma output current, high i oh2 total of all pins p20 to p27, p150 to p154 ? 1.3 ma per pin p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p60 to p63, p70 to p77, p120, p130, p140, p141 40 ma p00 to p04, p40 to p43, p120, p130, p140, p141 70 ma i ol1 total of all pins 170 ma p05, p06, p10 to p16, p30, p31, p50, p51, p60 to p63, p70 to p77 100 ma per pin 0.4 ma output current, low i ol2 total of all pins p20 to p27, p150 to p154 6.4 ma in normal operation mode operating ambient temperature t a in flash memory programming mode ? 40 to +105 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum rati ngs are rated values at which the product is on the verge of suffering physical damage, and theref ore the product must be used under conditions that ensure that the absolute maximum rati ngs are not exceeded. remark unless specified otherwise, the characteristics of alte rnate-function pins are the same as those of the port pins. rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 76 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 3.2 oscillator characteristics 3.2.1 x1, xt1 oscillator characteristics (t a = ? 40 to +105 c, 2.4 v v dd 3.6 v, v ss = 0 v) parameter resonator conditions min. typ. max. unit 2.7 v v dd 3.6 v 1.0 20.0 x1 clock oscillation frequency (f x ) note ceramic resonator/c rystal resonator 2.4 v v dd < 2.7 v 1.0 16.0 mhz xt1 clock oscillation frequency (f x ) note crystal resonator 32 32.768 35 khz note indicates only permissible oscillator frequency ranges. see ac characteristics for instruction execution time. request evaluation by the manufacturer of t he oscillator circuit mounted on a board to check the oscillator characteristics. caution since the cpu is started by the high-speed on-chip oscillator cl ock after a reset release, check the x1 clock oscillation stabilization time using th e oscillation stabilization time counter status register (ostc) by the user. de termine the oscillation stabilizat ion time of the ostc register and the oscillation stabilization time select register (osts) after sufficiently evaluating the oscillation stabilization time wit h the resonator to be used. 3.2.2 on-chip oscillator characteristics (t a = ? 40 to +105 c, 2.4 v v dd 3.6 v, v ss = 0 v) oscillators parameters conditions min. typ. max. unit high-speed on-chip oscillator oscillation frequency notes 1, 2 f ih 1 32 mhz +85 to +105 c 2.4 v v dd 3.6 v ? 2 +2 % ? 20 to +85 c 2.4 v v dd 3.6 v ? 1 +1 % high-speed on-chip oscillator oscillation frequency accuracy ? 40 to ? 20 c 2.4 v v dd 3.6 v ? 1.5 +1.5 % low-speed on-chip oscillator oscillation frequency f il 15 khz low-speed on-chip oscillator oscillation frequency accuracy ? 15 +15 % notes 1. high-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000c2h/010c2h) and bits 0 to 2 of hocodiv register. 2. this indicates the oscillator characteristics only. see ac characteristics for instruction execution time. rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 77 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 3.3 dc characteristics 3.3.1 pin characteristics (t a = ? 40 to +105 c, 2.4 v av dd v dd 3.6 v, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (1/5) items symbol conditions min. typ. max. unit per pin for p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 2.4 v ev dd0 3.6 v ? 3.0 note 2 ma 2.7 v ev dd0 3.6 v ? 10.0 ma total of p00 to p04, p40 to p43, p120, p130, p140, p141 (when duty 70% note 3 ) 2.4 v ev dd0 < 2.7 v ? 5.0 ma 2.7 v ev dd0 3.6 v ? 19.0 ma total of p05, p06, p10 to p16, p30, p31, p50, p51, p70 to p77, (when duty 70% note 3 ) 2.4 v ev dd0 < 2.7 v ? 10.0 ma i oh1 total of all pins (when duty 70% note 3 ) 2.4 v ev dd0 3.6 v ? 29.0 ma per pin for p20 to p27, p150 to p154 2.4 v av dd 3.6 v ? 0.1 note 2 ma output current, high note 1 i oh2 total of all pins (when duty 70% note 3 ) 2.4 v av dd 3.6 v ? 1.3 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from the ev dd0 , v dd pins to an output pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor 70%. the output current value that has changed to the dut y factor > 70% the duty ratio can be calculated with the following expression (when changi ng the duty factor from 70% to n%). ? total output current of pins = (i oh 0.7)/(n 0.01) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 78 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (t a = ? 40 to +105 c, 2.4 v av dd v dd 3.6 v, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (2/5) items symbol conditions min. typ. max. unit per pin for p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 8.5 note 2 ma per pin for p60 to p63 15.0 note 2 ma 2.7 v ev dd0 3.6 v 15.0 ma total of p00 to p04, p40 to p43, p120, p130, p140, p141 (when duty 70% note 3 ) 2.4 v ev dd0 < 2.7 v 9.0 ma 2.7 v ev dd0 3.6 v 35.0 ma total of p05, p06, p10 to p16, p30, p31, p50, p51, p60 to p63, p70 to p77 (when duty 70% note 3 ) 2.4 v ev dd0 < 2.7 v 20.0 ma i ol1 total of all pins (when duty 70% note 3 ) 50.0 ma per pin for p20 to p27, p150 to p154 0.4 note 2 ma output current, low note 1 i ol2 total of all pins (when duty 70% note 3 ) 2.4 v av dd 3.6 v 5.2 ma notes 1 . value of current at which the device operation is guaranteed even if the current flows from an output pin to the ev ss0 and v ss pin. 2. however, do not exceed the total current value. 3. specification under conditions where the duty factor 70%. the output current value that has changed to the dury factor > 70% the duty ratio can can be calculated with the following expression (when changing the duty factor from 70% to n%). ? total output current of pins = (i ol 0.7)/(n 0.01) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 79 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (t a = ? 40 to +105 c, 2.4 v av dd v dd 3.6 v, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (3/5) items symbol conditions min. typ. max. unit v ih1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p140, p141 normal input buffer 0.8ev dd0 ev dd0 v ttl input buffer 3.3 v ev dd0 3.6 v 2.0 ev dd0 v v ih2 p01, p03, p04, p10, p11, p13 to p16, p43 ttl input buffer 2.4 v ev dd0 < 3.3 v 1.5 ev dd0 v v ih3 p20 to p27, p150 to p154 0.7av dd av dd v v ih4 p60 to p63 0.7ev dd0 6.0 v input voltage, high v ih5 p121 to p124, p137, exclk, exclks, reset 0.8v dd v dd v v il1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p140, p141 normal input buffer 0 0.2ev dd0 v ttl input buffer 3.3 v ev dd0 3.6 v 0 0.5 v v il2 p01, p03, p04, p10, p11, p13 to p16, p43 ttl input buffer 2.4 v ev dd0 < 3.3 v 0 0.32 v v il3 p20 to p27, p150 to p154 0 0.3av dd v v il4 p60 to p63 0 0.3ev dd0 v input voltage, low v il5 p121 to p124, p137, exclk, exclks, reset 0 0.2v dd v caution the maximum value of v ih of pins p00, p02 to p04, p10 to p15, p43, p50, p71, and p74 is ev dd0 , even in the n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins. rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 80 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (t a = ? 40 to +105 c, 2.4 v av dd v dd 3.6 v, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (4/5) items symbol conditions min. typ. max. unit 2.7 v ev dd0 3.6 v, i oh1 = ? 2.0 ma ev dd0 ? 0.6 v v oh1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 2.4 v ev dd0 3.6 v, i oh1 = ? 1.5 ma ev dd0 ? 0.5 v output voltage, high v oh2 p20 to p27, p150 to p154 2.4 v av dd 3.6 v, i oh2 = ? 100 a av dd ? 0.5 v 2.7 v ev dd0 3.6 v, i ol1 = 3.0 ma 0.6 v 2.7 v ev dd0 3.6 v, i ol1 = 1.5 ma 0.4 v v ol1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p130, p140, p141 2.4 v ev dd0 3.6 v, i ol1 = 0.6 ma 0.4 v v ol2 p20 to p27, p150 to p154 2.4 v av dd 3.6 v, i ol2 = 400 a 0.4 v 2.7 v ev dd0 3.6 v, i ol3 = 3.0 ma 0.4 v output voltage, low v ol3 p60 to p63 2.4 v ev dd0 3.6 v, i ol3 = 2.0 ma 0.4 v caution p00, p02 to p04, p10 to p1 5, p43, p50, p71, and p74 do not ou tput high level in n-ch open-drain mode. remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins. rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 81 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (t a = ? 40 to +105 c, 2.4 v av dd v dd 3.6 v, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (5/5) items symbol conditions min. typ. max. unit i lih1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p60 to p63, p70 to p77, p120, p140, p141 v i = ev dd0 1 a i lih2 p137, reset v i = v dd 1 a in input port or external clock input 1 a i lih3 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v dd in resonator connection 10 a input leakage current, high i lih4 p20 to p27, p150 to p154 v i = av dd 1 a i lil1 p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p60 to p67, p70 to p77, p120, p140, p141 v i = ev ss0 ? 1 a i lil2 p137, reset v i = v ss ? 1 a in input port or external clock input ? 1 a i lil3 p121 to p124 (x1, x2, xt1, xt2, exclk, exclks) v i = v ss in resonator connection ? 10 a input leakage current, low i lil4 p20 to p27, p150 to p154 v i = av ss ? 1 a on-chip pull-up resistance r u p00 to p06, p10 to p16, p30, p31, p40 to p43, p50, p51, p70 to p77, p120, p140, p141 v i = ev ss0 , in input port 10 20 100 k remark unless specified otherwise, the charac teristics of alternate-function pi ns are the same as those of the port pins. rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 82 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 3.3.2 supply current characteristics (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (1/3) parameter symbol conditions min. typ. max. unit basic operation v dd = 3.0 v 2.1 ma f ih = 32 mhz note 3 normal operation v dd = 3.0 v 4.6 7.5 ma f ih = 24 mhz note 3 normal operation v dd = 3.0 v 3.7 5.8 ma hs (high-speed main) mode note 5 f ih = 16 mhz note 3 normal operation v dd = 3.0 v 2.7 4.2 ma square wave input 3.0 4.9 f mx = 20 mhz note 2 , v dd = 3.0 v normal operation resonator connection 3.2 5.0 ma square wave input 1.9 2.9 hs (high-speed main) mode note 5 f mx = 10 mhz note 2 , v dd = 3.0 v normal operation resonator connection 1.9 2.9 ma square wave input 4.1 4.9 f sub = 32.768 khz note 4 t a = ? 40 c normal operation resonator connection 4.2 5.0 a square wave input 4.2 4.9 f sub = 32.768 khz note 4 t a = +25 c normal operation resonator connection 4.3 5.0 a square wave input 4.3 5.5 f sub = 32.768 khz note 4 t a = +50 c normal operation resonator connection 4.4 5.6 a square wave input 4.5 6.3 f sub = 32.768 khz note 4 t a = +70 c normal operation resonator connection 4.6 6.4 a square wave input 4.8 7.7 f sub = 32.768 khz note 4 t a = +85 c normal operation resonator connection 4.9 7.8 a square wave input 6.9 19.7 supply current i dd1 note 1 operating mode subsystem clock mode f sub = 32.768 khz note 4 t a = +105 c normal operation resonator connection 7.0 19.8 a ( notes and remarks are listed on the next page.) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 83 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 notes 1. total current flowing into v dd and ev dd0 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 or v ss , ev ss0 . the values below the max. column include the peripheral operation current. however, not includin g the current flowing into the a/d converter, lvd circuit, i/o port, on-chip pull-up/pull-down resistors, and data flash rewriting. 2. when high-speed on-chip oscillator and subsystem clock are stopped. 3. when high-speed system clock and s ubsystem clock are stopped. 4. when high-speed on-chip oscillator and high-speed syst em clock are stopped. when setting ultra-low power consumption oscillation (amphs1 = 1). not in cluding the current flowing into the rtc, 12-bit interval timer and watchdog timer 5. relationship between operation voltage width, oper ation frequency of cpu and operation mode is as below. hs (high-speed main) mode: v dd = 2.7 v to 3.6 v@1 mhz to 32 mhz v dd = 2.4 v to 3.6 v@1 mhz to 16 mhz remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation, temper ature condition of t he typ. value is t a = 25 c rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 84 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (2/3) parameter symbol conditions min. typ. max. unit f ih = 32 mhz note 4 v dd = 3.0 v 0.54 2.90 ma f ih = 24 mhz note 4 v dd = 3.0 v 0.44 2.30 ma hs (high-speed main) mode note 7 f ih = 16 mhz note 4 v dd = 3.0 v 0.40 1.70 ma square wave input 0.28 1.90 f mx = 20 mhz note 3 , v dd = 3.0 v resonator connection 0.45 2.00 ma square wave input 0.19 1.02 hs (high-speed main) mode note 7 f mx = 10 mhz note 3 , v dd = 3.0 v resonator connection 0.26 1.10 ma square wave input 0.25 0.57 f sub = 32.768 khz note 5 t a = ? 40 c resonator connection 0.44 0.76 a square wave input 0.30 0.57 f sub = 32.768 khz note 5 t a = +25 c resonator connection 0.49 0.76 a square wave input 0.38 1.17 f sub = 32.768 khz note 5 t a = +50 c resonator connection 0.57 1.36 a square wave input 0.52 1.97 f sub = 32.768 khz note 5 t a = +70 c resonator connection 0.71 2.16 a square wave input 0.97 3.37 f sub = 32.768 khz note 5 t a = +85 c resonator connection 1.16 3.56 a square wave input 3.01 15.37 i dd2 note 2 halt mode subsystem clock mode f sub = 32.768 khz note 5 t a = +105 c resonator connection 3.20 15.56 a t a = ? 40 c 0.16 0.50 t a = +25 c 0.23 0.50 t a = +50 c 0.34 1.10 t a = +70 c 0.46 1.90 t a = +85 c 0.75 3.30 supply current note 1 i dd3 note 6 stop mode note 8 t a = +105 c 2.94 15.30 a ( notes and remarks are listed on the next page.) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 85 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 notes 1. total current flowing into v dd and ev dd0 , including the input leakage current flowing when the level of the input pin is fixed to v dd , ev dd0 or v ss , ev ss0 . the values below the max. column include the peripheral operation current. however, not includin g the current flowing into the a/d converter, lvd circuit, i/o port, on-chip pull-up/pull-down resistors, and data flash rewriting. 2. during halt instruction execution by flash memory. 3. when high-speed on-chip oscillator and subsystem clock are stopped. 4. when high-speed system clock and subsystem clock are stopped. 5. when high-speed on-chip oscillator and high-speed system clock are stopped. when rtclpc = 1 and setting ultra-low current consumption (amphs1 = 1). including the current flowing into the rtc. however, not including the current flowing into the 12-bit interval timer, and watchdog timer. 6. when subsystem clock is stopped. not including the cu rrent flowing into the rtc, 12-bit interval timer, watchdog timer. 7. relationship between operation voltage width, oper ation frequency of cpu and operation mode is as below. hs (high-speed main) mode: 2.7 v v dd 3.6 v@1 mhz to 32 mhz 2.4 v v dd 3.6 v@1 mhz to 16 mhz 8. regarding the value for current to operate the subsyst em clock in stop mode, refer to that in halt mode. remarks 1. f mx : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f ih : high-speed on-chip oscillator clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 4. except subsystem clock operation and stop mode, temperature condition of the typ. value is t a = 25 c rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 86 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) (3/3) parameter symbol conditions min. typ. max. unit low-speed on-chip oscillator operating current i fil note 1 0.20 a rtc operating current i rtc notes 1, 2, 3 0.02 a 12-bit interval timer operating current i it notes 1, 2, 4 0.02 a watchdog timer operating current i wdt notes 1, 2, 5 f il = 15 khz 0.22 a a/d converter operating current i adc notes 6, 7 av dd = 3.0 v, when conversion at maximum speed 420 720 a av dd = 3.0 v, adrefp1 = 0, adrefp0 = 0 note 7 14.0 25.0 a av refp = 3.0 v, adrefp1 = 0, adrefp0 = 1 note 10 14.0 25.0 a av ref(+) current i avref note 8 adrefp1 = 1, adrefp0 = 0 note 1 14.0 25.0 a a/d converter reference voltage current i adref notes 1, 9 v dd = 3.0 v 75.0 a temperature sensor operating current i tmps note 1 v dd = 3.0 v 75.0 a lvd operating current i lvd notes 1, 11 0.08 a bgo operating current i bgo notes 1, 12 2.5 12.2 ma self-programming operating current i fsp notes 1, 13 2.5 12.2 ma the mode is performed notes 1 0.50 1.10 ma during a/d conversion note 1 0.60 1.34 ma a/d converter operation (av dd = 3.0 v) during a/d conversion note 7 420 720 a snooze operating current i snoz csi/uart operation note 1 0.70 1.54 ma ( notes and remarks are listed on the next page.) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 87 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 notes 1. current flowing to v dd . 2. when high-speed on-chip oscillator and high-speed system clock are stopped. 3. current flowing only to the real-time clock (rtc) (excluding the operating current of the low-speed on-chip ocsillator and the xt1 oscillator). the supply current of the rl78 microc ontrollers is the sum of the values of either i dd1 or i dd2 , and i rtc , when the real-time clock operates in operation mode or halt mode. when the low-speed on-ch ip oscillator is selected, i fil should be added. i dd2 subsystem clock operation includes the operational current of the real-time clock. 4. current flowing only to the 12-bit interval timer (e xcluding the operating current of the low-speed on-chip ocsillator and the xt1 oscillator). the supply current of the rl78 mi crocontrollers is the sum of the values of either i dd1 or i dd2 , and i it , when the 12-bit interval timer operates in operation mode or halt mode. when the low-speed on-chip oscillator is selected, i fil should be added. 5. current flowing only to the watchdog timer (inclu ding the operating current of the low-speed on-chip oscillator). the supply current of t he rl78 microcontrollers is the sum of i dd1 , i dd2 , or i dd3 and i wdt when the watchdog timer is in operation. 6. current flowing only to the a/d conv erter. the supply current of the rl78 microcontrollers is the sum of i dd1 or i dd2 and i adc , i avref , i adref when the a/d converter operates in an operation mode or the halt mode. 7. current flowing to the av dd . 8. current flowing from the referenc e voltage source of a/d converter. 9. operation current flowing to the internal reference voltage. 10. current flowing to the av refp . 11. current flowing only to the lvd circuit. the supply current of the rl78 microcontrollers is the sum of i dd1 , i dd2 or i dd3 and i lvd when the lvd circuit is in operation. 12. current flowing only during data flash rewrite. 13. current flowing only during self programming. remarks 1. f il : low-speed on-chip oscillator clock frequency 2. f sub : subsystem clock frequency (xt1 clock oscillation frequency) 3. f clk : cpu/peripheral hardware clock frequency 4. temperature condition of the typ. value is t a = 25 c rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 88 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 3.4 ac characteristics (t a = ? 40 to +105 c, av dd v dd 3.6 v, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) items symbol conditions min. typ. max. unit 2.7 v v dd 3.6 v 0.03125 1 s main system clock (f main ) operation hs (high-speed main) mode 2.4 v v dd < 2.7 v 0.0625 1 s subsystem clock (f sub ) operation 2.4 v v dd 3.6 v 28.5 30.5 31.3 s 2.7 v v dd 3.6 v 0.03125 1 s instruction cycle (minimum instruction execution time) t cy in the self programming mode hs (high-speed main) mode 2.4 v v dd < 2.7 v 0.0625 1 s 2.7 v v dd 3.6 v 1.0 20.0 mhz f ex 2.4 v v dd < 2.7 v 1.0 16.0 mhz external system clock frequency f exs 32 35 khz 2.7 v v dd 3.6 v 24 ns t exh , t exl 2.4 v v dd < 2.7 v 30 ns external system clock input high-level width, low-level width t exhs , t exls 13.7 s ti00, ti01, ti03 to ti07 input high-level width, low-level width t tih , t til 1/f mck +10 ns note 2.7 v ev dd0 3.6 v 8 mhz to00, to01, to03 to to07 output frequency f to hs (high-speed main) mode 2.4 v ev dd0 < 2.7 v 4 mhz 2.7 v ev dd0 3.6 v 8 mhz pclbuz0, pclbuz1 output frequency f pcl hs (high-speed main) mode 2.4 v ev dd0 < 2.7 v 4 mhz intp0 2.4 v v dd 3.6 v 1 s interrupt input high-level width, low-level width t inth , t intl intp1 to intp11 2.4 v ev dd0 3.6 v 1 s key interrupt input high-level width, low-level width t kr kr0 to kr9 2.4 v ev dd0 3.6 v, 2.4 v av dd0 3.6 v 250 ns reset low-level width t rsl 10 s note the following conditions are required for low-voltage interface when ev dd0 < v dd . 2.4 v ev dd0 < 2.7 v : min. 125 ns remark f mck : timer array unit operation clock frequency (operation clock to be set by the cks0n bit of ti mer clock select register 0 (tps0) and timer mode register 0n (tmr0n). n: channel number (n = 0 to 7)) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 89 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 minimum instruction execution time dur ing main system clock operation t cy vs v dd (hs (high-speed main) mode) 1.0 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 3.6 2.7 0.01 2.4 0.03125 0.0625 0.05 cycle time t cy [ s] supply voltage v dd [v] when the high-speed on-chip oscillator clock is selected during self programming when high-speed system clock is selected rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 90 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 ac timing test points v ih /v oh v il /v ol test points v ih /v oh v il /v ol external system clock timing exclk 0.7 v dd min. 0.3 v dd max. 1/f ex t exl t exh ti/to timing ti00, ti01, ti03 to ti07 t til t tih to00, to01, to03 to to07 1/f to interrupt request input timing intp0 to intp11 t intl t inth key interrupt input timing kr0 to kr9 t kr reset input timing reset t rsl rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 91 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 3.5 peripheral functions characteristics ac timing test points v ih /v oh v il /v ol test points v ih /v oh v il /v ol 3.5.1 serial array unit (1) during communication at same potential (uart mode) (dedicat ed baud rate ge nerator output) (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit f mck /12 bps transfer rate note 1 theoretical value of the maximum transfer rate f clk = 32 mhz, f mck = f clk 2.6 note 2 mbps notes 1. transfer rate in the snooze mode is 4800 bps. 2. the following conditions are required for low-voltage interface when ev dd0 < v dd . 2.4 v ev dd0 < 2.7 v : max. 1.3 mbps caution select the normal input buffer for the rxdq pi n and the normal output mode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). uart mode connection diagram (duri ng communication at same potential) rl78 microcontroller txdq rxdq rx tx user device uart mode bit width (dur ing communication at same potential) (reference) baud rate error tolerance high-/low-bit width 1/transfer rate txdq rxdq remarks 1. q: uart number (q = 0 to 2), g: pim and pom number (g = 0, 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10, 11)) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 92 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (2) during communication at same pot ential (csi mode) (master mode, sckp... internal clock output) (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpm n = 1. the sip setup time or sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. c is the load capacitance of the sckp and sop output lines. caution select the normal input buffer for the sip pin and the normal output mode for the sop pin and sckp pin by using port input mode register g (pimg) and port ou tput mode register g (pomg). remark p: csi number (p = 00, 01, 10, 11, 20, 21), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim and pom numbers (g = 0, 1) parameter symbol conditions min. typ. max. unit 2.7 v ev dd0 3.6 v t kcy1 4/f clk 250 ns sckp cycle time t kcy1 2.4 v ev dd0 3.6 v t kcy1 4/f clk 500 ns 2.7 v ev dd0 3.6 v t kcy1 /2 ? 36 ns sckp high-/low-level width t kh1 , t kl1 2.4 v ev dd0 3.6 v t kcy1 /2 ? 76 ns 2.7 v ev dd0 3.6 v 66 ns sip setup time (to sckp ) note 1 t sik1 2.4 v ev dd0 3.6 v 113 ns sip hold time (from sckp ) note 1 t ksi1 38 ns delay time from sckp to sop output note 2 t kso1 c = 30 p note 3 50 ns rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 93 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (3) during communication at same potential (csi mode) (slave m ode, sckp... external clock input) (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit 16 mhz < f mck 16/f mck ns 2.7 v ev dd0 3.6 v f mck 16 mhz 12/f mck ns sckp cycle time note 1 t kcy2 2.4 v ev dd0 3.6 v 12/f mck and 1000 ns 2.7 v ev dd0 3.6 v t kcy2 /2 ? 14 ns sckp high-/low-level width t kh2 , t kl2 2.4 v ev dd0 3.6 v t kcy2 /2 ? 16 ns 2.7 v ev dd0 3.6 v 1/f mck + 40 ns sip setup time (to sckp ) note 2 t sik2 2.4 v ev dd0 3.6 v 1/f mck + 60 ns 2.7 v ev dd0 3.6 v 1/f mck +62 ns sip hold time (from sckp ) note 2 t ksi2 2.4 v ev dd0 3.6 v 1/f mck +62 ns 2.7 v ev dd0 3.6 v 2/f mck +66 ns delay time from sckp to sop output note 3 t kso2 c = 30 pf note 4 2.4 v ev dd0 3.6 v 2/f mck +113 ns notes 1. transfer rate in the snooze mode : max. 1 mbps 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpm n = 1. the sip setup time or sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 4. c is the load capacitance of the sop output lines. caution select the normal input buffer for the sip pi n and sckp pin and the normal output mode for the sop pin by using port input mode register g (pimg) and port out put mode register g (pomg). remarks 1. p: csi number (p = 00, 01, 10, 11, 20, 21), m: unit number (m = 0, 1), n: channel number (n = 0 to 3), g: pim number (g = 0, 1) 2. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10, 11)) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 94 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 csi mode connection diagram (duri ng communication at same potential) rl78 microcontroller sckp sop sck si user device sip so csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip sop t kcy1, 2 t kl1, 2 t kh1, 2 t sik1, 2 t ksi1, 2 input data t kso1, 2 output data sckp csi mode serial transfer timing (during communication at same potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip sop t kcy1, 2 t kh1, 2 t kl1, 2 t sik1, 2 t ksi1, 2 input data t kso1, 2 output data sckp remarks 1. p: csi number (p = 00, 01, 10, 11, 20, 21) 2. m: unit number, n: channel nu mber (mn = 00 to 03, 10, 11) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 95 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (4) during communication at sam e potential (simplified i 2 c mode) (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. max. unit 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 400 note 1 khz sclr clock frequency f scl 2.4 v ev dd0 3.6 v, c b = 100 pf, r b = 3 k 100 note 1 khz 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 1200 ns hold time when sclr = ?l? t low 2.4 v ev dd0 3.6 v, c b = 100 pf, r b = 3 k 4600 ns 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 1200 ns hold time when sclr = ?h? t high 2.4 v ev dd0 3.6 v, c b = 100 pf, r b = 3 k 4600 ns 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 1/f mck + 220 note 2 ns data setup time (reception) t su:dat 2.4 v ev dd 3.6 v, c b = 100 pf, r b = 3 k 1/f mck + 580 note 2 ns 2.7 v ev dd0 3.6 v, c b = 50 pf, r b = 2.7 k 0 770 ns data hold time (transmission) t hd:dat 2.4 v ev dd0 3.6 v, c b = 100 pf, r b = 3 k 0 1420 ns notes 1. the value must also be f clk /4 or lower. 2. set the f mck value to keep the hold time of sclr = ?l? and sclr = ?h?. caution select the normal input buffe r and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) mode for the sdar pin and the normal output mode for the sclr pin by using por t input mode register g (pimg) and port output mode register h (pomh). rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 96 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 simplified i 2 c mode mode connection diagram (dur ing communication at same potential) rl78 microcontroller sdar sclr sda scl user device v dd r b simplified i 2 c mode serial transfer timing (dur ing communication at same potential) sdar t low t high t hd : dat sclr t su : dat 1/f scl remarks 1. r b [ ]: communication line (sdar) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance 2. r: iic number (r = 00, 01, 10, 11, 20, 21), g: pim number (g = 0, 1), h: pom number (h = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number, mn = 00 to 03, 10, 11) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 97 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (5) communication at different potential (1.8 v, 2.5 v) (uart mode) (dedicated baud rate generator output) (1/2) (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit f mck /12 bps 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v theoretical value of the maximum transfer rate f clk = 32 mhz, f mck = f clk 2.6 mbps f mck /12 bps transfer rate note 1 reception 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v theoretical value of the maximum transfer rate f clk = 32 mhz, f mck = f clk 2.6 note 2 mbps notes 1. transfer rate in the snooze mode is 4800 bps. 2. the following conditions are required for low-voltage interface when ev dd0 < v dd . 2.4 v ev dd0 < 2.7 v : max. 1.3 mbps caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) m ode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remarks 1. v b [v]: communication line voltage 2. q: uart number (q = 0 to 2), g: pim and pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of seri al mode register mn (smrmn). m: unit number, n: channel number (mn = 00 to 03, 10, 11) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 98 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (5) communication at different potential (1.8 v, 2.5 v) (uart mode) (dedicated baud rate generator output) (2/2) (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit note 1 bps 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 2.7 k , v b = 2.3 v 1.2 note 2 mbps note 3 bps transfer rate transmission 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v theoretical value of the maximum transfer rate c b = 50 pf, r b = 5.5 k , v b = 1.6 v 0.43 note 4 mbps notes 1. the smaller maximum transfer rate derived by using f mck /12 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.7 v ev dd0 3.6 v and 2.3 v v b 2.7 v 1 maximum transfer rate = { ? c b r b ln (1 ? 2.0 v b )} 3 [bps] 1 transfer rate 2 ? { ? c b r b ln (1 ? 2.0 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relati ve difference between the transmission and reception sides. 2. this value as an example is calculated when the c onditions described in the ?conditions? column are met. see note 1 above to calculate the maximum transfer rate under conditions of the customer. 3. the smaller maximum transfer rate derived by using f mck /12 or the following expression is the valid maximum transfer rate. expression for calculating the transfer rate when 2.4 v ev dd0 < 3.3 v and 1.6 v v b 2.0 v 1 maximum transfer rate = [bps] { ? c b r b ln (1 ? 1.5 v b )} 3 1 transfer rate 2 ? { ? c b r b ln (1 ? 1.5 v b )} baud rate error (theoretical value) = 100 [%] ( 1 transfer rate ) number of transferred bits * this value is the theoretical value of the relati ve difference between the transmission and reception sides. 4. this value as an example is calculated when the c onditions described in the ?conditions? column are met. see note 3 above to calculate the maximum transfer rate under conditions of the customer. caution select the ttl input buffer for the rxdq pin and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) m ode for the txdq pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 99 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 uart mode connection diagram (during communication at different potential) rl78 microcontroller txdq rxdq rx tx user device v b r b uart mode bit width (during communication at different potential) (reference) baud rate error tolerance high-/low-bit width 1/transfer rate baud rate error tolerance high-bit width low-bit width 1/transfer rate txdq rxdq remarks 1. r b [ ]: communication line (txdq) pull-up resistance, c b [f]: communication line (txdq) load capacitance, v b [v]: communication line voltage 2. q: uart number (q = 0 to 2), g: pim and pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel nu mber (mn = 00 to 03, 10, 11)) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 100 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (6) communication at different potential (1.8 v, 2.5 v) (csi mode) (master mode, sckp... internal clock output) (1/2) (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 4/f clk 1000 ns sckp cycle time t kcy1 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 4/f clk 2300 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 340 ns sckp high-level width t kh1 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 /2 ? 916 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k t kcy1 /2 ? 36 ns sckp low-level width t kl1 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k t kcy1 /2 ? 100 ns caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) mode for the sop pin and sckp pin by using port input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. remarks 1. r b [ ]: communication line (sckp, sop) pull-up resistance, c b [f]: communication line (sckp, sop) load capacitance, v b [v]: communication line voltage 2. p: csi number (p = 00, 10, 20), m: unit number , n: channel number (mn = 00, 02, 10), g: pim and pom number (g = 0, 1) 3. csi01, csi11, and csi21 cannot communicate at different potential. use other csi for communication at different potential. rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 101 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (6) communication at different potential (1.8 v, 2.5 v) (csi mode) (master mode, sckp... internal clock output) (2/2) (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 354 ns sip setup time (to sckp ) note 1 t sik1 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 958 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 38 ns sip hold time (from sckp ) note 1 t ksi1 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 38 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 390 ns delay time from sckp to sop output note 1 t kso1 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 966 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 88 ns sip setup time (to sckp ) note 2 t sik1 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 220 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 38 ns sip hold time (from sckp ) note 2 t ksi1 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 38 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 50 ns delay time from sckp to sop output note 2 t kso1 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 50 ns notes 1. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. 2. when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pin and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) mode for the sop pin and sckp pin by using port input mode regi ster g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. csi mode connection diagram (during communication at different potential) v b r b sckp sop sck si user device sip so v b r b rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 102 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip sop t kcy1 t kl1 t kh1 t sik1 t ksi1 input data t kso1 output data sckp csi mode serial transfer timing (master mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip sop t kcy1 t kl1 t kh1 t sik1 t ksi1 input data t kso1 output data sckp remarks 1. p: csi number (p = 00, 10, 20), m: unit number, n: channel number (m = 00, 02, 10), g: pim and pom number (g = 0, 1) 2. csi01, csi11, and csi21 cannot communicate at different potential. use other csi for communication at different potential. rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 103 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (7) communication at different potential (1.8 v, 2.5 v) (csi mode) (slave mode, s ckp... external clock input) (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit 24 mhz < f mck 40/f mck ns 20 mhz < f mck 24 mhz 32/f mck ns 16 mhz < f mck 20 mhz 28/f mck ns 8 mhz < f mck 16 mhz 24/f mck ns 4 mhz < f mck 8 mhz 16/f mck ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v f mck 4 mhz 12/f mck ns 24 mhz < f mck 96/f mck ns 20 mhz < f mck 24 mhz 72/f mck ns 16 mhz < f mck 20 mhz 64/f mck ns 8 mhz < f mck 16 mhz 52/f mck ns 4 mhz < f mck 8 mhz 32/f mck ns sckp cycle time note 1 t kcy2 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v f mck 4 mhz 20/f mck ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v t kcy2 /2 ? 36 ns sckp high-/low-level width t kh2 , t kl2 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v t kcy2 /2 ? 100 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v 1/f mck + 40 sip setup time (to sckp ) note 2 t sik2 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v 1/f mck + 60 ns sip hold time (from sckp ) note 2 t ksi2 1/f mck + 62 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 30 pf, r b = 2.7 k 2/f mck + 428 ns delay time from sckp to sop output note 3 t kso2 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 30 pf, r b = 5.5 k 2/f mck + 1146 ns notes 1. transfer rate in the snooze mode : max. 1 mbps 2. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpm n = 1. the sip setup time or sip hold time becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. 3. when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1. the delay time to sop output becomes ?from sckp ? when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0. caution select the ttl input buffer for the sip pi n and sckp pin and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) mode for the sop pin by using port input mode re gister g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics with ttl input buffer selected. ( remarks are listed on the next page.) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 104 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 csi mode connection diagram (during communication at different potential) rl78 microcontroller sckp sop sck si user device sip so v b r b rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 105 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 csi mode serial transfer timi ng (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 0, or dapmn = 1 and ckpmn = 1.) sip sop t kcy2 t kl2 t kh2 t sik2 t ksi2 input data t kso2 output data sckp csi mode serial transfer timi ng (slave mode) (during communication at different potential) (when dapmn = 0 and ckpmn = 1, or dapmn = 1 and ckpmn = 0.) sip sop t kcy2 t kl2 t kh2 t sik2 t ksi2 input data t kso2 output data sckp remarks 1. p: csi number (p = 00, 10, 20), m: unit number, n: channel number (mn = 00, 02, 10), g: pim and pom number (g = 0, 1) 2. csi01, csi11, and csi21 cannot communicate at different potential. use other csi for communication at different potential. rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 106 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (8) communication at different potent ial (1.8 v, 2.5 v) (simplified i 2 c mode) (1/2) (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. max. unit 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 400 note 1 khz 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 100 note 1 khz sclr clock frequency f scl 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 100 note 1 khz 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 1200 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 4600 ns hold time when sclr = ?l? t low 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 4650 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 500 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 2400 ns hold time when sclr = ?h? t high 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 1830 ns ( notes , caution and remarks are listed on the next page.) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 107 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (8) communication at different potent ial (1.8 v, 2.5 v) (simplified i 2 c mode) (2/2) (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. max. unit 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 1/f mck + 340 note 2 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 1/f mck + 760 note 2 ns data setup time (reception) t su:dat 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 1/f mck + 570 note 2 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 50 pf, r b = 2.7 k 0 770 ns 2.7 v ev dd0 3.6 v, 2.3 v v b 2.7 v, c b = 100 pf, r b = 2.7 k 0 1420 ns data hold time (transmission) t hd:dat 2.4 v ev dd0 < 3.3 v, 1.6 v v b 2.0 v, c b = 100 pf, r b = 5.5 k 0 1215 ns notes 1. the value must also be f clk /4 or lower. 2. set the f mck value to keep the hold time of sclr = ?l? and sclr = ?h?. caution select the ttl input buffer and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) mode fo r the sdar pin and the n-ch open drain output (v dd tolerance (when 25- to 48-pin products)/ev dd tolerance (when 64-pin products)) mode for the sclr pin by using po rt input mode register g (pimg) and port output mode register g (pomg). for v ih and v il , see the dc characteristics wit h ttl input buffer selected. ( remarks are listed on the next page.) rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 108 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 simplified i 2 c mode connection diagram (during communication at different potential) sdar sclr sda scl user device v b r b v b r b rl78 microcontroller simplified i 2 c mode serial transfer timing (during co mmunication at different potential) sdar t low t high t hd : dat sclr t su : dat 1/f scl remarks 1. r b [ ]: communication line (sdar, sclr) pull-up resistance, c b [f]: communication line (sdar, sclr) load capacitance, v b [v]: communication line voltage 2. r: iic number (r = 00, 10, 20), g: pim, pom number (g = 0, 1) 3. f mck : serial array unit operation clock frequency (operation clock to be set by the cksmn bit of serial mode register mn (smrmn). m: unit number, n: channel number (mn = 00, 02, 10) 4. iic01, iic11, and iic21 cannot communicate at di fferent potential. use iic00, iic10, or iic20 for communication at different potential. rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 109 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 3.5.2 serial interface iica (1) i 2 c standard mode, fast mode (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) standard mode fast mode parameter symbol conditions min. max. min. max. unit fast mode: f clk 3.5 mhz 2.4 v ev dd0 3.6 v 0 400 khz scla0 clock frequency f scl normal mode: f clk 1 mhz 2.4 v ev dd0 3.6 v 0 100 khz setup time of restart condition t su:sta 4.7 0.6 s hold time note 1 t hd:sta 4.0 0.6 s hold time when scla0 = ?l? t low 4.7 1.3 s hold time when scla0 = ?h? t high 4.0 0.6 s data setup time (reception) t su:dat 250 100 ns data hold time (transmission) note 2 t hd:dat 0 3.45 0 0.9 s setup time of stop condition t su:sto 4.0 0.6 s bus-free time t buf 4.7 1.3 s notes 1. the first clock pulse is generated after this peri od when the start/restart condition is detected. 2. the maximum value (max.) of t hd:dat is during normal transfer and a wait state is inserted in the ack (acknowledge) timing. remark the maximum value of c b (communication line capacitance) and the value of r b (communication line pull-up resistor) at that time in each mode are as follows. standard mode: c b = 400 pf, r b = 2.7 k fast mode: c b = 320 pf, r b = 1.1 k iica serial transfer timing t low t high t hd : sta t buf stop condition start condition restart condition stop condition t su : dat t su : sta t su : sto t hd : sta t hd : dat scl0 sda0 rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 110 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 3.6 analog characteristics 3.6.1 a/d converter characteristics division of a/d converter characteristics reference voltag input channel reference voltage (+) = av refp reference voltage ( ? ) = av refm reference voltage (+) = av dd reference voltage ( ? ) = av ss reference voltage (+) = internal refrence voltage reference voltage ( ? ) = av ss high-accuracy channel; ani0 to ani12 (input buffer power supply: av dd ) see 3.6.1 (1) see 3.6.1 (2) standard channel; ani16 to ani30 (input buffer power supply: v dd or ev dd0 ) see 3.6.1 (3) see 3.6.1 (4) see 3.6.1 (5) temperature sensor, internal reference voltage output see 3.6.1 (3) see 3.6.1 (4) ? (1) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target for conversion: ani2 to ani12 (t a = ? 40 to +105 c, 2.4 v av refp av dd v dd 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 2.4 v av refp av dd 3.6 v 8. 12. bit overall error note ainl 12-bit resolution 2.4 v av refp av dd 3.6 v 6.0 lsb conversion time t conv adtyp = 0, 12-bit resolution 2.4 v av refp av dd 3.6 v 3.375 s zero-scale error note e zs 12-bit resolution 2.4 v av refp av dd 3.6 v 4.5 lsb full-scale error note e fs 12-bit resolution 2.4 v av refp av dd 3.6 v 4.5 lsb integral linearity error note ile 12-bit resolution 2.4 v av refp av dd 3.6 v 2.0 lsb differential linearity error note dle 12-bit resolution 2.4 v av refp av dd 3.6 v 1.5 lsb analog input voltage v ain 0 av refp v note excludes quantization error ( 1/2 lsb). rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 111 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (2) when reference voltage (+) = av dd (adrefp1 = 0, adrefp0 = 0), reference voltage ( ? ) = av ss (adrefm = 0), target for conversion: ani0 to ani12 (t a = ? 40 to +105 c, 2.4 v av dd v dd 3.6 v, v ss = 0 v, av ss = 0 v, reference voltage (+) = av dd , reference voltage ( ? ) = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 2.4 v av dd 3.6 v 8 12 bit overall error note ainl 12-bit resolution 2.4 v av dd 3.6 v 7.5 lsb conversion time t conv adtyp = 0, 12-bit resolution 2.4 v av dd 3.6 v 3.375 s zero-scale error note e zs 12-bit resolution 2.4 v av dd 3.6 v 6.0 lsb full-scale error note e fs 12-bit resolution 2.4 v av dd 3.6 v 6.0 lsb integral linearity error note ile 12-bit resolution 2.4 v av dd 3.6 v 3.0 lsb differential linearity error note dle 12-bit resolution 2.4 v av dd 3.6 v 2.0 lsb analog input voltage v ain 0 av dd v note excludes quantization error ( 1/2 lsb). rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 112 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (3) when reference voltage (+) = av refp /ani0 (adrefp1 = 0, adrefp0 = 1), reference voltage ( ? ) = av refm /ani1 (adrefm = 1), target for conversion: ani 16 to ani30, interanal reference voltage, temperature sensor output voltage (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, 2.4 v av refp av dd v dd 3.6 v, v ss = ev ss0 = 0 v, av ss = 0 v, reference voltage (+) = av refp , reference voltage ( ? ) = av refm = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 2.4 v av refp av dd 3.6 v 8 12 bit overall error note 1 ainl 12-bit resolution 2.4 v av refp av dd 3.6 v 7.0 lsb conversion time t conv adtyp = 0, 12-bit resolution 2.4 v av refp av dd 3.6 v 4.125 s zero-scale error note 1 e zs 12-bit resolution 2.4 v av refp av dd 3.6 v 5.0 lsb full-scale error note 1 e fs 12-bit resolution 2.4 v av refp av dd 3.6 v 5.0 lsb integral linearity error note 1 ile 12-bit resolution 2.4 v av refp av dd 3.6 v 3.0 lsb differential linearity error note 1 dle 12-bit resolution 2.4 v av refp av dd 3.6 v 2.0 lsb 0. av refp and ev dd0 v interanal reference voltage (2.4 v v dd 3.6 v, hs (high-speed main) mode) v bgr note 2 v analog input voltage v ain temperature sensor output voltage (2.4 v v dd 3.6 v, hs (high-speed main) mode) v tmps25 note 2 v notes 1. excludes quantization error ( 1/2 lsb). 2. see 3.6.2 temperature sensor, internal re ference voltage output characteristics . rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 113 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (4) when reference voltage (+) = av dd (adrefp1 = 0, adrefp0 = 0), reference voltage ( ? ) = av ss (adrefm = 0), target for conversion: ani16 to ani30, interanal reference voltage, temperature sensor output voltage (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd0 3.6 v, 2.4 v av dd v dd 3.6 v, v ss = ev ss0 = 0 v, av ss = 0 v, reference voltage (+) = av dd , reference voltage ( ? ) = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 2.4 v av dd 3.6 v 8 12 bit overall error note 1 ainl 12-bit resolution 2.4 v av dd 3.6 v 8.5 lsb conversion time t conv adtyp = 0, 12-bit resolution 2.4 v av dd 3.6 v 4.125 s zero-scale error note 1 e zs 12-bit resolution 2.4 v av dd 3.6 v 8.0 lsb full-scale error note 1 e fs 12-bit resolution 2.4 v av dd 3.6 v 8.0 lsb integral linearity error note 1 ile 12-bit resolution 2.4 v av dd 3.6 v 3.5 lsb differential linearity error note 1 dle 12-bit resolution 2.4 v av dd 3.6 v 2.5 lsb 0 av dd and ev dd0 v interanal reference voltage (2.4 v v dd 3.6 v, hs (high-speed main) mode) v bgr note 2 v analog input voltage v ain temperature sensor output voltage (2.4 v v dd 3.6 v, hs (high-speed main) mode) v tmps25 note 2 v notes 1. excludes quantization error ( 1/2 lsb). 2. see 3.6.2 temperature sensor, internal re ference voltage output characteristics . rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 114 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 (5) when reference voltage (+) = inte rnal reference voltage (1.45 v) (adrefp1 = 1, adrefp0 = 0), reference voltage ( ? ) = av ss (adrefm = 0), target for conver sion: ani0 to ani 12, ani16 to ani30 (t a = ? 40 to +105 c, 2.4 v v dd 3.6 v, 2.4 v ev dd v dd , 2.4 v av dd v dd , v ss = ev ss0 = 0 v, av ss = 0 v, reference voltage (+) = internal reference voltage, reference voltage ( ? ) = av ss = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit resolution r es 8 bit conversion time t conv 8-bit resolution 16.0 s zero-scale error note e zs 8-bit resolution 4.0 lsb integral linearity error note ile 8-bit resolution 2.0 lsb differential linearity error note dle 8-bit resolution 2.5 lsb reference voltage (+) av ref(+) = internal reference voltage (v bgr ) 1.38 1.45 1.50 v analog input voltage v ain 0 v bgr v note excludes quantization error ( 1/2 lsb). 3.6.2 temperature sensor, internal reference voltage output characteristics (t a = ? 40 to +105 c, 2.4 v v dd 3.6 v, v ss = 0 v, hs (high-speed main) mode) parameter symbol conditions min. typ. max. unit temperature sensor output voltage v tmps25 setting ads register = 80h, t a = +25 c 1.05 v internal reference voltage v bgr setting ads register = 81h 1.38 1.45 1.5 v temperature coefficient f vtmps temperature sensor output voltage that depends on the temperature ? 3.6 mv/ c operation stabilization wait time t amp 10 s 3.6.3 por circuit characteristics (t a = ? 40 to +105 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit v por power supply rise time 1.45 1.51 1.57 v detection voltage v pdr power supply fall time 1.44 1.50 1.56 v minimum pulse width note t pw 300 s note this is the time required for the por circuit to execute a reset when v dd falls below v pdr . when the microcontroller enters stop mode or if the main system clock (f main ) has been stopped by setting bit 0 (hiostop) and bit 7 (mstop) of the cl ock operation status control register (csc), this is the time required for the por circuit to execute a reset before v dd rises to v por after having fallen below 0.7 v. v por t pw power supply voltage (v dd ) v por or 0.7 v rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 115 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 3.6.4 lvd circuit characteristics lvd detection voltage of reset mode and interrupt mode (t a = ? 40 to +105 c, v pdr v dd 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit power supply rise time 3.01 3.13 3.25 v v lvd2 power supply fall time 2.94 3.06 3.18 v power supply rise time 2.90 3.02 3.14 v v lvd3 power supply fall time 2.85 2.96 3.07 v power supply rise time 2.81 2.92 3.03 v v lvd4 power supply fall time 2.75 2.86 2.97 v power supply rise time 2.70 2.81 2.92 v v lvd5 power supply fall time 2.64 2.75 2.86 v power supply rise time 2.61 2.71 2.81 v v lvd6 power supply fall time 2.55 2.65 2.75 v power supply rise time 2.51 2.61 2.71 v detection voltage supply voltage level v lvd7 power supply fall time 2.45 2.55 2.65 v minimum pulse width t lw 300 s detection delay time 300 s remark v lvd (n ? 1) > v lvdn : n = 3 to 7 lvd detection voltage of interrupt & reset mode (t a = ? 40 to +105 c, v pdr v dd 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit v lvd5 vpoc2, vpoc1, vpoc0 = 0, 1, 1, falling reset voltage 2.64 2.75 2.86 v rising release reset voltage 2.81 2.92 3.03 v v lvd4 lvis1, lvis0 = 1, 0 falling interrupt voltage 2.75 2.86 2.97 v rising release reset voltage 2.90 3.02 3.14 v interrupt & reset mode v lvd3 lvis1, lvis0 = 0, 1 falling interrupt voltage 2.85 2.96 3.07 v caution set the detection voltage (v lvd ) to be within the operating voltage range. the operating voltage range depends on the setting of the user option byte (000c2h/010c2h). the following shows the operating voltage range. hs (high-speed main) mode: v dd = 2.7 to 3.6 v@1 mhz to 32 mhz v dd = 2.4 to 3.6 v@1 mhz to 16 mhz 3.6.5 supply voltage rise slope characteristics (t a = ? 40 to +105 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit supply voltage rise sv dd 54 v/ms caution be sure to maintain the internal reset state until v dd reaches the operating voltage range specified in 3.4 ac characteristics, by using the lvd circuit or external reset pin. rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 116 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 3.7 data memory stop mode low supply voltage data retention characteristics (t a = ? 40 to +105 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 3.6 v note the value depends on the por detec tion voltage. when the voltage dr ops, the data is retained before a por reset is effected, but data is not re tained when a por reset is effected. v dd stop instruction execution standby release signal (inerrupt request) stop mode data hold mode v dddr operation mode 3.8 flash memory programming characteristics (t a = ? 40 to +105 c, 2.4 v v dd 3.6 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit cpu/peripheral hardware clock frequency f clk 2.4 v v dd 3.6 v 1 32 mhz number of code flash rewrites notes 1, 2, 3 retained for 20 years t a = 85 c 1,000 retained for 1 years t a = 25 c 1,000,000 retained for 5 years t a = 85 c 100,000 number of data flash rewrites notes 1, 2, 3 c erwr retained for 20 years t a = 85 c 10,000 times notes 1. 1 erase + 1 write after the er ase is regarded as 1 rewrite. the retaining years are until ne xt rewrite after the rewrite. 2. when using flash memory programmer and renesas electronics self programming library 3. these are the characteristics of the flash memory and the results obtained from reliability testing by renesas electronics corporation. 3.9 dedicated flash memory programmer communication (uart) (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit transfer rate during flash memory programming 115.2 k 1 m bps rl78/g1a 3. electrical specifications( g: industrial applications t a = ? 40 to +105 c) page 117 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 3.10 timing specs for switching flash memory programming modes (t a = ? 40 to +105 c, 2.4 v ev dd0 v dd 3.6 v, v ss = ev ss0 = 0 v) parameter symbol conditions min. typ. max. unit how long from when an external reset ends until the initial communication settings are specified t suinit por and lvd reset must end before the external reset ends. 100 ms how long from when the tool0 pin is placed at the low level until a external reset ends t su por and lvd reset must end before the external reset ends. 10 s how long the tool0 pin must be kept at the low level after an external reset ends (except flash firmware processing time) t hd por and lvd reset must end before the external reset ends. 1 ms reset tool0 <1> <2> <3> t suinit 00h reception (toolrxd, tooltxd mode) t su <4> 723 s + t hd process time <1> the low level is input to the tool0 pin. <2> the pins reset ends (por and lvd reset must end before the external reset ends.). <3> the tool0 pin is set to the high level. <4> setting of the flash memory programmi ng mode by uart reception and complete the baud rate setting. remark t suinit : the segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. t su : how long from when the tool0 pin is placed at the low level until a external reset ends t hd : how long to keep the tool0 pin at the low level from when the external resets end (except flash firmware processing time) rl78/g1a 4. package drawings page 118 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 4. package drawings 4.1 25-pin products r5f10e8aala, r5f10e8cala, r5f10e8dala, r5f10e8eala jeita package code renesas code previous code mass (typ.) [g] p-wflga25-3x3-0.50 pwlg0025ka-a p25fc-50-2n2-2 0.01 (aperture of solder resist) item dimensions d e w e a b x y y1 zd ze 3.00 0.10 3.00 0.10 0.05 0.20 0.69 0.07 0.08 0.50 0.24 0.05 (unit:mm) 0.20 0.50 0.50 s y1 s a s detail of c part y s x 21x b a b m e b 0.34 0.05 0.43 0.05 0.50 0.05 0.365 0.05 r0.17 0.05 r0.165 0.05 r0.215 0.05 0.365 0.05 0.50 0.05 0.33 0.05 0.43 0.05 s wb zd ze index mark b c a s wa d e 2.27 2.27 detail of d part d 1 2 edcba 3 4 5 (land pad) r0.12 0.05 0.33 0.05 index mark 2012 renesas electronics corporation. all rights reserved. rl78/g1a 4. package drawings page 119 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 4.2 32-pin products r5f10ebaana, r5f10ebcana, r5f10ebdana, r5f10ebeana r5f10ebagna, r5f10ebcgna, r5f10ebdgna, r5f10ebegna 2013 renesas electronics corporation. all rights reserved. s y e lp s x ba b m a d e 24 16 17 8 9 1 32 a s b a d e 25 detail of a part exposed die pad jeita package code renesas code previous code mass(typ.)[g] p-hwqfn32-5x5-0.50 pwqn0032kb-a p32k8-50-3b4-5 0.06 8 1 9 16 25 32 index area 2 2 d a lp 0.20 3.50 0.40 5.00 5.00 3.50 referance symbol min nom max dimension in millimeters 0.30 0.30 0.50 b 0.18 x a 0.80 y 0.05 0.00 0.25 e z z c d e 1 d e 2 2 2 e 0.50 0.05 0.75 0.75 0.15 0.25 a 1 c 2 5.05 4.95 5.05 4.95 z z d e 17 24 rl78/g1a 4. package drawings page 120 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 4.3 48-pin products r5f10egaafb, r5f10egcafb, r5f10egdafb, r5f10egeafb r5f10egagfb, r5f10egcgfb, r5f10egdgfb, r5f10egegfb jeita package code re n esas code pre v io u s code mass (typ.) [g] p-lfqfp4 8 -7x7-0.50 plqp004 8 kf-a p4 8 ga-50- 8 eu-1 0.16 s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.055 ? 0.045 (u n it:mm) item dimensions d e hd he a a1 a2 a3 7.00 0.20 7.00 0.20 9.00 0.20 9.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.0 8 0.0 8 0.75 0.75 l lp l1 0.50 0.60 0.15 1.00 0.20 3 + 5 ? 3 each lead centerline is located w ithin 0.0 8 mm of its tr u e position at maxim u m material condition. detail of lead end 0.22 0.05 b 12 24 1 4 8 13 25 37 36 2012 renesas electronics cor poration. all ri g hts reserved. rl78/g1a 4. package drawings page 121 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 r5f10egaana, r5f10egcana, r5f10egdana, r5f10egeana r5f10egagna, r5f10egcgna, r5f10egdgna, r5f10egegna 2013 renesas electronics corporation. all rights reserved. s y e lp s x ba b m a d e 36 24 25 12 13 1 48 a s b a d e 37 detail of a part exposed die pad jeita package code renesas code previous code mass(typ.)[g] p-hwqfn48-7x7-0.50 pwqn0040kb-a 48pjn-a 0.13 12 1 13 24 37 48 index area 2 2 d a lp 0.20 5.50 0.40 7.00 7.00 5.50 referance symbol min nom max dimension in millimeters 0.30 0.30 0.50 b 0.18 x a 0.80 y 0.05 0.00 0.25 e z z c d e 1 d e 2 2 2 e 0.50 0.05 0.75 0.75 0.15 0.25 a 1 c 2 7.05 6.95 7.05 6.95 z z d e 25 36 p40k8-50-5b4-6 rl78/g1a 4. package drawings page 122 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 4.4 64-pin products r5f10elcafb, r5f10eldafb, r5f10eleafb r5f10elcgfb, r5f10eldgfb, r5f10elegfb jeita package code renesas code previous code mass (typ.) [g] p-lfqfp64-10x10-0.50 plqp0064kf-a p64gb-50-ueu-2 0.35 s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.145 + 0.055 ? 0.045 (unit:mm) item dimensions d e hd he a a1 a2 a3 10.00 0.20 10.00 0.20 12.00 0.20 12.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22 0.05 b 16 32 1 64 17 33 49 48 2012 renesas electronics corporation. all rights reserved. rl78/g1a 4. package drawings page 123 of 123 r01ds0151ej0100 rev.1.00 2013.09.25 r5f10elcabg, r5f10eldabg, r5f10eleabg jeita package code renesas code previous code mass (typ.) [g] p-vfbga64-4x4-0.40 pvbg0064la-a p64f1-40-aa2-2 0.03 item dimensions d e w a a1 a2 e 4.00 0.10 4.00 0.10 0.40 0.05 0.08 0.20 0.60 0.60 0.15 0.20 0.05 0.05 0.89 0.10 0.69 0.25 (unit:mm) x y y1 zd ze b zd ze a index mark a2 a1 e s w a s wb b a s y s y1 s s x bab m 8 7 6 5 4 3 2 1 a b c d e f g h d e index mark 2012 renesas electronics corporation. all rights reserved. all trademarks and registered trademarks are t he property of their respective owners. c - 1 revision history rl78/g1a data sheet description rev. date page summary 0.01 dec 26, 2011 - first edition issued 1.00 sep 25, 2013 p.1 modifi cation of 1.1 features p.4 modification of table 1-1. list of ordering part numbers p.6 modification of remark 3 to 1.3.2 32-pin products. p.13 modification of 1.5.2 32-pin products. p.14 modification of 1.5.3 48-pin products. p.16 modification of 1. 6 outline of functions p.21 modification of 2.2.1 x1 , xt1 oscillator characteristics pp.31, 32 modification of note 1 in 2.3.2 supply current characteristics pp.34,35 modification of minimum instruction exec ution time during main system clock operation p.37 modification of ac timing test points in 2.5 peripheral functions characteristics pp.46 to p.58 modification of caution to 2.5.1 serial array unit. pp.63 to p.68 modification of 2.6.1 a/d converter characteristics p.71 modification of 2.7 data memory stop mode low supply voltage data retention characteristics p.71 modification of 2.8 flash memory programming characteristics p.72 modification of 2.10 timing specs for switching flash memory programming modes pp.73 to p.117 addition of 3 electrical specifications (g: industrial applications t a = ? 40 to +105 c) pp.118 to p.123 modification of 4. package drawings superflash is a registered trademark of silicon storage technology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc. notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc ., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is po ssible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave different ly than bipolar or nmos dev ices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static elec tricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequ ate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does no t guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the re set signal is received. a reset operation must be ex ecuted immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the exte rnal power su pply and then the internal power supply. use of the reverse powe r on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the corre ct power on/off sequence must be judged separately for each device and according to related sp ecifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. t he current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elemen ts. input of signals during the power off state must be judged separately for each device and according to re lated specifications governing the device. notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". t he recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactu re, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. htt p ://www.renesas.co m refer to "htt p ://www.renesas.com/" for the latest and detailed information . r e n esas el ec tr o ni cs am e ri ca in c . 2880 scott boulevard santa clara , ca 95050-2554 , u.s.a . tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-651-700, fax: +44-1628-651-804 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics mala y sia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petalin g jaya, selan g or darul ehsan, malaysi a tel: +60-3-7955-9390 , fax: +60-3-7955-951 0 renesas electronics korea co. , ltd . 11f., samik lavied' or bld g ., 720-2 yeoksam-don g , kan g nam-ku, seoul 135-080, korea tel: +82-2-558-3737 , fax: +82-2-558-514 1 s ale s o ffi c e s ? 2013 renesas electronics corporation. all ri g hts reserved . colo p hon 2. 2 |
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